ARM: dts: Add UART2 dt node for Exynos3250 SoC

This patch add the uart2 devicetree node for Exynos3250 SoC.

Change-Id: I28dd84bc645e26f14b7d0c7d630870cc812dccd8
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>

diff --git a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
index 5ab81c3..eac1d21 100644 (file)
--- a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
@@ -120,6 +120,13 @@
                samsung,pin-drv = <0>;
        };
 
+       uart2_data: uart2-data {
+               samsung,pins = "gpa1-0", "gpa1-1";
+               samsung,pin-function = <2>;
+               samsung,pin-pud = <0>;
+               samsung,pin-drv = <0>;
+       };
+
        i2c3_bus: i2c3-bus {
                samsung,pins = "gpa1-2", "gpa1-3";
                samsung,pin-function = <3>;

diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi
index 3056068..563c17c 100644 (file)
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -42,6 +42,7 @@
                i2c7 = &i2c_7;
                serial0 = &serial_0;
                serial1 = &serial_1;
+               serial2 = &serial_2;
        };
 
        cpus {
@@ -571,6 +572,17 @@
                        status = "disabled";
                };
 
+               serial_2: serial@13820000 {
+                       compatible = "samsung,exynos4210-uart";
+                       reg = <0x13820000 0x100>;
+                       interrupts = <0 111 0>;
+                       clocks = <&cmu CLK_UART2>, <&cmu CLK_SCLK_UART2>;
+                       clock-names = "uart", "clk_uart_baud0";
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&uart2_data>;
+                       status = "disabled";
+               };
+
                i2c_0: i2c@13860000 {
                        #address-cells = <1>;
                        #size-cells = <0>;