iris: Promote to MAP_DIRECTLY when required before NULL return

In some cases, we have to map directly (e.g. coherent/persistent maps).
In other cases (e.g. tiled), we /cannot/ map directly.  We should put
the code which adds the PIPE_MAP_DIRECTLY flag in mandatory cases before
the "bail and return NULL" check for cases where we can't do that.

We leave the "we would prefer to direct map this" cases after the error
check, since we -can- use blits for those, we'd just rather not.  ASTC
also stays because even though it's tiled, our tiled memcpy paths work.

Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10941>

diff --git a/src/gallium/drivers/iris/iris_resource.c b/src/gallium/drivers/iris/iris_resource.c
index 77c185f..9fbf636 100644 (file)
--- a/src/gallium/drivers/iris/iris_resource.c
+++ b/src/gallium/drivers/iris/iris_resource.c
@@ -1998,6 +1998,20 @@ iris_transfer_map(struct pipe_context *ctx,
       usage |= PIPE_MAP_UNSYNCHRONIZED;
    }
 
+   /* Avoid using GPU copies for persistent/coherent buffers, as the idea
+    * there is to access them simultaneously on the CPU & GPU.  This also
+    * avoids trying to use GPU copies for our u_upload_mgr buffers which
+    * contain state we're constructing for a GPU draw call, which would
+    * kill us with infinite stack recursion.
+    */
+   if (usage & (PIPE_MAP_PERSISTENT | PIPE_MAP_COHERENT))
+      usage |= PIPE_MAP_DIRECTLY;
+
+   /* We cannot provide a direct mapping of tiled resources */
+   if (surf->tiling != ISL_TILING_LINEAR &&
+       (usage & PIPE_MAP_DIRECTLY))
+      return NULL;
+
    bool map_would_stall = false;
 
    if (!(usage & PIPE_MAP_UNSYNCHRONIZED)) {
@@ -2010,10 +2024,6 @@ iris_transfer_map(struct pipe_context *ctx,
          return NULL;
    }
 
-   if (surf->tiling != ISL_TILING_LINEAR &&
-       (usage & PIPE_MAP_DIRECTLY))
-      return NULL;
-
    struct iris_transfer *map;
 
    if (usage & TC_TRANSFER_MAP_THREADED_UNSYNC)
@@ -2042,15 +2052,6 @@ iris_transfer_map(struct pipe_context *ctx,
    if (usage & PIPE_MAP_WRITE)
       util_range_add(&res->base.b, &res->valid_buffer_range, box->x, box->x + box->width);
 
-   /* Avoid using GPU copies for persistent/coherent buffers, as the idea
-    * there is to access them simultaneously on the CPU & GPU.  This also
-    * avoids trying to use GPU copies for our u_upload_mgr buffers which
-    * contain state we're constructing for a GPU draw call, which would
-    * kill us with infinite stack recursion.
-    */
-   if (usage & (PIPE_MAP_PERSISTENT | PIPE_MAP_COHERENT))
-      usage |= PIPE_MAP_DIRECTLY;
-
    /* GPU copies are not useful for buffer reads.  Instead of stalling to
     * read from the original buffer, we'd simply copy it to a temporary...
     * then stall (a bit longer) to read from that buffer.