[DirectX] Fix crash on ShuffleVectorInst in DXILBitcodeWriter

Use onstantDataSequential::getElementType to allow vector type.

Use getShuffleMaskForBitcode to get ShuffleMask.

Use old format for alloca Align.

Reviewed By: beanz

Differential Revision: https://reviews.llvm.org/D132102

diff --git a/llvm/lib/Target/DirectX/DXILWriter/DXILBitcodeWriter.cpp b/llvm/lib/Target/DirectX/DXILWriter/DXILBitcodeWriter.cpp
index 70004f4..f95d3a2 100644 (file)
--- a/llvm/lib/Target/DirectX/DXILWriter/DXILBitcodeWriter.cpp
+++ b/llvm/lib/Target/DirectX/DXILWriter/DXILBitcodeWriter.cpp
@@ -2070,7 +2070,7 @@ void DXILBitcodeWriter::writeConstants(unsigned FirstVal, unsigned LastVal,
     } else if (const ConstantDataSequential *CDS =
                    dyn_cast<ConstantDataSequential>(C)) {
       Code = bitc::CST_CODE_DATA;
-      Type *EltTy = CDS->getType()->getArrayElementType();
+      Type *EltTy = CDS->getElementType();
       if (isa<IntegerType>(EltTy)) {
         for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i)
           Record.push_back(CDS->getElementAsInteger(i));
@@ -2318,7 +2318,8 @@ void DXILBitcodeWriter::writeInstruction(const Instruction &I, unsigned InstID,
     Code = bitc::FUNC_CODE_INST_SHUFFLEVEC;
     pushValueAndType(I.getOperand(0), InstID, Vals);
     pushValue(I.getOperand(1), InstID, Vals);
-    pushValue(I.getOperand(2), InstID, Vals);
+    pushValue(cast<ShuffleVectorInst>(&I)->getShuffleMaskForBitcode(), InstID,
+              Vals);
     break;
   case Instruction::ICmp:
   case Instruction::FCmp: {
@@ -2449,15 +2450,13 @@ void DXILBitcodeWriter::writeInstruction(const Instruction &I, unsigned InstID,
     Vals.push_back(getTypeID(AI.getAllocatedType()));
     Vals.push_back(getTypeID(I.getOperand(0)->getType()));
     Vals.push_back(VE.getValueID(I.getOperand(0))); // size.
-    using APV = AllocaPackedValues;
-    unsigned Record = 0;
-    unsigned EncodedAlign = getEncodedAlign(AI.getAlign());
-    Bitfield::set<APV::AlignLower>(
-        Record, EncodedAlign & ((1 << APV::AlignLower::Bits) - 1));
-    Bitfield::set<APV::AlignUpper>(Record,
-                                   EncodedAlign >> APV::AlignLower::Bits);
-    Bitfield::set<APV::UsedWithInAlloca>(Record, AI.isUsedWithInAlloca());
-    Vals.push_back(Record);
+    unsigned AlignRecord = Log2_32(AI.getAlign().value()) + 1;
+    assert(Log2_32(Value::MaximumAlignment) + 1 < 1 << 5 &&
+           "not enough bits for maximum alignment");
+    assert(AlignRecord < 1 << 5 && "alignment greater than 1 << 64");
+    AlignRecord |= AI.isUsedWithInAlloca() << 5;
+    AlignRecord |= 1 << 6;
+    Vals.push_back(AlignRecord);
     break;
   }
 

diff --git a/llvm/test/tools/dxil-dis/shuffle.ll b/llvm/test/tools/dxil-dis/shuffle.ll
new file mode 100644 (file)
index 0000000..6e45adc
--- /dev/null
+++ b/llvm/test/tools/dxil-dis/shuffle.ll
@@ -0,0 +1,27 @@
+; RUN: llc --filetype=obj %s -o - 2>&1 | dxil-dis -o - | FileCheck %s\r
+target datalayout = "e-m:e-p:32:32-i1:32-i8:8-i16:16-i32:32-i64:64-f16:16-f32:32-f64:64-n8:16:32:64"\r
+target triple = "dxil-unknown-shadermodel6.7-library"\r
+\r
+; Make sure alloca is the same.\r
+; CHECK:alloca <2 x float>, align 8\r
+; Make sure shufflevector works for DXIL bitcode writer.\r
+; CHECK:shufflevector <2 x float> %{{.*}}, <2 x float> undef, <2 x i32> <i32 1, i32 0>\r
+\r
+; Function Attrs: noinline nounwind optnone\r
+define noundef <2 x float> @foo(<2 x float> noundef %a) #0 {\r
+entry:\r
+  %a.addr = alloca <2 x float>, align 8\r
+  store <2 x float> %a, ptr %a.addr, align 8\r
+  %0 = load <2 x float>, ptr %a.addr, align 8\r
+  %1 = shufflevector <2 x float> %0, <2 x float> poison, <2 x i32> <i32 1, i32 0>\r
+  ret <2 x float> %1\r
+}\r
+\r
+attributes #0 = { noinline nounwind optnone "frame-pointer"="all" "min-legal-vector-width"="64" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }\r
+\r
+!llvm.module.flags = !{!0, !1, !3}\r
+\r
+!0 = !{i32 1, !"wchar_size", i32 4}\r
+!1 = !{i32 6, !"dx.valver", !2}\r
+!2 = !{i32 1, i32 7}\r
+!3 = !{i32 7, !"frame-pointer", i32 2}\r