clk:starfive:Modify the clock to 'CLK_IGNORE_UNUSED' flag

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>

diff --git a/drivers/clk/starfive/clk-starfive-jh7110-gen.c b/drivers/clk/starfive/clk-starfive-jh7110-gen.c
index 7f6ba3a..437065b 100755 (executable)
--- a/drivers/clk/starfive/clk-starfive-jh7110-gen.c
+++ b/drivers/clk/starfive/clk-starfive-jh7110-gen.c
@@ -78,9 +78,9 @@ static int jh7110_clk_enable(struct clk_hw *hw)
 
 static void jh7110_clk_disable(struct clk_hw *hw)
 {
-       //struct jh7110_clk *clk = jh7110_clk_from(hw);
+       struct jh7110_clk *clk = jh7110_clk_from(hw);
 
-       //jh7110_clk_reg_rmw(clk, JH7110_CLK_ENABLE, 0);
+       jh7110_clk_reg_rmw(clk, JH7110_CLK_ENABLE, 0);
 }
 
 static int jh7110_clk_is_enabled(struct clk_hw *hw)

diff --git a/drivers/clk/starfive/clk-starfive-jh7110-stg.c b/drivers/clk/starfive/clk-starfive-jh7110-stg.c
index 3864b03..477df78 100755 (executable)
--- a/drivers/clk/starfive/clk-starfive-jh7110-stg.c
+++ b/drivers/clk/starfive/clk-starfive-jh7110-stg.c
@@ -53,24 +53,24 @@ static const struct jh7110_clk_data jh7110_clk_stg_data[] __initconst = {
                        GATE_FLAG_NORMAL, JH7110_STG_AXIAHB),
        //stg mtrx
        JH7110_GATE(JH7110_STG_MTRX_GRP0_CLK_MAIN, "u0_stg_mtrx_grp0_clk_main",
-                       GATE_FLAG_NORMAL, JH7110_CPU_BUS),
+                       CLK_IGNORE_UNUSED, JH7110_CPU_BUS),
        JH7110_GATE(JH7110_STG_MTRX_GRP0_CLK_BUS, "u0_stg_mtrx_grp0_clk_bus",
-                       GATE_FLAG_NORMAL, JH7110_NOCSTG_BUS),
+                       CLK_IGNORE_UNUSED, JH7110_NOCSTG_BUS),
        JH7110_GATE(JH7110_STG_MTRX_GRP0_CLK_STG, "u0_stg_mtrx_grp0_clk_stg",
-                       GATE_FLAG_NORMAL, JH7110_STG_AXIAHB),
+                       CLK_IGNORE_UNUSED, JH7110_STG_AXIAHB),
        JH7110_GATE(JH7110_STG_MTRX_GRP1_CLK_MAIN, "u0_stg_mtrx_grp1_clk_main",
-                       GATE_FLAG_NORMAL, JH7110_CPU_BUS),
+                       CLK_IGNORE_UNUSED, JH7110_CPU_BUS),
        JH7110_GATE(JH7110_STG_MTRX_GRP1_CLK_BUS, "u0_stg_mtrx_grp1_clk_bus",
-                       GATE_FLAG_NORMAL, JH7110_NOCSTG_BUS),
+                       CLK_IGNORE_UNUSED, JH7110_NOCSTG_BUS),
        JH7110_GATE(JH7110_STG_MTRX_GRP1_CLK_STG, "u0_stg_mtrx_grp1_clk_stg",
-                       GATE_FLAG_NORMAL, JH7110_STG_AXIAHB),
+                       CLK_IGNORE_UNUSED, JH7110_STG_AXIAHB),
        JH7110_GATE(JH7110_STG_MTRX_GRP1_CLK_HIFI, "u0_stg_mtrx_grp1_clk_hifi",
-                       GATE_FLAG_NORMAL, JH7110_HIFI4_AXI),
+                       CLK_IGNORE_UNUSED, JH7110_HIFI4_AXI),
        //e24_rvpi
        JH7110_GDIV(JH7110_E2_RTC_CLK, "u0_e2_sft7110_rtc_clk",
                        GATE_FLAG_NORMAL, 24, JH7110_OSC),
        JH7110_GATE(JH7110_E2_CLK_CORE, "u0_e2_sft7110_clk_core",
-                       GATE_FLAG_NORMAL, JH7110_STG_AXIAHB),
+                       CLK_IGNORE_UNUSED, JH7110_STG_AXIAHB),
        JH7110_GATE(JH7110_E2_CLK_DBG, "u0_e2_sft7110_clk_dbg",
                        GATE_FLAG_NORMAL, JH7110_STG_AXIAHB),
        //dw_sgdma1p

diff --git a/drivers/clk/starfive/clk-starfive-jh7110-sys.c b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
index 242f124..ecc00f9 100755 (executable)
--- a/drivers/clk/starfive/clk-starfive-jh7110-sys.c
+++ b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
@@ -33,11 +33,11 @@ static const struct jh7110_clk_data jh7110_clk_sys_data[] __initconst = {
        JH7110__DIV(JH7110_NOCSTG_BUS, "nocstg_bus", 3, JH7110_BUS_ROOT),
        JH7110__DIV(JH7110_AXI_CFG0, "axi_cfg0", 3, JH7110_BUS_ROOT),
        JH7110__DIV(JH7110_STG_AXIAHB, "stg_axiahb", 2, JH7110_AXI_CFG0),
-       JH7110_GATE(JH7110_AHB0, "ahb0", GATE_FLAG_NORMAL, JH7110_STG_AXIAHB),
-       JH7110_GATE(JH7110_AHB1, "ahb1", GATE_FLAG_NORMAL, JH7110_STG_AXIAHB),
+       JH7110_GATE(JH7110_AHB0, "ahb0", CLK_IGNORE_UNUSED, JH7110_STG_AXIAHB),
+       JH7110_GATE(JH7110_AHB1, "ahb1", CLK_IGNORE_UNUSED, JH7110_STG_AXIAHB),
        JH7110__DIV(JH7110_APB_BUS_FUNC, "apb_bus_func",
                        8, JH7110_STG_AXIAHB),
-       JH7110_GATE(JH7110_APB0, "apb0", GATE_FLAG_NORMAL, JH7110_APB_BUS),
+       JH7110_GATE(JH7110_APB0, "apb0", CLK_IGNORE_UNUSED, JH7110_APB_BUS),
        JH7110__DIV(JH7110_PLL0_DIV2, "pll0_div2", 2, JH7110_PLL0_OUT),
        JH7110__DIV(JH7110_PLL1_DIV2, "pll1_div2", 2, JH7110_PLL1_OUT),
        JH7110__DIV(JH7110_PLL2_DIV2, "pll2_div2", 2, JH7110_PLL2_OUT),
@@ -60,38 +60,38 @@ static const struct jh7110_clk_data jh7110_clk_sys_data[] __initconst = {
                        62, JH7110_PLL2_DIV2),
        /*u0_u7mc_sft7110*/
        JH7110_GATE(JH7110_U7_CORE_CLK, "u0_u7mc_sft7110_core_clk",
-                       GATE_FLAG_NORMAL, JH7110_CPU_CORE),
+                       CLK_IGNORE_UNUSED, JH7110_CPU_CORE),
        JH7110_GATE(JH7110_U7_CORE_CLK1, "u0_u7mc_sft7110_core_clk1",
-                       GATE_FLAG_NORMAL, JH7110_CPU_CORE),
+                       CLK_IGNORE_UNUSED, JH7110_CPU_CORE),
        JH7110_GATE(JH7110_U7_CORE_CLK2, "u0_u7mc_sft7110_core_clk2",
-                       GATE_FLAG_NORMAL, JH7110_CPU_CORE),
+                       CLK_IGNORE_UNUSED, JH7110_CPU_CORE),
        JH7110_GATE(JH7110_U7_CORE_CLK3, "u0_u7mc_sft7110_core_clk3",
-                       GATE_FLAG_NORMAL, JH7110_CPU_CORE),
+                       CLK_IGNORE_UNUSED, JH7110_CPU_CORE),
        JH7110_GATE(JH7110_U7_CORE_CLK4, "u0_u7mc_sft7110_core_clk4",
-                       GATE_FLAG_NORMAL, JH7110_CPU_CORE),
+                       CLK_IGNORE_UNUSED, JH7110_CPU_CORE),
        JH7110_GATE(JH7110_U7_DEBUG_CLK, "u0_u7mc_sft7110_debug_clk",
-                       GATE_FLAG_NORMAL, JH7110_CPU_BUS),
+                       CLK_IGNORE_UNUSED, JH7110_CPU_BUS),
        JH7110__DIV(JH7110_U7_RTC_TOGGLE, "u0_u7mc_sft7110_rtc_toggle",
                        6, JH7110_OSC),
        JH7110_GATE(JH7110_U7_TRACE_CLK0, "u0_u7mc_sft7110_trace_clk0",
-                       GATE_FLAG_NORMAL, JH7110_CPU_CORE),
+                       CLK_IGNORE_UNUSED, JH7110_CPU_CORE),
        JH7110_GATE(JH7110_U7_TRACE_CLK1, "u0_u7mc_sft7110_trace_clk1",
-                       GATE_FLAG_NORMAL, JH7110_CPU_CORE),
+                       CLK_IGNORE_UNUSED, JH7110_CPU_CORE),
        JH7110_GATE(JH7110_U7_TRACE_CLK2, "u0_u7mc_sft7110_trace_clk2",
-                       GATE_FLAG_NORMAL, JH7110_CPU_CORE),
+                       CLK_IGNORE_UNUSED, JH7110_CPU_CORE),
        JH7110_GATE(JH7110_U7_TRACE_CLK3, "u0_u7mc_sft7110_trace_clk3",
-                       GATE_FLAG_NORMAL, JH7110_CPU_CORE),
+                       CLK_IGNORE_UNUSED, JH7110_CPU_CORE),
        JH7110_GATE(JH7110_U7_TRACE_CLK4, "u0_u7mc_sft7110_trace_clk4",
-                       GATE_FLAG_NORMAL, JH7110_CPU_CORE),
+                       CLK_IGNORE_UNUSED, JH7110_CPU_CORE),
        JH7110_GATE(JH7110_U7_TRACE_COM_CLK, "u0_u7mc_sft7110_trace_com_clk",
-                       GATE_FLAG_NORMAL, JH7110_CPU_BUS),
+                       CLK_IGNORE_UNUSED, JH7110_CPU_BUS),
        //NOC
        JH7110_GATE(JH7110_NOC_BUS_CLK_CPU_AXI,
                        "u0_sft7110_noc_bus_clk_cpu_axi",
-                       GATE_FLAG_NORMAL, JH7110_CPU_BUS),
+                       CLK_IGNORE_UNUSED, JH7110_CPU_BUS),
        JH7110_GATE(JH7110_NOC_BUS_CLK_AXICFG0_AXI,
                        "u0_sft7110_noc_bus_clk_axicfg0_axi",
-                       GATE_FLAG_NORMAL, JH7110_AXI_CFG0),
+                       CLK_IGNORE_UNUSED, JH7110_AXI_CFG0),
        //DDRC
        JH7110__DIV(JH7110_OSC_DIV2, "osc_div2", 2, JH7110_OSC),
        JH7110__DIV(JH7110_PLL1_DIV4, "pll1_div4", 2, JH7110_PLL1_DIV2),
@@ -102,7 +102,7 @@ static const struct jh7110_clk_data jh7110_clk_sys_data[] __initconst = {
                        JH7110_PLL1_DIV4,
                        JH7110_PLL1_DIV8),
        JH7110_GATE(JH7110_DDR_CLK_AXI, "u0_ddr_sft7110_clk_axi",
-                       GATE_FLAG_NORMAL, JH7110_DDR_BUS),
+                       CLK_IGNORE_UNUSED, JH7110_DDR_BUS),
        //GPU
        JH7110__DIV(JH7110_GPU_CORE, "gpu_core", 7, JH7110_GPU_ROOT),
        JH7110_GATE(JH7110_GPU_CORE_CLK, "u0_img_gpu_core_clk",
@@ -125,15 +125,15 @@ static const struct jh7110_clk_data jh7110_clk_sys_data[] __initconst = {
                        GATE_FLAG_NORMAL, JH7110_ISP_AXI),
        JH7110_GATE(JH7110_NOC_BUS_CLK_ISP_AXI,
                        "u0_sft7110_noc_bus_clk_isp_axi",
-                       GATE_FLAG_NORMAL, JH7110_ISP_AXI),
+                       CLK_IGNORE_UNUSED, JH7110_ISP_AXI),
        //HIFI4
        JH7110__DIV(JH7110_HIFI4_CORE, "hifi4_core", 15, JH7110_BUS_ROOT),
        JH7110__DIV(JH7110_HIFI4_AXI, "hifi4_axi", 2, JH7110_HIFI4_CORE),
        //AXICFG1_DEC
        JH7110_GATE(JH7110_AXI_CFG1_DEC_CLK_MAIN, "u0_axi_cfg1_dec_clk_main",
-                       GATE_FLAG_NORMAL, JH7110_AXI_CFG1),
+                       CLK_IGNORE_UNUSED, JH7110_AXI_CFG1),
        JH7110_GATE(JH7110_AXI_CFG1_DEC_CLK_AHB, "u0_axi_cfg1_dec_clk_ahb",
-                       GATE_FLAG_NORMAL, JH7110_AHB0),
+                       CLK_IGNORE_UNUSED, JH7110_AHB0),
        //VOUT
        JH7110_GATE(JH7110_VOUT_SRC,
                        "u0_dom_vout_top_clk_dom_vout_top_clk_vout_src",
@@ -195,38 +195,38 @@ static const struct jh7110_clk_data jh7110_clk_sys_data[] __initconst = {
        //INTMEM
        JH7110_GATE(JH7110_AXI_CFG0_DEC_CLK_MAIN_DIV,
                        "u0_axi_cfg0_dec_clk_main_div",
-                       GATE_FLAG_NORMAL, JH7110_AHB1),
+                       CLK_IGNORE_UNUSED, JH7110_AHB1),
        JH7110_GATE(JH7110_AXI_CFG0_DEC_CLK_MAIN, "u0_axi_cfg0_dec_clk_main",
-                       GATE_FLAG_NORMAL, JH7110_AXI_CFG0),
+                       CLK_IGNORE_UNUSED, JH7110_AXI_CFG0),
        JH7110_GATE(JH7110_AXI_CFG0_DEC_CLK_HIFI4, "u0_axi_cfg0_dec_clk_hifi4",
-                       GATE_FLAG_NORMAL, JH7110_HIFI4_AXI),
+                       CLK_IGNORE_UNUSED, JH7110_HIFI4_AXI),
        JH7110_GATE(JH7110_AXIMEM2_128B_CLK_AXI, "u2_aximem_128b_clk_axi",
-                       GATE_FLAG_NORMAL, JH7110_AXI_CFG0),
+                       CLK_IGNORE_UNUSED, JH7110_AXI_CFG0),
        //QSPI
        JH7110_GATE(JH7110_QSPI_CLK_AHB, "u0_cdns_qspi_clk_ahb",
-                       GATE_FLAG_NORMAL, JH7110_AHB1),
+                       CLK_IGNORE_UNUSED, JH7110_AHB1),
        JH7110_GATE(JH7110_QSPI_CLK_APB, "u0_cdns_qspi_clk_apb",
-                       GATE_FLAG_NORMAL, JH7110_APB12),
+                       CLK_IGNORE_UNUSED, JH7110_APB12),
        JH7110__DIV(JH7110_QSPI_REF_SRC, "u0_cdns_qspi_ref_src",
                        16, JH7110_GMACUSB_ROOT),
        JH7110_GMUX(JH7110_QSPI_CLK_REF, "u0_cdns_qspi_clk_ref",
-                       GATE_FLAG_NORMAL, PARENT_NUMS_2,
+                       CLK_IGNORE_UNUSED, PARENT_NUMS_2,
                        JH7110_OSC,
                        JH7110_QSPI_REF_SRC),
        //SDIO
        JH7110_GATE(JH7110_SDIO0_CLK_AHB, "u0_dw_sdio_clk_ahb",
-                       GATE_FLAG_NORMAL, JH7110_AHB0),
+                       CLK_IGNORE_UNUSED, JH7110_AHB0),
        JH7110_GATE(JH7110_SDIO1_CLK_AHB, "u1_dw_sdio_clk_ahb",
-                       GATE_FLAG_NORMAL, JH7110_AHB0),
+                       CLK_IGNORE_UNUSED, JH7110_AHB0),
        JH7110_GDIV(JH7110_SDIO0_CLK_SDCARD, "u0_dw_sdio_clk_sdcard",
-                       GATE_FLAG_NORMAL, 15, JH7110_AXI_CFG0),
+                       CLK_IGNORE_UNUSED, 15, JH7110_AXI_CFG0),
        JH7110_GDIV(JH7110_SDIO1_CLK_SDCARD, "u1_dw_sdio_clk_sdcard",
-                       GATE_FLAG_NORMAL, 15, JH7110_AXI_CFG0),
+                       CLK_IGNORE_UNUSED, 15, JH7110_AXI_CFG0),
        //STG
        JH7110__DIV(JH7110_USB_125M, "usb_125m", 15, JH7110_GMACUSB_ROOT),
        JH7110_GATE(JH7110_NOC_BUS_CLK_STG_AXI,
                        "u0_sft7110_noc_bus_clk_stg_axi",
-                       GATE_FLAG_NORMAL, JH7110_NOCSTG_BUS),
+                       CLK_IGNORE_UNUSED, JH7110_NOCSTG_BUS),
        //GMAC1
        JH7110_GATE(JH7110_GMAC5_CLK_AHB, "u1_dw_gmac5_axi64_clk_ahb",
                        GATE_FLAG_NORMAL, JH7110_AHB0),
@@ -287,20 +287,20 @@ static const struct jh7110_clk_data jh7110_clk_sys_data[] __initconst = {
                        GATE_FLAG_NORMAL, JH7110_APB12),
        //WDT
        JH7110_GATE(JH7110_DSKIT_WDT_CLK_APB, "u0_dskit_wdt_clk_apb",
-                       GATE_FLAG_NORMAL, JH7110_APB12),
+                       CLK_IGNORE_UNUSED, JH7110_APB12),
        JH7110_GATE(JH7110_DSKIT_WDT_CLK_WDT, "u0_dskit_wdt_clk_wdt",
-                       GATE_FLAG_NORMAL, JH7110_OSC),
+                       CLK_IGNORE_UNUSED, JH7110_OSC),
        //TIMER
        JH7110_GATE(JH7110_TIMER_CLK_APB, "u0_si5_timer_clk_apb",
-                       GATE_FLAG_NORMAL, JH7110_APB12),
+                       CLK_IGNORE_UNUSED, JH7110_APB12),
        JH7110_GATE(JH7110_TIMER_CLK_TIMER0, "u0_si5_timer_clk_timer0",
-                       GATE_FLAG_NORMAL, JH7110_OSC),
+                       CLK_IGNORE_UNUSED, JH7110_OSC),
        JH7110_GATE(JH7110_TIMER_CLK_TIMER1, "u0_si5_timer_clk_timer1",
-                       GATE_FLAG_NORMAL, JH7110_OSC),
+                       CLK_IGNORE_UNUSED, JH7110_OSC),
        JH7110_GATE(JH7110_TIMER_CLK_TIMER2, "u0_si5_timer_clk_timer2",
-                       GATE_FLAG_NORMAL, JH7110_OSC),
+                       CLK_IGNORE_UNUSED, JH7110_OSC),
        JH7110_GATE(JH7110_TIMER_CLK_TIMER3, "u0_si5_timer_clk_timer3",
-                       GATE_FLAG_NORMAL, JH7110_OSC),
+                       CLK_IGNORE_UNUSED, JH7110_OSC),
        //TEMP SENSOR
        JH7110_GATE(JH7110_TEMP_SENSOR_CLK_APB, "u0_temp_sensor_clk_apb",
                        GATE_FLAG_NORMAL, JH7110_APB12),
@@ -338,9 +338,9 @@ static const struct jh7110_clk_data jh7110_clk_sys_data[] __initconst = {
                        GATE_FLAG_NORMAL, JH7110_APB12),
        //UART
        JH7110_GATE(JH7110_UART0_CLK_APB, "u0_dw_uart_clk_apb",
-                       GATE_FLAG_NORMAL, JH7110_APB0),
+                       CLK_IGNORE_UNUSED, JH7110_APB0),
        JH7110_GATE(JH7110_UART0_CLK_CORE, "u0_dw_uart_clk_core",
-                       GATE_FLAG_NORMAL, JH7110_OSC),
+                       CLK_IGNORE_UNUSED, JH7110_OSC),
        JH7110_GATE(JH7110_UART1_CLK_APB, "u1_dw_uart_clk_apb",
                        GATE_FLAG_NORMAL, JH7110_APB0),
        JH7110_GATE(JH7110_UART1_CLK_CORE, "u1_dw_uart_clk_core",