[Hexagon] Avoid some unnecessary sign-extend instructions

Simplify (sext_inreg (extractu ...)) -> (extract ...) where appropriate.

diff --git a/llvm/lib/Target/Hexagon/HexagonPatterns.td b/llvm/lib/Target/Hexagon/HexagonPatterns.td
index cbb437c..b00ed06 100644 (file)
--- a/llvm/lib/Target/Hexagon/HexagonPatterns.td
+++ b/llvm/lib/Target/Hexagon/HexagonPatterns.td
@@ -1057,6 +1057,30 @@ def: Pat<(v8i8 (splat_vector I32:$Rs)), (S6_vsplatrbp I32:$Rs)>,
 def: Pat<(v8i8 (splat_vector I32:$Rs)),
          (Combinew (S2_vsplatrb I32:$Rs), (S2_vsplatrb I32:$Rs))>;
 
+let AddedComplexity = 10 in {
+  def: Pat<(sext_inreg (HexagonEXTRACTU I32:$Rs,  8, u5_0ImmPred:$U5),  i8),
+           (S4_extract  I32:$Rs,  8, imm:$U5)>;
+  def: Pat<(sext_inreg (HexagonEXTRACTU I32:$Rs, 16, u5_0ImmPred:$U5), i16),
+           (S4_extract  I32:$Rs, 16, imm:$U5)>;
+  def: Pat<(sext_inreg (HexagonEXTRACTU I64:$Rs,  8, u6_0ImmPred:$U6),  i8),
+           (S4_extractp I64:$Rs,  8, imm:$U6)>;
+  def: Pat<(sext_inreg (HexagonEXTRACTU I64:$Rs, 16, u6_0ImmPred:$U6), i16),
+           (S4_extractp I64:$Rs, 16, imm:$U6)>;
+  def: Pat<(sext_inreg (HexagonEXTRACTU I64:$Rs, 32, u6_0ImmPred:$U6), i32),
+           (S4_extractp I64:$Rs, 32, imm:$U6)>;
+}
+
+def: Pat<(sext_inreg (HexagonEXTRACTU I32:$Rs,  8, I32:$Off),  i8),
+         (S4_extract_rp  I32:$Rs, (Combinew (ToI32 8), I32:$Off))>;
+def: Pat<(sext_inreg (HexagonEXTRACTU I32:$Rs, 16, I32:$Off), i16),
+         (S4_extract_rp  I32:$Rs, (Combinew (ToI32 16), I32:$Off))>;
+def: Pat<(sext_inreg (HexagonEXTRACTU I64:$Rs,  8, I32:$Off),  i8),
+         (S4_extractp_rp I64:$Rs, (Combinew (ToI32 8), I32:$Off))>;
+def: Pat<(sext_inreg (HexagonEXTRACTU I64:$Rs, 16, I32:$Off), i16),
+         (S4_extractp_rp I64:$Rs, (Combinew (ToI32 16), I32:$Off))>;
+def: Pat<(sext_inreg (HexagonEXTRACTU I64:$Rs, 32, I32:$Off), i32),
+         (S4_extractp_rp I64:$Rs, (Combinew (ToI32 32), I32:$Off))>;
+
 
 // --(8) Shift/permute ---------------------------------------------------
 //

diff --git a/llvm/test/CodeGen/Hexagon/vect/vect-shifts.ll b/llvm/test/CodeGen/Hexagon/vect/vect-shifts.ll
index 95235e2..46f73c5 100644 (file)
--- a/llvm/test/CodeGen/Hexagon/vect/vect-shifts.ll
+++ b/llvm/test/CodeGen/Hexagon/vect/vect-shifts.ll
@@ -240,29 +240,27 @@ define <4 x i8> @f15(<4 x i8> %a0) unnamed_addr #0 {
 ; CHECK-LABEL: f15:
 ; CHECK:       // %bb.0: // %b0
 ; CHECK-NEXT:    {
-; CHECK-NEXT:     r1 = extractu(r0,#8,#16)
-; CHECK-NEXT:     r2 = extractu(r0,#8,#24)
+; CHECK-NEXT:     r1 = extract(r0,#8,#16)
+; CHECK-NEXT:     r2 = extract(r0,#8,#8)
 ; CHECK-NEXT:     r3 = sxtb(r0)
 ; CHECK-NEXT:    }
 ; CHECK-NEXT:    {
-; CHECK-NEXT:     r4 = extract(r0,#8,#8)
-; CHECK-NEXT:     r3 = extractu(r3,#8,#1)
-; CHECK-NEXT:     r2 = sxtb(r2)
-; CHECK-NEXT:     r1 = sxtb(r1)
+; CHECK-NEXT:     r4 = extract(r0,#8,#24)
+; CHECK-NEXT:     r2 = asl(r2,#6)
 ; CHECK-NEXT:    }
 ; CHECK-NEXT:    {
-; CHECK-NEXT:     r0 = asl(r4,#6)
-; CHECK-NEXT:     r2 = asl(r2,#4)
+; CHECK-NEXT:     r3 = extractu(r3,#8,#1)
+; CHECK-NEXT:     r0 = asl(r4,#4)
 ; CHECK-NEXT:    }
 ; CHECK-NEXT:    {
 ; CHECK-NEXT:     r1 = extractu(r1,#8,#3)
-; CHECK-NEXT:     r0 = or(r3,and(r0,##65280))
+; CHECK-NEXT:     r2 = or(r3,and(r2,##65280))
 ; CHECK-NEXT:    }
 ; CHECK-NEXT:    {
-; CHECK-NEXT:     r2 = or(r1,and(r2,##65280))
+; CHECK-NEXT:     r0 = or(r1,and(r0,##65280))
 ; CHECK-NEXT:    }
 ; CHECK-NEXT:    {
-; CHECK-NEXT:     r0 = combine(r2.l,r0.l)
+; CHECK-NEXT:     r0 = combine(r0.l,r2.l)
 ; CHECK-NEXT:     jumpr r31
 ; CHECK-NEXT:    }
 b0:
@@ -472,11 +470,8 @@ define <2 x i16> @f21(<2 x i16> %a0) unnamed_addr #0 {
 ; CHECK-LABEL: f21:
 ; CHECK:       // %bb.0: // %b0
 ; CHECK-NEXT:    {
+; CHECK-NEXT:     r1 = extract(r0,#16,#16)
 ; CHECK-NEXT:     r2 = extract(r0,#15,#1)
-; CHECK-NEXT:     r1 = lsr(r0,#16)
-; CHECK-NEXT:    }
-; CHECK-NEXT:    {
-; CHECK-NEXT:     r1 = sxth(r1)
 ; CHECK-NEXT:    }
 ; CHECK-NEXT:    {
 ; CHECK-NEXT:     r1 = asr(r1,#2)