--- /dev/null
+#
+# Copyright (C) 2010 Samsung Electronics
+# Minkyu Kang <mk7.kang@samsung.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS-y := slp7.o
+SOBJS := lowlevel_init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(SOBJS) $(OBJS)
+ $(call cmd_link_o_target, $(SOBJS) $(OBJS))
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\r
+;;;;;;;;;;; <S5PC210 cmm file > ;;;;;;;;;;;;;;\r
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\r
+\r
+;----------------------------------------------------------------------;\r
+; Configuring Option\r
+;----------------------------------------------------------------------;\r
+reset\r
+;wait 2.s\r
+print "Reset System"\r
+\r
+&POP_TYPE_A='A'\r
+&POP_TYPE_B='B'\r
+\r
+&POP_TYPE=&POP_TYPE_A\r
+\r
+&DMC_DLL_ON=1\r
+;&DMC_DLL_ON=0\r
+\r
+&MIU_1BIT_12_INTERLEAVED='a'\r
+&MIU_1BIT_7_INTERLEAVED='b'\r
+&MIU_2BIT_21_12_INTERLEAVED='c'\r
+&MIU_2BIT_21_7_INTERLEAVED='d'\r
+\r
+;&IS_INTERLEAVED_MAPPING=&MIU_1BIT_12_INTERLEAVED\r
+;&IS_INTERLEAVED_MAPPING=&MIU_1BIT_7_INTERLEAVED\r
+;&IS_INTERLEAVED_MAPPING=&MIU_2BIT_21_12_INTERLEAVED\r
+&IS_INTERLEAVED_MAPPING=&MIU_2BIT_21_7_INTERLEAVED\r
+\r
+&USE_PLL=1\r
+\r
+;&ARMCLK=800 ; ARMCLK=800MHz\r
+&ARMCLK=1000 ; ARMCLK=1000MHz\r
+;&ARMCLK=400 ; ARMCLK=400MHz\r
+;&ARMCLK=100 ; ARMCLK=100MHz\r
+\r
+&CLK_165_330='a'\r
+&CLK_200_400='b'\r
+&CLK_160_100_200='c'\r
+;&CLK_BUS_DMC=&CLK_160_100_200\r
+;&CLK_BUS_DMC=&CLK_165_330\r
+&CLK_BUS_DMC=&CLK_200_400\r
+;&CLK_BUS_DMC=&CLK_200_200\r
+\r
+&AP_ODT_OFF='a'\r
+&AP_ODT_ON='b'\r
+&AP_ODT=&AP_ODT_OFF\r
+\r
+;------------------------------------------------------------------------------;\r
+; Configuring JTAG interface\r
+;------------------------------------------------------------------------------;\r
+\r
+print "Reset System"\r
+\r
+;;; start debugger\r
+Symbol.Reset\r
+System.Reset\r
+System.CPU CORTEXA9MPCORESMP2\r
+System.JtagClock 12Mhz\r
+ETM.OFF\r
+System.Option ResBreak OFF\r
+System.Option EnReset OFF\r
+\r
+; TrOnChip.Reset\r
+TrOnChip.Set FIQ OFF\r
+TrOnChip.Set IRQ OFF\r
+TrOnChip.Set DABORT OFF\r
+TrOnChip.Set PABORT OFF\r
+TrOnChip.Set UNDEF OFF\r
+\r
+Sys.Config.COREBASE 0x80110000 0x80112000\r
+\r
+Sys.Mode PREPARE\r
+Wait 0.1s\r
+\r
+System.Up\r
+Wait 0.2s\r
+\r
+;Core.Select 1\r
+;Register.Set PC 0x40110000\r
+;r.s cpsr (r(cpsr)&0xffffff00)|0xd3 ; change to supervisor mode\r
+;wait 0.1s\r
+\r
+Core.Select 0\r
+;Register.Set PC 0x40110000\r
+r.s cpsr (r(cpsr)&0xffffff00)|0xd3 ; change to supervisor mode\r
+wait 0.1s\r
+\r
+;------------------------------------------------------------------------------;\r
+; Watchdog\r
+;------------------------------------------------------------------------------;\r
+\r
+print "Disable Watchdog Timer"\r
+\r
+d.s SD:0x10060000 %LE %LONG 0x00000000 ;Disable Watchdog Timer\r
+\r
+;------------------------------------------------------------------------------;\r
+; Clock Controller for Init DMC\r
+;------------------------------------------------------------------------------;\r
+\r
+d.s SD:0x10040500 %LE %LONG 0x13113113 ;CLK_DIV_DMC0 on iROM DMC=50MHz for Init DMC(LPDDR2)\r
+\r
+;------------------------------------------------------------------------------;\r
+; MIU \r
+;------------------------------------------------------------------------------;\r
+\r
+print "Set MIU"\r
+\r
+if &IS_INTERLEAVED_MAPPING==&MIU_1BIT_12_INTERLEAVED\r
+(\r
+ d.s SD:0x10600400 %LE %LONG 0x0000000c ;MIU Interleaved Config\r
+ d.s SD:0x10600c00 %LE %LONG 0x00000001 ;MIU Set Interleaved Mapping and Update\r
+)\r
+else if &IS_INTERLEAVED_MAPPING==&MIU_1BIT_7_INTERLEAVED\r
+(\r
+d.s SD:0x10600400 %LE %LONG 0x00000007 ;MIU Interleaved Config\r
+d.s SD:0x10600c00 %LE %LONG 0x00000001 ;MIU Set Interleaved Mapping and Update\r
+)\r
+else if &IS_INTERLEAVED_MAPPING==&MIU_2BIT_21_12_INTERLEAVED\r
+(\r
+d.s SD:0x10600400 %LE %LONG 0x2000150c ;MIU Interleaved Config\r
+d.s SD:0x10600c00 %LE %LONG 0x00000001 ;MIU Set Interleaved Mapping and Update\r
+)\r
+else if &IS_INTERLEAVED_MAPPING==&MIU_2BIT_21_7_INTERLEAVED\r
+(\r
+d.s SD:0x10600400 %LE %LONG 0x20001507 ;MIU Interleaved Config\r
+d.s SD:0x10600c00 %LE %LONG 0x00000001 ;MIU Set Interleaved Mapping and Update\r
+)\r
+\r
+;------------------------------------------------------------------------------;\r
+; DREX0 \r
+;------------------------------------------------------------------------------;\r
+\r
+;LPDDR2\r
+;MEM1 = 64Mbit x 32bit, 8bank = 256MB\r
+;ROW = [13:0], COL = [8:0]\r
+print "Setting DREX0 - LPDDR2"\r
+\r
+; PhyControl\r
+; ----------\r
+d.s SD:0x10400044 %LE %LONG 0xE3855503 ;PhyControl0 // disable PhyZQControl.ctrl_zq_mode_noterm and enable PhyZQControl.ctrl_zq_start\r
+\r
+d.s SD:0x10400018 %LE %LONG 0x71101008 ;PhyControl0 // PhyControl0.ctrl_force to maximum value \r
+d.s SD:0x10400018 %LE %LONG 0x7110100A ;PhyControl0 // PhyControl0.ctrl_dll_on bit-field to 1\r
+d.s SD:0x1040001C %LE %LONG 0x00000084 ;PhyControl1 // PhyControl1.ctrl_shiftc=4, PhyControl1.ctrl_offsetc=0\r
+d.s SD:0x10400018 %LE %LONG 0x71101008 ;PhyControl0 // PhyControl0.ctrl_dll_on bit-field to 0\r
+\r
+d.s SD:0x1040001C %LE %LONG 0x0000008C ;PhyControl1 // PhyControl1.fp_resync bit-field to 1\r
+d.s SD:0x1040001C %LE %LONG 0x00000084 ;PhyControl1 // PhyControl1.fp_resync bit-field to 0\r
+d.s SD:0x1040001C %LE %LONG 0x0000008C ;PhyControl1 // PhyControl1.fp_resync bit-field to 1\r
+d.s SD:0x1040001C %LE %LONG 0x00000084 ;PhyControl1 // PhyControl1.fp_resync bit-field to 0\r
+\r
+d.s SD:0x10400020 %LE %LONG 0x00000000 ;PhyControl2\r
+\r
+; ConControl\r
+; ----------\r
+d.s SD:0x10400000 %LE %LONG 0x0FFF30da\r
+; [27:16] timeout_level0\r
+; [12]=3 rd_fetch\r
+; [7:6]=3 drv_type, [5]=0 auto refresh off, [4]=1 awr_on\r
+; [3]=1 div_pipe, [2:1]=1 ACLK:MCLK=1:2\r
+\r
+; MemControl\r
+; ----------\r
+d.s SD:0x10400004 %LE %LONG 0x00202500\r
+; [22:20]=2 bl=4\r
+; [19:16]=0 1chip\r
+; [15:12]=2 mem_width=32\r
+; [11:8]=5 LPDDR2\r
+; [5] dynamic self refresh off\r
+; [4] timeout precharge off\r
+; [1] dynamic power down off\r
+; [0] dynamic clock control off\r
+\r
+; MemConfig0\r
+; ----------\r
+if &POP_TYPE==&POP_TYPE_A\r
+(\r
+d.s SD:0x10400008 %LE %LONG 0x20f01223 ;MemConfig0\r
+)\r
+else if &POP_TYPE==&POP_TYPE_B\r
+(\r
+d.s SD:0x10400008 %LE %LONG 0x20e01323 ;MemConfig0\r
+)\r
+else\r
+(\r
+print "ERROR: check POP_TYPE"\r
+enddo\r
+)\r
+\r
+; [31:24]=0x20 or 0x40 base address\r
+; [23:16]=0xe0 mask=256MB\r
+; [15:12]=0 linear map\r
+; [11:8]=2 col=9bit\r
+; [7:4]=2 row=14bit\r
+; [3:0]=3 8bank\r
+\r
+; PrechConfig\r
+; -----------\r
+d.s SD:0x10400014 %LE %LONG 0xff000000 ;PrechConfig\r
+\r
+; Timing Param @mclk=400MHz or 330MHz\r
+; -----------------------------------\r
+d.s SD:0x10400030 %LE %LONG 0x0000005D ;TimingAref 3.9us*24MHz=93(0x5d) \r
+IF &CLK_BUS_DMC==&CLK_165_330\r
+(\r
+ d.s SD:0x10400034 %LE %LONG 0x2b47654e\r
+ d.s SD:0x10400038 %LE %LONG 0x35330306\r
+ d.s SD:0x1040003C %LE %LONG 0x442f0365\r
+)\r
+ELSE\r
+(\r
+ d.s SD:0x10400034 %LE %LONG 0x34498691\r
+ d.s SD:0x10400038 %LE %LONG 0x36330306\r
+ d.s SD:0x1040003C %LE %LONG 0x50380365\r
+)\r
+\r
+; Direct Command\r
+; --------------\r
+wait 0.1s ; wait 100ns\r
+d.s SD:0x10400010 %LE %LONG 0x07000000 ;DirectCmd chip0 Deselect, NOP\r
+wait 0.1s ; wait 200us\r
+d.s SD:0x10400010 %LE %LONG 0x00071C00 ;DirectCmd Reset MR[63]\r
+wait 0.1s ; wait 20us ; // whether Device Auto-Initialization is completed or not.\r
+d.s SD:0x10400010 %LE %LONG 0x00010BFC ;DirectCmd chip0 MRS, MA10 ZQINIT\r
+wait 0.1s ; wait 1us\r
+d.s SD:0x10400010 %LE %LONG 0x00000488 ;DirectCmd chip0 MRS, MA01 nWR[7:5]='b001(tWR=3),WC[4]='b0(Wrap),BT[3]='b0(Seq),BL[2:0]='b010(BL4) \r
+d.s SD:0x10400010 %LE %LONG 0x00000810 ;DirectCmd chip0 MRS, MA02 RL=6/WL=3\r
+d.s SD:0x10400010 %LE %LONG 0x00000C08 ;DirectCmd chip0 MRS, MA03 40-ohm\r
+\r
+;------------------------------------------------------------------------------;\r
+; DREX1 \r
+;------------------------------------------------------------------------------;\r
+\r
+;LPDDR2\r
+;MEM1 = 64Mbit x 32bit, 8bank = 256MB\r
+;ROW = [13:0], COL = [8:0]\r
+print "Setting DREX0 - LPDDR2"\r
+\r
+; PhyControl\r
+; ----------\r
+d.s SD:0x10410044 %LE %LONG 0xE3855503 ;PhyControl0 // disable PhyZQControl.ctrl_zq_mode_noterm and enable PhyZQControl.ctrl_zq_start\r
+\r
+d.s SD:0x10410018 %LE %LONG 0x71101008 ;PhyControl0 // PhyControl0.ctrl_force to maximum value \r
+d.s SD:0x10410018 %LE %LONG 0x7110100A ;PhyControl0 // PhyControl0.ctrl_dll_on bit-field to 1\r
+d.s SD:0x1041001C %LE %LONG 0x00000084 ;PhyControl1 // PhyControl1.ctrl_shiftc=4, PhyControl1.ctrl_offsetc=0\r
+d.s SD:0x10410018 %LE %LONG 0x71101008 ;PhyControl0 // PhyControl0.ctrl_dll_on bit-field to 0\r
+\r
+d.s SD:0x1041001C %LE %LONG 0x0000008C ;PhyControl1 // PhyControl1.fp_resync bit-field to 1\r
+d.s SD:0x1041001C %LE %LONG 0x00000084 ;PhyControl1 // PhyControl1.fp_resync bit-field to 0\r
+d.s SD:0x1041001C %LE %LONG 0x0000008C ;PhyControl1 // PhyControl1.fp_resync bit-field to 1\r
+d.s SD:0x1041001C %LE %LONG 0x00000084 ;PhyControl1 // PhyControl1.fp_resync bit-field to 0\r
+\r
+d.s SD:0x10410020 %LE %LONG 0x00000000 ;PhyControl2\r
+\r
+; ConControl\r
+; ----------\r
+d.s SD:0x10410000 %LE %LONG 0x0FFF30da\r
+; [27:16] timeout_level0\r
+; [12]=3 rd_fetch\r
+; [7:6]=3 drv_type, [5]=0 auto refresh off, [4]=1 awr_on\r
+; [3]=1 div_pipe, [2:1]=1 ACLK:MCLK=1:2\r
+\r
+; MemControl\r
+; ----------\r
+d.s SD:0x10410004 %LE %LONG 0x00202500\r
+; [22:20]=2 bl=4\r
+; [19:16]=0 1chip\r
+; [15:12]=2 mem_width=32\r
+; [11:8]=5 LPDDR2\r
+; [5] dynamic self refresh off\r
+; [4] timeout precharge off\r
+; [1] dynamic power down off\r
+; [0] dynamic clock control off\r
+\r
+; MemConfig0\r
+; ----------\r
+if &POP_TYPE==&POP_TYPE_A\r
+(\r
+ d.s SD:0x10410008 %LE %LONG 0x20f01223 ;MemConfig0\r
+)\r
+else if &POP_TYPE==&POP_TYPE_B\r
+(\r
+ d.s SD:0x10410008 %LE %LONG 0x20e01323 ;MemConfig0 \r
+)\r
+else\r
+(\r
+ print "ERROR: check POP_TYPE";\r
+ enddo\r
+)\r
+\r
+; [31:24]=0x20 or 0x40 base address\r
+; [23:16]=0xe0 mask=256MB\r
+; [15:12]=0 linear map\r
+; [11:8]=2 col=9bit\r
+; [7:4]=2 row=14bit\r
+; [3:0]=3 8bank\r
+\r
+; PrechConfig\r
+; -----------\r
+d.s SD:0x10410014 %LE %LONG 0xff000000 ;PrechConfig\r
+\r
+; Timing Param @mclk=400MHz or 330MHz\r
+; -----------------------------------\r
+d.s SD:0x10410030 %LE %LONG 0x0000005D ;TimingAref 3.9us*24MHz=93(0x5d) \r
+IF &CLK_BUS_DMC==&CLK_165_330\r
+(\r
+ d.s SD:0x10410034 %LE %LONG 0x2b47654e\r
+ d.s SD:0x10410038 %LE %LONG 0x35330306\r
+ d.s SD:0x1041003C %LE %LONG 0x442f0365\r
+)\r
+ELSE\r
+(\r
+ d.s SD:0x10410034 %LE %LONG 0x34498691\r
+ d.s SD:0x10410038 %LE %LONG 0x36330306\r
+ d.s SD:0x1041003C %LE %LONG 0x50380365\r
+)\r
+\r
+; Direct Command\r
+; --------------\r
+wait 0.1s ; wait 100ns\r
+d.s SD:0x10410010 %LE %LONG 0x07000000 ;DirectCmd chip0 Deselect, NOP\r
+wait 0.1s ; wait 200us\r
+d.s SD:0x10410010 %LE %LONG 0x00071C00 ;DirectCmd Reset MR[63]\r
+wait 0.1s ; wait 20us ; // whether Device Auto-Initialization is completed or not.\r
+d.s SD:0x10410010 %LE %LONG 0x00010BFC ;DirectCmd chip0 MRS, MA10 ZQINIT\r
+wait 0.1s ; wait 1us\r
+d.s SD:0x10410010 %LE %LONG 0x00000488 ;DirectCmd chip0 MRS, MA01 nWR[7:5]='b001(tWR=3),WC[4]='b0(Wrap),BT[3]='b0(Seq),BL[2:0]='b010(BL4) \r
+d.s SD:0x10410010 %LE %LONG 0x00000810 ;DirectCmd chip0 MRS, MA02 RL=6/WL=3\r
+d.s SD:0x10410010 %LE %LONG 0x00000C08 ;DirectCmd chip0 MRS, MA03 40-ohm\r
+\r
+;------------------------------------------------------------------------------;\r
+; Clock Controller\r
+;------------------------------------------------------------------------------;\r
+\r
+IF &USE_PLL==1\r
+(\r
+ ; CMU_CPU MUX / DIV\r
+ d.s SD:0x10044200 %LE %LONG 0x0 ;CLK_SRC_CPU MUX_A/MPLL out => FINPLL\r
+ wait 0.1s\r
+ d.s SD:0x10044500 %LE %LONG 0x00133730 ;CLK_DIV_CPU0\r
+ d.s SD:0x10044504 %LE %LONG 0x00000003 ;CLK_DIV_CPU1\r
+\r
+ ; CMU_DMC MUX / DIV\r
+ d.s SD:0x10040200 %LE %LONG 0x10000 ;CLK_SRC_DMC MUX out => SCLK_MPLL\r
+ wait 0.1s\r
+\r
+ IF &CLK_BUS_DMC==&CLK_160_100_200\r
+ (\r
+ d.s SD:0x10040500 %LE %LONG 0x13113113 ;CLK_DIV_DMC0 ; MPLL / 4 = DMC clock\r
+ )\r
+ ELSE\r
+ (\r
+ d.s SD:0x10040500 %LE %LONG 0x13111113 ;CLK_DIV_DMC0 ; MPLL / 2 = DMC clock\r
+ )\r
+ d.s SD:0x10040504 %LE %LONG 0x01010100 ;CLK_DIV_DMC1\r
+\r
+ ; CMU_TOP MUX / DIV\r
+ d.s SD:0x1003C210 %LE %LONG 0x0 ;CLK_SRC_TOP0\r
+ d.s SD:0x1003C214 %LE %LONG 0x0 ;CLK_SRC_TOP1\r
+ wait 0.1s\r
+ d.s SD:0x1003C510 %LE %LONG 0x00015473 ;CLK_DIV_TOP\r
+\r
+ ; CMU_LEFTBUS MUX / DIV\r
+ d.s SD:0x10034200 %LE %LONG 0x0 ;CLK_SRC_LEFTBUS\r
+ wait 0.1s\r
+ d.s SD:0x10034500 %LE %LONG 0x00000013 ;CLK_DIV_LEFTBUS\r
+\r
+ ; CMU_LEFTBUS MUX / DIV\r
+ d.s SD:0x10038200 %LE %LONG 0x0 ;CLK_SRC_RIGHTBUS\r
+ wait 0.1s\r
+ d.s SD:0x10038500 %LE %LONG 0x00000013 ;CLK_DIV_RIGHTBUS\r
+\r
+ ; Set PLL locktime\r
+ d.s SD:0x10044000 %LE %LONG 0x00001C20 ;APLL_LOCK 300us\r
+ d.s SD:0x10044008 %LE %LONG 0x00001C20 ;MPLL_LOCK 300us\r
+ d.s SD:0x1003C010 %LE %LONG 0x00001C20 ;EPLL_LOCK 300us\r
+ d.s SD:0x1003C020 %LE %LONG 0x00001C20 ;VPLL_LOCK 300us\r
+\r
+ ; Set PLL P,M,S ON\r
+ d.s SD:0x10044104 %LE %LONG 0x8000001C ;APLL_CON1\r
+\r
+ IF &ARMCLK==1000\r
+ (\r
+ d.s SD:0x10044100 %LE %LONG 0x80FA0601 ;APLL_CON0 APLL=1000MHz\r
+ )\r
+ ELSE IF &ARMCLK==800\r
+ (\r
+ d.s SD:0x10044100 %LE %LONG 0x80C80601 ;APLL_CON0 APLL=800MHz\r
+ )\r
+ ELSE IF &ARMCLK==400\r
+ (\r
+ d.s SD:0x10044100 %LE %LONG 0x80C80602 ;APLL_CON0 APLL=400MHz\r
+ )\r
+ ELSE IF &ARMCLK==100\r
+ (\r
+ d.s SD:0x10044100 %LE %LONG 0x80C80604 ;APLL_CON0 APLL=100MHz\r
+ )\r
+ ELSE\r
+ (\r
+ print "check variable &ARMCLK"\r
+ sys.d\r
+ )\r
+\r
+ IF &CLK_BUS_DMC==&CLK_200_400\r
+ (\r
+ d.s SD:0x1004410C %LE %LONG 0x8000001C ;MPLL_CON1\r
+ d.s SD:0x10044108 %LE %LONG 0x80C80601 ;MPLL_CON0 MPLL=800MHz\r
+ )\r
+ ELSE IF &CLK_BUS_DMC==&CLK_165_330\r
+ (\r
+ d.s SD:0x1004410C %LE %LONG 0x8000000D ;MPLL_CON1\r
+ d.s SD:0x10044108 %LE %LONG 0x806E0401 ;MPLL_CON0 MPLL=660MHz\r
+ )\r
+ ELSE IF &CLK_BUS_DMC==&CLK_160_100_200\r
+ (\r
+ d.s SD:0x1004410C %LE %LONG 0x8000001C ;MPLL_CON1\r
+ d.s SD:0x10044108 %LE %LONG 0x80C80601 ;MPLL_CON0 MPLL=800MHz\r
+ )\r
+ ELSE\r
+ (\r
+ print "check variable &CLK_BUS_DMC"\r
+ )\r
+\r
+ d.s SD:0x1003C114 %LE %LONG 0x00000000 ;EPLL_CON1\r
+ d.s SD:0x1003C110 %LE %LONG 0x80300302 ;EPLL_CON0 EPLL=96MHz\r
+\r
+ d.s SD:0x1003C124 %LE %LONG 0x11000400 ;VPLL_CON1\r
+ d.s SD:0x1003C120 %LE %LONG 0x80350302 ;VPLL_CON0 VPLL=108MHz\r
+\r
+ wait 0.3s\r
+\r
+ d.s SD:0x10044200 %LE %LONG 0x00000101 ;CLK_SRC_CPU MUX_A/MPLL out => PLL out\r
+ d.s SD:0x1003C210 %LE %LONG 0x00000110 ;CLK_SRC_TOP MUX_E/VPLL out => PLL out\r
+ wait 0.1s\r
+ print "pll enable"\r
+)\r
+\r
+; Clock out setting\r
+; for monitoring APLL\r
+d.s SD:0x10020A00 %LE %LONG 0x00000401 ;PMU_DEBUG ( CLKOUT = CMU_CPU )\r
+d.s SD:0x10044A00 %LE %LONG 0x00000904 ;CLKOUT_CMU_CPU ( CMU_CLKOUT = ARMCLK/2 )\r
+\r
+; for monitoring MPLL,EPLL,VPLL\r
+;d.s SD:0x10020A00 %LE %LONG 0x00000101 ;PMU_DEBUG ( CLKOUT = CMU_TOP )\r
+;d.s SD:0x1003CA00 %LE %LONG 0x0000090C ;CLKOUT_CMU_TOP ( CMU_CLKOUT = ACLK_200 )\r
+;d.s SD:0x1003CA00 %LE %LONG 0x00000900 ;CLKOUT_CMU_TOP ( CMU_CLKOUT = EPLLOUT )\r
+;d.s SD:0x1003CA00 %LE %LONG 0x00000901 ;CLKOUT_CMU_TOP ( CMU_CLKOUT = VPLLOUT )\r
+print "Clock Initialization done..."\r
+\r
+;------------------------------------------------------------------------------;\r
+; DREX0, DREX1\r
+;------------------------------------------------------------------------------;\r
+\r
+; ConControl\r
+; ----------\r
+\r
+if &DMC_DLL_ON==1\r
+(\r
+ d.s SD:0x10400018 %LE %LONG 0x6910100A ;PhyControl0 DLL on\r
+ if &AP_ODT==&AP_ODT_OFF\r
+ (\r
+ d.s SD:0x1040001C %LE %LONG 0x00000084 ;PhyControl1 // PhyControl1.ctrl_shiftc=4, PhyControl1.ctrl_offsetc=0\r
+ )\r
+ else\r
+ (\r
+ d.s SD:0x1040001C %LE %LONG 0xe0000084 ;PhyControl1 // PhyControl1.ctrl_shiftc=4, PhyControl1.ctrl_offsetc=0\r
+ )\r
+ d.s SD:0x10400018 %LE %LONG 0x6910100B ;PhyControl0 DLLÀ» start ½ÃÅ´\r
+ wait 0.2s ; // Check whether PHY DLL is locked\r
+ if &AP_ODT==&AP_ODT_OFF\r
+ (\r
+ d.s SD:0x1040001C %LE %LONG 0x0000008C ;PhyControl1 // PhyControl1.fp_resync bit-field to 1\r
+ d.s SD:0x1040001C %LE %LONG 0x00000084 ;PhyControl1 // PhyControl1.fp_resync bit-field to 0\r
+ )\r
+ else\r
+ (\r
+ d.s SD:0x1040001C %LE %LONG 0xe000008C ;PhyControl1 // PhyControl1.fp_resync bit-field to 1\r
+ d.s SD:0x1040001C %LE %LONG 0xe0000084 ;PhyControl1 // PhyControl1.fp_resync bit-field to 0\r
+ )\r
+)\r
+wait 0.2s ; // Check whether PHY DLL is locked\r
+\r
+if &DMC_DLL_ON==1\r
+(\r
+ d.s SD:0x10410018 %LE %LONG 0xe910100A ;PhyControl0 DLL on\r
+ if &AP_ODT==&AP_ODT_OFF\r
+ (\r
+ d.s SD:0x1041001C %LE %LONG 0x00000084 ;PhyControl1 // PhyControl1.ctrl_shiftc=4, PhyControl1.ctrl_offsetc=0\r
+ )\r
+ else\r
+ (\r
+ d.s SD:0x1041001C %LE %LONG 0xe0000084 ;PhyControl1 // PhyControl1.ctrl_shiftc=4, PhyControl1.ctrl_offsetc=0\r
+ )\r
+ d.s SD:0x10410018 %LE %LONG 0xe910100B ;PhyControl0 DLLÀ» start ½ÃÅ´\r
+ wait 0.2s ; // Check whether PHY DLL is locked\r
+ if &AP_ODT==&AP_ODT_OFF\r
+ (\r
+ d.s SD:0x1041001C %LE %LONG 0x0000008C ;PhyControl1 // PhyControl1.fp_resync bit-field to 1\r
+ d.s SD:0x1041001C %LE %LONG 0x00000084 ;PhyControl1 // PhyControl1.fp_resync bit-field to 0\r
+ )\r
+ else\r
+ (\r
+ d.s SD:0x1041001C %LE %LONG 0xe000008C ;PhyControl1 // PhyControl1.fp_resync bit-field to 1\r
+ d.s SD:0x1041001C %LE %LONG 0xe0000084 ;PhyControl1 // PhyControl1.fp_resync bit-field to 0\r
+ )\r
+)\r
+wait 0.2s ; // Check whether PHY DLL is locked\r
+\r
+d.s SD:0x10400000 %LE %LONG 0x0FFF30fa\r
+; [27:16] timeout_level0\r
+; [12]=3 rd_fetch\r
+; [7:6]=3 drv_type, [5]=1 auto refresh on, [4]=1 awr_on\r
+; [3]=1 div_pipe, [2:1]=1 ACLK:MCLK=1:2\r
+\r
+d.s SD:0x10410000 %LE %LONG 0x0FFF30fa\r
+; [27:16] timeout_level0\r
+; [12]=3 rd_fetch\r
+; [7:6]=3 drv_type, [5]=1 auto refresh on, [4]=1 awr_on\r
+; [3]=1 div_pipe, [2:1]=1 ACLK:MCLK=1:2\r
+\r
+; MemControl\r
+; ----------\r
+d.s SD:0x10400004 %LE %LONG 0x00202537\r
+; [22:20]=2 bl=4\r
+; [19:16]=0 1chip\r
+; [15:12]=2 mem_width=32\r
+; [11:8]=5 LPDDR2\r
+; [5] dynamic self refresh on\r
+; [4] timeout precharge on\r
+; [1] dynamic power down on\r
+; [0] dynamic clock control on\r
+print "DRAM Initialization done..."\r
+\r
+; MemControl\r
+; ----------\r
+d.s SD:0x10410004 %LE %LONG 0x00202537\r
+; [22:20]=2 bl=4\r
+; [19:16]=0 1chip\r
+; [15:12]=2 mem_width=32\r
+; [11:8]=5 LPDDR2\r
+; [5] dynamic self refresh on\r
+; [4] timeout precharge on\r
+; [1] dynamic power down on\r
+; [0] dynamic clock control on\r
+print "DRAM Initialization done..."\r
+\r
+;------------------------------------------------------------------------------;\r
+; Load IMAGE ;\r
+;------------------------------------------------------------------------------;\r
+\r
+print "Loading ..."\r
+\r
+&UBOOT_CODE="y:\u-boot-merge\u-boot" \r
+&UBOOT_IMAGE="y:\u-boot-merge\u-boot.bin"\r
+&ONENAND_IPL="y:\u-boot-merge\s-boot-onenand.bin"\r
+;&ONENAND_IPL_IMAGE="y:\u-boot-merge\onenand_ipl\onenand-ipl.bin"\r
+;&ONENAND_CODE="y:\u-boot-merge\onenand_ipl\onenand-ipl"\r
+\r
+;&IPL_LOAD_ADDRESS=0x02020000\r
+&UBOOT_EXECUTED_ADDRESS=0x44800000\r
+\r
+Data.LOAD.Binary &UBOOT_IMAGE &UBOOT_EXECUTED_ADDRESS\r
+Data.Load.Elf &UBOOT_CODE /ABSLIFETIMES /gnu /nocode /STRIPPART 6\r
+\r
+Data.load.binary &ONENAND_IPL 0x42008000\r
+;Data.Load.Elf &ONENAND_CODE /ABSLIFETIMES /gnu /nocode /STRIPPART 7\r
+\r
+; Break & Run\r
+Register.Set pc &UBOOT_EXECUTED_ADDRESS\r
+go\r
+\r
+data.list\r
--- /dev/null
+/*
+ * Lowlevel setup for universal board based on S5PC210
+ *
+ * Copyright (C) 2010 Samsung Electronics
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/power.h>
+
+/*
+ * Register usages:
+ *
+ * r5 has zero always
+ * r7 has GPIO part1 base 0x11400000
+ * r6 has GPIO part2 base 0x11000000
+ */
+
+ .globl lowlevel_init
+lowlevel_init:
+ mov r11, lr
+
+ /* r5 has always zero */
+ mov r5, #0
+
+ ldr r7, =S5PC210_GPIO_PART1_BASE
+ ldr r6, =S5PC210_GPIO_PART2_BASE
+
+ /* System Timer */
+ ldr r0, =S5PC210_SYSTIMER_BASE
+ ldr r1, =0x5000
+ str r1, [r0, #0x0]
+ ldr r1, =0xffffffff
+ str r1, [r0, #0x8]
+ ldr r1, =0x49
+ str r1, [r0, #0x4]
+
+ /* Workaround: PMIC manual reset */
+ /* nPOWER: XEINT_23: GPX2[7] */
+ add r0, r6, #0xC40 @ S5PC210_GPIO_X2_OFFSET
+ ldr r1, [r0, #0x0]
+ bic r1, r1, #(0xf << 28) @ 28 = 7 * 4-bit
+ orr r1, r1, #(0x1 << 28) @ Output
+ str r1, [r0, #0x0]
+
+ ldr r1, [r0, #0x4]
+ orr r1, r1, #(1 << 7) @ 7 = 7 * 1-bit
+ str r1, [r0, #0x4]
+
+ /* init system clock */
+ bl system_clock_init
+
+ /* Disable Watchdog */
+ ldr r0, =S5PC210_WATCHDOG_BASE @0x10060000
+ str r5, [r0]
+
+ /* UART */
+ bl uart_asm_init
+
+ /* PMU init */
+ bl system_power_init
+
+ bl tzpc_init
+
+#if 0
+ /* Enable NEON. Don't change the register r0 */
+ ldr r0, =0x00F00000
+ mcr p15, 0, r0, c1, c0, 2
+ ldr r0, =0x40000000
+ .word 0xeee80a10 /* VMSR_FPSCR_r0 */
+ .word 0xeef80a10 /* VMRS_r0_FPSCR */
+#endif
+
+ mov lr, r11
+ mov pc, lr
+ nop
+ nop
+ nop
+
+/*
+ * uart_asm_init: Initialize UART's pins
+ */
+uart_asm_init:
+ /*
+ * setup UART0-UART4 GPIOs (part1)
+ * GPA1CON[3] = I2C_3_SCL (3)
+ * GPA1CON[2] = I2C_3_SDA (3)
+ */
+ mov r0, r7
+ ldr r1, =0x22222222
+ str r1, [r0, #0x00] @ S5PC210_GPIO_A0_OFFSET
+ ldr r1, =0x00223322
+ str r1, [r0, #0x20] @ S5PC210_GPIO_A1_OFFSET
+
+ /* UART_SEL GPY4[7] (part2) at S5PC210 */
+ add r0, r6, #0x1A0 @ S5PC210_GPIO_Y4_OFFSET
+ ldr r1, [r0, #0x0]
+ bic r1, r1, #(0xf << 28) @ 28 = 7 * 4-bit
+ orr r1, r1, #(0x1 << 28)
+ str r1, [r0, #0x0]
+
+ ldr r1, [r0, #0x8]
+ bic r1, r1, #(0x3 << 14) @ 14 = 7 * 2-bit
+ orr r1, r1, #(0x3 << 14) @ Pull-up enabled
+ str r1, [r0, #0x8]
+
+ ldr r1, [r0, #0x4]
+ orr r1, r1, #(1 << 7) @ 7 = 7 * 1-bit
+ str r1, [r0, #0x4]
+
+#if 0
+ ldr r0, =0x13800000 @ S5PC210_PA_UART
+ orr r0, r0, #0x20000 @ UART2
+ mov r1, #0x3
+ str r1, [r0, #0x000] @ ULCON
+ ldr r1, =0x3c5
+ str r1, [r0, #0x004] @ UCON
+ mov r1, #0x2B
+ str r1, [r0, #0x028] @ UBRDIV
+ mov r1, #0xC
+ str r1, [r0, #0x02C] @ UFRACVAL
+
+ mov r2, #'W'
+ strb r2, [r0, #0x020] @ UTXH
+1001:
+ ldrb r3, [r0, #0x010] @ UTRSTAT
+ tst r3, #(1 << 2)
+ beq 1001b
+#endif
+
+ mov pc, lr
+ nop
+ nop
+ nop
+
+system_clock_init:
+ ldr r0, =S5PC210_CLOCK_BASE
+
+ /* APLL(1), MPLL(1), CORE(0), HPM(0) */
+ ldr r1, =0x0101
+ ldr r2, =0x14200 @ CLK_SRC_CPU
+ str r1, [r0, r2]
+
+ /* wait ?us */
+ mov r1, #0x10000
+1: subs r1, r1, #1
+ bne 1b
+
+ /*
+ * CLK_SRC_TOP0
+ * MUX_ONENAND_SEL[28] 0: DOUT133, 1: DOUT166
+ * MUX_VPLL_SEL[8] 0: FINPLL, 1: FOUTVPLL
+ * MUX_EPLL_SEL[4] 0: FINPLL, 1: FOUTEPLL
+ */
+ ldr r1, =0x10000110
+ ldr r2, =0x0C210 @ CLK_SRC_TOP
+ str r1, [r0, r2]
+
+ /* SATA: SCLKMPLL(0), MMC[0:4]: SCLKMPLL(6) */
+ ldr r1, =0x0066666
+ ldr r2, =0x0C240 @ CLK_SRC_FSYS
+ str r1, [r0, r2]
+ /* UART[0:5], PWM: SCLKMPLL(6) */
+ ldr r1, =0x6666666
+ ldr r2, =0x0C250 @ CLK_SRC_PERIL0_OFFSET
+ str r1, [r0, r2]
+
+ /* CPU0: CORE, COREM0, COREM1, PERI, ATB, PCLK_DBG, APLL */
+ ldr r1, =0x0133730
+ ldr r2, =0x14500 @ CLK_DIV_CPU0
+ str r1, [r0, r2]
+ /* CPU1: COPY, HPM */
+ ldr r1, =0x03
+ ldr r2, =0x14504 @ CLK_DIV_CPU1
+ str r1, [r0, r2]
+ /* DMC0: ACP, ACP_PCLK, DPHY, DMC, DMCD, DMCP, COPY2 CORE_TIMER */
+ ldr r1, =0x13111113
+ ldr r2, =0x10500 @ CLK_DIV_DMC0
+ str r1, [r0, r2]
+ /* DMC1: PWI, DVSEM, DPM */
+ ldr r1, =0x01010100
+ ldr r2, =0x10504 @ CLK_DIV_DMC1
+ str r1, [r0, r2]
+ /* LEFTBUS: GDL, GPL */
+ ldr r1, =0x13
+ ldr r2, =0x04500 @ CLK_DIV_LEFTBUS
+ str r1, [r0, r2]
+ /* RIGHHTBUS: GDR, GPR */
+ ldr r1, =0x13
+ ldr r2, =0x08500 @ CLK_DIV_RIGHTBUS
+ str r1, [r0, r2]
+ /*
+ * CLK_DIV_TOP
+ * ONENAND_RATIOD[18:16]: 0 SCLK_ONENAND = MOUTONENAND / (n + 1)
+ * ACLK_200, ACLK_100, ACLK_160, ACLK_133,
+ */
+ ldr r1, =0x00005473
+ ldr r2, =0x0C510 @ CLK_DIV_TOP
+ str r1, [r0, r2]
+ /* MMC[0:1] */
+ ldr r1, =0x000f000f /* 800(MPLL) / (15 + 1) */
+ ldr r2, =0x0C544 @ CLK_DIV_FSYS1
+ str r1, [r0, r2]
+ /* MMC[2:3] */
+ ldr r1, =0x000f000f /* 800(MPLL) / (15 + 1) */
+ ldr r2, =0x0C548 @ CLK_DIV_FSYS2
+ str r1, [r0, r2]
+ /* MMC4 */
+ ldr r1, =0x000f /* 800(MPLL) / (15 + 1) */
+ ldr r2, =0x0C54C @ CLK_DIV_FSYS3
+ str r1, [r0, r2]
+ /* UART[0:5] */
+ ldr r1, =0x774777
+ ldr r2, =0x0C550 @ CLK_DIV_PERIL0
+ str r1, [r0, r2]
+ /* SLIMBUS: ???, PWM */
+ ldr r1, =0x8
+ ldr r2, =0x0C55C @ CLK_DIV_PERIL3
+ str r1, [r0, r2]
+
+ /* PLL Setting */
+ ldr r1, =0x1C20
+ ldr r2, =0x14000 @ APLL_LOCK
+ str r1, [r0, r2]
+ ldr r2, =0x14008 @ MPLL_LOCK
+ str r1, [r0, r2]
+ ldr r2, =0x0C010 @ EPLL_LOCK
+ str r1, [r0, r2]
+ ldr r2, =0x0C020 @ VPLL_LOCK
+ str r1, [r0, r2]
+
+ /* APLL */
+ ldr r1, =0x8000001c
+ ldr r2, =0x14104 @ APLL_CON1
+ str r1, [r0, r2]
+ ldr r1, =0x80c80601 @ 800MHz
+ ldr r2, =0x14100 @ APLL_CON0
+ str r1, [r0, r2]
+ /* MPLL */
+ ldr r1, =0x8000001C
+ ldr r2, =0x1410C @ MPLL_CON1
+ str r1, [r0, r2]
+ ldr r1, =0x80c80601 @ 800MHz
+ ldr r2, =0x14108 @ MPLL_CON0
+ str r1, [r0, r2]
+ /* EPLL */
+ ldr r1, =0x0
+ ldr r2, =0x0C114 @ EPLL_CON1
+ str r1, [r0, r2]
+ ldr r1, =0x80300302 @ 96MHz
+ ldr r2, =0x0C110 @ EPLL_CON0
+ str r1, [r0, r2]
+ /* VPLL */
+ ldr r1, =0x11000400
+ ldr r2, =0x0C124 @ VPLL_CON1
+ str r1, [r0, r2]
+ ldr r1, =0x80350302 @ 108MHz
+ ldr r2, =0x0C120 @ VPLL_CON0
+ str r1, [r0, r2]
+
+ /*
+ * SMMUJPEG[11], JPEG[6], CSIS1[5] : 0111 1001
+ * Turn off all
+ */
+ ldr r1, =0xFFF80000
+ ldr r2, =0x0C920 @ CLK_GATE_IP_CAM
+ str r1, [r0, r2]
+
+ /* Turn off all */
+ ldr r1, =0xFFFFFFC0
+ ldr r2, =0x0C924 @ CLK_GATE_IP_VP
+ str r1, [r0, r2]
+
+ /* Turn off all */
+ ldr r1, =0xFFFFFFE0
+ ldr r2, =0x0C928 @ CLK_GATE_IP_MFC
+ str r1, [r0, r2]
+
+ /* Turn off all */
+ ldr r1, =0xFFFFFFFC
+ ldr r2, =0x0C92C @ CLK_GATE_IP_G3D
+ str r1, [r0, r2]
+
+ /* Turn off all */
+ ldr r1, =0xFFFFFC00
+ ldr r2, =0x0C930 @ CLK_GATE_IP_IMAGE
+ str r1, [r0, r2]
+
+ /* DSIM0[3], MDNIE0[2], MIE0[1] : 0001 */
+ ldr r1, =0xFFFFFFF1
+ ldr r2, =0x0C934 @ CLK_GATE_IP_LCD0
+ str r1, [r0, r2]
+
+ /* Turn off all */
+ ldr r1, =0xFFFFFFC0
+ ldr r2, =0x0C938 @ CLK_GATE_IP_LCD1
+ str r1, [r0, r2]
+
+ /*
+ * SMMUPCIE[18], NFCON[16] : 1111 1010
+ * PCIE[14], SATA[10], SDMMC43[9:8] : 1011 1000
+ * SDMMC1[6], TSI[4], SATAPHY[3], PCIEPHY[2] : 1010 0011
+ */
+ ldr r1, =0xFFFAB8A3
+ ldr r2, =0x0C940 @ CLK_GATE_IP_FSYS
+ str r1, [r0, r2]
+
+ /* Turn off all */
+ ldr r1, =0xFFFFFFFC
+ ldr r2, =0x0C94C @ CLK_GATE_IP_GPS
+ str r1, [r0, r2]
+
+ /*
+ * AC97[27], SPDIF[26], SLIMBUS[25] : 1111 0001
+ * I2C2[8] : 1111 1110
+ */
+ ldr r1, =0xF1FFFEFF
+ ldr r2, =0x0C950 @ CLK_GATE_IP_PERIL
+ str r1, [r0, r2]
+
+ /*
+ * KEYIF[16] : 1111 1110
+ */
+ ldr r1, =0xFFFEFFFF
+ ldr r2, =0x0C960 @ CLK_GATE_IP_PERIR
+ str r1, [r0, r2]
+
+ /* LCD1[5], G3D[3], MFC[2], TV[1] : 1101 0001 */
+ ldr r1, =0xFFFFFFD1
+ ldr r2, =0x0C970 @ CLK_GATE_BLOCK
+ str r1, [r0, r2]
+ mov pc, lr
+ nop
+ nop
+ nop
+
+system_power_init:
+ ldr r0, =S5PC210_POWER_BASE @ 0x10020000
+
+ ldr r2, =0x330C @ PS_HOLD_CONTROL
+ ldr r1, [r0, r2]
+ orr r1, r1, #(0x3 << 8) @ Data High, Output En
+ str r1, [r0, r2]
+
+ /* Power Down */
+ add r2, r0, #0x3000
+ @str r5, [r2, #0xC00] @ CAM_CONFIGURATION
+ str r5, [r2, #0xC20] @ TV_CONFIGURATION
+ str r5, [r2, #0xC40] @ MFC_CONFIGURATION
+ str r5, [r2, #0xC60] @ G3D_CONFIGURATION
+ str r5, [r2, #0xCA0] @ LCD1_CONFIGURATION
+ /* FIXME Don't turn off MAUDIO why??? */
+ @str r5, [r2, #0xCC0] @ MAUDIO_CONFIGURATION
+ str r5, [r2, #0xCE0] @ GPS_CONFIGURATION
+
+ mov pc, lr
+ nop
+ nop
+ nop
+
+tzpc_init:
+ ldr r0, =0x10110000
+ mov r1, #0x0
+ str r1, [r0]
+ mov r1, #0xff
+ str r1, [r0, #0x0804]
+ str r1, [r0, #0x0810]
+ str r1, [r0, #0x081C]
+ str r1, [r0, #0x0828]
+
+ ldr r0, =0x10120000
+ mov r1, #0x0
+ str r1, [r0]
+ mov r1, #0xff
+ str r1, [r0, #0x0804]
+ str r1, [r0, #0x0810]
+ str r1, [r0, #0x081C]
+ str r1, [r0, #0x0828]
+
+ ldr r0, =0x10130000
+ mov r1, #0x0
+ str r1, [r0]
+ mov r1, #0xff
+ str r1, [r0, #0x0804]
+ str r1, [r0, #0x0810]
+ str r1, [r0, #0x081C]
+ str r1, [r0, #0x0828]
+
+ ldr r0, =0x10140000
+ mov r1, #0x0
+ str r1, [r0]
+ mov r1, #0xff
+ str r1, [r0, #0x0804]
+ str r1, [r0, #0x0810]
+ str r1, [r0, #0x081C]
+ str r1, [r0, #0x0828]
+
+ ldr r0, =0x10150000
+ mov r1, #0x0
+ str r1, [r0]
+ mov r1, #0xff
+ str r1, [r0, #0x0804]
+ str r1, [r0, #0x0810]
+ str r1, [r0, #0x081C]
+ str r1, [r0, #0x0828]
+
+ mov pc, lr
--- /dev/null
+/*
+ * Copyright (C) 2011 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <lcd.h>
+#include <spi.h>
+#include <asm/io.h>
+#include <asm/arch/adc.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mmc.h>
+#include <asm/arch/power.h>
+#include <asm/arch/clk.h>
+#include <ramoops.h>
+#include <info_action.h>
+#include <max8998.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct s5pc210_gpio_part1 *gpio1;
+static struct s5pc210_gpio_part2 *gpio2;
+
+static unsigned int battery_soc;
+static unsigned int board_rev;
+
+u32 get_board_rev(void)
+{
+ return board_rev;
+}
+
+static int get_hwrev(void)
+{
+ return board_rev & 0xFF;
+}
+
+enum {
+ I2C_0, I2C_1, I2C_2, I2C_3,
+ I2C_4, I2C_5, I2C_6, I2C_7,
+ I2C_8, I2C_9, I2C_10, I2C_11,
+ I2C_12, I2C_13, I2C_NUM,
+};
+
+/* i2c0 (CAM) SDA: GPD1[0] SCL: GPD1[1] */
+static struct i2c_gpio_bus_data i2c_0 = {
+ .sda_pin = 0,
+ .scl_pin = 1,
+};
+
+/* i2c1 (Gryo) SDA: GPD1[2] SCL: GPD1[3] */
+static struct i2c_gpio_bus_data i2c_1 = {
+ .sda_pin = 2,
+ .scl_pin = 3,
+};
+
+/* i2c3 (TSP) SDA: GPA1[2] SCL: GPA1[3] */
+static struct i2c_gpio_bus_data i2c_3 = {
+ .sda_pin = 2,
+ .scl_pin = 3,
+};
+
+/* i2c4 SDA: GPB[2] SCL: GPB[3] */
+static struct i2c_gpio_bus_data i2c_4 = {
+ .sda_pin = 2,
+ .scl_pin = 3,
+};
+
+/* i2c5 (PMIC) SDA: GPB[6] SCL: GPB[7] */
+static struct i2c_gpio_bus_data i2c_5 = {
+ .sda_pin = 6,
+ .scl_pin = 7,
+};
+
+/* i2c6 (CODEC) SDA: GPC1[3] SCL: GPC1[4] */
+static struct i2c_gpio_bus_data i2c_6 = {
+ .sda_pin = 3,
+ .scl_pin = 4,
+};
+
+/* i2c7 SDA: GPD0[2] SCL: GPD0[3] */
+static struct i2c_gpio_bus_data i2c_7 = {
+ .sda_pin = 2,
+ .scl_pin = 3,
+};
+
+/* i2c9 SDA: SPY4[0] SCL: SPY4[1] */
+static struct i2c_gpio_bus_data i2c_9 = {
+ .sda_pin = 0,
+ .scl_pin = 1,
+};
+
+/* i2c10 SDA: SPE1[0] SCL: SPE1[1] */
+static struct i2c_gpio_bus_data i2c_10 = {
+ .sda_pin = 0,
+ .scl_pin = 1,
+};
+
+/* i2c12 SDA: SPE4[0] SCL: SPE4[1] */
+static struct i2c_gpio_bus_data i2c_12 = {
+ .sda_pin = 0,
+ .scl_pin = 1,
+};
+
+/* i2c13 SDA: SPE4[2] SCL: SPE4[3] */
+static struct i2c_gpio_bus_data i2c_13 = {
+ .sda_pin = 2,
+ .scl_pin = 3,
+};
+
+static struct i2c_gpio_bus i2c_gpio[I2C_NUM];
+
+static void check_battery(int mode);
+static void init_pmic_lp3974(void);
+static void init_pmic_max8952(void);
+
+void i2c_init_board(void)
+{
+ gpio1 = (struct s5pc210_gpio_part1 *) S5PC210_GPIO_PART1_BASE;
+ gpio2 = (struct s5pc210_gpio_part2 *) S5PC210_GPIO_PART2_BASE;
+
+ i2c_gpio[I2C_0].bus = &i2c_0;
+ i2c_gpio[I2C_1].bus = &i2c_1;
+ i2c_gpio[I2C_2].bus = NULL;
+ i2c_gpio[I2C_3].bus = &i2c_3;
+ i2c_gpio[I2C_4].bus = &i2c_4;
+ i2c_gpio[I2C_5].bus = &i2c_5;
+ i2c_gpio[I2C_6].bus = &i2c_6;
+ i2c_gpio[I2C_7].bus = &i2c_7;
+ i2c_gpio[I2C_8].bus = NULL;
+ i2c_gpio[I2C_9].bus = &i2c_9;
+ i2c_gpio[I2C_10].bus = &i2c_10;
+ i2c_gpio[I2C_11].bus = NULL;
+ i2c_gpio[I2C_12].bus = &i2c_12;
+ i2c_gpio[I2C_13].bus = &i2c_13;
+
+ i2c_gpio[I2C_0].bus->gpio_base = (unsigned int)&gpio1->d1;
+ i2c_gpio[I2C_1].bus->gpio_base = (unsigned int)&gpio1->d1;
+ i2c_gpio[I2C_3].bus->gpio_base = (unsigned int)&gpio1->a1;
+ i2c_gpio[I2C_4].bus->gpio_base = (unsigned int)&gpio1->b;
+ i2c_gpio[I2C_5].bus->gpio_base = (unsigned int)&gpio1->b;
+ i2c_gpio[I2C_6].bus->gpio_base = (unsigned int)&gpio1->c1;
+ i2c_gpio[I2C_7].bus->gpio_base = (unsigned int)&gpio1->d0;
+ i2c_gpio[I2C_9].bus->gpio_base = (unsigned int)&gpio2->y4;
+ i2c_gpio[I2C_10].bus->gpio_base = (unsigned int)&gpio1->e1;
+ i2c_gpio[I2C_12].bus->gpio_base = (unsigned int)&gpio1->e4;
+ i2c_gpio[I2C_13].bus->gpio_base = (unsigned int)&gpio1->e4;
+
+ i2c_gpio_init(i2c_gpio, I2C_NUM, I2C_5);
+}
+
+static void check_hw_revision(void);
+
+int board_init(void)
+{
+ gpio1 = (struct s5pc210_gpio_part1 *) S5PC210_GPIO_PART1_BASE;
+ gpio2 = (struct s5pc210_gpio_part2 *) S5PC210_GPIO_PART2_BASE;
+
+ gd->bd->bi_arch_number = MACH_TYPE;
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ check_hw_revision();
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE;
+
+ /* Early init for i2c devices - Where these funcions should go?? */
+
+ /* Reset on max17040 */
+ check_battery(1);
+
+ /* pmic init */
+ init_pmic_lp3974();
+ init_pmic_max8952();
+
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+ gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+ gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+
+ gd->ram_size = gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size;
+}
+
+static void check_auto_burn(void)
+{
+ unsigned int magic_base = CONFIG_SYS_SDRAM_BASE + 0x02000000;
+ unsigned int count = 0;
+ char buf[64];
+
+ /* OneNAND */
+ if (readl(magic_base) == 0x426f6f74) { /* ASICC: Boot */
+ puts("Auto buring bootloader\n");
+ count += sprintf(buf + count, "run updateb; ");
+ }
+ /* MMC */
+ if (readl(magic_base) == 0x654D4D43) { /* ASICC: eMMC */
+ puts("Auto buring bootloader (eMMC)\n");
+ count += sprintf(buf + count, "run updatemmc; ");
+ }
+ if (readl(magic_base + 0x4) == 0x4b65726e) { /* ASICC: Kern */
+ puts("Auto buring kernel\n");
+ count += sprintf(buf + count, "run updatek; ");
+ }
+ /* Backup u-boot in eMMC */
+ if (readl(magic_base + 0x8) == 0x4261636B) { /* ASICC: Back */
+ puts("Auto buring u-boot image (boot partition2 in eMMC)\n");
+ count += sprintf(buf + count, "run updatebackup; ");
+ }
+
+ if (count) {
+ count += sprintf(buf + count, "reset");
+ setenv("bootcmd", buf);
+ }
+
+ /* Clear the magic value */
+ memset((void *)magic_base, 0, 2);
+}
+
+static void check_battery(int mode)
+{
+ unsigned char val[2];
+ unsigned char addr = 0x36; /* max17040 fuel gauge */
+
+ i2c_set_bus_num(I2C_9);
+
+ if (i2c_probe(addr)) {
+ puts("Can't found max17042 fuel gauge\n");
+ return;
+ }
+
+ /* mode 0: check mode / 1: enable mode */
+ if (mode) {
+ val[0] = 0x40;
+ val[1] = 0x00;
+ i2c_write(addr, 0xfe, 1, val, 2);
+ } else {
+ i2c_read(addr, 0x04, 1, val, 1);
+ printf("battery:\t%d%%\n", val[0]);
+ battery_soc = val[0];
+ }
+}
+
+#define LP3974_REG_IRQ1 0x00
+#define LP3974_REG_IRQ2 0x01
+#define LP3974_REG_IRQ3 0x02
+#define LP3974_REG_ONOFF1 0x11
+#define LP3974_REG_ONOFF2 0x12
+#define LP3974_REG_ONOFF3 0x13
+#define LP3974_REG_ONOFF4 0x14
+#define LP3974_REG_LDO7 0x21
+#define LP3974_REG_LDO17 0x29
+#define LP3974_REG_UVLO 0xB9
+#define LP3974_REG_MODCHG 0xEF
+/* ONOFF1 */
+#define LP3974_LDO3 (1 << 2)
+/* ONOFF2 */
+#define LP3974_LDO6 (1 << 7)
+#define LP3974_LDO7 (1 << 6)
+#define LP3974_LDO8 (1 << 5)
+#define LP3974_LDO9 (1 << 4)
+#define LP3974_LDO10 (1 << 3)
+#define LP3974_LDO11 (1 << 2)
+#define LP3974_LDO12 (1 << 1)
+#define LP3974_LDO13 (1 << 0)
+/* ONOFF3 */
+#define LP3974_LDO14 (1 << 7)
+#define LP3974_LDO15 (1 << 6)
+#define LP3974_LDO16 (1 << 5)
+#define LP3974_LDO17 (1 << 4)
+
+static int lp3974_probe(void)
+{
+ unsigned char addr = 0xCC >> 1;
+
+ i2c_set_bus_num(I2C_5);
+
+ if (i2c_probe(addr)) {
+ puts("Can't found lp3974\n");
+ return 1;
+ }
+
+ return 0;
+}
+
+static int max8952_probe(void)
+{
+ unsigned char addr = 0xC0 >> 1;
+
+ i2c_set_bus_num(I2C_5);
+
+ if (i2c_probe(addr)) {
+ puts("Cannot find MAX8952\n");
+ return 1;
+ }
+
+ return 0;
+}
+
+static void init_pmic_lp3974(void)
+{
+ unsigned char addr;
+ unsigned char val[2];
+
+ addr = 0xCC >> 1; /* LP3974 */
+ if (lp3974_probe())
+ return;
+
+ /* LDO2 1.2V LDO3 1.1V */
+ val[0] = 0x86; /* (((1200 - 800) / 50) << 4) | (((1100 - 800) / 50)) */
+ i2c_write(addr, 0x1D, 1, val, 1);
+
+ /* LDO4 3.3V */
+ val[0] = 0x11; /* (3300 - 1600) / 100; */
+ i2c_write(addr, 0x1E, 1, val, 1);
+
+ /* LDO5 2.8V */
+ val[0] = 0x0c; /* (2800 - 1600) / 100; */
+ i2c_write(addr, 0x1F, 1, val, 1);
+
+ /* LDO6 not used: minimum */
+ val[0] = 0;
+ i2c_write(addr, 0x20, 1, val, 1);
+
+ /* LDO7 1.8V */
+ val[0] = 0x02; /* (1800 - 1600) / 100; */
+ i2c_write(addr, 0x21, 1, val, 1);
+
+ /* LDO8 3.3V LDO9 2.8V*/
+ val[0] = 0x30; /* (((3300 - 3000) / 100) << 4) | (((2800 - 2800) / 100) << 0); */
+ i2c_write(addr, 0x22, 1, val, 1);
+
+ /* LDO10 1.1V LDO11 3.3V */
+ val[0] = 0x71; /* (((1100 - 950) / 50) << 5) | (((3300 - 1600) / 100) << 0); */
+ i2c_write(addr, 0x23, 1, val, 1);
+
+ /* LDO12 2.8V */
+ val[0] = 0x14; /* (2800 - 1200) / 100 + 4; */
+ i2c_write(addr, 0x24, 1, val, 1);
+
+ /* LDO13 1.2V */
+ val[0] = 0x4; /* (1200 - 1200) / 100 + 4; */
+ i2c_write(addr, 0x25, 1, val, 1);
+
+ /* LDO14 1.8V */
+ val[0] = 0x6; /* (1800 - 1200) / 100; */
+ i2c_write(addr, 0x26, 1, val, 1);
+
+ /* LDO15 1.2V */
+ val[0] = 0; /* (1200 - 1200) / 100; */
+ i2c_write(addr, 0x27, 1, val, 1);
+
+ /* LDO16 2.8V */
+ val[0] = 0xc; /* (2800 - 1600) / 100; */
+ i2c_write(addr, 0x28, 1, val, 1);
+
+ /* LDO17 3.0V */
+ val[0] = 0xe; /* (3000 - 1600) / 100; */
+ i2c_write(addr, 0x29, 1, val, 1);
+
+ /*
+ * Because the data sheet of LP3974 does NOT mention default
+ * register values of ONOFF1~4 (ENABLE1~4), we ignore the given
+ * default values and set as we want
+ */
+
+ /* Note: To remove USB detect warning, Turn off LDO 8 first */
+
+ /*
+ * ONOFF2
+ * LDO6 OFF, LDO7 ON, LDO8 OFF, LDO9 ON,
+ * LDO10 OFF, LDO11 OFF, LDO12 OFF, LDO13 OFF
+ */
+ val[0] = 0x50;
+ i2c_write(addr, LP3974_REG_ONOFF2, 1, val, 1);
+
+ /*
+ * ONOFF1
+ * Buck1 ON, Buck2 OFF, Buck3 ON, Buck4 ON
+ * LDO2 ON, LDO3 OFF, LDO4 ON, LDO5 ON
+ */
+ val[0] = 0xBB;
+ i2c_write(addr, LP3974_REG_ONOFF1, 1, val, 1);
+
+ /*
+ * ONOFF3
+ * LDO14 OFF, LDO15 OFF, LGO16 OFF, LDO17 ON,
+ * EPWRHOLD OFF, EBATTMON OFF, ELBCNFG2 OFF, ELBCNFG1 OFF
+ */
+ val[0] = 0x10;
+ i2c_write(addr, LP3974_REG_ONOFF3, 1, val, 1);
+
+ /*
+ * ONOFF4
+ * EN32kAP ON, EN32kCP ON, ENVICHG ON, ENRAMP ON,
+ * RAMP 12mV/us (fastest)
+ */
+ val[0] = 0xFB;
+ i2c_write(addr, LP3974_REG_ONOFF4, 1, val, 1);
+
+ /*
+ * CHGCNTL1
+ * ICHG: 500mA (0x3) / 600mA (0x5)
+ * RESTART LEVEL: 100mA (0x1)
+ * EOC LEVEL: 30% (0x4) / 25% (0x3) : both 150mA of ICHG
+ * Let's start with slower charging mode and let micro usb driver
+ * determine whether we can do it fast or not. Thus, using the slower
+ * setting...
+ */
+ val[0] = 0x8B;
+ i2c_write(addr, 0xC, 1, val, 1);
+
+ /*
+ * CHGCNTL2
+ * CHARGER DISABLE: Enable (0x0)
+ * TEMP CONTROL: 105C (0x0)
+ * BATT SEL: 4.2V (0x0)
+ * FULL TIMEOUT: 5hr (0x0)
+ * ESAFEOUT2: ON (0x1)
+ * ESAFEOUT1: OFF (0x0)
+ */
+ val[0] = 0x40;
+ i2c_write(addr, 0xD, 1, val, 1);
+
+ val[0] = 0x0E; /* 1.1V @ DVSARM1(VINT) */
+ i2c_write(addr, 0x15, 1, val, 1);
+ val[0] = 0x0E; /* 1.1V @ DVSARM2(VINT) */
+ i2c_write(addr, 0x16, 1, val, 1);
+ val[0] = 0x0E; /* 1.1V @ DVSARM3(VINT) */
+ i2c_write(addr, 0x17, 1, val, 1);
+ val[0] = 0x0A; /* 1.0V @ DVSARM4(VINT) */
+ i2c_write(addr, 0x18, 1, val, 1);
+ val[0] = 0x12; /* 1.2V @ DVSINT1(VG3D) */
+ i2c_write(addr, 0x19, 1, val, 1);
+ val[0] = 0x0E; /* 1.1V @ DVSINT2(VG3D) */
+ i2c_write(addr, 0x1A, 1, val, 1);
+
+ val[0] = 0x2; /* 1.8V for BUCK3 VCC 1.8V PDA */
+ i2c_write(addr, 0x1B, 1, val, 1);
+ val[0] = 0x4; /* 1.2V for BUCK4 VMEM 1.2V C210 */
+ i2c_write(addr, 0x1C, 1, val, 1);
+
+ /* Use DVSARM1 for VINT */
+ gpio_direction_output(&gpio2->x0, 5, 0);
+ gpio_direction_output(&gpio2->x0, 6, 0);
+ /* Use DVSINT2 for VG3D */
+ gpio_direction_output(&gpio1->e2, 0, 1);
+
+ /*
+ * Default level of UVLO.
+ * UVLOf = 2.7V (0x3 << 4), UVLOr = 3.1V (0xB)
+ * set UVLOf to 2.55V (0 << 4).
+ */
+ val[0] = 0x2C;
+ i2c_write(addr, LP3974_REG_MODCHG, 1, val, 1);
+ val[0] = 0x58;
+ i2c_write(addr, LP3974_REG_MODCHG, 1, val, 1);
+ val[0] = 0xB1;
+ i2c_write(addr, LP3974_REG_MODCHG, 1, val, 1);
+
+ i2c_read_r(addr, LP3974_REG_UVLO, 1, val, 1);
+ val[0] = (val[0] & 0xf) | (0 << 4);
+ i2c_write(addr, LP3974_REG_UVLO, 1, val, 1);
+
+ val[0] = 0x00;
+ i2c_write(addr, LP3974_REG_MODCHG, 1, val, 1);
+}
+
+static int poweron_key_check(void)
+{
+ unsigned char addr, val[2];
+
+ addr = 0xCC >> 1;
+ if (lp3974_probe())
+ return 0;
+
+ i2c_read_r(addr, LP3974_REG_IRQ3, 1, val, 1);
+ return val[0] & 0x1;
+}
+
+int check_exit_key(void)
+{
+ return poweron_key_check();
+}
+
+static int power_key_check(void)
+{
+ unsigned char addr, val[4];
+ int tmp;
+
+ addr = 0xCC >> 1;
+ if (lp3974_probe())
+ return -1;
+
+ /* power_key check */
+ i2c_read_r(addr, LP3974_REG_IRQ1, 1, val, 4);
+
+ tmp = ((val[0] & (1 << 7)) >> 7);
+
+ return tmp;
+}
+
+static void check_keypad(void)
+{
+ unsigned int val = 0;
+ unsigned int power_key, auto_download = 0;
+
+ val = ~(gpio_get_value(&gpio2->x2, 1));
+
+ power_key = power_key_check();
+
+ if (power_key && (val & 0x1))
+ auto_download = 1;
+
+ if (auto_download)
+ setenv("bootcmd", "usbdown");
+}
+
+/*
+ * charger_en(): set lp3974 pmic's charger mode
+ * enable 0: disable charger
+ * 600: 600mA
+ * 500: 500mA
+ */
+static void charger_en(int enable)
+{
+ unsigned char addr = 0xCC >> 1; /* LP3974 */
+ unsigned char val[2];
+
+ if (lp3974_probe())
+ return;
+
+ switch (enable) {
+ case 0:
+ puts("Disable the charger.\n");
+ i2c_read(addr, 0x0D, 1, val, 1);
+ val[0] |= 0x1;
+ i2c_write(addr, 0xD, 1, val, 1);
+ break;
+ case 500:
+ puts("Enable the charger @ 500mA\n");
+ /*
+ * CHGCNTL1
+ * ICHG: 500mA (0x3) / 600mA (0x5)
+ * RESTART LEVEL: 100mA (0x1)
+ * EOC LEVEL: 30% (0x4) / 25% (0x3) : both 150mA of ICHG
+ * Let's start with slower charging mode and
+ * let micro usb driver determine whether we can do it
+ * fast or not. Thus, using the slower setting...
+ */
+ val[0] = 0x8B;
+ i2c_write(addr, 0x0C, 1, val, 1);
+ i2c_read(addr, 0x0D, 1, val, 1);
+ val[0] &= ~(0x1);
+ i2c_write(addr, 0x0D, 1, val, 1);
+ break;
+ case 600:
+ puts("Enable the charger @ 600mA\n");
+ val[0] = 0x6D;
+ i2c_write(addr, 0x0C, 1, val, 1);
+ i2c_read(addr, 0x0D, 1, val, 1);
+ val[0] &= ~(0x1);
+ i2c_write(addr, 0x0D, 1, val, 1);
+ break;
+ default:
+ puts("Incorrect charger setting.\n");
+ }
+}
+
+struct thermister_stat {
+ short centigrade;
+ unsigned short adc;
+};
+
+static struct thermister_stat adc_to_temperature_data[] = {
+ { .centigrade = -20, .adc = 1856, },
+ { .centigrade = -15, .adc = 1799, },
+ { .centigrade = -10, .adc = 1730, },
+ { .centigrade = -5, .adc = 1649, },
+ { .centigrade = 0, .adc = 1556, },
+ { .centigrade = 5, .adc = 1454, },
+ { .centigrade = 10, .adc = 1343, },
+ { .centigrade = 15, .adc = 1227, },
+ { .centigrade = 20, .adc = 1109, },
+ { .centigrade = 25, .adc = 992, },
+ { .centigrade = 30, .adc = 880, },
+ { .centigrade = 35, .adc = 773, },
+ { .centigrade = 40, .adc = 675, },
+ { .centigrade = 45, .adc = 586, },
+ { .centigrade = 50, .adc = 507, },
+ { .centigrade = 55, .adc = 436, },
+ { .centigrade = 58, .adc = 399, },
+ { .centigrade = 63, .adc = 343, },
+ { .centigrade = 65, .adc = 322, },
+};
+
+#ifndef USHRT_MAX
+#define USHRT_MAX 0xFFFFU
+#endif
+
+static int adc_to_temperature_centigrade(unsigned short adc)
+{
+ int i;
+ int approximation;
+ /* low_*: Greatest Lower Bound,
+ * * * * high_*: Smallest Upper Bound */
+ int low_temp = 0, high_temp = 0;
+ unsigned short low_adc = 0, high_adc = USHRT_MAX;
+ for (i = 0; i < ARRAY_SIZE(adc_to_temperature_data); i++) {
+ if (adc_to_temperature_data[i].adc <= adc &&
+ adc_to_temperature_data[i].adc >= low_adc) {
+ low_temp = adc_to_temperature_data[i].centigrade;
+ low_adc = adc_to_temperature_data[i].adc;
+ }
+ if (adc_to_temperature_data[i].adc >= adc &&
+ adc_to_temperature_data[i].adc <= high_adc) {
+ high_temp = adc_to_temperature_data[i].centigrade;
+ high_adc = adc_to_temperature_data[i].adc;
+ }
+ }
+
+ /* Linear approximation between cloest low and high,
+ * which is the weighted average of the two. */
+
+ /* The following equation is correct only when the two are different */
+ if (low_adc == high_adc)
+ return low_temp;
+ if (ARRAY_SIZE(adc_to_temperature_data) < 2)
+ return 20; /* The room temperature */
+ if (low_adc == 0)
+ return high_temp;
+ if (high_adc == USHRT_MAX)
+ return low_temp;
+
+ approximation = low_temp * (adc - low_adc) +
+ high_temp * (high_adc - adc);
+ approximation /= high_adc - low_adc;
+
+ return approximation;
+}
+
+static unsigned short get_adc_value(int channel);
+static int adc_get_average_ambient_temperature(void)
+{
+ unsigned short min = USHRT_MAX;
+ unsigned short max = 0;
+ unsigned int sum = 0;
+ unsigned int measured = 0;
+ int i;
+
+ for (i = 0; i < 7; i++) {
+ /* XADCAIN6 */
+ unsigned short measurement = get_adc_value(6);
+ sum += measurement;
+ measured++;
+ if (min > measurement)
+ min = measurement;
+ if (max < measurement)
+ max = measurement;
+ }
+ if (measured >= 3) {
+ measured -= 2;
+ sum -= min;
+ sum -= max;
+ }
+ sum /= measured;
+ printf("Average Ambient Temperature = %d(ADC=%d)\n",
+ adc_to_temperature_centigrade(sum), sum);
+ return adc_to_temperature_centigrade(sum);
+}
+
+enum temperature_level {
+ _TEMP_OK,
+ _TEMP_OK_HIGH,
+ _TEMP_OK_LOW,
+ _TEMP_TOO_HIGH,
+ _TEMP_TOO_LOW,
+};
+
+static enum temperature_level temperature_check(void)
+{
+ int temp = adc_get_average_ambient_temperature();
+ if (temp < -5)
+ return _TEMP_TOO_LOW;
+ if (temp < 0)
+ return _TEMP_OK_LOW;
+ if (temp > 63)
+ return _TEMP_TOO_HIGH;
+ if (temp > 58)
+ return _TEMP_OK_HIGH;
+ return _TEMP_OK;
+}
+
+/*
+ * into_charge_mode()
+ * Run a charge loop with animation and temperature check with sleep
+**/
+static void into_charge_mode(int charger_speed)
+{
+ int i, j, delay;
+ enum temperature_level previous_state = _TEMP_OK;
+ unsigned int wakeup_stat = 0;
+
+ /* 1. Show Animation */
+ for (i = 0; i < 5; i++) {
+ for (j = 0; j < 5; j++) {
+ printf(".");
+ for (delay = 0; delay < 1000; delay++)
+ udelay(1000);
+ }
+ printf("\n");
+ }
+
+ /* 2. Loop with temperature check and sleep */
+ do {
+ /* TODO: 2.A. Setup wakeup source and rtc tick */
+
+ /* TODO: 2.B. Go to sleep */
+ for (delay = 0; delay < 4000; delay++)
+ udelay(1000);
+
+ /* 2.C. Check the temperature */
+ switch (temperature_check()) {
+ case _TEMP_OK:
+ charger_en(charger_speed);
+ previous_state = _TEMP_OK;
+ break;
+ case _TEMP_TOO_LOW:
+ charger_en(0);
+ previous_state = _TEMP_TOO_LOW;
+ break;
+ case _TEMP_TOO_HIGH:
+ charger_en(0);
+ previous_state = _TEMP_TOO_HIGH;
+ break;
+ case _TEMP_OK_LOW:
+ if (previous_state == _TEMP_TOO_LOW) {
+ charger_en(0);
+ } else {
+ charger_en(charger_speed);
+ previous_state = _TEMP_OK;
+ }
+ break;
+ case _TEMP_OK_HIGH:
+ if (previous_state == _TEMP_TOO_HIGH) {
+ charger_en(0);
+ } else {
+ charger_en(charger_speed);
+ previous_state = _TEMP_OK;
+ }
+ break;
+ }
+ } while (wakeup_stat == 0x04);
+}
+
+static void init_pmic_max8952(void)
+{
+ unsigned char addr;
+ unsigned char val[2];
+
+ addr = 0xC0 >> 1; /* MAX8952 */
+ if (max8952_probe())
+ return;
+
+ /* MODE0: 1.10V: Default */
+ val[0] = 33;
+ i2c_write(addr, 0x00, 1, val, 1);
+ /* MODE1: 1.20V */
+ val[0] = 43;
+ i2c_write(addr, 0x01, 1, val, 1);
+ /* MODE2: 1.05V */
+ val[0] = 28;
+ i2c_write(addr, 0x02, 1, val, 1);
+ /* MODE3: 0.95V */
+ val[0] = 18;
+ i2c_write(addr, 0x03, 1, val, 1);
+
+ /*
+ * Note: use the default setting and configure pins high
+ * to generate the 1.1V
+ */
+ /* VARM_OUTPUT_SEL_A / VID_0 / XEINT_3 (GPX0[3]) = default 0 */
+ gpio_direction_output(&gpio2->x0, 3, 0);
+ /* VARM_OUTPUT_SEL_B / VID_1 / XEINT_4 (GPX0[4]) = default 0 */
+ gpio_direction_output(&gpio2->x0, 4, 0);
+
+ /* CONTROL: Disable PULL_DOWN */
+ val[0] = 0;
+ i2c_write(addr, 0x04, 1, val, 1);
+
+ /* SYNC: Do Nothing */
+ /* RAMP: As Fast As Possible: Default: Do Nothing */
+}
+
+#ifdef CONFIG_LCD
+void fimd_clk_set(void)
+{
+ struct s5pc210_clock *clk =
+ (struct s5pc210_clock *)samsung_get_base_clock();
+
+ /* workaround */
+ unsigned long display_ctrl = 0x10010210;
+ unsigned int cfg = 0;
+
+ /* LCD0_BLK FIFO S/W reset */
+ cfg = readl(display_ctrl);
+ cfg |= (1 << 9);
+ writel(cfg, display_ctrl);
+
+ cfg = 0;
+
+ /* FIMD of LBLK0 Bypass Selection */
+ cfg = readl(display_ctrl);
+ cfg &= ~(1 << 9);
+ cfg |= (1 << 1);
+ writel(cfg, display_ctrl);
+
+ /* set lcd src clock */
+ cfg = readl(&clk->src_lcd0);
+ cfg &= ~(0xf);
+ cfg |= 0x6;
+ writel(cfg, &clk->src_lcd0);
+
+ /* set fimd ratio */
+ cfg = readl(&clk->div_lcd0);
+ cfg &= ~(0xf);
+ cfg |= 0x1;
+ writel(cfg, &clk->div_lcd0);
+}
+
+extern void ld9040_set_platform_data(struct spi_platform_data *pd);
+
+struct spi_platform_data spi_pd;
+
+static void lcd_cfg_gpio(void)
+{
+ unsigned int i;
+
+ for (i = 0; i < 8; i++) {
+ /* set GPF0,1,2[0:7] for RGB Interface and Data lines (32bit) */
+ gpio_cfg_pin(&gpio1->f0, i, GPIO_FUNC(2));
+ gpio_cfg_pin(&gpio1->f1, i, GPIO_FUNC(2));
+ gpio_cfg_pin(&gpio1->f2, i, GPIO_FUNC(2));
+ /* pull-up/down disable */
+ gpio_set_pull(&gpio1->f0, i, GPIO_PULL_NONE);
+ gpio_set_pull(&gpio1->f1, i, GPIO_PULL_NONE);
+ gpio_set_pull(&gpio1->f2, i, GPIO_PULL_NONE);
+
+ /* drive strength to max (24bit) */
+ gpio_set_drv(&gpio1->f0, i, GPIO_DRV_4X);
+ gpio_set_rate(&gpio1->f0, i, GPIO_DRV_SLOW);
+ gpio_set_drv(&gpio1->f1, i, GPIO_DRV_4X);
+ gpio_set_rate(&gpio1->f1, i, GPIO_DRV_SLOW);
+ gpio_set_drv(&gpio1->f2, i, GPIO_DRV_4X);
+ gpio_set_rate(&gpio1->f2, i, GPIO_DRV_SLOW);
+ }
+
+ for (i = 0; i < 4; i++) {
+ /* set GPF3[0:3] for RGB Interface and Data lines (32bit) */
+ gpio_cfg_pin(&gpio1->f3, i, GPIO_PULL_UP);
+ /* pull-up/down disable */
+ gpio_set_pull(&gpio1->f3, i, GPIO_PULL_NONE);
+ /* drive strength to max (24bit) */
+ gpio_set_drv(&gpio1->f3, i, GPIO_DRV_4X);
+ gpio_set_rate(&gpio1->f3, i, GPIO_DRV_SLOW);
+ }
+
+ /* gpio pad configuration for LCD reset. */
+ gpio_direction_output(&gpio2->y4, 5, 1);
+
+ /*
+ * gpio pad configuration for
+ * DISPLAY_CS, DISPLAY_CLK, DISPLAY_SO, DISPLAY_SI.
+ */
+ gpio_cfg_pin(&gpio2->y4, 3, GPIO_OUTPUT);
+ gpio_cfg_pin(&gpio2->y3, 1, GPIO_OUTPUT);
+ gpio_cfg_pin(&gpio2->y3, 3, GPIO_OUTPUT);
+
+ spi_pd.cs_bank = &gpio2->y4;
+ spi_pd.cs_num = 3;
+ spi_pd.clk_bank = &gpio2->y3;
+ spi_pd.clk_num = 1;
+ spi_pd.si_bank = &gpio2->y3;
+ spi_pd.si_num = 3;
+
+ spi_pd.mode = SPI_MODE_3;
+
+ spi_pd.cs_active = ACTIVE_LOW;
+ spi_pd.word_len = 8;
+
+ ld9040_set_platform_data(&spi_pd);
+
+ return;
+}
+
+extern void ld9040_cfg_ldo(void);
+extern void ld9040_enable_ldo(unsigned int onoff);
+
+int s5p_no_lcd_support(void)
+{
+ return 0;
+}
+
+void init_panel_info(vidinfo_t *vid)
+{
+ vid->vl_freq = 60;
+ vid->vl_col = 480;
+ vid->vl_row = 800;
+ vid->vl_width = 480;
+ vid->vl_height = 800;
+ vid->vl_clkp = CONFIG_SYS_HIGH;
+ vid->vl_hsp = CONFIG_SYS_HIGH;
+ vid->vl_vsp = CONFIG_SYS_HIGH;
+ vid->vl_dp = CONFIG_SYS_HIGH;
+
+ vid->vl_bpix = 32;
+ /* disable dual lcd mode. */
+ vid->dual_lcd_enabled = 0;
+
+ /* LD9040 LCD Panel */
+ vid->vl_hspw = 2;
+ vid->vl_hbpd = 16;
+ vid->vl_hfpd = 16;
+
+ vid->vl_vspw = 2;
+ vid->vl_vbpd = 6;
+ vid->vl_vfpd = 4;
+
+ vid->cfg_gpio = lcd_cfg_gpio;
+ vid->backlight_on = NULL;
+ vid->lcd_power_on = NULL; /* Don't need the poweron squence */
+ vid->reset_lcd = NULL; /* Don't need the reset squence */
+
+ vid->cfg_ldo = ld9040_cfg_ldo;
+ vid->enable_ldo = ld9040_enable_ldo;
+
+ vid->init_delay = 0;
+ vid->power_on_delay = 0;
+ vid->reset_delay = 0;
+ vid->interface_mode = FIMD_RGB_INTERFACE;
+
+ /* board should be detected at here. */
+
+ /* for LD8040. */
+ vid->pclk_name = MPLL;
+ vid->sclk_div = 1;
+
+ setenv("lcdinfo", "lcd=ld9040");
+}
+#endif
+
+static unsigned short get_adc_value(int channel)
+{
+ struct s5p_adc *adc = (struct s5p_adc *)samsung_get_base_adc();
+ unsigned short ret = 0;
+ unsigned int reg;
+ unsigned int loop = 0;
+
+ writel(channel & 0xF, &adc->adcmux);
+ writel((1 << 14) | (49 << 6), &adc->adccon);
+ writel(1000 & 0xffff, &adc->adcdly);
+ writel(readl(&adc->adccon) | (1 << 16), &adc->adccon); /* 12 bit */
+ udelay(10);
+ writel(readl(&adc->adccon) | (1 << 0), &adc->adccon); /* Enable */
+ udelay(10);
+
+ do {
+ udelay(1);
+ reg = readl(&adc->adccon);
+ } while (!(reg & (1 << 15)) && (loop++ < 1000));
+
+ ret = readl(&adc->adcdat0) & 0xFFF;
+
+ return ret;
+}
+
+static unsigned int get_hw_revision(void)
+{
+ int hwrev = 0, mode0, mode1;
+
+ debug("mode0: %d, mode1: %d, hwrev 0x%x\n", mode0, mode1, hwrev);
+
+ return hwrev;
+}
+
+static const char * const pcb_rev[] = {
+ "SLP_MAIN_7INCH",
+};
+
+static void check_hw_revision(void)
+{
+ int hwrev;
+
+ hwrev = get_hw_revision();
+
+ board_rev |= hwrev;
+}
+
+static void show_hw_revision(void)
+{
+ printf("HW Revision:\t0x%x\n", board_rev);
+ printf("PCB Revision:\t%s\n", pcb_rev[board_rev & 0xf]);
+}
+
+void get_rev_info(char *rev_info)
+{
+ sprintf(rev_info, "HW Revision: 0x%x (%s)\n",
+ board_rev, pcb_rev[board_rev & 0xf]);
+}
+
+static void check_reset_status(void)
+{
+ int status = get_reset_status();
+
+ puts("Reset Status: ");
+
+ switch (status) {
+ case EXTRESET:
+ puts("Pin(Ext) Reset\n");
+ break;
+ case WARMRESET:
+ puts("Warm Reset\n");
+ break;
+ case WDTRESET:
+ puts("Watchdog Reset\n");
+ break;
+ case SWRESET:
+ puts("S/W Reset\n");
+ break;
+ default:
+ printf("Unknown (0x%x)\n", status);
+ }
+}
+
+#ifdef CONFIG_CMD_RAMOOPS
+static void show_dump_msg(void)
+{
+ int ret;
+
+ ret = ramoops_init(samsung_get_base_modem());
+
+ if (!ret)
+ setenv("bootdelay", "-1");
+}
+#endif
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+ check_reset_status();
+#ifdef CONFIG_CMD_RAMOOPS
+ show_dump_msg();
+#endif
+
+ show_hw_revision();
+ check_keypad();
+
+ check_auto_burn();
+
+ /* check max17040 */
+ check_battery(0);
+
+#ifdef CONFIG_INFO_ACTION
+ info_action_check();
+#endif
+
+#ifdef CONFIG_CMD_PMIC
+ max8998_init(I2C_5);
+ run_command("pmic ldo 4 off", 0); /* adc off */
+#endif
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_CMD_USBDOWN
+int usb_board_init(void)
+{
+ /* interrupt clear */
+ poweron_key_check();
+
+#ifdef CONFIG_CMD_PMIC
+ run_command("pmic ldo 8 on", 0);
+ run_command("pmic ldo 3 on", 0);
+ run_command("pmic safeout 1 on", 0);
+#endif
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_GENERIC_MMC
+int s5p_no_mmc_support(void)
+{
+ return 0;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ int i, err;
+
+ /* MASSMEMORY_EN: XGNSS_SDA: GPL1[1] */
+ gpio_direction_output(&gpio2->l1, 1, 0);
+
+ /*
+ * eMMC GPIO:
+ * SDR 8-bit@48MHz at MMC0
+ * GPK0[0] SD_0_CLK(2)
+ * GPK0[1] SD_0_CMD(2)
+ * GPK0[2] SD_0_CDn -> Not used
+ * GPK0[3:6] SD_0_DATA[0:3](2)
+ * GPK1[3:6] SD_0_DATA[0:3](3)
+ *
+ * DDR 4-bit@26MHz at MMC4
+ * GPK0[0] SD_4_CLK(3)
+ * GPK0[1] SD_4_CMD(3)
+ * GPK0[2] SD_4_CDn -> Not used
+ * GPK0[3:6] SD_4_DATA[0:3](3)
+ * GPK1[3:6] SD_4_DATA[4:7](4)
+ */
+ for (i = 0; i < 7; i++) {
+ if (i == 2)
+ continue;
+ /* GPK0[0:6] special function 2 */
+ gpio_cfg_pin(&gpio2->k0, i, 0x2);
+ /* GPK0[0:6] pull disable */
+ gpio_set_pull(&gpio2->k0, i, GPIO_PULL_NONE);
+ /* GPK0[0:6] drv 4x */
+ gpio_set_drv(&gpio2->k0, i, GPIO_DRV_4X);
+ }
+
+ for (i = 3; i < 7; i++) {
+ /* GPK1[3:6] special function 3 */
+ gpio_cfg_pin(&gpio2->k1, i, 0x3);
+ /* GPK1[3:6] pull disable */
+ gpio_set_pull(&gpio2->k1, i, GPIO_PULL_NONE);
+ /* GPK1[3:6] drv 4x */
+ gpio_set_drv(&gpio2->k1, i, GPIO_DRV_4X);
+ }
+
+ /* T-flash detect */
+ gpio_cfg_pin(&gpio2->x3, 4, 0xf);
+ gpio_set_pull(&gpio2->x3, 4, GPIO_PULL_UP);
+
+ /*
+ * MMC device init
+ * mmc0 : eMMC (8-bit buswidth)
+ * mmc2 : SD card (4-bit buswidth)
+ */
+ err = s5p_mmc_init(0, 8);
+
+ /*
+ * Check the T-flash detect pin
+ * GPX3[4] T-flash detect pin
+ */
+ if (!gpio_get_value(&gpio2->x3, 4)) {
+ /*
+ * SD card GPIO:
+ * GPK2[0] SD_2_CLK(2)
+ * GPK2[1] SD_2_CMD(2)
+ * GPK2[2] SD_2_CDn -> Not used
+ * GPK2[3:6] SD_2_DATA[0:3](2)
+ */
+ for (i = 0; i < 7; i++) {
+ if (i == 2)
+ continue;
+ /* GPK2[0:6] special function 2 */
+ gpio_cfg_pin(&gpio2->k2, i, 0x2);
+ /* GPK2[0:6] pull disable */
+ gpio_set_pull(&gpio2->k2, i, GPIO_PULL_NONE);
+ /* GPK2[0:6] drv 4x */
+ gpio_set_drv(&gpio2->k2, i, GPIO_DRV_4X);
+ }
+ err = s5p_mmc_init(2, 4);
+ }
+
+ return err;
+
+}
+#endif
s5pc110_f1 arm armv7 f1_c110 samsung s5pc1xx
s5pc110_universal arm armv7 universal_c110 samsung s5pc1xx
s5pc210_universal arm armv7 universal_c210 samsung s5pc2xx
+s5pc210_slp7 arm armv7 slp7_c210 samsung s5pc2xx
actux1 arm ixp
actux2 arm ixp
actux3 arm ixp
--- /dev/null
+/*
+ * Copyright (C) 2010 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * Configuation settings for the SAMSUNG Universal (s5pc100) board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */
+#define CONFIG_SAMSUNG 1 /* in a SAMSUNG core */
+#define CONFIG_S5P 1 /* which is in a S5P Family */
+#define CONFIG_S5PC210 1 /* which is in a S5PC210 */
+#define CONFIG_SLP7 1 /* working with Universal */
+#define CONFIG_SBOOT 1 /* use the s-boot */
+
+#include <asm/arch/cpu.h> /* get chip and board defs */
+
+#define CONFIG_ARCH_CPU_INIT
+
+/* Keep L2 Cache Disabled */
+#define CONFIG_L2_OFF 1
+
+#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CONFIG_SYS_TEXT_BASE 0x44800000
+
+/* input clock of PLL: Universal has 24MHz input clock at S5PC210 */
+#define CONFIG_SYS_CLK_FREQ_C210 24000000
+
+#define CONFIG_MEMORY_UPPER_CODE
+
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+/*
+ * Architecture magic and machine type
+ */
+#define MACH_TYPE 2989
+
+#define CONFIG_DISPLAY_CPUINFO
+
+#undef CONFIG_SKIP_RELOCATE_UBOOT
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes for initial data */
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_SERIAL_MULTI 1
+#define CONFIG_SERIAL2 1 /* we use SERIAL 2 on S5PC210 */
+
+/* INFORM0~3 registers are cleared by asserting XnRESET pin */
+/* INFORM4~7 registers are cleared only by power-up reset */
+#define CONFIG_INFO_ADDRESS 0x10020810 /* INFORM4 */
+
+/*
+ * spi gpio
+ */
+#define CONFIG_SPI_GPIO 1
+
+/* MMC */
+#if 1
+#define CONFIG_GENERIC_MMC 1
+#define CONFIG_MMC 1
+#define CONFIG_S5P_MMC 1
+#define CONFIG_MMC_ASYNC_WRITE 1
+#endif
+
+#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
+#ifdef CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#endif
+
+#define CONFIG_CMDLINE_EDITING
+
+#define CONFIG_BAUDRATE 115200
+
+/* It should define before config_cmd_default.h */
+#define CONFIG_SYS_NO_FLASH 1
+/***********************************************************
+ * Command definition
+ ***********************************************************/
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_BOOTD
+#undef CONFIG_CMD_CONSOLE
+#undef CONFIG_CMD_ECHO
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_ITEST
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_LOADB
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_NAND
+#undef CONFIG_CMD_MISC
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_SOURCE
+#undef CONFIG_CMD_XIMG
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_SLEEP
+#define CONFIG_CMD_PMIC
+#define CONFIG_CMD_DEVICE_POWER
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_RAMOOPS
+#define CONFIG_CMD_MBR
+#define CONFIG_INFO_ACTION
+
+#undef CONFIG_CRC16
+#undef CONFIG_XYZMODEM
+
+#define CONFIG_SYS_64BIT_VSPRINTF 1
+
+#define CONFIG_BOOTDELAY 0
+
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+
+#define CONFIG_FAT_WRITE
+
+/* To use the TFTPBOOT over USB, Please enable the CONFIG_CMD_NET */
+#undef CONFIG_CMD_NET
+
+#ifdef CONFIG_CMD_NET
+/* Ethernet */
+#define CONFIG_NET_MULTI 1
+#define CONFIG_NET_RETRY_COUNT 2
+#define CONFIG_NET_DO_NOT_TRY_ANOTHER 1
+
+/* NFS support in Ethernet over USB is broken */
+
+/* Configure Ethernet over USB */
+#define CONFIG_USB_ETH_RNDIS 1
+#define CONFIG_USB_GADGET 1
+#define CONFIG_USB_GADGET_S3C_UDC_OTG 1
+#define CONFIG_USB_GADGET_DUALSPEED 1
+#define CONFIG_USB_ETHER 1
+#define CONFIG_USBNET_MANUFACTURER "S5PC1xx U-Boot"
+/* ethaddr settings can be overruled via environment settings */
+#define CONFIG_USBNET_DEV_ADDR "8e:28:0f:fa:3c:39"
+#define CONFIG_USBNET_HOST_ADDR "0a:fa:63:8b:e8:0a"
+#define CONFIG_USB_CDC_VENDOR_ID 0x0525
+#define CONFIG_USB_CDC_PRODUCT_ID 0xa4a1
+#define CONFIG_USB_RNDIS_VENDOR_ID 0x0525
+#define CONFIG_USB_RNDIS_PRODUCT_ID 0xa4a2
+
+#endif
+
+#define CONFIG_NETMASK 255.255.255.0
+#define CONFIG_IPADDR 192.168.129.3
+#define CONFIG_SERVERIP 192.168.129.1
+#define CONFIG_GATEWAYIP 192.168.129.1
+#define CONFIG_ETHADDR 8e:28:0f:fa:3c:39
+
+#define MBRPARTS_DEFAULT "20M(permanent)"\
+ ",20M(boot)"\
+ ",1G(system)"\
+ ",100M(swap)"\
+ ",-(UMS)\0"
+
+#define CONFIG_BOOTLOADER_SECTOR 0x80
+
+#define CONFIG_BOOTARGS "Please use defined boot"
+#define CONFIG_BOOTCOMMAND "run mmcboot"
+#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0"
+#define CONFIG_ENV_COMMON_BOOT "${console} ${meminfo}"
+
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_AUTOSAVE
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "bootk=run loaduimage; bootm 0x40007FC0\0" \
+ "updatemmc=mmc boot 0 1 1 1; mmc write 0 0x42008000 0 0x200;" \
+ " mmc boot 0 1 1 0\0" \
+ "updatebackup=mmc boot 0 1 1 2; mmc write 0 0x42100000 0 0x200;" \
+ " mmc boot 0 1 1 0\0" \
+ "updatebootb=mmc read 0 0x42100000 0x80 0x200; run updatebackup\0" \
+ "lpj=lpj=3981312\0" \
+ "nfsboot=set bootargs root=/dev/nfs rw " \
+ "nfsroot=${nfsroot},nolock,tcp " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:" \
+ "${netmask}:generic:usb0:off " CONFIG_ENV_COMMON_BOOT \
+ "; run bootk\0" \
+ "ramfsboot=set bootargs root=/dev/ram0 rw rootfstype=ext2 " \
+ "${console} ${meminfo} " \
+ "initrd=0x43000000,8M ramdisk=8192\0" \
+ "mmcboot=set bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} ${lpj} " \
+ "rootwait ${console} ${meminfo} ${opts} ${lcdinfo}; " \
+ "run loaduimage; bootm 0x40007FC0\0" \
+ "bootchart=set opts init=/sbin/bootchartd; run bootcmd\0" \
+ "boottrace=setenv opts initcall_debug; run bootcmd\0" \
+ "mmcoops=mmc read 0 0x40000000 0x40 8; md 0x40000000 0x400\0" \
+ "verify=n\0" \
+ "rootfstype=ext4\0" \
+ "console=" CONFIG_DEFAULT_CONSOLE \
+ "mbrparts=" MBRPARTS_DEFAULT \
+ "meminfo=crashkernel=32M@0x50000000\0" \
+ "nfsroot=/nfsroot/arm\0" \
+ "loaduimage=fatload mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 uImage\0" \
+ "mmcdev=0\0" \
+ "mmcbootpart=2\0" \
+ "mmcrootpart=3\0" \
+ "opts=always_resume=1"
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_PROMPT "SLP7 # " /* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5000000)
+#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4800000)
+
+#define CONFIG_SYS_HZ 1000
+
+/* valid baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (256 << 10) /* regular stack 256KB */
+
+/* Universal has 2 banks of DRAM, but swap the bank */
+#define CONFIG_NR_DRAM_BANKS 2
+#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* LDDDR2 DMC 0 */
+#define PHYS_SDRAM_1_SIZE (256 << 20) /* 256 MB in CS 0 */
+#define PHYS_SDRAM_2 0x50000000 /* LPDDR2 DMC 1 */
+#define PHYS_SDRAM_2_SIZE (256 << 20) /* 256 MB in CS 0 */
+
+#define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* 1MB for ram console */
+
+#define CONFIG_SYS_MONITOR_BASE 0x00000000
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
+
+#define CONFIG_ENV_IS_IN_MMC 1
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_ENV_SIZE 4096
+#define CONFIG_ENV_OFFSET ((32 - 4) << 10)/* 32KiB - 4KiB */
+
+#define CONFIG_DOS_PARTITION 1
+
+#define CONFIG_MISC_INIT_R
+
+/* I2C */
+#include <i2c-gpio.h>
+#define CONFIG_S5P_GPIO_I2C 1
+#define CONFIG_SOFT_I2C 1
+#define CONFIG_SOFT_I2C_READ_REPEATED_START
+#define CONFIG_SYS_I2C_INIT_BOARD
+#define CONFIG_SYS_I2C_SPEED 50000
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_SYS_MAX_I2C_BUS 15
+
+/* USB Downloader */
+#define CONFIG_CMD_USBDOWN
+#define CONFIG_SAMSUNG_USB
+/* select USB operation mode: CONFIG_S5P_USB_DMA or CONFIG_S5P_USB_CPU */
+#define CONFIG_S5P_USB_DMA
+#define CONFIG_OTG_CLK_OSCC
+#define CONFIG_SYS_DOWN_ADDR CONFIG_SYS_SDRAM_BASE
+
+/* LCD */
+#if 0
+#define CONFIG_LCD 1
+#define CONFIG_FB_ADDR 0x52504000
+#define CONFIG_S5PC1XXFB 1
+#define CONFIG_LD9040 1
+#define CONFIG_DSIM 1
+/* Insert bmp animation compressed */
+#define CONFIG_VIDEO_BMP_GZIP
+#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (250*250*4)
+#endif
+
+#define CONFIG_SYS_SP_ADDR (CONFIG_SYS_LOAD_ADDR - 0x1000000)
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SP_ADDR - CONFIG_SYS_GBL_DATA_SIZE)
+
+#define CONFIG_TEST_BOOTTIME
+
+#endif /* __CONFIG_H */
projects / kernel / u-boot.git / commitdiff