# endif
#endif
-#if defined(__alpha__) && defined(__linux__)
-extern unsigned long _bus_base(void);
-#define BUS_BASE _bus_base()
-#endif
-
/* Not all systems have MAP_FAILED defined */
#ifndef MAP_FAILED
#define MAP_FAILED ((void *)-1)
drm_map_t map;
map.offset = offset;
-#ifdef __alpha__
- /* Make sure we add the bus_base to all but shm */
- if (type != DRM_SHM)
- map.offset += BUS_BASE;
-#endif
map.size = size;
map.handle = 0;
map.type = type;
drm_agp_head_t *agp;
#endif
#ifdef __alpha__
+#if LINUX_VERSION_CODE < 0x020403
struct pci_controler *hose;
+#else
+ struct pci_controller *hose;
+#endif
#endif
drm_sg_mem_t *sg; /* Scatter gather memory */
unsigned long *ctx_bitmap;
#define RADEON_FIFO_DEBUG 0
+#if defined(__alpha__)
+# define PCIGART_ENABLED
+#else
+# undef PCIGART_ENABLED
+#endif
+
/* CP microcode (from ATI) */
static u32 radeon_cp_microcode[][2] = {
dev_priv->is_pci = init->is_pci;
-#if 1
+#if !defined(PCIGART_ENABLED)
/* PCI support is not 100% working, so we disable it here.
*/
if ( dev_priv->is_pci ) {
#endif
if ( dev_priv->is_pci && !dev->sg ) {
- DRM_DEBUG( "PCI GART memory not allocated!\n" );
DRM_ERROR( "PCI GART memory not allocated!\n" );
DRM(free)( dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER );
dev->dev_private = NULL;
if ( dev_priv->is_pci ) {
dev_priv->phys_pci_gart = DRM(ati_pcigart_init)( dev );
if ( !dev_priv->phys_pci_gart ) {
- DRM_DEBUG( "failed to init PCI GART!\n" );
DRM_ERROR( "failed to init PCI GART!\n" );
DRM(free)( dev_priv, sizeof(*dev_priv),
DRM_MEM_DRIVER );
/* Turn off AGP aperture -- is this required for PCIGART?
*/
- RADEON_WRITE( RADEON_MC_AGP_LOCATION, 0 );
+ RADEON_WRITE( RADEON_MC_AGP_LOCATION, 0xffffffc0 ); /* ?? */
+ RADEON_WRITE( RADEON_AGP_COMMAND, 0 ); /* clear AGP_COMMAND */
+#if defined(__alpha__)
+ /* HACK! something is clobbering MEM_CNTL on Alpha! */
+ DRM_ERROR( "MEM_CNTL 0x%x\n",
+ RADEON_READ(0x0140) );
+ RADEON_WRITE(0x0140, 0x29002901);
+#endif
} else {
/* Turn off PCI GART
*/