}
}
-static void
-radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
+void
+radv_write_scissors(struct radv_cmd_buffer *cmd_buffer, struct radeon_cmdbuf *cs)
{
struct radv_graphics_pipeline *pipeline = cmd_buffer->state.graphics_pipeline;
uint32_t count = cmd_buffer->state.dynamic.scissor.count;
rast_prim = si_conv_prim_to_gs_out(cmd_buffer->state.dynamic.primitive_topology);
}
- si_write_scissors(cmd_buffer->cs, 0, count, cmd_buffer->state.dynamic.scissor.scissors,
+ si_write_scissors(cs, 0, count, cmd_buffer->state.dynamic.scissor.scissors,
cmd_buffer->state.dynamic.viewport.viewports, rast_prim,
cmd_buffer->state.dynamic.line_width);
+}
+
+static void
+radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
+{
+ radv_write_scissors(cmd_buffer, cmd_buffer->cs);
cmd_buffer->state.context_roll_without_scissor_emitted = false;
}
void radv_write_vertex_descriptors(const struct radv_cmd_buffer *cmd_buffer,
const struct radv_graphics_pipeline *pipeline,
bool full_null_descriptors, void *vb_ptr);
+void radv_write_scissors(struct radv_cmd_buffer *cmd_buffer, struct radeon_cmdbuf *cs);
void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);