drm/amd/display: fix deep color ratio

Fix enum mapping for deep color ratio

Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Alan Liu <HaoPing.Liu@amd.com>
Signed-off-by: Hansen Dsouza <Hansen.Dsouza@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
index 2c7eb98..9285bde 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
@@ -971,6 +971,81 @@ static bool dce112_program_pix_clk(
        return true;
 }
 
+#if defined(CONFIG_DRM_AMD_DC_DCN)
+static bool dcn31_program_pix_clk(
+               struct clock_source *clock_source,
+               struct pixel_clk_params *pix_clk_params,
+               struct pll_settings *pll_settings)
+{
+       struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source);
+       struct bp_pixel_clock_parameters bp_pc_params = {0};
+       enum transmitter_color_depth bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_24;
+
+       if (IS_FPGA_MAXIMUS_DC(clock_source->ctx->dce_environment)) {
+               unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0;
+               unsigned dp_dto_ref_100hz = 7000000;
+               unsigned clock_100hz = pll_settings->actual_pix_clk_100hz;
+
+               /* Set DTO values: phase = target clock, modulo = reference clock */
+               REG_WRITE(PHASE[inst], clock_100hz);
+               REG_WRITE(MODULO[inst], dp_dto_ref_100hz);
+
+               /* Enable DTO */
+               REG_UPDATE(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, 1);
+               return true;
+       }
+
+       /*ATOMBIOS expects pixel rate adjusted by deep color ratio)*/
+       bp_pc_params.controller_id = pix_clk_params->controller_id;
+       bp_pc_params.pll_id = clock_source->id;
+       bp_pc_params.target_pixel_clock_100hz = pll_settings->actual_pix_clk_100hz;
+       bp_pc_params.encoder_object_id = pix_clk_params->encoder_object_id;
+       bp_pc_params.signal_type = pix_clk_params->signal_type;
+
+       // Make sure we send the correct color depth to DMUB for HDMI
+       if (pix_clk_params->signal_type == SIGNAL_TYPE_HDMI_TYPE_A) {
+               switch (pix_clk_params->color_depth) {
+               case COLOR_DEPTH_888:
+                       bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_24;
+                       break;
+               case COLOR_DEPTH_101010:
+                       bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_30;
+                       break;
+               case COLOR_DEPTH_121212:
+                       bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_36;
+                       break;
+               case COLOR_DEPTH_161616:
+                       bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_48;
+                       break;
+               default:
+                       bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_24;
+                       break;
+               }
+               bp_pc_params.color_depth = bp_pc_colour_depth;
+       }
+
+       if (clock_source->id != CLOCK_SOURCE_ID_DP_DTO) {
+               bp_pc_params.flags.SET_GENLOCK_REF_DIV_SRC =
+                                               pll_settings->use_external_clk;
+               bp_pc_params.flags.SET_XTALIN_REF_SRC =
+                                               !pll_settings->use_external_clk;
+               if (pix_clk_params->flags.SUPPORT_YCBCR420) {
+                       bp_pc_params.flags.SUPPORT_YUV_420 = 1;
+               }
+       }
+       if (clk_src->bios->funcs->set_pixel_clock(
+                       clk_src->bios, &bp_pc_params) != BP_RESULT_OK)
+               return false;
+       /* Resync deep color DTO */
+       if (clock_source->id != CLOCK_SOURCE_ID_DP_DTO)
+               dce112_program_pixel_clk_resync(clk_src,
+                                       pix_clk_params->signal_type,
+                                       pix_clk_params->color_depth,
+                                       pix_clk_params->flags.SUPPORT_YCBCR420);
+
+       return true;
+}
+#endif
 
 static bool dce110_clock_source_power_down(
                struct clock_source *clk_src)
@@ -1205,6 +1280,13 @@ static const struct clock_source_funcs dcn3_clk_src_funcs = {
        .get_pix_clk_dividers = dcn3_get_pix_clk_dividers,
        .get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz
 };
+
+static const struct clock_source_funcs dcn31_clk_src_funcs = {
+       .cs_power_down = dce110_clock_source_power_down,
+       .program_pix_clk = dcn31_program_pix_clk,
+       .get_pix_clk_dividers = dcn3_get_pix_clk_dividers,
+       .get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz
+};
 #endif
 /*****************************************/
 /* Constructor                           */
@@ -1610,6 +1692,24 @@ bool dcn3_clk_src_construct(
 #endif
 
 #if defined(CONFIG_DRM_AMD_DC_DCN)
+bool dcn31_clk_src_construct(
+       struct dce110_clk_src *clk_src,
+       struct dc_context *ctx,
+       struct dc_bios *bios,
+       enum clock_source_id id,
+       const struct dce110_clk_src_regs *regs,
+       const struct dce110_clk_src_shift *cs_shift,
+       const struct dce110_clk_src_mask *cs_mask)
+{
+       bool ret = dce112_clk_src_construct(clk_src, ctx, bios, id, regs, cs_shift, cs_mask);
+
+       clk_src->base.funcs = &dcn31_clk_src_funcs;
+
+       return ret;
+}
+#endif
+
+#if defined(CONFIG_DRM_AMD_DC_DCN)
 bool dcn301_clk_src_construct(
        struct dce110_clk_src *clk_src,
        struct dc_context *ctx,

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h
index 692fa23..069de76 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h
@@ -292,6 +292,15 @@ bool dcn301_clk_src_construct(
        const struct dce110_clk_src_regs *regs,
        const struct dce110_clk_src_shift *cs_shift,
        const struct dce110_clk_src_mask *cs_mask);
+
+bool dcn31_clk_src_construct(
+       struct dce110_clk_src *clk_src,
+       struct dc_context *ctx,
+       struct dc_bios *bios,
+       enum clock_source_id id,
+       const struct dce110_clk_src_regs *regs,
+       const struct dce110_clk_src_shift *cs_shift,
+       const struct dce110_clk_src_mask *cs_mask);
 #endif
 
 /* this table is use to find *1.001 and /1.001 pixel rates from non-precise pixel rate */

diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
index 2ecd7bb..3c5efa6 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
@@ -2177,7 +2177,7 @@ static struct clock_source *dcn30_clock_source_create(
        if (!clk_src)
                return NULL;
 
-       if (dcn3_clk_src_construct(clk_src, ctx, bios, id,
+       if (dcn31_clk_src_construct(clk_src, ctx, bios, id,
                        regs, &cs_shift, &cs_mask)) {
                clk_src->base.dp_clk_src = dp_clk_src;
                return &clk_src->base;

diff --git a/drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.c b/drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.c
index 72d581c..2e378d9 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.c
@@ -1759,7 +1759,7 @@ static struct clock_source *dcn31_clock_source_create(
        if (!clk_src)
                return NULL;
 
-       if (dcn3_clk_src_construct(clk_src, ctx, bios, id,
+       if (dcn31_clk_src_construct(clk_src, ctx, bios, id,
                        regs, &cs_shift, &cs_mask)) {
                clk_src->base.dp_clk_src = dp_clk_src;
                return &clk_src->base;