return nullptr;
}
+namespace {
class LookupVisibleHelper {
public:
LookupVisibleHelper(VisibleDeclConsumer &Consumer, bool IncludeDependentBases,
bool IncludeDependentBases;
bool LoadExternal;
};
+} // namespace
void Sema::LookupVisibleDecls(Scope *S, LookupNameKind Kind,
VisibleDeclConsumer &Consumer,
+
//===------------ MIRVRegNamerUtils.h - MIR VReg Renaming Utilities -------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
//
//===----------------------------------------------------------------------===//
+#ifndef LLVM_LIB_CODEGEN_MIRVREGNAMERUTILS_H
+#define LLVM_LIB_CODEGEN_MIRVREGNAMERUTILS_H
+
#include "llvm/ADT/PostOrderIterator.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include <queue>
-using namespace llvm;
+namespace llvm {
/// NamedVRegCursor - The cursor is an object that keeps track of what the next
/// vreg name should be. It does book keeping to determine when to skip the
// @return changed
bool renameVRegs(MachineBasicBlock *MBB);
};
+
+} // namespace llvm
+
+#endif
// "Stage=%d Cycle=%d".
//===----------------------------------------------------------------------===//
+namespace {
class ModuloScheduleTest : public MachineFunctionPass {
public:
static char ID;
MachineFunctionPass::getAnalysisUsage(AU);
}
};
+} // namespace
char ModuloScheduleTest::ID = 0;
Invalid
};
-PredicateConstraint parsePredicateConstraint(StringRef Constraint) {
+static PredicateConstraint parsePredicateConstraint(StringRef Constraint) {
PredicateConstraint P = PredicateConstraint::Invalid;
if (Constraint == "Upa")
P = PredicateConstraint::Upa;
TETE = 15 // 0b1111
};
-unsigned VCMPOpcodeToVPT(unsigned Opcode) {
+static unsigned VCMPOpcodeToVPT(unsigned Opcode) {
switch (Opcode) {
case ARM::MVE_VCMPf32:
return ARM::MVE_VPTv4f32;
}
}
-MachineInstr *findVCMPToFoldIntoVPST(MachineBasicBlock::iterator MI,
- const TargetRegisterInfo *TRI,
- unsigned &NewOpcode) {
+static MachineInstr *findVCMPToFoldIntoVPST(MachineBasicBlock::iterator MI,
+ const TargetRegisterInfo *TRI,
+ unsigned &NewOpcode) {
// Search backwards to the instruction that defines VPR. This may or not
// be a VCMP, we check that after this loop. If we find another instruction
// that reads cpsr, we return nullptr.
// Return true if there are no non-ehpad successors to MBB and there are no
// non-meta instructions between MBBI and MBB.end().
-bool blockEndIsUnreachable(const MachineBasicBlock &MBB,
- MachineBasicBlock::const_iterator MBBI) {
+static bool blockEndIsUnreachable(const MachineBasicBlock &MBB,
+ MachineBasicBlock::const_iterator MBBI) {
return std::all_of(
MBB.succ_begin(), MBB.succ_end(),
[](const MachineBasicBlock *Succ) { return Succ->isEHPad(); }) &&
/// limit how much effort is invested, we will never visit more values than
/// specified by \p MaxValues.
template <typename AAType, typename StateTy>
-bool genericValueTraversal(
+static bool genericValueTraversal(
Attributor &A, IRPosition IRP, const AAType &QueryingAA, StateTy &State,
const function_ref<bool(Value &, StateTy &, bool)> &VisitValueCB,
int MaxValues = 8) {
}
}
+namespace {
/// Helper functions to clamp a state \p S of type \p StateType with the
/// information in \p R and indicate/return if \p S did change (as-in update is
/// required to be run again).
BUILD_STAT_NAME(MallocCalls, Function) += MallocCalls.size();
}
};
+} // namespace
/// ----------------------------------------------------------------------------
/// Attributor