drm/i915/gvt: Init vreg GUC_STATUS to GS_MIA_IN_RESET

Although GVT doesn't support guest GuC, MIA core is still expected
to be GS_MIA_IN_RESET after uc HW reset.

Reviewed-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Colin Xu <colin.xu@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20200819010900.54598-1-colin.xu@intel.com

diff --git a/drivers/gpu/drm/i915/gvt/mmio.c b/drivers/gpu/drm/i915/gvt/mmio.c
index 291993615af995f00f8f93ae1cf471152b55c17a..b6811f6a230df4e18291bdc59f6b2d564ceb75c3 100644 (file)
--- a/drivers/gpu/drm/i915/gvt/mmio.c
+++ b/drivers/gpu/drm/i915/gvt/mmio.c
@@ -251,6 +251,9 @@ void intel_vgpu_reset_mmio(struct intel_vgpu *vgpu, bool dmlr)
                /* set the bit 0:2(Core C-State ) to C0 */
                vgpu_vreg_t(vgpu, GEN6_GT_CORE_STATUS) = 0;
 
+               /* uc reset hw expect GS_MIA_IN_RESET */
+               vgpu_vreg_t(vgpu, GUC_STATUS) |= GS_MIA_IN_RESET;
+
                if (IS_BROXTON(vgpu->gvt->gt->i915)) {
                        vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) &=
                                    ~(BIT(0) | BIT(1));