dt-bindings: net: fsl,fec: add RGMII internal clock delay

Add RGMII internal clock delay for FEC controller.

Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/Documentation/devicetree/bindings/net/fsl,fec.yaml b/Documentation/devicetree/bindings/net/fsl,fec.yaml
index b14e0e7..eca4144 100644 (file)
--- a/Documentation/devicetree/bindings/net/fsl,fec.yaml
+++ b/Documentation/devicetree/bindings/net/fsl,fec.yaml
@@ -96,6 +96,8 @@ properties:
       SOC internal PLL.
       The "enet_out"(option), output clock for external device, like supply clock
       for PHY. The clock is required if PHY clock source from SOC.
+      The "enet_2x_txclk"(option), for RGMII sampling clock which fixed at 250Mhz.
+      The clock is required if SoC RGMII enable clock delay.
 
   clock-names:
     minItems: 2
@@ -107,6 +109,7 @@ properties:
         - ptp
         - enet_clk_ref
         - enet_out
+        - enet_2x_txclk
 
   phy-mode: true
 
@@ -118,6 +121,12 @@ properties:
 
   mac-address: true
 
+  tx-internal-delay-ps:
+    enum: [0, 2000]
+
+  rx-internal-delay-ps:
+    enum: [0, 2000]
+
   phy-supply:
     description:
       Regulator that powers the Ethernet PHY.