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clk: samsung: exynos4: set parent of sclk_hdmiphy to hdmi
author
Andrzej Hajda
<a.hajda@samsung.com>
Mon, 24 Nov 2014 07:30:50 +0000
(08:30 +0100)
committer
Sylwester Nawrocki
<s.nawrocki@samsung.com>
Tue, 2 Dec 2014 15:22:58 +0000
(16:22 +0100)
sclk_hdmiphy clock is generated by HDMI-PHY and depends on hdmi gate clock.
The patch models this dependency using parent/child hirerarchy.
The patch fixes issue with system hangs during mixer device access, mixer uses
sclk_hdmiphy descendant clock.
Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
drivers/clk/samsung/clk-exynos4.c
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diff --git
a/drivers/clk/samsung/clk-exynos4.c
b/drivers/clk/samsung/clk-exynos4.c
index
940f028
..
88e8c6b
100644
(file)
--- a/
drivers/clk/samsung/clk-exynos4.c
+++ b/
drivers/clk/samsung/clk-exynos4.c
@@
-505,7
+505,7
@@
static struct samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[] __initdata
/* fixed rate clocks generated inside the soc */
static struct samsung_fixed_rate_clock exynos4_fixed_rate_clks[] __initdata = {
FRATE(0, "sclk_hdmi24m", NULL, CLK_IS_ROOT, 24000000),
- FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy",
NULL, CLK_IS_ROOT
, 27000000),
+ FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy",
"hdmi", 0
, 27000000),
FRATE(0, "sclk_usbphy0", NULL, CLK_IS_ROOT, 48000000),
};