ARM: MediaTek: Add support for MT8516 SoC
authorFabien Parent <fparent@baylibre.com>
Sun, 24 Mar 2019 15:46:38 +0000 (16:46 +0100)
committerTom Rini <trini@konsulko.com>
Tue, 23 Apr 2019 21:57:26 +0000 (17:57 -0400)
Add support for MediaTek MT8516 SoC. This include the file
that will initialize the SoC after boot and its device tree.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
arch/arm/dts/mt8516-u-boot.dtsi [new file with mode: 0644]
arch/arm/dts/mt8516.dtsi [new file with mode: 0644]
arch/arm/mach-mediatek/Kconfig
arch/arm/mach-mediatek/Makefile
arch/arm/mach-mediatek/mt8516/Makefile [new file with mode: 0644]
arch/arm/mach-mediatek/mt8516/init.c [new file with mode: 0644]

diff --git a/arch/arm/dts/mt8516-u-boot.dtsi b/arch/arm/dts/mt8516-u-boot.dtsi
new file mode 100644 (file)
index 0000000..3c0d843
--- /dev/null
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2019 BayLibre, SAS
+ * Author: Fabien Parent <fparent@baylibre.com>
+ */
+
+&infracfg {
+       u-boot,dm-pre-reloc;
+};
+
+&topckgen_ {
+       u-boot,dm-pre-reloc;
+};
+
+&topckgen_cg {
+       u-boot,dm-pre-reloc;
+};
+
+&apmixedsys {
+       u-boot,dm-pre-reloc;
+};
+
+&uart0 {
+       u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/mt8516.dtsi b/arch/arm/dts/mt8516.dtsi
new file mode 100644 (file)
index 0000000..1c33582
--- /dev/null
@@ -0,0 +1,136 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2019 BayLibre, SAS
+ * Author: Fabien Parent <fparent@baylibre.com>
+ */
+
+#include <dt-bindings/clock/mt8516-clk.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+       compatible = "mediatek,mt8516";
+       interrupt-parent = <&sysirq>;
+       #address-cells = <1>;
+       #size-cells = <1>;
+
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               enable-method = "mediatek,mt8516-smp";
+
+               cpu@0 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a35";
+                       reg = <0x0>;
+                       clock-frequency = <1300000000>;
+               };
+
+               cpu@1 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a35";
+                       reg = <0x1>;
+                       clock-frequency = <1300000000>;
+               };
+
+               cpu@2 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a35";
+                       reg = <0x2>;
+                       clock-frequency = <1300000000>;
+               };
+
+               cpu@3 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a35";
+                       reg = <0x3>;
+                       clock-frequency = <1300000000>;
+               };
+       };
+
+       topckgen: clock-controller@10000000 {
+               compatible = "mediatek,mt8516-topckgen";
+               reg = <0x10000000 0x1000>;
+               #clock-cells = <1>;
+       };
+
+       topckgen_cg: clock-controller-cg@10000000 {
+               compatible = "mediatek,mt8516-topckgen-cg";
+               reg = <0x10000000 0x1000>;
+               #clock-cells = <1>;
+       };
+
+       infracfg: clock-controller@10001000 {
+               compatible = "mediatek,mt8516-infracfg";
+               reg = <0x10001000 0x1000>;
+               #clock-cells = <1>;
+       };
+
+       apmixedsys: clock-controller@10018000 {
+               compatible = "mediatek,mt8516-apmixedsys";
+               reg = <0x10018000 0x710>;
+               #clock-cells = <1>;
+       };
+
+       gic: interrupt-controller@10310000 {
+               compatible = "arm,gic-400";
+               interrupt-controller;
+               #interrupt-cells = <3>;
+               interrupt-parent = <&gic>;
+               reg = <0x10310000 0x1000>,
+                     <0x10320000 0x1000>,
+                     <0x10340000 0x2000>,
+                     <0x10360000 0x2000>;
+               interrupts = <GIC_PPI 9
+                            (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+       };
+
+       sysirq: interrupt-controller@10200620 {
+               compatible = "mediatek,sysirq";
+               interrupt-controller;
+               #interrupt-cells = <3>;
+               interrupt-parent = <&gic>;
+               reg = <0x10200620 0x20>;
+       };
+
+       watchdog: watchdog@10007000 {
+               compatible = "mediatek,wdt";
+               reg = <0x10007000 0x1000>;
+               interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_FALLING>;
+               #reset-cells = <1>;
+               status = "disabled";
+       };
+
+       pinctrl: pinctrl@10005000 {
+               compatible = "mediatek,mt8516-pinctrl";
+               reg = <0x10005000 0x1000>;
+
+               gpio: gpio-controller {
+                       gpio-controller;
+                       #gpio-cells = <2>;
+               };
+       };
+
+       mmc0: mmc@11120000 {
+               compatible = "mediatek,mt8516-mmc";
+               reg = <0x11120000 0x1000>;
+               interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
+               clocks = <&topckgen_cg CLK_TOP_MSDC0>,
+                        <&topckgen CLK_TOP_AHB_INFRA_SEL>,
+                        <&topckgen_cg CLK_TOP_MSDC0_INFRA>;
+               clock-names = "source", "hclk", "source_cg";
+               status = "disabled";
+       };
+
+       uart0: serial@11005000 {
+               compatible = "mediatek,hsuart";
+               reg = <0x11005000 0x1000>;
+               reg-shift = <2>;
+               interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
+               clocks = <&topckgen CLK_TOP_UART0_SEL>,
+                        <&topckgen_cg CLK_TOP_UART0>;
+               clock-names = "baud","bus";
+               status = "disabled";
+       };
+};
index 7a733e9..b5e91d4 100644 (file)
@@ -31,6 +31,16 @@ config TARGET_MT7629
          including DDR3, crypto engine, 3x3 11n/ac Wi-Fi, Gigabit Ethernet,
          switch, USB3.0, PCIe, UART, SPI, I2C and PWM.
 
+config TARGET_MT8516
+       bool "MediaTek MT8516 SoC"
+       select ARM64
+       select ARCH_MISC_INIT
+       help
+         The MediaTek MT8516 is a ARM64-based SoC with a quad-core Cortex-A35.
+         including UART, SPI, USB2.0 and OTG, SD and MMC cards, NAND, PWM,
+         Ethernet, IR TX/RX, I2C, I2S, S/PDIF, and built-in Wi-Fi / Bluetooth combo
+         chip and several DDR3 and DDR4 options.
+
 endchoice
 
 source "board/mediatek/mt7623/Kconfig"
index b5d3a37..ea414dc 100644 (file)
@@ -5,3 +5,4 @@ obj-$(CONFIG_SPL_BUILD) += spl.o
 
 obj-$(CONFIG_TARGET_MT7623) += mt7623/
 obj-$(CONFIG_TARGET_MT7629) += mt7629/
+obj-$(CONFIG_TARGET_MT8516) += mt8516/
diff --git a/arch/arm/mach-mediatek/mt8516/Makefile b/arch/arm/mach-mediatek/mt8516/Makefile
new file mode 100644 (file)
index 0000000..886ab7e
--- /dev/null
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier:     GPL-2.0
+
+obj-y += init.o
diff --git a/arch/arm/mach-mediatek/mt8516/init.c b/arch/arm/mach-mediatek/mt8516/init.c
new file mode 100644 (file)
index 0000000..26a215a
--- /dev/null
@@ -0,0 +1,120 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ * Copyright (C) 2019 BayLibre, SAS
+ * Author: Fabien Parent <fparent@baylibre.com>
+ */
+
+#include <clk.h>
+#include <common.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <ram.h>
+#include <asm/arch/misc.h>
+#include <asm/armv8/mmu.h>
+#include <asm/sections.h>
+#include <dm/uclass.h>
+#include <linux/io.h>
+#include <dt-bindings/clock/mt8516-clk.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define WDOG_SWRST             0x10007014
+#define WDOG_SWRST_KEY         0x1209
+
+int dram_init(void)
+{
+       int ret;
+
+       ret = fdtdec_setup_memory_banksize();
+       if (ret)
+               return ret;
+
+       return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void)
+{
+       gd->bd->bi_dram[0].start = gd->ram_base;
+       gd->bd->bi_dram[0].size = gd->ram_size;
+
+       return 0;
+}
+
+int mtk_pll_early_init(void)
+{
+       unsigned long pll_rates[] = {
+               [CLK_APMIXED_ARMPLL] =   1300000000,
+               [CLK_APMIXED_MAINPLL] =  1501000000,
+               [CLK_APMIXED_UNIVPLL] =  1248000000,
+               [CLK_APMIXED_MMPLL] =     380000000,
+       };
+       struct udevice *dev;
+       int ret, i;
+
+       ret = uclass_get_device_by_driver(UCLASS_CLK,
+                       DM_GET_DRIVER(mtk_clk_apmixedsys), &dev);
+       if (ret)
+               return ret;
+
+       /* configure default rate then enable apmixedsys */
+       for (i = 0; i < ARRAY_SIZE(pll_rates); i++) {
+               struct clk clk = { .id = i, .dev = dev };
+
+               ret = clk_set_rate(&clk, pll_rates[i]);
+               if (ret)
+                       return ret;
+
+               ret = clk_enable(&clk);
+               if (ret)
+                       return ret;
+       }
+
+       return 0;
+}
+
+int mtk_soc_early_init(void)
+{
+       int ret;
+
+       /* initialize early clocks */
+       ret = mtk_pll_early_init();
+       if (ret)
+               return ret;
+
+       return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+       while (1) {
+               writel(WDOG_SWRST_KEY, WDOG_SWRST);
+               mdelay(5);
+       }
+}
+
+int print_cpuinfo(void)
+{
+       printf("CPU:   MediaTek MT8516\n");
+       return 0;
+}
+
+static struct mm_region mt8516_mem_map[] = {
+       {
+               /* DDR */
+               .virt = 0x40000000UL,
+               .phys = 0x40000000UL,
+               .size = 0x20000000UL,
+               .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
+       }, {
+               .virt = 0x00000000UL,
+               .phys = 0x00000000UL,
+               .size = 0x20000000UL,
+               .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+                        PTE_BLOCK_NON_SHARE |
+                        PTE_BLOCK_PXN | PTE_BLOCK_UXN
+       }, {
+               0,
+       }
+};
+struct mm_region *mem_map = mt8516_mem_map;