[SCEV] Support negative values in signed/unsigned predicate reasoning

There is a piece of logic that uses the fact that signed and unsigned
versions of the same predicate are equivalent when both values are
non-negative. It's also true when both of them are negative.

Differential Revision: https://reviews.llvm.org/D109957
Reviewed By: nikic

diff --git a/llvm/lib/Analysis/ScalarEvolution.cpp b/llvm/lib/Analysis/ScalarEvolution.cpp
index 0af91d3..09e98dc 100644 (file)
--- a/llvm/lib/Analysis/ScalarEvolution.cpp
+++ b/llvm/lib/Analysis/ScalarEvolution.cpp
@@ -10703,10 +10703,11 @@ bool ScalarEvolution::isImpliedCondBalancedTypes(
   }
 
   // Unsigned comparison is the same as signed comparison when both the operands
-  // are non-negative.
+  // are non-negative or negative.
   if (CmpInst::isUnsigned(FoundPred) &&
       CmpInst::getSignedPredicate(FoundPred) == Pred &&
-      isKnownNonNegative(FoundLHS) && isKnownNonNegative(FoundRHS))
+      ((isKnownNonNegative(FoundLHS) && isKnownNonNegative(FoundRHS)) ||
+       (isKnownNegative(FoundLHS) && isKnownNegative(FoundRHS))))
     return isImpliedCondOperands(Pred, LHS, RHS, FoundLHS, FoundRHS, Context);
 
   // Check if we can make progress by sharpening ranges.

diff --git a/llvm/test/Transforms/IndVarSimplify/negative_ranges.ll b/llvm/test/Transforms/IndVarSimplify/negative_ranges.ll
index 41b5b48..5db305a 100644 (file)
--- a/llvm/test/Transforms/IndVarSimplify/negative_ranges.ll
+++ b/llvm/test/Transforms/IndVarSimplify/negative_ranges.ll
@@ -53,7 +53,6 @@ side_exit:
   ret i32 0
 }
 
-; FIXME: 2nd check is implied by the 1st one as both values are negative.
 define i32 @test_02(i32* %p, i32* %s) {
 ; CHECK-LABEL: @test_02(
 ; CHECK-NEXT:  entry:
@@ -65,8 +64,7 @@ define i32 @test_02(i32* %p, i32* %s) {
 ; CHECK-NEXT:    [[C1:%.*]] = icmp ult i32 [[IV]], [[END]]
 ; CHECK-NEXT:    br i1 [[C1]], label [[GUARDED:%.*]], label [[SIDE_EXIT:%.*]]
 ; CHECK:       guarded:
-; CHECK-NEXT:    [[C2:%.*]] = icmp slt i32 [[IV]], [[END]]
-; CHECK-NEXT:    br i1 [[C2]], label [[BACKEDGE]], label [[SIDE_EXIT]]
+; CHECK-NEXT:    br i1 true, label [[BACKEDGE]], label [[SIDE_EXIT]]
 ; CHECK:       backedge:
 ; CHECK-NEXT:    [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
 ; CHECK-NEXT:    [[LOOP_COND:%.*]] = call i1 @cond()