radv: pass the pipeline key to the backend compilers

It exactly matches the shader keys now. Everything was copied from
the pipeline key to the shader keys.

There is still some work to completely remove radv_shader_variant_key.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13032>

diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp
index 6639d71..9dc15e3 100644 (file)
--- a/src/amd/compiler/aco_instruction_selection.cpp
+++ b/src/amd/compiler/aco_instruction_selection.cpp
@@ -5022,7 +5022,7 @@ visit_load_input(isel_context* ctx, nir_intrinsic_instr* instr)
       uint32_t attrib_stride = ctx->options->key.vs.vertex_attribute_strides[location];
       unsigned attrib_format = ctx->options->key.vs.vertex_attribute_formats[location];
       unsigned binding_align = ctx->options->key.vs.vertex_binding_align[attrib_binding];
-      enum ac_fetch_format alpha_adjust = ctx->options->key.vs.alpha_adjust[location];
+      enum ac_fetch_format alpha_adjust = ctx->options->key.vs.vertex_alpha_adjust[location];
 
       unsigned dfmt = attrib_format & 0xf;
       unsigned nfmt = (attrib_format >> 4) & 0x7;
@@ -5030,7 +5030,7 @@ visit_load_input(isel_context* ctx, nir_intrinsic_instr* instr)
 
       unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa) << component;
       unsigned num_channels = MIN2(util_last_bit(mask), vtx_info->num_channels);
-      bool post_shuffle = ctx->options->key.vs.post_shuffle & (1 << location);
+      bool post_shuffle = ctx->options->key.vs.vertex_post_shuffle & (1 << location);
       if (post_shuffle)
          num_channels = MAX2(num_channels, 3);
 
@@ -7388,9 +7388,9 @@ visit_load_sample_mask_in(isel_context* ctx, nir_intrinsic_instr* instr)
 {
    uint8_t log2_ps_iter_samples;
    if (ctx->program->info->ps.uses_sample_shading) {
-      log2_ps_iter_samples = util_logbase2(ctx->options->key.fs.num_samples);
+      log2_ps_iter_samples = util_logbase2(ctx->options->key.ps.num_samples);
    } else {
-      log2_ps_iter_samples = ctx->options->key.fs.log2_ps_iter_samples;
+      log2_ps_iter_samples = ctx->options->key.ps.log2_ps_iter_samples;
    }
 
    Builder bld(ctx->program, ctx->block);
@@ -8000,7 +8000,7 @@ visit_intrinsic(isel_context* ctx, nir_intrinsic_instr* instr)
    }
    case nir_intrinsic_load_barycentric_at_sample: {
       uint32_t sample_pos_offset = RING_PS_SAMPLE_POSITIONS * 16;
-      switch (ctx->options->key.fs.num_samples) {
+      switch (ctx->options->key.ps.num_samples) {
       case 2: sample_pos_offset += 1 << 3; break;
       case 4: sample_pos_offset += 3 << 3; break;
       case 8: sample_pos_offset += 7 << 3; break;
@@ -8899,7 +8899,7 @@ visit_intrinsic(isel_context* ctx, nir_intrinsic_instr* instr)
              ctx->shader->info.stage == MESA_SHADER_TESS_EVAL);
 
       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
-      bld.copy(Definition(dst), Operand::c32(ctx->args->options->key.tcs.input_vertices));
+      bld.copy(Definition(dst), Operand::c32(ctx->args->options->key.tcs.tess_input_vertices));
       break;
    }
    case nir_intrinsic_emit_vertex_with_counter: {
@@ -10987,10 +10987,10 @@ export_fs_mrt_color(isel_context* ctx, int slot)
 
    slot -= FRAG_RESULT_DATA0;
    target = V_008DFC_SQ_EXP_MRT + slot;
-   col_format = (ctx->options->key.fs.col_format >> (4 * slot)) & 0xf;
+   col_format = (ctx->options->key.ps.col_format >> (4 * slot)) & 0xf;
 
-   bool is_int8 = (ctx->options->key.fs.is_int8 >> slot) & 1;
-   bool is_int10 = (ctx->options->key.fs.is_int10 >> slot) & 1;
+   bool is_int8 = (ctx->options->key.ps.is_int8 >> slot) & 1;
+   bool is_int10 = (ctx->options->key.ps.is_int10 >> slot) & 1;
    bool is_16bit = values[0].regClass() == v2b;
 
    /* Replace NaN by zero (only 32-bit) to fix game bugs if requested. */

diff --git a/src/amd/vulkan/radv_nir_to_llvm.c b/src/amd/vulkan/radv_nir_to_llvm.c
index 5804c24..a29a7da 100644 (file)
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -259,7 +259,7 @@ load_sample_position(struct ac_shader_abi *abi, LLVMValueRef sample_id)
 
    ptr = LLVMBuildBitCast(ctx->ac.builder, ptr, ac_array_in_const_addr_space(ctx->ac.v2f32), "");
 
-   uint32_t sample_pos_offset = radv_get_sample_pos_offset(ctx->args->options->key.fs.num_samples);
+   uint32_t sample_pos_offset = radv_get_sample_pos_offset(ctx->args->options->key.ps.num_samples);
 
    sample_id = LLVMBuildAdd(ctx->ac.builder, sample_id,
                             LLVMConstInt(ctx->ac.i32, sample_pos_offset, false), "");
@@ -275,9 +275,9 @@ load_sample_mask_in(struct ac_shader_abi *abi)
    uint8_t log2_ps_iter_samples;
 
    if (ctx->args->shader_info->ps.uses_sample_shading) {
-      log2_ps_iter_samples = util_logbase2(ctx->args->options->key.fs.num_samples);
+      log2_ps_iter_samples = util_logbase2(ctx->args->options->key.ps.num_samples);
    } else {
-      log2_ps_iter_samples = ctx->args->options->key.fs.log2_ps_iter_samples;
+      log2_ps_iter_samples = ctx->args->options->key.ps.log2_ps_iter_samples;
    }
 
    LLVMValueRef result, sample_id;
@@ -716,9 +716,9 @@ load_vs_input(struct radv_shader_context *ctx, unsigned driver_location, LLVMTyp
    unsigned attrib_binding = ctx->args->options->key.vs.vertex_attribute_bindings[attrib_index];
    unsigned attrib_offset = ctx->args->options->key.vs.vertex_attribute_offsets[attrib_index];
    unsigned attrib_stride = ctx->args->options->key.vs.vertex_attribute_strides[attrib_index];
-   unsigned alpha_adjust = ctx->args->options->key.vs.alpha_adjust[attrib_index];
+   unsigned alpha_adjust = ctx->args->options->key.vs.vertex_alpha_adjust[attrib_index];
 
-   if (ctx->args->options->key.vs.post_shuffle & (1 << attrib_index)) {
+   if (ctx->args->options->key.vs.vertex_post_shuffle & (1 << attrib_index)) {
       /* Always load, at least, 3 channels for formats that need to be shuffled because X<->Z. */
       num_channels = MAX2(num_channels, 3);
    }
@@ -775,7 +775,7 @@ load_vs_input(struct radv_shader_context *ctx, unsigned driver_location, LLVMTyp
          ctx->ac.i32_0, ctx->ac.i32_0, num_channels, data_format, num_format, 0, true);
    }
 
-   if (ctx->args->options->key.vs.post_shuffle & (1 << attrib_index)) {
+   if (ctx->args->options->key.vs.vertex_post_shuffle & (1 << attrib_index)) {
       LLVMValueRef c[4];
       c[0] = ac_llvm_extract_elem(&ctx->ac, input, 2);
       c[1] = ac_llvm_extract_elem(&ctx->ac, input, 1);
@@ -899,9 +899,9 @@ si_llvm_init_export_args(struct radv_shader_context *ctx, LLVMValueRef *values,
    bool is_16bit = ac_get_type_size(LLVMTypeOf(values[0])) == 2;
    if (ctx->stage == MESA_SHADER_FRAGMENT) {
       unsigned index = target - V_008DFC_SQ_EXP_MRT;
-      unsigned col_format = (ctx->args->options->key.fs.col_format >> (4 * index)) & 0xf;
-      bool is_int8 = (ctx->args->options->key.fs.is_int8 >> index) & 1;
-      bool is_int10 = (ctx->args->options->key.fs.is_int10 >> index) & 1;
+      unsigned col_format = (ctx->args->options->key.ps.col_format >> (4 * index)) & 0xf;
+      bool is_int8 = (ctx->args->options->key.ps.is_int8 >> index) & 1;
+      bool is_int10 = (ctx->args->options->key.ps.is_int10 >> index) & 1;
 
       LLVMValueRef (*packf)(struct ac_llvm_context * ctx, LLVMValueRef args[2]) = NULL;
       LLVMValueRef (*packi)(struct ac_llvm_context * ctx, LLVMValueRef args[2], unsigned bits,

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 344a7e3..8144dff 100644 (file)
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -3618,7 +3618,7 @@ radv_create_shaders(struct radv_pipeline *pipeline, struct radv_device *device,
 
          pipeline->shaders[MESA_SHADER_FRAGMENT] = radv_shader_variant_compile(
             device, modules[MESA_SHADER_FRAGMENT], &nir[MESA_SHADER_FRAGMENT], 1, pipeline->layout,
-            keys + MESA_SHADER_FRAGMENT, infos + MESA_SHADER_FRAGMENT, keep_executable_info,
+            pipeline_key, infos + MESA_SHADER_FRAGMENT, keep_executable_info,
             keep_statistic_info, disable_optimizations, &binaries[MESA_SHADER_FRAGMENT]);
 
          radv_stop_feedback(stage_feedbacks[MESA_SHADER_FRAGMENT], false);
@@ -3634,7 +3634,7 @@ radv_create_shaders(struct radv_pipeline *pipeline, struct radv_device *device,
          radv_start_feedback(stage_feedbacks[MESA_SHADER_TESS_CTRL]);
 
          pipeline->shaders[MESA_SHADER_TESS_CTRL] = radv_shader_variant_compile(
-            device, modules[MESA_SHADER_TESS_CTRL], combined_nir, 2, pipeline->layout, key,
+            device, modules[MESA_SHADER_TESS_CTRL], combined_nir, 2, pipeline->layout, pipeline_key,
             &infos[MESA_SHADER_TESS_CTRL], keep_executable_info, keep_statistic_info,
             disable_optimizations, &binaries[MESA_SHADER_TESS_CTRL]);
 
@@ -3652,8 +3652,8 @@ radv_create_shaders(struct radv_pipeline *pipeline, struct radv_device *device,
          radv_start_feedback(stage_feedbacks[MESA_SHADER_GEOMETRY]);
 
          pipeline->shaders[MESA_SHADER_GEOMETRY] = radv_shader_variant_compile(
-            device, modules[MESA_SHADER_GEOMETRY], combined_nir, 2, pipeline->layout,
-            &keys[pre_stage], &infos[MESA_SHADER_GEOMETRY], keep_executable_info,
+            device, modules[MESA_SHADER_GEOMETRY], combined_nir, 2, pipeline->layout, pipeline_key,
+            &infos[MESA_SHADER_GEOMETRY], keep_executable_info,
             keep_statistic_info, disable_optimizations, &binaries[MESA_SHADER_GEOMETRY]);
 
          radv_stop_feedback(stage_feedbacks[MESA_SHADER_GEOMETRY], false);
@@ -3666,7 +3666,7 @@ radv_create_shaders(struct radv_pipeline *pipeline, struct radv_device *device,
          radv_start_feedback(stage_feedbacks[i]);
 
          pipeline->shaders[i] = radv_shader_variant_compile(
-            device, modules[i], &nir[i], 1, pipeline->layout, keys + i, infos + i,
+            device, modules[i], &nir[i], 1, pipeline->layout, pipeline_key, infos + i,
             keep_executable_info, keep_statistic_info, disable_optimizations, &binaries[i]);
 
          radv_stop_feedback(stage_feedbacks[i], false);

diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 162aff9..bd32e21 100644 (file)
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -347,45 +347,6 @@ struct radv_pipeline_cache {
    VkAllocationCallbacks alloc;
 };
 
-struct radv_pipeline_key {
-   uint32_t has_multiview_view_index : 1;
-   uint32_t optimisations_disabled : 1;
-
-   struct {
-      uint32_t instance_rate_inputs;
-      uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
-      uint8_t vertex_attribute_formats[MAX_VERTEX_ATTRIBS];
-      uint32_t vertex_attribute_bindings[MAX_VERTEX_ATTRIBS];
-      uint32_t vertex_attribute_offsets[MAX_VERTEX_ATTRIBS];
-      uint32_t vertex_attribute_strides[MAX_VERTEX_ATTRIBS];
-      uint8_t vertex_binding_align[MAX_VBS];
-      enum ac_fetch_format vertex_alpha_adjust[MAX_VERTEX_ATTRIBS];
-      uint32_t vertex_post_shuffle;
-      uint32_t provoking_vtx_last : 1;
-      uint8_t topology;
-   } vs;
-
-   struct {
-      unsigned tess_input_vertices;
-   } tcs;
-
-   struct {
-      uint32_t col_format;
-      uint32_t is_int8;
-      uint32_t is_int10;
-      uint8_t log2_ps_iter_samples;
-      uint8_t num_samples;
-   } ps;
-
-   struct {
-      /* Non-zero if a required subgroup size is specified via
-       * VK_EXT_subgroup_size_control.
-       */
-      uint8_t compute_subgroup_size;
-      bool require_full_subgroups;
-   } cs;
-};
-
 struct radv_shader_binary;
 struct radv_shader_variant;
 struct radv_pipeline_shader_stack_size;
@@ -1698,6 +1659,8 @@ struct radv_event {
 #define RADV_HASH_SHADER_ROBUST_BUFFER_ACCESS (1 << 14)
 #define RADV_HASH_SHADER_ROBUST_BUFFER_ACCESS2 (1 << 15)
 
+struct radv_pipeline_key;
+
 void radv_hash_shaders(unsigned char *hash, const VkPipelineShaderStageCreateInfo **stages,
                        const struct radv_pipeline_layout *layout,
                        const struct radv_pipeline_key *key, uint32_t flags);

diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index d9694fb..d1a2c73 100644 (file)
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -1633,7 +1633,7 @@ struct radv_shader_variant *
 radv_shader_variant_compile(struct radv_device *device, struct vk_shader_module *module,
                             struct nir_shader *const *shaders, int shader_count,
                             struct radv_pipeline_layout *layout,
-                            const struct radv_shader_variant_key *key,
+                            const struct radv_pipeline_key *key,
                             struct radv_shader_info *info, bool keep_shader_info,
                             bool keep_statistic_info, bool disable_optimizations,
                             struct radv_shader_binary **binary_out)

diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h
index ce9333c..abce1c9 100644 (file)
--- a/src/amd/vulkan/radv_shader.h
+++ b/src/amd/vulkan/radv_shader.h
@@ -113,6 +113,45 @@ struct radv_shader_variant_key {
    bool has_multiview_view_index;
 };
 
+struct radv_pipeline_key {
+   uint32_t has_multiview_view_index : 1;
+   uint32_t optimisations_disabled : 1;
+
+   struct {
+      uint32_t instance_rate_inputs;
+      uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
+      uint8_t vertex_attribute_formats[MAX_VERTEX_ATTRIBS];
+      uint32_t vertex_attribute_bindings[MAX_VERTEX_ATTRIBS];
+      uint32_t vertex_attribute_offsets[MAX_VERTEX_ATTRIBS];
+      uint32_t vertex_attribute_strides[MAX_VERTEX_ATTRIBS];
+      uint8_t vertex_binding_align[MAX_VBS];
+      enum ac_fetch_format vertex_alpha_adjust[MAX_VERTEX_ATTRIBS];
+      uint32_t vertex_post_shuffle;
+      uint32_t provoking_vtx_last : 1;
+      uint8_t topology;
+   } vs;
+
+   struct {
+      unsigned tess_input_vertices;
+   } tcs;
+
+   struct {
+      uint32_t col_format;
+      uint32_t is_int8;
+      uint32_t is_int10;
+      uint8_t log2_ps_iter_samples;
+      uint8_t num_samples;
+   } ps;
+
+   struct {
+      /* Non-zero if a required subgroup size is specified via
+       * VK_EXT_subgroup_size_control.
+       */
+      uint8_t compute_subgroup_size;
+      bool require_full_subgroups;
+   } cs;
+};
+
 enum radv_compiler_debug_level {
    RADV_COMPILER_DEBUG_LEVEL_PERFWARN,
    RADV_COMPILER_DEBUG_LEVEL_ERROR,
@@ -120,7 +159,7 @@ enum radv_compiler_debug_level {
 
 struct radv_nir_compiler_options {
    struct radv_pipeline_layout *layout;
-   struct radv_shader_variant_key key;
+   struct radv_pipeline_key key;
    bool explicit_scratch_args;
    bool clamp_shadow_reference;
    bool robust_buffer_access;
@@ -455,7 +494,7 @@ struct radv_shader_variant *radv_shader_variant_create(struct radv_device *devic
                                                        bool keep_shader_info);
 struct radv_shader_variant *radv_shader_variant_compile(
    struct radv_device *device, struct vk_shader_module *module, struct nir_shader *const *shaders,
-   int shader_count, struct radv_pipeline_layout *layout, const struct radv_shader_variant_key *key,
+   int shader_count, struct radv_pipeline_layout *layout, const struct radv_pipeline_key *key,
    struct radv_shader_info *info, bool keep_shader_info, bool keep_statistic_info,
    bool disable_optimizations, struct radv_shader_binary **binary_out);