if (!FS.empty())
ArchFS = (Twine(ArchFS) + "," + FS).str();
- std::string CPUName = std::string(CPU);
- if (CPUName.empty())
- CPUName = "generic";
+ if (CPU.empty())
+ CPU = "generic";
- return createX86MCSubtargetInfoImpl(TT, CPUName, ArchFS);
+ return createX86MCSubtargetInfoImpl(TT, CPU, ArchFS);
}
static MCInstrInfo *createX86MCInstrInfo() {
}
void X86Subtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
- std::string CPUName = std::string(CPU);
- if (CPUName.empty())
- CPUName = "generic";
+ if (CPU.empty())
+ CPU = "generic";
std::string FullFS = std::string(FS);
if (In64BitMode) {
FullFS = "+sse2";
// If no CPU was specified, enable 64bit feature to satisy later check.
- if (CPUName == "generic") {
+ if (CPU == "generic") {
if (!FullFS.empty())
FullFS = "+64bit," + FullFS;
else
}
// Parse features string and set the CPU.
- ParseSubtargetFeatures(CPUName, FullFS);
+ ParseSubtargetFeatures(CPU, FullFS);
// All CPUs that implement SSE4.2 or SSE4A support unaligned accesses of
// 16-bytes and under that are reasonably fast. These features were