dmaengine: stm32-dma: pass DMA_SxSCR value to stm32_dma_handle_chan_done()

stm32_dma_handle_chan_done() is called on Transfer Complete interrupt.
As DMA_SxSCR register is read in interrupt handler, pass the value as
parameter of stm32_dma_handle_chan_done(). Also return directly if
chan->desc is null to remove one ident level.
Then, stm32_dma_configure_next_sg() is doing something only if
Double-Buffer Mode (DBM) is enabled, so, check it is enabled prior calling
stm32_dma_configure_next_sg(), to remove one ident level in
stm32_dma_configure_next_sg().

Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com>
Link: https://lore.kernel.org/r/20220505115611.38845-3-amelie.delaunay@foss.st.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

diff --git a/drivers/dma/stm32-dma.c b/drivers/dma/stm32-dma.c
index 5afe420..eecd137 100644 (file)
--- a/drivers/dma/stm32-dma.c
+++ b/drivers/dma/stm32-dma.c
@@ -612,38 +612,38 @@ static void stm32_dma_configure_next_sg(struct stm32_dma_chan *chan)
        id = chan->id;
        dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(id));
 
-       if (dma_scr & STM32_DMA_SCR_DBM) {
-               sg_req = &chan->desc->sg_req[chan->next_sg];
-
-               if (dma_scr & STM32_DMA_SCR_CT) {
-                       dma_sm0ar = sg_req->chan_reg.dma_sm0ar;
-                       stm32_dma_write(dmadev, STM32_DMA_SM0AR(id), dma_sm0ar);
-                       dev_dbg(chan2dev(chan), "CT=1 <=> SM0AR: 0x%08x\n",
-                               stm32_dma_read(dmadev, STM32_DMA_SM0AR(id)));
-               } else {
-                       dma_sm1ar = sg_req->chan_reg.dma_sm1ar;
-                       stm32_dma_write(dmadev, STM32_DMA_SM1AR(id), dma_sm1ar);
-                       dev_dbg(chan2dev(chan), "CT=0 <=> SM1AR: 0x%08x\n",
-                               stm32_dma_read(dmadev, STM32_DMA_SM1AR(id)));
-               }
+       sg_req = &chan->desc->sg_req[chan->next_sg];
+
+       if (dma_scr & STM32_DMA_SCR_CT) {
+               dma_sm0ar = sg_req->chan_reg.dma_sm0ar;
+               stm32_dma_write(dmadev, STM32_DMA_SM0AR(id), dma_sm0ar);
+               dev_dbg(chan2dev(chan), "CT=1 <=> SM0AR: 0x%08x\n",
+                       stm32_dma_read(dmadev, STM32_DMA_SM0AR(id)));
+       } else {
+               dma_sm1ar = sg_req->chan_reg.dma_sm1ar;
+               stm32_dma_write(dmadev, STM32_DMA_SM1AR(id), dma_sm1ar);
+               dev_dbg(chan2dev(chan), "CT=0 <=> SM1AR: 0x%08x\n",
+                       stm32_dma_read(dmadev, STM32_DMA_SM1AR(id)));
        }
 }
 
-static void stm32_dma_handle_chan_done(struct stm32_dma_chan *chan)
+static void stm32_dma_handle_chan_done(struct stm32_dma_chan *chan, u32 scr)
 {
-       if (chan->desc) {
-               if (chan->desc->cyclic) {
-                       vchan_cyclic_callback(&chan->desc->vdesc);
-                       stm32_dma_sg_inc(chan);
+       if (!chan->desc)
+               return;
+
+       if (chan->desc->cyclic) {
+               vchan_cyclic_callback(&chan->desc->vdesc);
+               stm32_dma_sg_inc(chan);
+               if (scr & STM32_DMA_SCR_DBM)
                        stm32_dma_configure_next_sg(chan);
-               } else {
-                       chan->busy = false;
-                       if (chan->next_sg == chan->desc->num_sgs) {
-                               vchan_cookie_complete(&chan->desc->vdesc);
-                               chan->desc = NULL;
-                       }
-                       stm32_dma_start_transfer(chan);
+       } else {
+               chan->busy = false;
+               if (chan->next_sg == chan->desc->num_sgs) {
+                       vchan_cookie_complete(&chan->desc->vdesc);
+                       chan->desc = NULL;
                }
+               stm32_dma_start_transfer(chan);
        }
 }
 
@@ -680,7 +680,7 @@ static irqreturn_t stm32_dma_chan_irq(int irq, void *devid)
        if (status & STM32_DMA_TCI) {
                stm32_dma_irq_clear(chan, STM32_DMA_TCI);
                if (scr & STM32_DMA_SCR_TCIE)
-                       stm32_dma_handle_chan_done(chan);
+                       stm32_dma_handle_chan_done(chan, scr);
                status &= ~STM32_DMA_TCI;
        }