struct malone_fmt_mapping {
u32 pixelformat;
enum vpu_malone_format malone_format;
+ u32 is_disabled;
};
struct malone_scode_t {
u32 i;
for (i = 0; i < ARRAY_SIZE(fmt_mappings); i++) {
+ if (fmt_mappings[i].is_disabled)
+ continue;
if (pixelformat == fmt_mappings[i].pixelformat)
return fmt_mappings[i].malone_format;
}
return MALONE_FMT_NULL;
}
+bool vpu_malone_check_fmt(enum vpu_core_type type, u32 pixelfmt)
+{
+ if (!vpu_imx8q_check_fmt(type, pixelfmt))
+ return false;
+
+ if (pixelfmt == V4L2_PIX_FMT_NV12M_8L128 || pixelfmt == V4L2_PIX_FMT_NV12M_10BE_8L128)
+ return true;
+ if (vpu_malone_format_remap(pixelfmt) == MALONE_FMT_NULL)
+ return false;
+
+ return true;
+}
+
static void vpu_malone_set_stream_cfg(struct vpu_shared_addr *shared,
u32 instance,
enum vpu_malone_format malone_format)
int vpu_malone_post_cmd(struct vpu_shared_addr *shared, u32 instance);
int vpu_malone_init_instance(struct vpu_shared_addr *shared, u32 instance);
u32 vpu_malone_get_max_instance_count(struct vpu_shared_addr *shared);
+bool vpu_malone_check_fmt(enum vpu_core_type type, u32 pixelfmt);
#endif
},
[VPU_CORE_TYPE_DEC] = {
.check_codec = vpu_imx8q_check_codec,
- .check_fmt = vpu_imx8q_check_fmt,
+ .check_fmt = vpu_malone_check_fmt,
.boot_core = vpu_imx8q_boot_core,
.get_power_state = vpu_imx8q_get_power_state,
.on_firmware_loaded = vpu_imx8q_on_firmware_loaded,