spi: synquacer: DMSTART bit must not be set while transferring
authorMasahisa Kojima <masahisa.kojima@linaro.org>
Tue, 17 May 2022 08:41:38 +0000 (17:41 +0900)
committerTom Rini <trini@konsulko.com>
Fri, 10 Jun 2022 17:37:32 +0000 (13:37 -0400)
DMSTART bit must not be set while there is active transfer.
This commit sets the DMSTART bit only when the transfer begins.

Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Signed-off-by: Satoru Okamoto <okamoto.satoru@socionext.com>
Acked-by: Jassi Brar <jaswinder.singh@linaro.org>
drivers/spi/spi-synquacer.c

index f1422cf..5e1b3ae 100644 (file)
@@ -330,9 +330,11 @@ static int synquacer_spi_xfer(struct udevice *dev, unsigned int bitlen,
        writel(~0, priv->base + RXC);
 
        /* Trigger */
-       val = readl(priv->base + DMSTART);
-       val |= BIT(TRIGGER);
-       writel(val, priv->base + DMSTART);
+       if (flags & SPI_XFER_BEGIN) {
+               val = readl(priv->base + DMSTART);
+               val |= BIT(TRIGGER);
+               writel(val, priv->base + DMSTART);
+       }
 
        while (busy & (BIT(RXBIT) | BIT(TXBIT))) {
                if (priv->rx_words)