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sh: clock-cpg div4 set_rate() shift fix
author
Magnus Damm
<damm@opensource.se>
Fri, 19 Feb 2010 09:12:00 +0000
(09:12 +0000)
committer
Paul Mundt
<lethal@linux-sh.org>
Mon, 22 Feb 2010 10:11:19 +0000
(19:11 +0900)
Make sure the div4 bitfield is shifted according
to the enable_bit value in sh_clk_div4_set_rate().
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
arch/sh/kernel/cpu/clock-cpg.c
patch
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diff --git
a/arch/sh/kernel/cpu/clock-cpg.c
b/arch/sh/kernel/cpu/clock-cpg.c
index
2827abb
..
72a5e62
100644
(file)
--- a/
arch/sh/kernel/cpu/clock-cpg.c
+++ b/
arch/sh/kernel/cpu/clock-cpg.c
@@
-192,8
+192,8
@@
static int sh_clk_div4_set_rate(struct clk *clk, unsigned long rate, int algo_id
return idx;
value = __raw_readl(clk->enable_reg);
- value &= ~
0xf
;
- value |=
idx
;
+ value &= ~
(0xf << clk->enable_bit)
;
+ value |=
(idx << clk->enable_bit)
;
__raw_writel(value, clk->enable_reg);
return 0;