{
radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
+ /* radeon 7200 have stencil bug, DEC and INC_WRAP will actually both do DEC_WRAP,
+ and DEC_WRAP (and INVERT) will do INVERT. No way to get correct INC_WRAP and DEC,
+ but DEC_WRAP can be fixed by using DEC and INC_WRAP at least use INC. */
+
+ GLuint tempRADEON_STENCIL_FAIL_DEC_WRAP;
+ GLuint tempRADEON_STENCIL_FAIL_INC_WRAP;
+ GLuint tempRADEON_STENCIL_ZFAIL_DEC_WRAP;
+ GLuint tempRADEON_STENCIL_ZFAIL_INC_WRAP;
+ GLuint tempRADEON_STENCIL_ZPASS_DEC_WRAP;
+ GLuint tempRADEON_STENCIL_ZPASS_INC_WRAP;
+
+ if (rmesa->radeonScreen->chipset & RADEON_CHIPSET_BROKEN_STENCIL) {
+ tempRADEON_STENCIL_FAIL_DEC_WRAP = RADEON_STENCIL_FAIL_DEC;
+ tempRADEON_STENCIL_FAIL_INC_WRAP = RADEON_STENCIL_FAIL_INC;
+ tempRADEON_STENCIL_ZFAIL_DEC_WRAP = RADEON_STENCIL_ZFAIL_DEC;
+ tempRADEON_STENCIL_ZFAIL_INC_WRAP = RADEON_STENCIL_ZFAIL_INC;
+ tempRADEON_STENCIL_ZPASS_DEC_WRAP = RADEON_STENCIL_ZPASS_DEC;
+ tempRADEON_STENCIL_ZPASS_INC_WRAP = RADEON_STENCIL_ZPASS_INC;
+ }
+ else {
+ tempRADEON_STENCIL_FAIL_DEC_WRAP = RADEON_STENCIL_FAIL_DEC_WRAP;
+ tempRADEON_STENCIL_FAIL_INC_WRAP = RADEON_STENCIL_FAIL_INC_WRAP;
+ tempRADEON_STENCIL_ZFAIL_DEC_WRAP = RADEON_STENCIL_ZFAIL_DEC_WRAP;
+ tempRADEON_STENCIL_ZFAIL_INC_WRAP = RADEON_STENCIL_ZFAIL_INC_WRAP;
+ tempRADEON_STENCIL_ZPASS_DEC_WRAP = RADEON_STENCIL_ZPASS_DEC_WRAP;
+ tempRADEON_STENCIL_ZPASS_INC_WRAP = RADEON_STENCIL_ZPASS_INC_WRAP;
+ }
+
RADEON_STATECHANGE( rmesa, ctx );
rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] &= ~(RADEON_STENCIL_FAIL_MASK |
RADEON_STENCIL_ZFAIL_MASK |
case GL_DECR:
rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_FAIL_DEC;
break;
+ case GL_INCR_WRAP:
+ rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= tempRADEON_STENCIL_FAIL_INC_WRAP;
+ break;
+ case GL_DECR_WRAP:
+ rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= tempRADEON_STENCIL_FAIL_DEC_WRAP;
+ break;
case GL_INVERT:
rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_FAIL_INVERT;
break;
case GL_DECR:
rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_ZFAIL_DEC;
break;
+ case GL_INCR_WRAP:
+ rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= tempRADEON_STENCIL_ZFAIL_INC_WRAP;
+ break;
+ case GL_DECR_WRAP:
+ rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= tempRADEON_STENCIL_ZFAIL_DEC_WRAP;
+ break;
case GL_INVERT:
rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_ZFAIL_INVERT;
break;
case GL_DECR:
rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_ZPASS_DEC;
break;
+ case GL_INCR_WRAP:
+ rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= tempRADEON_STENCIL_ZPASS_INC_WRAP;
+ break;
+ case GL_DECR_WRAP:
+ rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= tempRADEON_STENCIL_ZPASS_DEC_WRAP;
+ break;
case GL_INVERT:
rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_ZPASS_INVERT;
break;
# define RADEON_STENCIL_FAIL_INC (3 << 16)
# define RADEON_STENCIL_FAIL_DEC (4 << 16)
# define RADEON_STENCIL_FAIL_INVERT (5 << 16)
+# define RADEON_STENCIL_FAIL_INC_WRAP (6 << 16)
+# define RADEON_STENCIL_FAIL_DEC_WRAP (7 << 16)
# define RADEON_STENCIL_FAIL_MASK (0x7 << 16)
# define RADEON_STENCIL_ZPASS_KEEP (0 << 20)
# define RADEON_STENCIL_ZPASS_ZERO (1 << 20)
# define RADEON_STENCIL_ZPASS_INC (3 << 20)
# define RADEON_STENCIL_ZPASS_DEC (4 << 20)
# define RADEON_STENCIL_ZPASS_INVERT (5 << 20)
+# define RADEON_STENCIL_ZPASS_INC_WRAP (6 << 20)
+# define RADEON_STENCIL_ZPASS_DEC_WRAP (7 << 20)
# define RADEON_STENCIL_ZPASS_MASK (0x7 << 20)
# define RADEON_STENCIL_ZFAIL_KEEP (0 << 24)
# define RADEON_STENCIL_ZFAIL_ZERO (1 << 24)
# define RADEON_STENCIL_ZFAIL_INC (3 << 24)
# define RADEON_STENCIL_ZFAIL_DEC (4 << 24)
# define RADEON_STENCIL_ZFAIL_INVERT (5 << 24)
+# define RADEON_STENCIL_ZFAIL_INC_WRAP (6 << 24)
+# define RADEON_STENCIL_ZFAIL_DEC_WRAP (7 << 24)
# define RADEON_STENCIL_ZFAIL_MASK (0x7 << 24)
# define RADEON_Z_COMPRESSION_ENABLE (1 << 28)
# define RADEON_FORCE_Z_DIRTY (1 << 29)