arm: socfpga: Restructure clock manager driver
authorLey Foon Tan <ley.foon.tan@intel.com>
Tue, 25 Apr 2017 18:44:33 +0000 (02:44 +0800)
committerMarek Vasut <marex@denx.de>
Thu, 18 May 2017 09:33:16 +0000 (11:33 +0200)
Restructure clock manager driver in the preparation to support A10.
Move the Gen5 specific code to _gen5 files.

- Change all uint32_t to u32 and change to use macro BIT(n) for bit shift.
- Check return value from wait_for_bit(). So change return type to int for
  cm_write_with_phase() and cm_basic_init().

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
arch/arm/mach-socfpga/Makefile
arch/arm/mach-socfpga/clock_manager.c
arch/arm/mach-socfpga/clock_manager_gen5.c [new file with mode: 0644]
arch/arm/mach-socfpga/include/mach/clock_manager.h
arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h [new file with mode: 0644]
arch/arm/mach-socfpga/spl.c

index 809cd47..b76de4c 100644 (file)
@@ -13,7 +13,8 @@ obj-y += misc.o timer.o reset_manager.o system_manager.o clock_manager.o \
 obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
 
 # QTS-generated config file wrappers
-obj-$(CONFIG_TARGET_SOCFPGA_GEN5)      += scan_manager.o wrap_pll_config.o
+obj-$(CONFIG_TARGET_SOCFPGA_GEN5)      += scan_manager.o wrap_pll_config.o \
+                                          clock_manager_gen5.o
 obj-$(CONFIG_SPL_BUILD) += wrap_iocsr_config.o wrap_pinmux_config.o    \
                           wrap_sdram_config.o
 CFLAGS_wrap_iocsr_config.o     += -I$(srctree)/board/$(BOARDDIR)
index 29e18f8..8051995 100644 (file)
@@ -1,10 +1,11 @@
 /*
- *  Copyright (C) 2013 Altera Corporation <www.altera.com>
+ *  Copyright (C) 2013-2017 Altera Corporation <www.altera.com>
  *
  * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
+#include <wait_bit.h>
 #include <asm/io.h>
 #include <asm/arch/clock_manager.h>
 
@@ -13,10 +14,10 @@ DECLARE_GLOBAL_DATA_PTR;
 static const struct socfpga_clock_manager *clock_manager_base =
        (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
 
-static void cm_wait_for_lock(uint32_t mask)
+void cm_wait_for_lock(u32 mask)
 {
-       register uint32_t inter_val;
-       uint32_t retry = 0;
+       u32 inter_val;
+       u32 retry = 0;
        do {
                inter_val = readl(&clock_manager_base->inter) & mask;
                if (inter_val == mask)
@@ -29,510 +30,10 @@ static void cm_wait_for_lock(uint32_t mask)
 }
 
 /* function to poll in the fsm busy bit */
-static void cm_wait_for_fsm(void)
+int cm_wait_for_fsm(void)
 {
-       while (readl(&clock_manager_base->stat) & CLKMGR_STAT_BUSY)
-               ;
-}
-
-/*
- * function to write the bypass register which requires a poll of the
- * busy bit
- */
-static void cm_write_bypass(uint32_t val)
-{
-       writel(val, &clock_manager_base->bypass);
-       cm_wait_for_fsm();
-}
-
-/* function to write the ctrl register which requires a poll of the busy bit */
-static void cm_write_ctrl(uint32_t val)
-{
-       writel(val, &clock_manager_base->ctrl);
-       cm_wait_for_fsm();
-}
-
-/* function to write a clock register that has phase information */
-static void cm_write_with_phase(uint32_t value,
-                               uint32_t reg_address, uint32_t mask)
-{
-       /* poll until phase is zero */
-       while (readl(reg_address) & mask)
-               ;
-
-       writel(value, reg_address);
-
-       while (readl(reg_address) & mask)
-               ;
-}
-
-/*
- * Setup clocks while making no assumptions about previous state of the clocks.
- *
- * Start by being paranoid and gate all sw managed clocks
- * Put all plls in bypass
- * Put all plls VCO registers back to reset value (bandgap power down).
- * Put peripheral and main pll src to reset value to avoid glitch.
- * Delay 5 us.
- * Deassert bandgap power down and set numerator and denominator
- * Start 7 us timer.
- * set internal dividers
- * Wait for 7 us timer.
- * Enable plls
- * Set external dividers while plls are locking
- * Wait for pll lock
- * Assert/deassert outreset all.
- * Take all pll's out of bypass
- * Clear safe mode
- * set source main and peripheral clocks
- * Ungate clocks
- */
-
-void cm_basic_init(const struct cm_config * const cfg)
-{
-       unsigned long end;
-
-       /* Start by being paranoid and gate all sw managed clocks */
-
-       /*
-        * We need to disable nandclk
-        * and then do another apb access before disabling
-        * gatting off the rest of the periperal clocks.
-        */
-       writel(~CLKMGR_PERPLLGRP_EN_NANDCLK_MASK &
-               readl(&clock_manager_base->per_pll.en),
-               &clock_manager_base->per_pll.en);
-
-       /* DO NOT GATE OFF DEBUG CLOCKS & BRIDGE CLOCKS */
-       writel(CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK |
-               CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK |
-               CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK |
-               CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK |
-               CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK |
-               CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK,
-               &clock_manager_base->main_pll.en);
-
-       writel(0, &clock_manager_base->sdr_pll.en);
-
-       /* now we can gate off the rest of the peripheral clocks */
-       writel(0, &clock_manager_base->per_pll.en);
-
-       /* Put all plls in bypass */
-       cm_write_bypass(CLKMGR_BYPASS_PERPLL | CLKMGR_BYPASS_SDRPLL |
-                       CLKMGR_BYPASS_MAINPLL);
-
-       /* Put all plls VCO registers back to reset value. */
-       writel(CLKMGR_MAINPLLGRP_VCO_RESET_VALUE &
-              ~CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK,
-              &clock_manager_base->main_pll.vco);
-       writel(CLKMGR_PERPLLGRP_VCO_RESET_VALUE &
-              ~CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK,
-              &clock_manager_base->per_pll.vco);
-       writel(CLKMGR_SDRPLLGRP_VCO_RESET_VALUE &
-              ~CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK,
-              &clock_manager_base->sdr_pll.vco);
-
-       /*
-        * The clocks to the flash devices and the L4_MAIN clocks can
-        * glitch when coming out of safe mode if their source values
-        * are different from their reset value.  So the trick it to
-        * put them back to their reset state, and change input
-        * after exiting safe mode but before ungating the clocks.
-        */
-       writel(CLKMGR_PERPLLGRP_SRC_RESET_VALUE,
-              &clock_manager_base->per_pll.src);
-       writel(CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE,
-              &clock_manager_base->main_pll.l4src);
-
-       /* read back for the required 5 us delay. */
-       readl(&clock_manager_base->main_pll.vco);
-       readl(&clock_manager_base->per_pll.vco);
-       readl(&clock_manager_base->sdr_pll.vco);
-
-
-       /*
-        * We made sure bgpwr down was assert for 5 us. Now deassert BG PWR DN
-        * with numerator and denominator.
-        */
-       writel(cfg->main_vco_base, &clock_manager_base->main_pll.vco);
-       writel(cfg->peri_vco_base, &clock_manager_base->per_pll.vco);
-       writel(cfg->sdram_vco_base, &clock_manager_base->sdr_pll.vco);
-
-       /*
-        * Time starts here. Must wait 7 us from
-        * BGPWRDN_SET(0) to VCO_ENABLE_SET(1).
-        */
-       end = timer_get_us() + 7;
-
-       /* main mpu */
-       writel(cfg->mpuclk, &clock_manager_base->main_pll.mpuclk);
-
-       /* altera group mpuclk */
-       writel(cfg->altera_grp_mpuclk, &clock_manager_base->altera.mpuclk);
-
-       /* main main clock */
-       writel(cfg->mainclk, &clock_manager_base->main_pll.mainclk);
-
-       /* main for dbg */
-       writel(cfg->dbgatclk, &clock_manager_base->main_pll.dbgatclk);
-
-       /* main for cfgs2fuser0clk */
-       writel(cfg->cfg2fuser0clk,
-              &clock_manager_base->main_pll.cfgs2fuser0clk);
-
-       /* Peri emac0 50 MHz default to RMII */
-       writel(cfg->emac0clk, &clock_manager_base->per_pll.emac0clk);
-
-       /* Peri emac1 50 MHz default to RMII */
-       writel(cfg->emac1clk, &clock_manager_base->per_pll.emac1clk);
-
-       /* Peri QSPI */
-       writel(cfg->mainqspiclk, &clock_manager_base->main_pll.mainqspiclk);
-
-       writel(cfg->perqspiclk, &clock_manager_base->per_pll.perqspiclk);
-
-       /* Peri pernandsdmmcclk */
-       writel(cfg->mainnandsdmmcclk,
-              &clock_manager_base->main_pll.mainnandsdmmcclk);
-
-       writel(cfg->pernandsdmmcclk,
-              &clock_manager_base->per_pll.pernandsdmmcclk);
-
-       /* Peri perbaseclk */
-       writel(cfg->perbaseclk, &clock_manager_base->per_pll.perbaseclk);
-
-       /* Peri s2fuser1clk */
-       writel(cfg->s2fuser1clk, &clock_manager_base->per_pll.s2fuser1clk);
-
-       /* 7 us must have elapsed before we can enable the VCO */
-       while (timer_get_us() < end)
-               ;
-
-       /* Enable vco */
-       /* main pll vco */
-       writel(cfg->main_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
-              &clock_manager_base->main_pll.vco);
-
-       /* periferal pll */
-       writel(cfg->peri_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
-              &clock_manager_base->per_pll.vco);
-
-       /* sdram pll vco */
-       writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
-              &clock_manager_base->sdr_pll.vco);
-
-       /* L3 MP and L3 SP */
-       writel(cfg->maindiv, &clock_manager_base->main_pll.maindiv);
-
-       writel(cfg->dbgdiv, &clock_manager_base->main_pll.dbgdiv);
-
-       writel(cfg->tracediv, &clock_manager_base->main_pll.tracediv);
-
-       /* L4 MP, L4 SP, can0, and can1 */
-       writel(cfg->perdiv, &clock_manager_base->per_pll.div);
-
-       writel(cfg->gpiodiv, &clock_manager_base->per_pll.gpiodiv);
-
-#define LOCKED_MASK \
-       (CLKMGR_INTER_SDRPLLLOCKED_MASK  | \
-       CLKMGR_INTER_PERPLLLOCKED_MASK  | \
-       CLKMGR_INTER_MAINPLLLOCKED_MASK)
-
-       cm_wait_for_lock(LOCKED_MASK);
-
-       /* write the sdram clock counters before toggling outreset all */
-       writel(cfg->ddrdqsclk & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK,
-              &clock_manager_base->sdr_pll.ddrdqsclk);
-
-       writel(cfg->ddr2xdqsclk & CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK,
-              &clock_manager_base->sdr_pll.ddr2xdqsclk);
-
-       writel(cfg->ddrdqclk & CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK,
-              &clock_manager_base->sdr_pll.ddrdqclk);
-
-       writel(cfg->s2fuser2clk & CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK,
-              &clock_manager_base->sdr_pll.s2fuser2clk);
-
-       /*
-        * after locking, but before taking out of bypass
-        * assert/deassert outresetall
-        */
-       uint32_t mainvco = readl(&clock_manager_base->main_pll.vco);
-
-       /* assert main outresetall */
-       writel(mainvco | CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK,
-              &clock_manager_base->main_pll.vco);
-
-       uint32_t periphvco = readl(&clock_manager_base->per_pll.vco);
-
-       /* assert pheriph outresetall */
-       writel(periphvco | CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK,
-              &clock_manager_base->per_pll.vco);
-
-       /* assert sdram outresetall */
-       writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN|
-               CLKMGR_SDRPLLGRP_VCO_OUTRESETALL,
-               &clock_manager_base->sdr_pll.vco);
-
-       /* deassert main outresetall */
-       writel(mainvco & ~CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK,
-              &clock_manager_base->main_pll.vco);
-
-       /* deassert pheriph outresetall */
-       writel(periphvco & ~CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK,
-              &clock_manager_base->per_pll.vco);
-
-       /* deassert sdram outresetall */
-       writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
-              &clock_manager_base->sdr_pll.vco);
-
-       /*
-        * now that we've toggled outreset all, all the clocks
-        * are aligned nicely; so we can change any phase.
-        */
-       cm_write_with_phase(cfg->ddrdqsclk,
-                           (uint32_t)&clock_manager_base->sdr_pll.ddrdqsclk,
-                           CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK);
-
-       /* SDRAM DDR2XDQSCLK */
-       cm_write_with_phase(cfg->ddr2xdqsclk,
-                           (uint32_t)&clock_manager_base->sdr_pll.ddr2xdqsclk,
-                           CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK);
-
-       cm_write_with_phase(cfg->ddrdqclk,
-                           (uint32_t)&clock_manager_base->sdr_pll.ddrdqclk,
-                           CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK);
-
-       cm_write_with_phase(cfg->s2fuser2clk,
-                           (uint32_t)&clock_manager_base->sdr_pll.s2fuser2clk,
-                           CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK);
-
-       /* Take all three PLLs out of bypass when safe mode is cleared. */
-       cm_write_bypass(0);
-
-       /* clear safe mode */
-       cm_write_ctrl(readl(&clock_manager_base->ctrl) | CLKMGR_CTRL_SAFEMODE);
-
-       /*
-        * now that safe mode is clear with clocks gated
-        * it safe to change the source mux for the flashes the the L4_MAIN
-        */
-       writel(cfg->persrc, &clock_manager_base->per_pll.src);
-       writel(cfg->l4src, &clock_manager_base->main_pll.l4src);
-
-       /* Now ungate non-hw-managed clocks */
-       writel(~0, &clock_manager_base->main_pll.en);
-       writel(~0, &clock_manager_base->per_pll.en);
-       writel(~0, &clock_manager_base->sdr_pll.en);
-
-       /* Clear the loss of lock bits (write 1 to clear) */
-       writel(CLKMGR_INTER_SDRPLLLOST_MASK | CLKMGR_INTER_PERPLLLOST_MASK |
-              CLKMGR_INTER_MAINPLLLOST_MASK,
-              &clock_manager_base->inter);
-}
-
-static unsigned int cm_get_main_vco_clk_hz(void)
-{
-       uint32_t reg, clock;
-
-       /* get the main VCO clock */
-       reg = readl(&clock_manager_base->main_pll.vco);
-       clock = cm_get_osc_clk_hz(1);
-       clock /= ((reg & CLKMGR_MAINPLLGRP_VCO_DENOM_MASK) >>
-                 CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) + 1;
-       clock *= ((reg & CLKMGR_MAINPLLGRP_VCO_NUMER_MASK) >>
-                 CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET) + 1;
-
-       return clock;
-}
-
-static unsigned int cm_get_per_vco_clk_hz(void)
-{
-       uint32_t reg, clock = 0;
-
-       /* identify PER PLL clock source */
-       reg = readl(&clock_manager_base->per_pll.vco);
-       reg = (reg & CLKMGR_PERPLLGRP_VCO_SSRC_MASK) >>
-             CLKMGR_PERPLLGRP_VCO_SSRC_OFFSET;
-       if (reg == CLKMGR_VCO_SSRC_EOSC1)
-               clock = cm_get_osc_clk_hz(1);
-       else if (reg == CLKMGR_VCO_SSRC_EOSC2)
-               clock = cm_get_osc_clk_hz(2);
-       else if (reg == CLKMGR_VCO_SSRC_F2S)
-               clock = cm_get_f2s_per_ref_clk_hz();
-
-       /* get the PER VCO clock */
-       reg = readl(&clock_manager_base->per_pll.vco);
-       clock /= ((reg & CLKMGR_PERPLLGRP_VCO_DENOM_MASK) >>
-                 CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET) + 1;
-       clock *= ((reg & CLKMGR_PERPLLGRP_VCO_NUMER_MASK) >>
-                 CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET) + 1;
-
-       return clock;
-}
-
-unsigned long cm_get_mpu_clk_hz(void)
-{
-       uint32_t reg, clock;
-
-       clock = cm_get_main_vco_clk_hz();
-
-       /* get the MPU clock */
-       reg = readl(&clock_manager_base->altera.mpuclk);
-       clock /= (reg + 1);
-       reg = readl(&clock_manager_base->main_pll.mpuclk);
-       clock /= (reg + 1);
-       return clock;
-}
-
-unsigned long cm_get_sdram_clk_hz(void)
-{
-       uint32_t reg, clock = 0;
-
-       /* identify SDRAM PLL clock source */
-       reg = readl(&clock_manager_base->sdr_pll.vco);
-       reg = (reg & CLKMGR_SDRPLLGRP_VCO_SSRC_MASK) >>
-             CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET;
-       if (reg == CLKMGR_VCO_SSRC_EOSC1)
-               clock = cm_get_osc_clk_hz(1);
-       else if (reg == CLKMGR_VCO_SSRC_EOSC2)
-               clock = cm_get_osc_clk_hz(2);
-       else if (reg == CLKMGR_VCO_SSRC_F2S)
-               clock = cm_get_f2s_sdr_ref_clk_hz();
-
-       /* get the SDRAM VCO clock */
-       reg = readl(&clock_manager_base->sdr_pll.vco);
-       clock /= ((reg & CLKMGR_SDRPLLGRP_VCO_DENOM_MASK) >>
-                 CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET) + 1;
-       clock *= ((reg & CLKMGR_SDRPLLGRP_VCO_NUMER_MASK) >>
-                 CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET) + 1;
-
-       /* get the SDRAM (DDR_DQS) clock */
-       reg = readl(&clock_manager_base->sdr_pll.ddrdqsclk);
-       reg = (reg & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK) >>
-             CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET;
-       clock /= (reg + 1);
-
-       return clock;
-}
-
-unsigned int cm_get_l4_sp_clk_hz(void)
-{
-       uint32_t reg, clock = 0;
-
-       /* identify the source of L4 SP clock */
-       reg = readl(&clock_manager_base->main_pll.l4src);
-       reg = (reg & CLKMGR_MAINPLLGRP_L4SRC_L4SP) >>
-             CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET;
-
-       if (reg == CLKMGR_L4_SP_CLK_SRC_MAINPLL) {
-               clock = cm_get_main_vco_clk_hz();
-
-               /* get the clock prior L4 SP divider (main clk) */
-               reg = readl(&clock_manager_base->altera.mainclk);
-               clock /= (reg + 1);
-               reg = readl(&clock_manager_base->main_pll.mainclk);
-               clock /= (reg + 1);
-       } else if (reg == CLKMGR_L4_SP_CLK_SRC_PERPLL) {
-               clock = cm_get_per_vco_clk_hz();
-
-               /* get the clock prior L4 SP divider (periph_base_clk) */
-               reg = readl(&clock_manager_base->per_pll.perbaseclk);
-               clock /= (reg + 1);
-       }
-
-       /* get the L4 SP clock which supplied to UART */
-       reg = readl(&clock_manager_base->main_pll.maindiv);
-       reg = (reg & CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_MASK) >>
-             CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET;
-       clock = clock / (1 << reg);
-
-       return clock;
-}
-
-unsigned int cm_get_mmc_controller_clk_hz(void)
-{
-       uint32_t reg, clock = 0;
-
-       /* identify the source of MMC clock */
-       reg = readl(&clock_manager_base->per_pll.src);
-       reg = (reg & CLKMGR_PERPLLGRP_SRC_SDMMC_MASK) >>
-             CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET;
-
-       if (reg == CLKMGR_SDMMC_CLK_SRC_F2S) {
-               clock = cm_get_f2s_per_ref_clk_hz();
-       } else if (reg == CLKMGR_SDMMC_CLK_SRC_MAIN) {
-               clock = cm_get_main_vco_clk_hz();
-
-               /* get the SDMMC clock */
-               reg = readl(&clock_manager_base->main_pll.mainnandsdmmcclk);
-               clock /= (reg + 1);
-       } else if (reg == CLKMGR_SDMMC_CLK_SRC_PER) {
-               clock = cm_get_per_vco_clk_hz();
-
-               /* get the SDMMC clock */
-               reg = readl(&clock_manager_base->per_pll.pernandsdmmcclk);
-               clock /= (reg + 1);
-       }
-
-       /* further divide by 4 as we have fixed divider at wrapper */
-       clock /= 4;
-       return clock;
-}
-
-unsigned int cm_get_qspi_controller_clk_hz(void)
-{
-       uint32_t reg, clock = 0;
-
-       /* identify the source of QSPI clock */
-       reg = readl(&clock_manager_base->per_pll.src);
-       reg = (reg & CLKMGR_PERPLLGRP_SRC_QSPI_MASK) >>
-             CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET;
-
-       if (reg == CLKMGR_QSPI_CLK_SRC_F2S) {
-               clock = cm_get_f2s_per_ref_clk_hz();
-       } else if (reg == CLKMGR_QSPI_CLK_SRC_MAIN) {
-               clock = cm_get_main_vco_clk_hz();
-
-               /* get the qspi clock */
-               reg = readl(&clock_manager_base->main_pll.mainqspiclk);
-               clock /= (reg + 1);
-       } else if (reg == CLKMGR_QSPI_CLK_SRC_PER) {
-               clock = cm_get_per_vco_clk_hz();
-
-               /* get the qspi clock */
-               reg = readl(&clock_manager_base->per_pll.perqspiclk);
-               clock /= (reg + 1);
-       }
-
-       return clock;
-}
-
-unsigned int cm_get_spi_controller_clk_hz(void)
-{
-       uint32_t reg, clock = 0;
-
-       clock = cm_get_per_vco_clk_hz();
-
-       /* get the clock prior L4 SP divider (periph_base_clk) */
-       reg = readl(&clock_manager_base->per_pll.perbaseclk);
-       clock /= (reg + 1);
-
-       return clock;
-}
-
-static void cm_print_clock_quick_summary(void)
-{
-       printf("MPU       %10ld kHz\n", cm_get_mpu_clk_hz() / 1000);
-       printf("DDR       %10ld kHz\n", cm_get_sdram_clk_hz() / 1000);
-       printf("EOSC1       %8d kHz\n", cm_get_osc_clk_hz(1) / 1000);
-       printf("EOSC2       %8d kHz\n", cm_get_osc_clk_hz(2) / 1000);
-       printf("F2S_SDR_REF %8d kHz\n", cm_get_f2s_sdr_ref_clk_hz() / 1000);
-       printf("F2S_PER_REF %8d kHz\n", cm_get_f2s_per_ref_clk_hz() / 1000);
-       printf("MMC         %8d kHz\n", cm_get_mmc_controller_clk_hz() / 1000);
-       printf("QSPI        %8d kHz\n", cm_get_qspi_controller_clk_hz() / 1000);
-       printf("UART        %8d kHz\n", cm_get_l4_sp_clk_hz() / 1000);
-       printf("SPI         %8d kHz\n", cm_get_spi_controller_clk_hz() / 1000);
+       return wait_for_bit(__func__, (const u32 *)&clock_manager_base->stat,
+                           CLKMGR_STAT_BUSY, false, 20000, false);
 }
 
 int set_cpu_clk_info(void)
diff --git a/arch/arm/mach-socfpga/clock_manager_gen5.c b/arch/arm/mach-socfpga/clock_manager_gen5.c
new file mode 100644 (file)
index 0000000..31fd510
--- /dev/null
@@ -0,0 +1,524 @@
+/*
+ *  Copyright (C) 2013-2017 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock_manager.h>
+#include <wait_bit.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct socfpga_clock_manager *clock_manager_base =
+       (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
+
+/*
+ * function to write the bypass register which requires a poll of the
+ * busy bit
+ */
+static void cm_write_bypass(u32 val)
+{
+       writel(val, &clock_manager_base->bypass);
+       cm_wait_for_fsm();
+}
+
+/* function to write the ctrl register which requires a poll of the busy bit */
+static void cm_write_ctrl(u32 val)
+{
+       writel(val, &clock_manager_base->ctrl);
+       cm_wait_for_fsm();
+}
+
+/* function to write a clock register that has phase information */
+static int cm_write_with_phase(u32 value, u32 reg_address, u32 mask)
+{
+       int ret;
+
+       /* poll until phase is zero */
+       ret = wait_for_bit(__func__, (const u32 *)reg_address, mask,
+                          false, 20000, false);
+       if (ret)
+               return ret;
+
+       writel(value, reg_address);
+
+       return wait_for_bit(__func__, (const u32 *)reg_address, mask,
+                           false, 20000, false);
+}
+
+/*
+ * Setup clocks while making no assumptions about previous state of the clocks.
+ *
+ * Start by being paranoid and gate all sw managed clocks
+ * Put all plls in bypass
+ * Put all plls VCO registers back to reset value (bandgap power down).
+ * Put peripheral and main pll src to reset value to avoid glitch.
+ * Delay 5 us.
+ * Deassert bandgap power down and set numerator and denominator
+ * Start 7 us timer.
+ * set internal dividers
+ * Wait for 7 us timer.
+ * Enable plls
+ * Set external dividers while plls are locking
+ * Wait for pll lock
+ * Assert/deassert outreset all.
+ * Take all pll's out of bypass
+ * Clear safe mode
+ * set source main and peripheral clocks
+ * Ungate clocks
+ */
+
+int cm_basic_init(const struct cm_config * const cfg)
+{
+       unsigned long end;
+       int ret;
+
+       /* Start by being paranoid and gate all sw managed clocks */
+
+       /*
+        * We need to disable nandclk
+        * and then do another apb access before disabling
+        * gatting off the rest of the periperal clocks.
+        */
+       writel(~CLKMGR_PERPLLGRP_EN_NANDCLK_MASK &
+               readl(&clock_manager_base->per_pll.en),
+               &clock_manager_base->per_pll.en);
+
+       /* DO NOT GATE OFF DEBUG CLOCKS & BRIDGE CLOCKS */
+       writel(CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK |
+               CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK |
+               CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK |
+               CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK |
+               CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK |
+               CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK,
+               &clock_manager_base->main_pll.en);
+
+       writel(0, &clock_manager_base->sdr_pll.en);
+
+       /* now we can gate off the rest of the peripheral clocks */
+       writel(0, &clock_manager_base->per_pll.en);
+
+       /* Put all plls in bypass */
+       cm_write_bypass(CLKMGR_BYPASS_PERPLL | CLKMGR_BYPASS_SDRPLL |
+                       CLKMGR_BYPASS_MAINPLL);
+
+       /* Put all plls VCO registers back to reset value. */
+       writel(CLKMGR_MAINPLLGRP_VCO_RESET_VALUE &
+              ~CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK,
+              &clock_manager_base->main_pll.vco);
+       writel(CLKMGR_PERPLLGRP_VCO_RESET_VALUE &
+              ~CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK,
+              &clock_manager_base->per_pll.vco);
+       writel(CLKMGR_SDRPLLGRP_VCO_RESET_VALUE &
+              ~CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK,
+              &clock_manager_base->sdr_pll.vco);
+
+       /*
+        * The clocks to the flash devices and the L4_MAIN clocks can
+        * glitch when coming out of safe mode if their source values
+        * are different from their reset value.  So the trick it to
+        * put them back to their reset state, and change input
+        * after exiting safe mode but before ungating the clocks.
+        */
+       writel(CLKMGR_PERPLLGRP_SRC_RESET_VALUE,
+              &clock_manager_base->per_pll.src);
+       writel(CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE,
+              &clock_manager_base->main_pll.l4src);
+
+       /* read back for the required 5 us delay. */
+       readl(&clock_manager_base->main_pll.vco);
+       readl(&clock_manager_base->per_pll.vco);
+       readl(&clock_manager_base->sdr_pll.vco);
+
+
+       /*
+        * We made sure bgpwr down was assert for 5 us. Now deassert BG PWR DN
+        * with numerator and denominator.
+        */
+       writel(cfg->main_vco_base, &clock_manager_base->main_pll.vco);
+       writel(cfg->peri_vco_base, &clock_manager_base->per_pll.vco);
+       writel(cfg->sdram_vco_base, &clock_manager_base->sdr_pll.vco);
+
+       /*
+        * Time starts here. Must wait 7 us from
+        * BGPWRDN_SET(0) to VCO_ENABLE_SET(1).
+        */
+       end = timer_get_us() + 7;
+
+       /* main mpu */
+       writel(cfg->mpuclk, &clock_manager_base->main_pll.mpuclk);
+
+       /* altera group mpuclk */
+       writel(cfg->altera_grp_mpuclk, &clock_manager_base->altera.mpuclk);
+
+       /* main main clock */
+       writel(cfg->mainclk, &clock_manager_base->main_pll.mainclk);
+
+       /* main for dbg */
+       writel(cfg->dbgatclk, &clock_manager_base->main_pll.dbgatclk);
+
+       /* main for cfgs2fuser0clk */
+       writel(cfg->cfg2fuser0clk,
+              &clock_manager_base->main_pll.cfgs2fuser0clk);
+
+       /* Peri emac0 50 MHz default to RMII */
+       writel(cfg->emac0clk, &clock_manager_base->per_pll.emac0clk);
+
+       /* Peri emac1 50 MHz default to RMII */
+       writel(cfg->emac1clk, &clock_manager_base->per_pll.emac1clk);
+
+       /* Peri QSPI */
+       writel(cfg->mainqspiclk, &clock_manager_base->main_pll.mainqspiclk);
+
+       writel(cfg->perqspiclk, &clock_manager_base->per_pll.perqspiclk);
+
+       /* Peri pernandsdmmcclk */
+       writel(cfg->mainnandsdmmcclk,
+              &clock_manager_base->main_pll.mainnandsdmmcclk);
+
+       writel(cfg->pernandsdmmcclk,
+              &clock_manager_base->per_pll.pernandsdmmcclk);
+
+       /* Peri perbaseclk */
+       writel(cfg->perbaseclk, &clock_manager_base->per_pll.perbaseclk);
+
+       /* Peri s2fuser1clk */
+       writel(cfg->s2fuser1clk, &clock_manager_base->per_pll.s2fuser1clk);
+
+       /* 7 us must have elapsed before we can enable the VCO */
+       while (timer_get_us() < end)
+               ;
+
+       /* Enable vco */
+       /* main pll vco */
+       writel(cfg->main_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
+              &clock_manager_base->main_pll.vco);
+
+       /* periferal pll */
+       writel(cfg->peri_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
+              &clock_manager_base->per_pll.vco);
+
+       /* sdram pll vco */
+       writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
+              &clock_manager_base->sdr_pll.vco);
+
+       /* L3 MP and L3 SP */
+       writel(cfg->maindiv, &clock_manager_base->main_pll.maindiv);
+
+       writel(cfg->dbgdiv, &clock_manager_base->main_pll.dbgdiv);
+
+       writel(cfg->tracediv, &clock_manager_base->main_pll.tracediv);
+
+       /* L4 MP, L4 SP, can0, and can1 */
+       writel(cfg->perdiv, &clock_manager_base->per_pll.div);
+
+       writel(cfg->gpiodiv, &clock_manager_base->per_pll.gpiodiv);
+
+       cm_wait_for_lock(LOCKED_MASK);
+
+       /* write the sdram clock counters before toggling outreset all */
+       writel(cfg->ddrdqsclk & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK,
+              &clock_manager_base->sdr_pll.ddrdqsclk);
+
+       writel(cfg->ddr2xdqsclk & CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK,
+              &clock_manager_base->sdr_pll.ddr2xdqsclk);
+
+       writel(cfg->ddrdqclk & CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK,
+              &clock_manager_base->sdr_pll.ddrdqclk);
+
+       writel(cfg->s2fuser2clk & CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK,
+              &clock_manager_base->sdr_pll.s2fuser2clk);
+
+       /*
+        * after locking, but before taking out of bypass
+        * assert/deassert outresetall
+        */
+       u32 mainvco = readl(&clock_manager_base->main_pll.vco);
+
+       /* assert main outresetall */
+       writel(mainvco | CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK,
+              &clock_manager_base->main_pll.vco);
+
+       u32 periphvco = readl(&clock_manager_base->per_pll.vco);
+
+       /* assert pheriph outresetall */
+       writel(periphvco | CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK,
+              &clock_manager_base->per_pll.vco);
+
+       /* assert sdram outresetall */
+       writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN|
+               CLKMGR_SDRPLLGRP_VCO_OUTRESETALL,
+               &clock_manager_base->sdr_pll.vco);
+
+       /* deassert main outresetall */
+       writel(mainvco & ~CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK,
+              &clock_manager_base->main_pll.vco);
+
+       /* deassert pheriph outresetall */
+       writel(periphvco & ~CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK,
+              &clock_manager_base->per_pll.vco);
+
+       /* deassert sdram outresetall */
+       writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
+              &clock_manager_base->sdr_pll.vco);
+
+       /*
+        * now that we've toggled outreset all, all the clocks
+        * are aligned nicely; so we can change any phase.
+        */
+       ret = cm_write_with_phase(cfg->ddrdqsclk,
+                                 (u32)&clock_manager_base->sdr_pll.ddrdqsclk,
+                                 CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK);
+       if (ret)
+               return ret;
+
+       /* SDRAM DDR2XDQSCLK */
+       ret = cm_write_with_phase(cfg->ddr2xdqsclk,
+                                 (u32)&clock_manager_base->sdr_pll.ddr2xdqsclk,
+                                 CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK);
+       if (ret)
+               return ret;
+
+       ret = cm_write_with_phase(cfg->ddrdqclk,
+                                 (u32)&clock_manager_base->sdr_pll.ddrdqclk,
+                                 CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK);
+       if (ret)
+               return ret;
+
+       ret = cm_write_with_phase(cfg->s2fuser2clk,
+                                 (u32)&clock_manager_base->sdr_pll.s2fuser2clk,
+                                 CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK);
+       if (ret)
+               return ret;
+
+       /* Take all three PLLs out of bypass when safe mode is cleared. */
+       cm_write_bypass(0);
+
+       /* clear safe mode */
+       cm_write_ctrl(readl(&clock_manager_base->ctrl) | CLKMGR_CTRL_SAFEMODE);
+
+       /*
+        * now that safe mode is clear with clocks gated
+        * it safe to change the source mux for the flashes the the L4_MAIN
+        */
+       writel(cfg->persrc, &clock_manager_base->per_pll.src);
+       writel(cfg->l4src, &clock_manager_base->main_pll.l4src);
+
+       /* Now ungate non-hw-managed clocks */
+       writel(~0, &clock_manager_base->main_pll.en);
+       writel(~0, &clock_manager_base->per_pll.en);
+       writel(~0, &clock_manager_base->sdr_pll.en);
+
+       /* Clear the loss of lock bits (write 1 to clear) */
+       writel(CLKMGR_INTER_SDRPLLLOST_MASK | CLKMGR_INTER_PERPLLLOST_MASK |
+              CLKMGR_INTER_MAINPLLLOST_MASK,
+              &clock_manager_base->inter);
+
+       return 0;
+}
+
+static unsigned int cm_get_main_vco_clk_hz(void)
+{
+       u32 reg, clock;
+
+       /* get the main VCO clock */
+       reg = readl(&clock_manager_base->main_pll.vco);
+       clock = cm_get_osc_clk_hz(1);
+       clock /= ((reg & CLKMGR_MAINPLLGRP_VCO_DENOM_MASK) >>
+                 CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) + 1;
+       clock *= ((reg & CLKMGR_MAINPLLGRP_VCO_NUMER_MASK) >>
+                 CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET) + 1;
+
+       return clock;
+}
+
+static unsigned int cm_get_per_vco_clk_hz(void)
+{
+       u32 reg, clock = 0;
+
+       /* identify PER PLL clock source */
+       reg = readl(&clock_manager_base->per_pll.vco);
+       reg = (reg & CLKMGR_PERPLLGRP_VCO_SSRC_MASK) >>
+             CLKMGR_PERPLLGRP_VCO_SSRC_OFFSET;
+       if (reg == CLKMGR_VCO_SSRC_EOSC1)
+               clock = cm_get_osc_clk_hz(1);
+       else if (reg == CLKMGR_VCO_SSRC_EOSC2)
+               clock = cm_get_osc_clk_hz(2);
+       else if (reg == CLKMGR_VCO_SSRC_F2S)
+               clock = cm_get_f2s_per_ref_clk_hz();
+
+       /* get the PER VCO clock */
+       reg = readl(&clock_manager_base->per_pll.vco);
+       clock /= ((reg & CLKMGR_PERPLLGRP_VCO_DENOM_MASK) >>
+                 CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET) + 1;
+       clock *= ((reg & CLKMGR_PERPLLGRP_VCO_NUMER_MASK) >>
+                 CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET) + 1;
+
+       return clock;
+}
+
+unsigned long cm_get_mpu_clk_hz(void)
+{
+       u32 reg, clock;
+
+       clock = cm_get_main_vco_clk_hz();
+
+       /* get the MPU clock */
+       reg = readl(&clock_manager_base->altera.mpuclk);
+       clock /= (reg + 1);
+       reg = readl(&clock_manager_base->main_pll.mpuclk);
+       clock /= (reg + 1);
+       return clock;
+}
+
+unsigned long cm_get_sdram_clk_hz(void)
+{
+       u32 reg, clock = 0;
+
+       /* identify SDRAM PLL clock source */
+       reg = readl(&clock_manager_base->sdr_pll.vco);
+       reg = (reg & CLKMGR_SDRPLLGRP_VCO_SSRC_MASK) >>
+             CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET;
+       if (reg == CLKMGR_VCO_SSRC_EOSC1)
+               clock = cm_get_osc_clk_hz(1);
+       else if (reg == CLKMGR_VCO_SSRC_EOSC2)
+               clock = cm_get_osc_clk_hz(2);
+       else if (reg == CLKMGR_VCO_SSRC_F2S)
+               clock = cm_get_f2s_sdr_ref_clk_hz();
+
+       /* get the SDRAM VCO clock */
+       reg = readl(&clock_manager_base->sdr_pll.vco);
+       clock /= ((reg & CLKMGR_SDRPLLGRP_VCO_DENOM_MASK) >>
+                 CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET) + 1;
+       clock *= ((reg & CLKMGR_SDRPLLGRP_VCO_NUMER_MASK) >>
+                 CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET) + 1;
+
+       /* get the SDRAM (DDR_DQS) clock */
+       reg = readl(&clock_manager_base->sdr_pll.ddrdqsclk);
+       reg = (reg & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK) >>
+             CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET;
+       clock /= (reg + 1);
+
+       return clock;
+}
+
+unsigned int cm_get_l4_sp_clk_hz(void)
+{
+       u32 reg, clock = 0;
+
+       /* identify the source of L4 SP clock */
+       reg = readl(&clock_manager_base->main_pll.l4src);
+       reg = (reg & CLKMGR_MAINPLLGRP_L4SRC_L4SP) >>
+             CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET;
+
+       if (reg == CLKMGR_L4_SP_CLK_SRC_MAINPLL) {
+               clock = cm_get_main_vco_clk_hz();
+
+               /* get the clock prior L4 SP divider (main clk) */
+               reg = readl(&clock_manager_base->altera.mainclk);
+               clock /= (reg + 1);
+               reg = readl(&clock_manager_base->main_pll.mainclk);
+               clock /= (reg + 1);
+       } else if (reg == CLKMGR_L4_SP_CLK_SRC_PERPLL) {
+               clock = cm_get_per_vco_clk_hz();
+
+               /* get the clock prior L4 SP divider (periph_base_clk) */
+               reg = readl(&clock_manager_base->per_pll.perbaseclk);
+               clock /= (reg + 1);
+       }
+
+       /* get the L4 SP clock which supplied to UART */
+       reg = readl(&clock_manager_base->main_pll.maindiv);
+       reg = (reg & CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_MASK) >>
+             CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET;
+       clock = clock / (1 << reg);
+
+       return clock;
+}
+
+unsigned int cm_get_mmc_controller_clk_hz(void)
+{
+       u32 reg, clock = 0;
+
+       /* identify the source of MMC clock */
+       reg = readl(&clock_manager_base->per_pll.src);
+       reg = (reg & CLKMGR_PERPLLGRP_SRC_SDMMC_MASK) >>
+             CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET;
+
+       if (reg == CLKMGR_SDMMC_CLK_SRC_F2S) {
+               clock = cm_get_f2s_per_ref_clk_hz();
+       } else if (reg == CLKMGR_SDMMC_CLK_SRC_MAIN) {
+               clock = cm_get_main_vco_clk_hz();
+
+               /* get the SDMMC clock */
+               reg = readl(&clock_manager_base->main_pll.mainnandsdmmcclk);
+               clock /= (reg + 1);
+       } else if (reg == CLKMGR_SDMMC_CLK_SRC_PER) {
+               clock = cm_get_per_vco_clk_hz();
+
+               /* get the SDMMC clock */
+               reg = readl(&clock_manager_base->per_pll.pernandsdmmcclk);
+               clock /= (reg + 1);
+       }
+
+       /* further divide by 4 as we have fixed divider at wrapper */
+       clock /= 4;
+       return clock;
+}
+
+unsigned int cm_get_qspi_controller_clk_hz(void)
+{
+       u32 reg, clock = 0;
+
+       /* identify the source of QSPI clock */
+       reg = readl(&clock_manager_base->per_pll.src);
+       reg = (reg & CLKMGR_PERPLLGRP_SRC_QSPI_MASK) >>
+             CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET;
+
+       if (reg == CLKMGR_QSPI_CLK_SRC_F2S) {
+               clock = cm_get_f2s_per_ref_clk_hz();
+       } else if (reg == CLKMGR_QSPI_CLK_SRC_MAIN) {
+               clock = cm_get_main_vco_clk_hz();
+
+               /* get the qspi clock */
+               reg = readl(&clock_manager_base->main_pll.mainqspiclk);
+               clock /= (reg + 1);
+       } else if (reg == CLKMGR_QSPI_CLK_SRC_PER) {
+               clock = cm_get_per_vco_clk_hz();
+
+               /* get the qspi clock */
+               reg = readl(&clock_manager_base->per_pll.perqspiclk);
+               clock /= (reg + 1);
+       }
+
+       return clock;
+}
+
+unsigned int cm_get_spi_controller_clk_hz(void)
+{
+       u32 reg, clock = 0;
+
+       clock = cm_get_per_vco_clk_hz();
+
+       /* get the clock prior L4 SP divider (periph_base_clk) */
+       reg = readl(&clock_manager_base->per_pll.perbaseclk);
+       clock /= (reg + 1);
+
+       return clock;
+}
+
+void cm_print_clock_quick_summary(void)
+{
+       printf("MPU       %10ld kHz\n", cm_get_mpu_clk_hz() / 1000);
+       printf("DDR       %10ld kHz\n", cm_get_sdram_clk_hz() / 1000);
+       printf("EOSC1       %8d kHz\n", cm_get_osc_clk_hz(1) / 1000);
+       printf("EOSC2       %8d kHz\n", cm_get_osc_clk_hz(2) / 1000);
+       printf("F2S_SDR_REF %8d kHz\n", cm_get_f2s_sdr_ref_clk_hz() / 1000);
+       printf("F2S_PER_REF %8d kHz\n", cm_get_f2s_per_ref_clk_hz() / 1000);
+       printf("MMC         %8d kHz\n", cm_get_mmc_controller_clk_hz() / 1000);
+       printf("QSPI        %8d kHz\n", cm_get_qspi_controller_clk_hz() / 1000);
+       printf("UART        %8d kHz\n", cm_get_l4_sp_clk_hz() / 1000);
+       printf("SPI         %8d kHz\n", cm_get_spi_controller_clk_hz() / 1000);
+}
index 803c926..b076497 100644 (file)
 /*
- *  Copyright (C) 2013 Altera Corporation <www.altera.com>
+ *  Copyright (C) 2013-2017 Altera Corporation <www.altera.com>
  *
  * SPDX-License-Identifier:    GPL-2.0+
  */
 
-#ifndef        _CLOCK_MANAGER_H_
-#define        _CLOCK_MANAGER_H_
+#ifndef _CLOCK_MANAGER_H_
+#define _CLOCK_MANAGER_H_
 
 #ifndef __ASSEMBLER__
-/* Clock speed accessors */
-unsigned long cm_get_mpu_clk_hz(void);
-unsigned long cm_get_sdram_clk_hz(void);
-unsigned int cm_get_l4_sp_clk_hz(void);
-unsigned int cm_get_mmc_controller_clk_hz(void);
-unsigned int cm_get_qspi_controller_clk_hz(void);
-unsigned int cm_get_spi_controller_clk_hz(void);
-const unsigned int cm_get_osc_clk_hz(const int osc);
-const unsigned int cm_get_f2s_per_ref_clk_hz(void);
-const unsigned int cm_get_f2s_sdr_ref_clk_hz(void);
-
-/* Clock configuration accessors */
-const struct cm_config * const cm_get_default_config(void);
+void cm_wait_for_lock(u32 mask);
+int cm_wait_for_fsm(void);
+void cm_print_clock_quick_summary(void);
 #endif
 
-struct cm_config {
-       /* main group */
-       uint32_t main_vco_base;
-       uint32_t mpuclk;
-       uint32_t mainclk;
-       uint32_t dbgatclk;
-       uint32_t mainqspiclk;
-       uint32_t mainnandsdmmcclk;
-       uint32_t cfg2fuser0clk;
-       uint32_t maindiv;
-       uint32_t dbgdiv;
-       uint32_t tracediv;
-       uint32_t l4src;
-
-       /* peripheral group */
-       uint32_t peri_vco_base;
-       uint32_t emac0clk;
-       uint32_t emac1clk;
-       uint32_t perqspiclk;
-       uint32_t pernandsdmmcclk;
-       uint32_t perbaseclk;
-       uint32_t s2fuser1clk;
-       uint32_t perdiv;
-       uint32_t gpiodiv;
-       uint32_t persrc;
-
-       /* sdram pll group */
-       uint32_t sdram_vco_base;
-       uint32_t ddrdqsclk;
-       uint32_t ddr2xdqsclk;
-       uint32_t ddrdqclk;
-       uint32_t s2fuser2clk;
-
-       /* altera group */
-       uint32_t altera_grp_mpuclk;
-};
-
-void cm_basic_init(const struct cm_config * const cfg);
-
-struct socfpga_clock_manager_main_pll {
-       u32     vco;
-       u32     misc;
-       u32     mpuclk;
-       u32     mainclk;
-       u32     dbgatclk;
-       u32     mainqspiclk;
-       u32     mainnandsdmmcclk;
-       u32     cfgs2fuser0clk;
-       u32     en;
-       u32     maindiv;
-       u32     dbgdiv;
-       u32     tracediv;
-       u32     l4src;
-       u32     stat;
-       u32     _pad_0x38_0x40[2];
-};
-
-struct socfpga_clock_manager_per_pll {
-       u32     vco;
-       u32     misc;
-       u32     emac0clk;
-       u32     emac1clk;
-       u32     perqspiclk;
-       u32     pernandsdmmcclk;
-       u32     perbaseclk;
-       u32     s2fuser1clk;
-       u32     en;
-       u32     div;
-       u32     gpiodiv;
-       u32     src;
-       u32     stat;
-       u32     _pad_0x34_0x40[3];
-};
-
-struct socfpga_clock_manager_sdr_pll {
-       u32     vco;
-       u32     ctrl;
-       u32     ddrdqsclk;
-       u32     ddr2xdqsclk;
-       u32     ddrdqclk;
-       u32     s2fuser2clk;
-       u32     en;
-       u32     stat;
-};
-
-struct socfpga_clock_manager_altera {
-       u32     mpuclk;
-       u32     mainclk;
-};
-
-struct socfpga_clock_manager {
-       u32     ctrl;
-       u32     bypass;
-       u32     inter;
-       u32     intren;
-       u32     dbctrl;
-       u32     stat;
-       u32     _pad_0x18_0x3f[10];
-       struct socfpga_clock_manager_main_pll main_pll;
-       struct socfpga_clock_manager_per_pll per_pll;
-       struct socfpga_clock_manager_sdr_pll sdr_pll;
-       struct socfpga_clock_manager_altera altera;
-       u32     _pad_0xe8_0x200[70];
-};
-
-#define CLKMGR_CTRL_SAFEMODE                           (1 << 0)
-#define CLKMGR_CTRL_SAFEMODE_OFFSET                    0
-
-#define CLKMGR_BYPASS_PERPLLSRC                                (1 << 4)
-#define CLKMGR_BYPASS_PERPLLSRC_OFFSET                 4
-#define CLKMGR_BYPASS_PERPLL                           (1 << 3)
-#define CLKMGR_BYPASS_PERPLL_OFFSET                    3
-#define CLKMGR_BYPASS_SDRPLLSRC                                (1 << 2)
-#define CLKMGR_BYPASS_SDRPLLSRC_OFFSET                 2
-#define CLKMGR_BYPASS_SDRPLL                           (1 << 1)
-#define CLKMGR_BYPASS_SDRPLL_OFFSET                    1
-#define CLKMGR_BYPASS_MAINPLL                          (1 << 0)
-#define CLKMGR_BYPASS_MAINPLL_OFFSET                   0
-
-#define CLKMGR_INTER_SDRPLLLOCKED_MASK                 0x00000100
-#define CLKMGR_INTER_PERPLLLOCKED_MASK                 0x00000080
-#define CLKMGR_INTER_MAINPLLLOCKED_MASK                        0x00000040
-#define CLKMGR_INTER_PERPLLLOST_MASK                   0x00000010
-#define CLKMGR_INTER_SDRPLLLOST_MASK                   0x00000020
-#define CLKMGR_INTER_MAINPLLLOST_MASK                  0x00000008
-
-#define CLKMGR_STAT_BUSY                               (1 << 0)
-
-/* Main PLL */
-#define CLKMGR_MAINPLLGRP_VCO_BGPWRDN                  (1 << 0)
-#define CLKMGR_MAINPLLGRP_VCO_BGPWRDN_OFFSET           0
-#define CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET             16
-#define CLKMGR_MAINPLLGRP_VCO_DENOM_MASK               0x003f0000
-#define CLKMGR_MAINPLLGRP_VCO_EN                       (1 << 1)
-#define CLKMGR_MAINPLLGRP_VCO_EN_OFFSET                        1
-#define CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET             3
-#define CLKMGR_MAINPLLGRP_VCO_NUMER_MASK               0x0000fff8
-#define CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK         0x01000000
-#define CLKMGR_MAINPLLGRP_VCO_PWRDN                    (1 << 2)
-#define CLKMGR_MAINPLLGRP_VCO_PWRDN_OFFSET             2
-#define CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK           0x80000000
-#define CLKMGR_MAINPLLGRP_VCO_RESET_VALUE              0x8001000d
-
-#define CLKMGR_MAINPLLGRP_MPUCLK_CNT_OFFSET            0
-#define CLKMGR_MAINPLLGRP_MPUCLK_CNT_MASK              0x000001ff
-
-#define CLKMGR_MAINPLLGRP_MAINCLK_CNT_OFFSET           0
-#define CLKMGR_MAINPLLGRP_MAINCLK_CNT_MASK             0x000001ff
-
-#define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_OFFSET          0
-#define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_MASK            0x000001ff
-
-#define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_OFFSET       0
-#define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_MASK         0x000001ff
-
-#define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_OFFSET  0
-#define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_MASK    0x000001ff
-
-#define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_OFFSET    0
-#define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_MASK      0x000001ff
-
-#define CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK             0x00000010
-#define CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK               0x00000020
-#define CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK          0x00000080
-#define CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK          0x00000040
-#define CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK              0x00000004
-#define CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK          0x00000200
-
-#define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_OFFSET       0
-#define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_MASK         0x00000003
-#define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_OFFSET       2
-#define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_MASK         0x0000000c
-#define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_OFFSET       4
-#define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_MASK         0x00000070
-#define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET       7
-#define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_MASK         0x00000380
-
-#define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_OFFSET       0
-#define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_MASK         0x00000003
-#define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_OFFSET         2
-#define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_MASK           0x0000000c
-
-#define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_OFFSET     0
-#define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_MASK       0x00000007
-
-#define CLKMGR_MAINPLLGRP_L4SRC_L4MP                   (1 << 0)
-#define CLKMGR_MAINPLLGRP_L4SRC_L4MP_OFFSET            0
-#define CLKMGR_MAINPLLGRP_L4SRC_L4SP                   (1 << 1)
-#define CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET            1
-#define CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE            0x00000000
-#define CLKMGR_L4_SP_CLK_SRC_MAINPLL                   0x0
-#define CLKMGR_L4_SP_CLK_SRC_PERPLL                    0x1
-
-/* Per PLL */
-#define CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET              16
-#define CLKMGR_PERPLLGRP_VCO_DENOM_MASK                        0x003f0000
-#define CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET              3
-#define CLKMGR_PERPLLGRP_VCO_NUMER_MASK                        0x0000fff8
-#define CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK          0x01000000
-#define CLKMGR_PERPLLGRP_VCO_PSRC_OFFSET               22
-#define CLKMGR_PERPLLGRP_VCO_PSRC_MASK                 0x00c00000
-#define CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK            0x80000000
-#define CLKMGR_PERPLLGRP_VCO_RESET_VALUE               0x8001000d
-#define CLKMGR_PERPLLGRP_VCO_SSRC_OFFSET               22
-#define CLKMGR_PERPLLGRP_VCO_SSRC_MASK                 0x00c00000
-
-#define CLKMGR_VCO_SSRC_EOSC1                          0x0
-#define CLKMGR_VCO_SSRC_EOSC2                          0x1
-#define CLKMGR_VCO_SSRC_F2S                            0x2
-
-#define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_OFFSET           0
-#define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_MASK             0x000001ff
-
-#define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_OFFSET           0
-#define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_MASK             0x000001ff
-
-#define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_OFFSET         0
-#define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_MASK           0x000001ff
-
-#define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET    0
-#define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_MASK      0x000001ff
-
-#define CLKMGR_PERPLLGRP_PERBASECLK_CNT_OFFSET         0
-#define CLKMGR_PERPLLGRP_PERBASECLK_CNT_MASK           0x000001ff
-
-#define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_OFFSET                0
-#define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_MASK          0x000001ff
-
-#define CLKMGR_PERPLLGRP_EN_NANDCLK_MASK               0x00000400
-#define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK              0x00000100
-
-#define CLKMGR_PERPLLGRP_DIV_CAN0CLK_OFFSET            6
-#define CLKMGR_PERPLLGRP_DIV_CAN0CLK_MASK              0x000001c0
-#define CLKMGR_PERPLLGRP_DIV_CAN1CLK_OFFSET            9
-#define CLKMGR_PERPLLGRP_DIV_CAN1CLK_MASK              0x00000e00
-#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET            3
-#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET            3
-#define CLKMGR_PERPLLGRP_DIV_USBCLK_OFFSET             0
-#define CLKMGR_PERPLLGRP_DIV_USBCLK_MASK               0x00000007
-
-#define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_OFFSET      0
-#define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_MASK                0x00ffffff
-
-#define CLKMGR_PERPLLGRP_SRC_NAND_OFFSET               2
-#define CLKMGR_PERPLLGRP_SRC_NAND_MASK                 0x0000000c
-#define CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET               4
-#define CLKMGR_PERPLLGRP_SRC_QSPI_MASK                 0x00000030
-#define CLKMGR_PERPLLGRP_SRC_RESET_VALUE               0x00000015
-#define CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET              0
-#define CLKMGR_PERPLLGRP_SRC_SDMMC_MASK                        0x00000003
-#define CLKMGR_SDMMC_CLK_SRC_F2S                       0x0
-#define CLKMGR_SDMMC_CLK_SRC_MAIN                      0x1
-#define CLKMGR_SDMMC_CLK_SRC_PER                       0x2
-#define CLKMGR_QSPI_CLK_SRC_F2S                                0x0
-#define CLKMGR_QSPI_CLK_SRC_MAIN                       0x1
-#define CLKMGR_QSPI_CLK_SRC_PER                                0x2
-
-/* SDR PLL */
-#define CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET              16
-#define CLKMGR_SDRPLLGRP_VCO_DENOM_MASK                        0x003f0000
-#define CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET              3
-#define CLKMGR_SDRPLLGRP_VCO_NUMER_MASK                        0x0000fff8
-#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL               (1 << 24)
-#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_OFFSET                24
-#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_OFFSET           25
-#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_MASK             0x7e000000
-#define CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK            0x80000000
-#define CLKMGR_SDRPLLGRP_VCO_RESET_VALUE               0x8001000d
-#define CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET               22
-#define CLKMGR_SDRPLLGRP_VCO_SSRC_MASK                 0x00c00000
-
-#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET          0
-#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK            0x000001ff
-#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_OFFSET                9
-#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK          0x00000e00
-
-#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_OFFSET                0
-#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK          0x000001ff
-#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_OFFSET      9
-#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK                0x00000e00
-
-#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_OFFSET           0
-#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK             0x000001ff
-#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_OFFSET         9
-#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK           0x00000e00
-
-#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET                0
-#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK          0x000001ff
-#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET      9
-#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK                0x00000e00
-
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+#include <asm/arch/clock_manager_gen5.h>
+#endif
 #endif /* _CLOCK_MANAGER_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h b/arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h
new file mode 100644 (file)
index 0000000..9227dfb
--- /dev/null
@@ -0,0 +1,322 @@
+/*
+ *  Copyright (C) 2013-2017 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef _CLOCK_MANAGER_GEN5_H_
+#define _CLOCK_MANAGER_GEN5_H_
+
+#ifndef __ASSEMBLER__
+
+struct cm_config {
+       /* main group */
+       u32 main_vco_base;
+       u32 mpuclk;
+       u32 mainclk;
+       u32 dbgatclk;
+       u32 mainqspiclk;
+       u32 mainnandsdmmcclk;
+       u32 cfg2fuser0clk;
+       u32 maindiv;
+       u32 dbgdiv;
+       u32 tracediv;
+       u32 l4src;
+
+       /* peripheral group */
+       u32 peri_vco_base;
+       u32 emac0clk;
+       u32 emac1clk;
+       u32 perqspiclk;
+       u32 pernandsdmmcclk;
+       u32 perbaseclk;
+       u32 s2fuser1clk;
+       u32 perdiv;
+       u32 gpiodiv;
+       u32 persrc;
+
+       /* sdram pll group */
+       u32 sdram_vco_base;
+       u32 ddrdqsclk;
+       u32 ddr2xdqsclk;
+       u32 ddrdqclk;
+       u32 s2fuser2clk;
+
+       /* altera group */
+       u32 altera_grp_mpuclk;
+};
+
+struct socfpga_clock_manager_main_pll {
+       u32     vco;
+       u32     misc;
+       u32     mpuclk;
+       u32     mainclk;
+       u32     dbgatclk;
+       u32     mainqspiclk;
+       u32     mainnandsdmmcclk;
+       u32     cfgs2fuser0clk;
+       u32     en;
+       u32     maindiv;
+       u32     dbgdiv;
+       u32     tracediv;
+       u32     l4src;
+       u32     stat;
+       u32     _pad_0x38_0x40[2];
+};
+
+struct socfpga_clock_manager_per_pll {
+       u32     vco;
+       u32     misc;
+       u32     emac0clk;
+       u32     emac1clk;
+       u32     perqspiclk;
+       u32     pernandsdmmcclk;
+       u32     perbaseclk;
+       u32     s2fuser1clk;
+       u32     en;
+       u32     div;
+       u32     gpiodiv;
+       u32     src;
+       u32     stat;
+       u32     _pad_0x34_0x40[3];
+};
+
+struct socfpga_clock_manager_sdr_pll {
+       u32     vco;
+       u32     ctrl;
+       u32     ddrdqsclk;
+       u32     ddr2xdqsclk;
+       u32     ddrdqclk;
+       u32     s2fuser2clk;
+       u32     en;
+       u32     stat;
+};
+
+struct socfpga_clock_manager_altera {
+       u32     mpuclk;
+       u32     mainclk;
+};
+
+struct socfpga_clock_manager {
+       u32     ctrl;
+       u32     bypass;
+       u32     inter;
+       u32     intren;
+       u32     dbctrl;
+       u32     stat;
+       u32     _pad_0x18_0x3f[10];
+       struct socfpga_clock_manager_main_pll main_pll;
+       struct socfpga_clock_manager_per_pll per_pll;
+       struct socfpga_clock_manager_sdr_pll sdr_pll;
+       struct socfpga_clock_manager_altera altera;
+       u32     _pad_0xe8_0x200[70];
+};
+
+/* Clock speed accessors */
+unsigned long cm_get_mpu_clk_hz(void);
+unsigned long cm_get_sdram_clk_hz(void);
+unsigned int cm_get_l4_sp_clk_hz(void);
+unsigned int cm_get_mmc_controller_clk_hz(void);
+unsigned int cm_get_qspi_controller_clk_hz(void);
+unsigned int cm_get_spi_controller_clk_hz(void);
+const unsigned int cm_get_osc_clk_hz(const int osc);
+const unsigned int cm_get_f2s_per_ref_clk_hz(void);
+const unsigned int cm_get_f2s_sdr_ref_clk_hz(void);
+
+/* Clock configuration accessors */
+int cm_basic_init(const struct cm_config * const cfg);
+const struct cm_config * const cm_get_default_config(void);
+#endif /* __ASSEMBLER__ */
+
+#define LOCKED_MASK \
+       (CLKMGR_INTER_SDRPLLLOCKED_MASK  | \
+       CLKMGR_INTER_PERPLLLOCKED_MASK  | \
+       CLKMGR_INTER_MAINPLLLOCKED_MASK)
+
+#define CLKMGR_CTRL_SAFEMODE                           BIT(0)
+#define CLKMGR_CTRL_SAFEMODE_OFFSET                    0
+
+#define CLKMGR_BYPASS_PERPLLSRC                                BIT(4)
+#define CLKMGR_BYPASS_PERPLLSRC_OFFSET                 4
+#define CLKMGR_BYPASS_PERPLL                           BIT(3)
+#define CLKMGR_BYPASS_PERPLL_OFFSET                    3
+#define CLKMGR_BYPASS_SDRPLLSRC                                BIT(2)
+#define CLKMGR_BYPASS_SDRPLLSRC_OFFSET                 2
+#define CLKMGR_BYPASS_SDRPLL                           BIT(1)
+#define CLKMGR_BYPASS_SDRPLL_OFFSET                    1
+#define CLKMGR_BYPASS_MAINPLL                          BIT(0)
+#define CLKMGR_BYPASS_MAINPLL_OFFSET                   0
+
+#define CLKMGR_INTER_MAINPLLLOST_MASK                  BIT(3)
+#define CLKMGR_INTER_PERPLLLOST_MASK                   BIT(4)
+#define CLKMGR_INTER_SDRPLLLOST_MASK                   BIT(5)
+#define CLKMGR_INTER_MAINPLLLOCKED_MASK                        BIT(6)
+#define CLKMGR_INTER_PERPLLLOCKED_MASK                 BIT(7)
+#define CLKMGR_INTER_SDRPLLLOCKED_MASK                 BIT(8)
+
+#define CLKMGR_STAT_BUSY                               BIT(0)
+
+/* Main PLL */
+#define CLKMGR_MAINPLLGRP_VCO_BGPWRDN                  BIT(0)
+#define CLKMGR_MAINPLLGRP_VCO_BGPWRDN_OFFSET           0
+#define CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET             16
+#define CLKMGR_MAINPLLGRP_VCO_DENOM_MASK               0x003f0000
+#define CLKMGR_MAINPLLGRP_VCO_EN                       BIT(1)
+#define CLKMGR_MAINPLLGRP_VCO_EN_OFFSET                        1
+#define CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET             3
+#define CLKMGR_MAINPLLGRP_VCO_NUMER_MASK               0x0000fff8
+#define CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK         0x01000000
+#define CLKMGR_MAINPLLGRP_VCO_PWRDN                    BIT(2)
+#define CLKMGR_MAINPLLGRP_VCO_PWRDN_OFFSET             2
+#define CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK           0x80000000
+#define CLKMGR_MAINPLLGRP_VCO_RESET_VALUE              0x8001000d
+
+#define CLKMGR_MAINPLLGRP_MPUCLK_CNT_OFFSET            0
+#define CLKMGR_MAINPLLGRP_MPUCLK_CNT_MASK              0x000001ff
+
+#define CLKMGR_MAINPLLGRP_MAINCLK_CNT_OFFSET           0
+#define CLKMGR_MAINPLLGRP_MAINCLK_CNT_MASK             0x000001ff
+
+#define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_OFFSET          0
+#define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_MASK            0x000001ff
+
+#define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_OFFSET       0
+#define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_MASK         0x000001ff
+
+#define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_OFFSET  0
+#define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_MASK    0x000001ff
+
+#define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_OFFSET    0
+#define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_MASK      0x000001ff
+
+#define CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK              BIT(2)
+#define CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK             BIT(4)
+#define CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK               BIT(5)
+#define CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK          BIT(6)
+#define CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK          BIT(7)
+#define CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK          BIT(9)
+
+#define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_OFFSET       0
+#define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_MASK         0x00000003
+#define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_OFFSET       2
+#define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_MASK         0x0000000c
+#define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_OFFSET       4
+#define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_MASK         0x00000070
+#define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET       7
+#define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_MASK         0x00000380
+
+#define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_OFFSET       0
+#define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_MASK         0x00000003
+#define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_OFFSET         2
+#define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_MASK           0x0000000c
+
+#define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_OFFSET     0
+#define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_MASK       0x00000007
+
+#define CLKMGR_MAINPLLGRP_L4SRC_L4MP                   BIT(0)
+#define CLKMGR_MAINPLLGRP_L4SRC_L4MP_OFFSET            0
+#define CLKMGR_MAINPLLGRP_L4SRC_L4SP                   BIT(1)
+#define CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET            1
+#define CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE            0x00000000
+#define CLKMGR_L4_SP_CLK_SRC_MAINPLL                   0x0
+#define CLKMGR_L4_SP_CLK_SRC_PERPLL                    0x1
+
+/* Per PLL */
+#define CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET              16
+#define CLKMGR_PERPLLGRP_VCO_DENOM_MASK                        0x003f0000
+#define CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET              3
+#define CLKMGR_PERPLLGRP_VCO_NUMER_MASK                        0x0000fff8
+#define CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK          0x01000000
+#define CLKMGR_PERPLLGRP_VCO_PSRC_OFFSET               22
+#define CLKMGR_PERPLLGRP_VCO_PSRC_MASK                 0x00c00000
+#define CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK            0x80000000
+#define CLKMGR_PERPLLGRP_VCO_RESET_VALUE               0x8001000d
+#define CLKMGR_PERPLLGRP_VCO_SSRC_OFFSET               22
+#define CLKMGR_PERPLLGRP_VCO_SSRC_MASK                 0x00c00000
+
+#define CLKMGR_VCO_SSRC_EOSC1                          0x0
+#define CLKMGR_VCO_SSRC_EOSC2                          0x1
+#define CLKMGR_VCO_SSRC_F2S                            0x2
+
+#define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_OFFSET           0
+#define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_MASK             0x000001ff
+
+#define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_OFFSET           0
+#define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_MASK             0x000001ff
+
+#define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_OFFSET         0
+#define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_MASK           0x000001ff
+
+#define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET    0
+#define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_MASK      0x000001ff
+
+#define CLKMGR_PERPLLGRP_PERBASECLK_CNT_OFFSET         0
+#define CLKMGR_PERPLLGRP_PERBASECLK_CNT_MASK           0x000001ff
+
+#define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_OFFSET                0
+#define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_MASK          0x000001ff
+
+#define CLKMGR_PERPLLGRP_EN_NANDCLK_MASK               0x00000400
+#define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK              0x00000100
+
+#define CLKMGR_PERPLLGRP_DIV_CAN0CLK_OFFSET            6
+#define CLKMGR_PERPLLGRP_DIV_CAN0CLK_MASK              0x000001c0
+#define CLKMGR_PERPLLGRP_DIV_CAN1CLK_OFFSET            9
+#define CLKMGR_PERPLLGRP_DIV_CAN1CLK_MASK              0x00000e00
+#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET            3
+#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET            3
+#define CLKMGR_PERPLLGRP_DIV_USBCLK_OFFSET             0
+#define CLKMGR_PERPLLGRP_DIV_USBCLK_MASK               0x00000007
+
+#define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_OFFSET      0
+#define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_MASK                0x00ffffff
+
+#define CLKMGR_PERPLLGRP_SRC_NAND_OFFSET               2
+#define CLKMGR_PERPLLGRP_SRC_NAND_MASK                 0x0000000c
+#define CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET               4
+#define CLKMGR_PERPLLGRP_SRC_QSPI_MASK                 0x00000030
+#define CLKMGR_PERPLLGRP_SRC_RESET_VALUE               0x00000015
+#define CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET              0
+#define CLKMGR_PERPLLGRP_SRC_SDMMC_MASK                        0x00000003
+#define CLKMGR_SDMMC_CLK_SRC_F2S                       0x0
+#define CLKMGR_SDMMC_CLK_SRC_MAIN                      0x1
+#define CLKMGR_SDMMC_CLK_SRC_PER                       0x2
+#define CLKMGR_QSPI_CLK_SRC_F2S                                0x0
+#define CLKMGR_QSPI_CLK_SRC_MAIN                       0x1
+#define CLKMGR_QSPI_CLK_SRC_PER                                0x2
+
+/* SDR PLL */
+#define CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET              16
+#define CLKMGR_SDRPLLGRP_VCO_DENOM_MASK                        0x003f0000
+#define CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET              3
+#define CLKMGR_SDRPLLGRP_VCO_NUMER_MASK                        0x0000fff8
+#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL               BIT(24)
+#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_OFFSET                24
+#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_OFFSET           25
+#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_MASK             0x7e000000
+#define CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK            BIT(31)
+#define CLKMGR_SDRPLLGRP_VCO_RESET_VALUE               0x8001000d
+#define CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET               22
+#define CLKMGR_SDRPLLGRP_VCO_SSRC_MASK                 0x00c00000
+
+#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET          0
+#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK            0x000001ff
+#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_OFFSET                9
+#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK          0x00000e00
+
+#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_OFFSET                0
+#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK          0x000001ff
+#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_OFFSET      9
+#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK                0x00000e00
+
+#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_OFFSET           0
+#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK             0x000001ff
+#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_OFFSET         9
+#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK           0x00000e00
+
+#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET                0
+#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK          0x000001ff
+#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET      9
+#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK                0x00000e00
+
+#endif /* _CLOCK_MANAGER_GEN5_H_ */
index fec4c7a..0064fc8 100644 (file)
@@ -127,7 +127,8 @@ void board_init_f(ulong dummy)
 
        debug("Reconfigure Clock Manager\n");
        /* reconfigure the PLLs */
-       cm_basic_init(cm_default_cfg);
+       if (cm_basic_init(cm_default_cfg))
+               hang();
 
        /* Enable bootrom to configure IOs. */
        sysmgr_config_warmrstcfgio(1);