arm: mvebu: a38x: serdes: Update comment about PCIE*_ENABLE_* defines
authorPali Rohár <pali@kernel.org>
Fri, 24 Sep 2021 20:59:22 +0000 (22:59 +0200)
committerStefan Roese <sr@denx.de>
Fri, 8 Oct 2021 06:33:52 +0000 (08:33 +0200)
These are part of SOC_CONTROL_REG1 register, not PEX_CAPABILITIES_REG.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h

index 55a4c26..64193d5 100644 (file)
@@ -12,7 +12,7 @@
 /* Direct access to PEX0 Root Port's PCIe Capability structure */
 #define PEX0_RP_PCIE_CFG_OFFSET                (0x00080000 + 0x60)
 
-/* PEX_CAPABILITIES_REG fields */
+/* SOC_CONTROL_REG1 fields */
 #define PCIE0_ENABLE_OFFS              0
 #define PCIE0_ENABLE_MASK              (0x1 << PCIE0_ENABLE_OFFS)
 #define PCIE1_ENABLE_OFFS              1