[RISCV] Don't fold (sub C, (setcc x, y, eq/neq)) -> (add C-1, (setcc x, y, neq/eq...

We still need to materialize the constant in a register and we
may not be removing all uses of the original constant so it may
increase code size.

diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index ea38077..1311d7b 100644 (file)
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -8294,12 +8294,16 @@ static SDValue performSUBCombine(SDNode *N, SelectionDAG &DAG) {
     EVT SetCCOpVT = N1.getOperand(0).getValueType();
     if (!N0C->isZero() && SetCCOpVT.isInteger() && isIntEqualitySetCC(CCVal)) {
       EVT VT = N->getValueType(0);
-      const APInt &ImmVal = N0C->getAPIntValue();
-      CCVal = ISD::getSetCCInverse(CCVal, SetCCOpVT);
-      SDValue NewN0 =
-          DAG.getSetCC(SDLoc(N), VT, N1.getOperand(0), N1.getOperand(1), CCVal);
-      SDValue NewN1 = DAG.getConstant(ImmVal - 1, SDLoc(N), VT);
-      return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewN0, NewN1);
+      APInt ImmValMinus1 = N0C->getAPIntValue() - 1;
+      // If this doesn't form ADDI, the transform won't save any instructions
+      // and may increase the number of constants we need.
+      if (ImmValMinus1.isSignedIntN(12)) {
+        CCVal = ISD::getSetCCInverse(CCVal, SetCCOpVT);
+        SDValue NewN0 =
+            DAG.getSetCC(SDLoc(N), VT, N1.getOperand(0), N1.getOperand(1), CCVal);
+        SDValue NewN1 = DAG.getConstant(ImmValMinus1, SDLoc(N), VT);
+        return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewN0, NewN1);
+      }
     }
   }
 

diff --git a/llvm/test/CodeGen/RISCV/select-const.ll b/llvm/test/CodeGen/RISCV/select-const.ll
index 25980ab..071626e 100644 (file)
--- a/llvm/test/CodeGen/RISCV/select-const.ll
+++ b/llvm/test/CodeGen/RISCV/select-const.ll
@@ -448,19 +448,19 @@ define i32 @select_eq_10000_10001(i32 signext %a, i32 signext %b) {
 ; RV32-LABEL: select_eq_10000_10001:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    xor a0, a0, a1
-; RV32-NEXT:    snez a0, a0
+; RV32-NEXT:    seqz a0, a0
 ; RV32-NEXT:    lui a1, 2
-; RV32-NEXT:    addi a1, a1, 1809
-; RV32-NEXT:    add a0, a0, a1
+; RV32-NEXT:    addi a1, a1, 1810
+; RV32-NEXT:    sub a0, a1, a0
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: select_eq_10000_10001:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    xor a0, a0, a1
-; RV64-NEXT:    snez a0, a0
+; RV64-NEXT:    seqz a0, a0
 ; RV64-NEXT:    lui a1, 2
-; RV64-NEXT:    addiw a1, a1, 1809
-; RV64-NEXT:    add a0, a0, a1
+; RV64-NEXT:    addiw a1, a1, 1810
+; RV64-NEXT:    sub a0, a1, a0
 ; RV64-NEXT:    ret
   %1 = icmp eq i32 %a, %b
   %2 = select i1 %1, i32 10001, i32 10002
@@ -471,19 +471,19 @@ define i32 @select_ne_10001_10002(i32 signext %a, i32 signext %b) {
 ; RV32-LABEL: select_ne_10001_10002:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    xor a0, a0, a1
-; RV32-NEXT:    seqz a0, a0
+; RV32-NEXT:    snez a0, a0
 ; RV32-NEXT:    lui a1, 2
-; RV32-NEXT:    addi a1, a1, 1809
-; RV32-NEXT:    add a0, a0, a1
+; RV32-NEXT:    addi a1, a1, 1810
+; RV32-NEXT:    sub a0, a1, a0
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: select_ne_10001_10002:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    xor a0, a0, a1
-; RV64-NEXT:    seqz a0, a0
+; RV64-NEXT:    snez a0, a0
 ; RV64-NEXT:    lui a1, 2
-; RV64-NEXT:    addiw a1, a1, 1809
-; RV64-NEXT:    add a0, a0, a1
+; RV64-NEXT:    addiw a1, a1, 1810
+; RV64-NEXT:    sub a0, a1, a0
 ; RV64-NEXT:    ret
   %1 = icmp ne i32 %a, %b
   %2 = select i1 %1, i32 10001, i32 10002