phy: tegra: Add PCIe PIPE2UPHY support for Tegra234

Synopsys DesignWare core based PCIe controllers in Tegra234 SoC
interface with Universal PHY (UPHY) module through a PIPE2UPHY (P2U)
module. For each PCIe lane of a controller, there is a P2U unit
instantiated at hardware level. This driver provides support for the
programming required for each P2U that is going to be used for a PCIe
controller.

Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Link: https://lore.kernel.org/r/20220629060435.25297-9-vidyas@nvidia.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

diff --git a/drivers/phy/tegra/phy-tegra194-p2u.c b/drivers/phy/tegra/phy-tegra194-p2u.c
index 3ee02b9..1415ca7 100644 (file)
--- a/drivers/phy/tegra/phy-tegra194-p2u.c
+++ b/drivers/phy/tegra/phy-tegra194-p2u.c
@@ -2,7 +2,7 @@
 /*
  * P2U (PIPE to UPHY) driver for Tegra T194 SoC
  *
- * Copyright (C) 2019 NVIDIA Corporation.
+ * Copyright (C) 2019-2022 NVIDIA Corporation.
  *
  * Author: Vidya Sagar <vidyas@nvidia.com>
  */
@@ -14,6 +14,9 @@
 #include <linux/of_platform.h>
 #include <linux/phy/phy.h>
 
+#define P2U_CONTROL_CMN                        0x74
+#define P2U_CONTROL_CMN_SKP_SIZE_PROTECTION_EN                 BIT(20)
+
 #define P2U_PERIODIC_EQ_CTRL_GEN3      0xc0
 #define P2U_PERIODIC_EQ_CTRL_GEN3_PERIODIC_EQ_EN               BIT(0)
 #define P2U_PERIODIC_EQ_CTRL_GEN3_INIT_PRESET_EQ_TRAIN_EN      BIT(1)
@@ -24,8 +27,17 @@
 #define P2U_RX_DEBOUNCE_TIME_DEBOUNCE_TIMER_MASK       0xffff
 #define P2U_RX_DEBOUNCE_TIME_DEBOUNCE_TIMER_VAL                160
 
+#define P2U_DIR_SEARCH_CTRL                            0xd4
+#define P2U_DIR_SEARCH_CTRL_GEN4_FINE_GRAIN_SEARCH_TWICE       BIT(18)
+
+struct tegra_p2u_of_data {
+       bool one_dir_search;
+};
+
 struct tegra_p2u {
        void __iomem *base;
+       bool skip_sz_protection_en; /* Needed to support two retimers */
+       struct tegra_p2u_of_data *of_data;
 };
 
 static inline void p2u_writel(struct tegra_p2u *phy, const u32 value,
@@ -44,6 +56,12 @@ static int tegra_p2u_power_on(struct phy *x)
        struct tegra_p2u *phy = phy_get_drvdata(x);
        u32 val;
 
+       if (phy->skip_sz_protection_en) {
+               val = p2u_readl(phy, P2U_CONTROL_CMN);
+               val |= P2U_CONTROL_CMN_SKP_SIZE_PROTECTION_EN;
+               p2u_writel(phy, val, P2U_CONTROL_CMN);
+       }
+
        val = p2u_readl(phy, P2U_PERIODIC_EQ_CTRL_GEN3);
        val &= ~P2U_PERIODIC_EQ_CTRL_GEN3_PERIODIC_EQ_EN;
        val |= P2U_PERIODIC_EQ_CTRL_GEN3_INIT_PRESET_EQ_TRAIN_EN;
@@ -58,6 +76,12 @@ static int tegra_p2u_power_on(struct phy *x)
        val |= P2U_RX_DEBOUNCE_TIME_DEBOUNCE_TIMER_VAL;
        p2u_writel(phy, val, P2U_RX_DEBOUNCE_TIME);
 
+       if (phy->of_data->one_dir_search) {
+               val = p2u_readl(phy, P2U_DIR_SEARCH_CTRL);
+               val &= ~P2U_DIR_SEARCH_CTRL_GEN4_FINE_GRAIN_SEARCH_TWICE;
+               p2u_writel(phy, val, P2U_DIR_SEARCH_CTRL);
+       }
+
        return 0;
 }
 
@@ -77,10 +101,19 @@ static int tegra_p2u_probe(struct platform_device *pdev)
        if (!phy)
                return -ENOMEM;
 
+       phy->of_data =
+               (struct tegra_p2u_of_data *)of_device_get_match_data(dev);
+       if (!phy->of_data)
+               return -EINVAL;
+
        phy->base = devm_platform_ioremap_resource_byname(pdev, "ctl");
        if (IS_ERR(phy->base))
                return PTR_ERR(phy->base);
 
+       phy->skip_sz_protection_en =
+               of_property_read_bool(dev->of_node,
+                                     "nvidia,skip-sz-protect-en");
+
        platform_set_drvdata(pdev, phy);
 
        generic_phy = devm_phy_create(dev, NULL, &ops);
@@ -96,9 +129,22 @@ static int tegra_p2u_probe(struct platform_device *pdev)
        return 0;
 }
 
+static const struct tegra_p2u_of_data tegra194_p2u_of_data = {
+       .one_dir_search = false,
+};
+
+static const struct tegra_p2u_of_data tegra234_p2u_of_data = {
+       .one_dir_search = true,
+};
+
 static const struct of_device_id tegra_p2u_id_table[] = {
        {
                .compatible = "nvidia,tegra194-p2u",
+               .data = &tegra194_p2u_of_data,
+       },
+       {
+               .compatible = "nvidia,tegra234-p2u",
+               .data = &tegra234_p2u_of_data,
        },
        {}
 };