#include <mpc512x.h>
#include <asm/bitops.h>
#include <command.h>
+#include <asm/processor.h>
#include <fdt_support.h>
#ifdef CONFIG_MISC_INIT_R
#include <i2c.h>
* Configure Flash Speed
*/
*((volatile u32 *)(CFG_IMMR + LPC_OFFSET + CS0_CONFIG)) = CFG_CS0_CFG;
+ if (SVR_MJREV (im->sysconf.spridr) >= 2) {
+ *((volatile u32 *)(CFG_IMMR + LPC_OFFSET + CS_ALE_TIMING_CONFIG)) = CFG_CS_ALETIMING;
+ }
/*
* Enable clocks
*/
* Serial Boot: The dram is already initialized in start.S
* only require to return DRAM size
*/
- dramsize = CFG_SDRAM_SIZE * 0x100000 >> 1;
+ dramsize = CFG_SDRAM_SIZE * 0x100000;
#else
volatile sdramc_t *sdram = (volatile sdramc_t *)(MMAP_SDRAM);
volatile gpio_t *gpio = (volatile gpio_t *)(MMAP_GPIO);
}
i--;
- gpio->mscr_sdram = 0x44;
+ gpio->mscr_sdram = CFG_SDRAM_DRV_STRENGTH;
sdram->sdcs0 = (CFG_SDRAM_BASE | i);
}
#endif /* CONFIG_PCI */
-#if defined(CFG_FLASH_CFI)
+#if defined(CONFIG_FLASH_CFI_LEGACY)
#include <flash.h>
ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info)
{
info->erase_blk_tout = 16384;
info->write_tout = 2;
info->buffer_write_tout = 5;
- info->vendor = 2; /* CFI_CMDSET_AMD_STANDARD */
+ info->vendor = 0xFFF0; /* CFI_CMDSET_AMD_LEGACY */
info->cmd_reset = 0x00F0;
info->interface = FLASH_CFI_X8;
info->legacy_unlock = 0;
info->ext_addr = 0;
info->cfi_version = 0x3133;
- info->cfi_offset = 0x0055;
+ info->cfi_offset = 0x0000;
info->addr_unlock1 = 0x00000555;
info->addr_unlock2 = 0x000002AA;
info->name = "CFI conformant";
-
info->size = 0;
info->sector_count = CFG_ATMEL_TOTALSECT;
info->start[0] = base;
fecp = (fec_t *) info->miibase;
+ fecpin_setclear(dev, 1);
+
+ mii_reset(info);
+
/* We use strictly polling mode only */
fecp->eimr = 0;
gd->bus_clk = gd->flb_clk;
}
+#ifdef CONFIG_FSL_I2C
+ gd->i2c1_clk = gd->bus_clk;
+#endif
+
return (0);
}
#endif
#ifdef CONFIG_FSL_I2C
- gpio->par_feci2c &= ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK);
- gpio->par_feci2c |= (GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA);
+ CFG_I2C_PINMUX_REG &= CFG_I2C_PINMUX_CLR;
+ CFG_I2C_PINMUX_REG |= CFG_I2C_PINMUX_SET;
#endif
icache_enable();
gd->bus_clk = CFG_CLK;
gd->cpu_clk = (gd->bus_clk * 2);
+#ifdef CONFIG_FSL_I2C
+ gd->i2c1_clk = gd->bus_clk;
+#endif
+
return (0);
}
mbar_writeShort(MCFSIM_CSCR0, CFG_CSCR0);
mbar_writeLong(MCFSIM_CSMR0, CFG_CSMR0);
+#ifdef CONFIG_FSL_I2C
+ CFG_I2C_PINMUX_REG = CFG_I2C_PINMUX_REG & CFG_I2C_PINMUX_CLR;
+ CFG_I2C_PINMUX_REG |= CFG_I2C_PINMUX_SET;
+#ifdef CFG_I2C2_OFFSET
+ CFG_I2C2_PINMUX_REG &= CFG_I2C2_PINMUX_CLR;
+ CFG_I2C2_PINMUX_REG |= CFG_I2C2_PINMUX_SET;
+#endif
+#endif
+
/* enable instruction cache now */
icache_enable();
}
#endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */
#ifdef CONFIG_FSL_I2C
- gpio_reg->par_feci2c = 0x000F;
+ CFG_I2C_PINMUX_REG &= CFG_I2C_PINMUX_CLR;
+ CFG_I2C_PINMUX_REG |= CFG_I2C_PINMUX_SET;
#endif
/* enable instruction cache now */
#else
gd->bus_clk = gd->cpu_clk;
#endif
+
+#ifdef CONFIG_FSL_I2C
+ gd->i2c1_clk = gd->bus_clk;
+#ifdef CFG_I2C2_OFFSET
+ gd->i2c2_clk = gd->bus_clk;
+#endif
+#endif
+
return (0);
}
{
gd->bus_clk = clock_pll(CFG_CLK / 1000, 0) * 1000;
gd->cpu_clk = (gd->bus_clk * 3);
+
+#ifdef CONFIG_FSL_I2C
+ gd->i2c1_clk = gd->bus_clk;
+#endif
+
return (0);
}
#endif
}
+#ifdef CONFIG_FSL_I2C
+ gd->i2c1_clk = gd->bus_clk;
+#endif
+
return (0);
}
gd->bus_clk = CFG_CLK;
gd->cpu_clk = (gd->bus_clk * 2);
+
+#ifdef CONFIG_FSL_I2C
+ gd->i2c1_clk = gd->bus_clk;
+#endif
+
return (0);
}
LIB = $(obj)lib$(CPU).a
START = start.o
-COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o serial.o fec.o i2c.o iopin.o
+COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o serial.o i2c.o iopin.o
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
START = start.o
SOBJS = io.o firmware_sc_task_bestcomm.impl.o firmware_sc_task.impl.o
-COBJS = i2c.o traps.o cpu.o cpu_init.o fec.o ide.o interrupts.o \
+COBJS = i2c.o traps.o cpu.o cpu_init.o ide.o interrupts.o \
loadtask.o pci_mpc5200.o serial.o speed.o usb_ohci.o usb.o
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
* For this table, the values are based on a value of 1 for the DFSR
* register. See the application note AN2919 "Determining the I2C Frequency
* Divider Ratio for SCL"
+ *
+ * ColdFire I2C frequency dividers for FDR values are different from
+ * PowerPC. The protocol to use the I2C module is still the same.
+ * A different table is defined and are based on MCF5xxx user manual.
+ *
*/
static const struct {
unsigned short divider;
+#ifdef __PPC__
u8 dfsr;
+#endif
u8 fdr;
} fsl_i2c_speed_map[] = {
+#ifdef __PPC__
{160, 1, 32}, {192, 1, 33}, {224, 1, 34}, {256, 1, 35},
{288, 1, 0}, {320, 1, 1}, {352, 6, 1}, {384, 1, 2}, {416, 6, 2},
{448, 1, 38}, {480, 1, 3}, {512, 1, 39}, {544, 11, 3}, {576, 1, 4},
{20480, 1, 25}, {24576, 1, 26}, {28672, 1, 62}, {30720, 1, 27},
{32768, 1, 63}, {36864, 1, 28}, {40960, 1, 29}, {49152, 1, 30},
{61440, 1, 31}, {-1, 1, 31}
+#elif defined(__M68K__)
+ {20, 32}, {22, 33}, {24, 34}, {26, 35},
+ {28, 0}, {28, 36}, {30, 1}, {32, 37},
+ {34, 2}, {36, 38}, {40, 3}, {40, 39},
+ {44, 4}, {48, 5}, {48, 40}, {56, 6},
+ {56, 41}, {64, 42}, {68, 7}, {72, 43},
+ {80, 8}, {80, 44}, {88, 9}, {96, 41},
+ {104, 10}, {112, 42}, {128, 11}, {128, 43},
+ {144, 12}, {160, 13}, {160, 48}, {192, 14},
+ {192, 49}, {224, 50}, {240, 15}, {256, 51},
+ {288, 16}, {320, 17}, {320, 52}, {384, 18},
+ {384, 53}, {448, 54}, {480, 19}, {512, 55},
+ {576, 20}, {640, 21}, {640, 56}, {768, 22},
+ {768, 57}, {960, 23}, {896, 58}, {1024, 59},
+ {1152, 24}, {1280, 25}, {1280, 60}, {1536, 26},
+ {1536, 61}, {1792, 62}, {1920, 27}, {2048, 63},
+ {2304, 28}, {2560, 29}, {3072, 30}, {3840, 31},
+ {-1, 31}
+#endif
};
/**
for (i = 0; i < ARRAY_SIZE(fsl_i2c_speed_map); i++)
if (fsl_i2c_speed_map[i].divider >= divider) {
- u8 fdr, dfsr;
+ u8 fdr;
+#ifdef __PPC__
+ u8 dfsr;
dfsr = fsl_i2c_speed_map[i].dfsr;
+#endif
fdr = fsl_i2c_speed_map[i].fdr;
speed = i2c_clk / fsl_i2c_speed_map[i].divider;
writeb(fdr, &dev->fdr); /* set bus speed */
+#ifdef __PPC__
writeb(dfsr, &dev->dfsrr); /* set default filter */
+#endif
break;
}
COBJS-$(CONFIG_DRIVER_LAN91C96) += lan91c96.o
COBJS-$(CONFIG_MACB) += macb.o
COBJS-$(CONFIG_MCFFEC) += mcffec.o
+COBJS-$(CONFIG_MPC5xxx_FEC) += mpc5xxx_fec.o
+COBJS-$(CONFIG_MPC512x_FEC) += mpc512x_fec.o
COBJS-$(CONFIG_NATSEMI) += natsemi.o
ifeq ($(CONFIG_DRIVER_NE2000),y)
COBJS-y += ne2000.o
#include <malloc.h>
#include <net.h>
#include <miiphy.h>
-#include "fec.h"
+#include "mpc512x_fec.h"
DECLARE_GLOBAL_DATA_PTR;
#include <common.h>
#include <mpc5xxx.h>
+#include <mpc5xxx_sdma.h>
#include <malloc.h>
#include <net.h>
#include <miiphy.h>
-#include "sdma.h"
-#include "fec.h"
+#include "mpc5xxx_fec.h"
DECLARE_GLOBAL_DATA_PTR;
#ifndef __MPC5XXX_FEC_H
#define __MPC5XXX_FEC_H
-#include <common.h>
-#include <mpc5xxx.h>
-#include "sdma.h"
-
typedef unsigned long uint32;
typedef unsigned short uint16;
typedef unsigned char uint8;
#define I2C_DR 0xFF
#define I2C_DR_SHIFT 0
#define I2C_DR_RES ~(I2C_DR)
-
- u8 dfsrr; /* I2C digital filter sampling rate register */
- u8 res5[3];
-#define I2C_DFSRR 0x3F
-#define I2C_DFSRR_SHIFT 0
-#define I2C_DFSRR_RES ~(I2C_DR)
-
- /* Fill out the reserved block */
- u8 res6[0xE8];
} fsl_i2c_t;
#endif /* _ASM_I2C_H_ */
/* I2C */
#define CONFIG_FSL_I2C
-#define CONFIG_HARD_I2C /* I2C with hw support */
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CONFIG_HARD_I2C /* I2C with hw support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 80000
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_OFFSET 0x00000300
#define CFG_IMMR CFG_MBAR
+#define CFG_I2C_PINMUX_REG (gpio->par_qspi)
+#define CFG_I2C_PINMUX_CLR ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK)
+#define CFG_I2C_PINMUX_SET (GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA)
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
#define CONFIG_MCFUART
#define CFG_UART_PORT (0)
-#define CONFIG_BAUDRATE 19200
-#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
+#define CONFIG_BAUDRATE 115200
+#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
#undef CONFIG_WATCHDOG
#define CONFIG_HOSTNAME M5253DEMO
+/* I2C */
+#define CONFIG_FSL_I2C
+#define CONFIG_HARD_I2C /* I2C with hw support */
+#define CFG_I2C_SPEED 80000
+#define CFG_I2C_SLAVE 0x7F
+#define CFG_I2C_OFFSET 0x00000280
+#define CFG_IMMR CFG_MBAR
+#define CFG_I2C_PINMUX_REG (*(u32 *) (CFG_MBAR+0x19C))
+#define CFG_I2C_PINMUX_CLR (0xFFFFE7FF)
+#define CFG_I2C_PINMUX_SET (0)
+
#define CFG_PROMPT "=> "
#define CFG_LONGHELP /* undef to save memory */
#define CONFIG_MCFUART
#define CFG_UART_PORT (0)
-#define CONFIG_BAUDRATE 19200
+#define CONFIG_BAUDRATE 115200
#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
#undef CONFIG_WATCHDOG /* disable watchdog */
#define CONFIG_MCFUART
#define CFG_UART_PORT (0)
-#define CONFIG_BAUDRATE 19200
-#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
+#define CONFIG_BAUDRATE 115200
+#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
#undef CONFIG_WATCHDOG
#define CONFIG_WATCHDOG_TIMEOUT 10000 /* timeout in milliseconds */
#ifdef CONFIG_MCFFEC
# define CONFIG_NET_MULTI 1
# define CONFIG_MII 1
+# define CONFIG_MII_INIT 1
# define CFG_DISCOVER_PHY
# define CFG_RX_ETH_BUFFER 8
# define CFG_FAULT_ECHO_LINK_DOWN
#define CONFIG_MCFUART
#define CFG_UART_PORT (0)
-#define CONFIG_BAUDRATE 19200
+#define CONFIG_BAUDRATE 115200
#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
/* Configuration for environment
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_OFFSET 0x00000300
#define CFG_IMMR CFG_MBAR
+#define CFG_I2C_PINMUX_REG (gpio_reg->par_feci2c)
+#define CFG_I2C_PINMUX_CLR (0xFFF0)
+#define CFG_I2C_PINMUX_SET (0x000F)
#ifdef CONFIG_MCFFEC
#define CONFIG_ETHADDR 00:06:3b:01:41:55
#define CONFIG_MCFUART
#define CFG_UART_PORT (0)
-#define CONFIG_BAUDRATE 19200
-#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
+#define CONFIG_BAUDRATE 115200
+#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
#undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */
"u-boot=u-boot.bin\0" \
"load=tftp ${loadaddr) ${u-boot}\0" \
"upd=run load; run prog\0" \
- "prog=prot off 0 " MK_STR(CFG_UBOOT_END)\
- "; era 0 " MK_STR(CFG_UBOOT_END) \
- "2ffff;" \
+ "prog=prot off 0 " MK_STR(CFG_UBOOT_END) \
+ "; era 0 " MK_STR(CFG_UBOOT_END) " ;" \
"cp.b ${loadaddr} 0 ${filesize};" \
"save\0" \
""
" " MK_STR(CFG_UBOOT_END) ";" \
"era " MK_STR(CFG_FLASH_BASE) " " \
MK_STR(CFG_UBOOT_END) ";" \
- "cp.b ${loadaddr} " MK_STR(CFG_FLASH_BASE)\
+ "cp.b ${loadaddr} " MK_STR(CFG_FLASH_BASE) \
" ${filesize}; save\0" \
""
#endif
#endif
#endif
-#define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
-#define CFG_FLASH_CHECKSUM
-
/*
* This is setting for JFFS2 support in u-boot.
* NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
*/
#define CFG_SDRAM_BASE 0x00000000
#define CFG_SDRAM_CFG1 0x73711630
-#define CFG_SDRAM_CFG2 0x46370000
+#define CFG_SDRAM_CFG2 0x46770000
#define CFG_SDRAM_CTRL 0xE10B0000
#define CFG_SDRAM_EMOD 0x40010000
#define CFG_SDRAM_MODE 0x018D0000
*/
#define CFG_SDRAM_BASE 0x00000000
#define CFG_SDRAM_CFG1 0x73711630
-#define CFG_SDRAM_CFG2 0x46370000
+#define CFG_SDRAM_CFG2 0x46770000
#define CFG_SDRAM_CTRL 0xE10B0000
#define CFG_SDRAM_EMOD 0x40010000
#define CFG_SDRAM_MODE 0x018D0000
#define CFG_CS0_CFG 0x05059310 /* ALE active low, data size 4bytes */
#define CFG_CS2_CFG 0x05059010 /* ALE active low, data size 1byte */
+#define CFG_CS_ALETIMING 0x00000005 /* Use alternative CS timing for CS0 and CS2 */
/* Use SRAM for initial stack */
#define CFG_INIT_RAM_ADDR CFG_SRAM_BASE /* Initial RAM address */
#define CS5_CONFIG 0x00014
#define CS6_CONFIG 0x00018
#define CS7_CONFIG 0x0001C
+#define CS_ALE_TIMING_CONFIG 0x00034
#define CS_CTRL 0x00020
#define CS_CTRL_ME 0x01000000 /* CS Master Enable bit */
#include <spi.h>
#endif
+#include <nand.h>
+
DECLARE_GLOBAL_DATA_PTR;
static char *failed = "*** failed ***\n";