They have been superseded by the gallium equivalents.
Acked-by: Michel Dänzer <michel@daenzer.net>
Acked-by: Alex Deucher <alexdeucher@gmail.com>
Acked-by: Dave Airlie <airlied@gmail.com>
Acked-by: Corbin Simpson <mostawesomedude@gmail.com>
+++ /dev/null
-#!/bin/sh
-indent -npro -kr -i8 -ts8 -sob -l80 -ss -ncs "$@"
+++ /dev/null
-# src/mesa/drivers/dri/r300/Makefile
-
-TOP = ../../../../..
-include $(TOP)/configs/current
-
-LIBNAME = r300_dri.so
-
-include ../Makefile.defines
-
-ifeq ($(RADEON_LDFLAGS),)
-CS_SOURCES = radeon_cs_space_drm.c radeon_bo.c radeon_cs.c
-endif
-
-RADEON_COMMON_SOURCES = \
- radeon_bo_legacy.c \
- radeon_buffer_objects.c \
- radeon_common_context.c \
- radeon_common.c \
- radeon_cs_legacy.c \
- radeon_dma.c \
- radeon_debug.c \
- radeon_fbo.c \
- radeon_lock.c \
- radeon_mipmap_tree.c \
- radeon_pixel_read.c \
- radeon_queryobj.c \
- radeon_span.c \
- radeon_texture.c \
- radeon_tex_copy.c \
- radeon_tile.c
-
-DRIVER_SOURCES = \
- radeon_screen.c \
- r300_blit.c \
- r300_context.c \
- r300_draw.c \
- r300_cmdbuf.c \
- r300_state.c \
- r300_render.c \
- r300_tex.c \
- r300_texstate.c \
- r300_vertprog.c \
- r300_fragprog_common.c \
- r300_shader.c \
- radeon_mesa_to_rc.c \
- r300_emit.c \
- r300_swtcl.c \
- $(RADEON_COMMON_SOURCES) \
- $(EGL_SOURCES) \
- $(CS_SOURCES)
-
-C_SOURCES = $(COMMON_SOURCES) $(DRIVER_SOURCES)
-
-DRIVER_DEFINES = -DRADEON_R300
-# -DRADEON_BO_TRACK \
-
-INCLUDES += $(RADEON_CFLAGS)
-DRI_LIB_DEPS += $(RADEON_LDFLAGS)
-
-SUBDIRS = compiler
-
-EXTRA_MODULES = compiler/libr300compiler.a
-
-
-##### TARGETS #####
-
-include ../Makefile.targets
-
+++ /dev/null
-/*
- * Copyright (C) 2009 Maciej Cencora <m.cencora@gmail.com>
- *
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial
- * portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
- * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
- * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
- * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-
-#include "radeon_common.h"
-#include "r300_context.h"
-
-#include "r300_blit.h"
-#include "r300_cmdbuf.h"
-#include "r300_emit.h"
-#include "r300_tex.h"
-#include "compiler/radeon_compiler.h"
-#include "compiler/radeon_opcodes.h"
-
-static void vp_ins_outs(struct r300_vertex_program_compiler *c)
-{
- c->code->inputs[VERT_ATTRIB_POS] = 0;
- c->code->inputs[VERT_ATTRIB_TEX0] = 1;
- c->code->outputs[VERT_RESULT_HPOS] = 0;
- c->code->outputs[VERT_RESULT_TEX0] = 1;
-}
-
-static void fp_allocate_hw_inputs(
- struct r300_fragment_program_compiler * c,
- void (*allocate)(void * data, unsigned input, unsigned hwreg),
- void * mydata)
-{
- allocate(mydata, FRAG_ATTRIB_TEX0, 0);
-}
-
-static void create_vertex_program(struct r300_context *r300)
-{
- struct r300_vertex_program_compiler compiler;
- struct rc_instruction *inst;
-
- memset(&compiler, 0, sizeof(compiler));
- rc_init(&compiler.Base);
-
- inst = rc_insert_new_instruction(&compiler.Base, compiler.Base.Program.Instructions.Prev);
- inst->U.I.Opcode = RC_OPCODE_MOV;
- inst->U.I.DstReg.File = RC_FILE_OUTPUT;
- inst->U.I.DstReg.Index = VERT_RESULT_HPOS;
- inst->U.I.DstReg.WriteMask = RC_MASK_XYZW;
- inst->U.I.SrcReg[0].Abs = 0;
- inst->U.I.SrcReg[0].File = RC_FILE_INPUT;
- inst->U.I.SrcReg[0].Index = VERT_ATTRIB_POS;
- inst->U.I.SrcReg[0].Negate = 0;
- inst->U.I.SrcReg[0].RelAddr = 0;
- inst->U.I.SrcReg[0].Swizzle = RC_SWIZZLE_XYZW;
-
- inst = rc_insert_new_instruction(&compiler.Base, compiler.Base.Program.Instructions.Prev);
- inst->U.I.Opcode = RC_OPCODE_MOV;
- inst->U.I.DstReg.File = RC_FILE_OUTPUT;
- inst->U.I.DstReg.Index = VERT_RESULT_TEX0;
- inst->U.I.DstReg.WriteMask = RC_MASK_XYZW;
- inst->U.I.SrcReg[0].Abs = 0;
- inst->U.I.SrcReg[0].File = RC_FILE_INPUT;
- inst->U.I.SrcReg[0].Index = VERT_ATTRIB_TEX0;
- inst->U.I.SrcReg[0].Negate = 0;
- inst->U.I.SrcReg[0].RelAddr = 0;
- inst->U.I.SrcReg[0].Swizzle = RC_SWIZZLE_XYZW;
-
- compiler.Base.Program.InputsRead = (1 << VERT_ATTRIB_POS) | (1 << VERT_ATTRIB_TEX0);
- compiler.RequiredOutputs = compiler.Base.Program.OutputsWritten = (1 << VERT_RESULT_HPOS) | (1 << VERT_RESULT_TEX0);
- compiler.SetHwInputOutput = vp_ins_outs;
- compiler.code = &r300->blit.vp_code;
- compiler.Base.is_r500 = r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515;
- compiler.Base.disable_optimizations = 0;
- compiler.Base.has_half_swizzles = 0;
- compiler.Base.max_temp_regs = 32;
- compiler.Base.max_constants = 256;
- compiler.Base.max_alu_insts = compiler.Base.is_r500 ? 1024 : 256;
-
- r3xx_compile_vertex_program(&compiler);
-}
-
-static void create_fragment_program(struct r300_context *r300)
-{
- struct r300_fragment_program_compiler compiler;
- struct rc_instruction *inst;
-
- memset(&compiler, 0, sizeof(struct r300_fragment_program_compiler));
- rc_init(&compiler.Base);
-
- inst = rc_insert_new_instruction(&compiler.Base, compiler.Base.Program.Instructions.Prev);
- inst->U.I.Opcode = RC_OPCODE_TEX;
- inst->U.I.TexSrcTarget = RC_TEXTURE_2D;
- inst->U.I.TexSrcUnit = 0;
- inst->U.I.DstReg.File = RC_FILE_OUTPUT;
- inst->U.I.DstReg.Index = FRAG_RESULT_COLOR;
- inst->U.I.DstReg.WriteMask = RC_MASK_XYZW;
- inst->U.I.SrcReg[0].Abs = 0;
- inst->U.I.SrcReg[0].File = RC_FILE_INPUT;
- inst->U.I.SrcReg[0].Index = FRAG_ATTRIB_TEX0;
- inst->U.I.SrcReg[0].Negate = 0;
- inst->U.I.SrcReg[0].RelAddr = 0;
- inst->U.I.SrcReg[0].Swizzle = RC_SWIZZLE_XYZW;
- inst->U.I.TexSwizzle = RC_SWIZZLE_XYZW;
-
- compiler.Base.Program.InputsRead = (1 << FRAG_ATTRIB_TEX0);
- compiler.OutputColor[0] = FRAG_RESULT_COLOR;
- compiler.OutputDepth = FRAG_RESULT_DEPTH;
- compiler.enable_shadow_ambient = GL_TRUE;
- compiler.Base.is_r500 = (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515);
- compiler.Base.disable_optimizations = 0;
- compiler.Base.has_half_swizzles = 1;
- compiler.Base.max_temp_regs = (compiler.Base.is_r500) ? 128 : 32;
- compiler.Base.max_constants = compiler.Base.is_r500 ? 256 : 32;
- compiler.Base.max_alu_insts = compiler.Base.is_r500 ? 512 : 64;
- compiler.Base.max_tex_insts = compiler.Base.is_r500 ? 512 : 32;
- compiler.code = &r300->blit.fp_code;
- compiler.AllocateHwInputs = fp_allocate_hw_inputs;
-
- r3xx_compile_fragment_program(&compiler);
-}
-
-void r300_blit_init(struct r300_context *r300)
-{
- if (r300->options.hw_tcl_enabled)
- create_vertex_program(r300);
- create_fragment_program(r300);
-}
-
-static void r300_emit_tx_setup(struct r300_context *r300,
- gl_format mesa_format,
- struct radeon_bo *bo,
- intptr_t offset,
- unsigned width,
- unsigned height,
- unsigned pitch)
-{
- int is_r500 = r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515;
- BATCH_LOCALS(&r300->radeon);
-
- assert(is_r500 ? width <= 4096 : width <= 2048);
- assert(is_r500 ? height <= 4096 : height <= 2048);
- assert(r300TranslateTexFormat(mesa_format) >= 0);
- assert(offset % 32 == 0);
-
- BEGIN_BATCH(17);
- OUT_BATCH_REGVAL(R300_TX_FILTER0_0,
- (R300_TX_CLAMP_TO_EDGE << R300_TX_WRAP_S_SHIFT) |
- (R300_TX_CLAMP_TO_EDGE << R300_TX_WRAP_T_SHIFT) |
- (R300_TX_CLAMP_TO_EDGE << R300_TX_WRAP_R_SHIFT) |
- R300_TX_MIN_FILTER_MIP_NONE |
- R300_TX_MIN_FILTER_NEAREST |
- R300_TX_MAG_FILTER_NEAREST |
- (0 << 28));
- OUT_BATCH_REGVAL(R300_TX_FILTER1_0, 0);
- OUT_BATCH_REGVAL(R300_TX_SIZE_0,
- (((width - 1) & 0x7ff) << R300_TX_WIDTHMASK_SHIFT) |
- (((height - 1) & 0x7ff) << R300_TX_HEIGHTMASK_SHIFT) |
- (0 << R300_TX_DEPTHMASK_SHIFT) |
- (0 << R300_TX_MAX_MIP_LEVEL_SHIFT) |
- R300_TX_SIZE_TXPITCH_EN);
-
- OUT_BATCH_REGVAL(R300_TX_FORMAT_0, r300TranslateTexFormat(mesa_format));
- OUT_BATCH_REGVAL(R300_TX_FORMAT2_0,
- (pitch - 1) |
- (is_r500 && width > 2048 ? R500_TXWIDTH_BIT11 : 0) |
- (is_r500 && height > 2048 ? R500_TXHEIGHT_BIT11 : 0));
- OUT_BATCH_REGSEQ(R300_TX_OFFSET_0, 1);
- OUT_BATCH_RELOC(0, bo, offset, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
-
- OUT_BATCH_REGSEQ(R300_TX_INVALTAGS, 2);
- OUT_BATCH(0);
- OUT_BATCH(1);
-
- END_BATCH();
-}
-
-#define EASY_US_FORMAT(FMT, C0, C1, C2, C3, SIGN) \
- (FMT | R500_C0_SEL_##C0 | R500_C1_SEL_##C1 | \
- R500_C2_SEL_##C2 | R500_C3_SEL_##C3 | R500_OUT_SIGN(SIGN))
-
-static uint32_t mesa_format_to_us_format(gl_format mesa_format)
-{
- switch(mesa_format)
- {
- case MESA_FORMAT_RGBA8888: // x
- return EASY_US_FORMAT(R500_OUT_FMT_C4_8, A, B, G, R, 0);
- case MESA_FORMAT_RGB565: // x
- case MESA_FORMAT_ARGB1555: // x
- case MESA_FORMAT_RGBA8888_REV: // x
- return EASY_US_FORMAT(R500_OUT_FMT_C4_8, R, G, B, A, 0);
- case MESA_FORMAT_ARGB8888: // x
- return EASY_US_FORMAT(R500_OUT_FMT_C4_8, B, G, R, A, 0);
- case MESA_FORMAT_ARGB8888_REV:
- return EASY_US_FORMAT(R500_OUT_FMT_C4_8, A, R, G, B, 0);
- case MESA_FORMAT_XRGB8888:
- return EASY_US_FORMAT(R500_OUT_FMT_C4_8, A, R, G, B, 0);
-
- case MESA_FORMAT_RGB332:
- return EASY_US_FORMAT(R500_OUT_FMT_C_3_3_2, A, R, G, B, 0);
-
- case MESA_FORMAT_RGBA_FLOAT32:
- return EASY_US_FORMAT(R500_OUT_FMT_C4_32_FP, R, G, B, A, 0);
- case MESA_FORMAT_RGBA_FLOAT16:
- return EASY_US_FORMAT(R500_OUT_FMT_C4_16_FP, R, G, B, A, 0);
- case MESA_FORMAT_ALPHA_FLOAT32:
- return EASY_US_FORMAT(R500_OUT_FMT_C_32_FP, A, A, A, A, 0);
- case MESA_FORMAT_ALPHA_FLOAT16:
- return EASY_US_FORMAT(R500_OUT_FMT_C_16_FP, A, A, A, A, 0);
-
- case MESA_FORMAT_SIGNED_RGBA8888:
- return EASY_US_FORMAT(R500_OUT_FMT_C4_8, R, G, B, A, 0xf);
- case MESA_FORMAT_SIGNED_RGBA8888_REV:
- return EASY_US_FORMAT(R500_OUT_FMT_C4_8, A, B, G, R, 0xf);
- case MESA_FORMAT_SIGNED_RGBA_16:
- return EASY_US_FORMAT(R500_OUT_FMT_C4_16, R, G, B, A, 0xf);
-
- default:
- fprintf(stderr, "Unsupported format %s for US output\n", _mesa_get_format_name(mesa_format));
- assert(0);
- return 0;
- }
-}
-#undef EASY_US_FORMAT
-
-static void r500_emit_fp_setup(struct r300_context *r300,
- struct r500_fragment_program_code *fp,
- gl_format dst_format)
-{
- r500_emit_fp(r300, (uint32_t *)fp->inst, (fp->inst_end + 1) * 6, 0, 0, 0);
- BATCH_LOCALS(&r300->radeon);
-
- BEGIN_BATCH(10);
- OUT_BATCH_REGSEQ(R500_US_CODE_ADDR, 3);
- OUT_BATCH(R500_US_CODE_START_ADDR(0) | R500_US_CODE_END_ADDR(fp->inst_end));
- OUT_BATCH(R500_US_CODE_RANGE_ADDR(0) | R500_US_CODE_RANGE_SIZE(fp->inst_end));
- OUT_BATCH(0);
- OUT_BATCH_REGVAL(R500_US_CONFIG, 0);
- OUT_BATCH_REGVAL(R500_US_OUT_FMT_0, mesa_format_to_us_format(dst_format));
- OUT_BATCH_REGVAL(R500_US_PIXSIZE, fp->max_temp_idx);
- END_BATCH();
-}
-
-static void r500_emit_rs_setup(struct r300_context *r300)
-{
- BATCH_LOCALS(&r300->radeon);
-
- BEGIN_BATCH(7);
- OUT_BATCH_REGSEQ(R300_RS_COUNT, 2);
- OUT_BATCH((4 << R300_IT_COUNT_SHIFT) | R300_HIRES_EN);
- OUT_BATCH(0);
- OUT_BATCH_REGVAL(R500_RS_INST_0,
- (0 << R500_RS_INST_TEX_ID_SHIFT) |
- (0 << R500_RS_INST_TEX_ADDR_SHIFT) |
- R500_RS_INST_TEX_CN_WRITE |
- R500_RS_INST_COL_CN_NO_WRITE);
- OUT_BATCH_REGVAL(R500_RS_IP_0,
- (0 << R500_RS_IP_TEX_PTR_S_SHIFT) |
- (1 << R500_RS_IP_TEX_PTR_T_SHIFT) |
- (2 << R500_RS_IP_TEX_PTR_R_SHIFT) |
- (3 << R500_RS_IP_TEX_PTR_Q_SHIFT));
- END_BATCH();
-}
-
-static void r300_emit_fp_setup(struct r300_context *r300,
- struct r300_fragment_program_code *code,
- gl_format dst_format)
-{
- unsigned i;
- BATCH_LOCALS(&r300->radeon);
-
- BEGIN_BATCH((code->alu.length + 1) * 4 + code->tex.length + 1 + 11);
-
- OUT_BATCH_REGSEQ(R300_US_ALU_RGB_INST_0, code->alu.length);
- for (i = 0; i < code->alu.length; i++) {
- OUT_BATCH(code->alu.inst[i].rgb_inst);
- }
- OUT_BATCH_REGSEQ(R300_US_ALU_RGB_ADDR_0, code->alu.length);
- for (i = 0; i < code->alu.length; i++) {
- OUT_BATCH(code->alu.inst[i].rgb_addr);
- }
- OUT_BATCH_REGSEQ(R300_US_ALU_ALPHA_INST_0, code->alu.length);
- for (i = 0; i < code->alu.length; i++) {
- OUT_BATCH(code->alu.inst[i].alpha_inst);
- }
- OUT_BATCH_REGSEQ(R300_US_ALU_ALPHA_ADDR_0, code->alu.length);
- for (i = 0; i < code->alu.length; i++) {
- OUT_BATCH(code->alu.inst[i].alpha_addr);
- }
-
- OUT_BATCH_REGSEQ(R300_US_TEX_INST_0, code->tex.length);
- OUT_BATCH_TABLE(code->tex.inst, code->tex.length);
-
- OUT_BATCH_REGSEQ(R300_US_CONFIG, 3);
- OUT_BATCH(R300_PFS_CNTL_FIRST_NODE_HAS_TEX);
- OUT_BATCH(code->pixsize);
- OUT_BATCH(code->code_offset);
- OUT_BATCH_REGSEQ(R300_US_CODE_ADDR_0, 4);
- OUT_BATCH_TABLE(code->code_addr, 4);
- OUT_BATCH_REGVAL(R500_US_OUT_FMT_0, mesa_format_to_us_format(dst_format));
- END_BATCH();
-}
-
-static void r300_emit_rs_setup(struct r300_context *r300)
-{
- BATCH_LOCALS(&r300->radeon);
-
- BEGIN_BATCH(7);
- OUT_BATCH_REGSEQ(R300_RS_COUNT, 2);
- OUT_BATCH((4 << R300_IT_COUNT_SHIFT) | R300_HIRES_EN);
- OUT_BATCH(0);
- OUT_BATCH_REGVAL(R300_RS_INST_0,
- R300_RS_INST_TEX_ID(0) |
- R300_RS_INST_TEX_ADDR(0) |
- R300_RS_INST_TEX_CN_WRITE);
- OUT_BATCH_REGVAL(R300_RS_IP_0,
- R300_RS_TEX_PTR(0) |
- R300_RS_SEL_S(R300_RS_SEL_C0) |
- R300_RS_SEL_T(R300_RS_SEL_C1) |
- R300_RS_SEL_R(R300_RS_SEL_K0) |
- R300_RS_SEL_Q(R300_RS_SEL_K1));
- END_BATCH();
-}
-
-static void emit_pvs_setup(struct r300_context *r300,
- uint32_t *vp_code,
- unsigned vp_len)
-{
- BATCH_LOCALS(&r300->radeon);
-
- r300_emit_vpu(r300, vp_code, vp_len * 4, R300_PVS_CODE_START);
-
- BEGIN_BATCH(4);
- OUT_BATCH_REGSEQ(R300_VAP_PVS_CODE_CNTL_0, 3);
- OUT_BATCH((0 << R300_PVS_FIRST_INST_SHIFT) |
- ((vp_len - 1) << R300_PVS_XYZW_VALID_INST_SHIFT) |
- ((vp_len - 1)<< R300_PVS_LAST_INST_SHIFT));
- OUT_BATCH(0);
- OUT_BATCH((vp_len - 1) << R300_PVS_LAST_VTX_SRC_INST_SHIFT);
- END_BATCH();
-}
-
-static void emit_vap_setup(struct r300_context *r300)
-{
- int tex_offset;
- BATCH_LOCALS(&r300->radeon);
-
- if (r300->options.hw_tcl_enabled)
- tex_offset = 1;
- else
- tex_offset = 6;
-
- BEGIN_BATCH(12);
- OUT_BATCH_REGSEQ(R300_SE_VTE_CNTL, 2);
- OUT_BATCH(R300_VTX_XY_FMT | R300_VTX_Z_FMT);
- OUT_BATCH(4);
-
- OUT_BATCH_REGVAL(R300_VAP_PSC_SGN_NORM_CNTL, 0xaaaaaaaa);
- OUT_BATCH_REGVAL(R300_VAP_PROG_STREAM_CNTL_0,
- ((R300_DATA_TYPE_FLOAT_2 | (0 << R300_DST_VEC_LOC_SHIFT)) << 0) |
- (((tex_offset << R300_DST_VEC_LOC_SHIFT) | R300_DATA_TYPE_FLOAT_2 | R300_LAST_VEC) << 16));
- OUT_BATCH_REGVAL(R300_VAP_PROG_STREAM_CNTL_EXT_0,
- ((((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_SHIFT) |
- (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_SHIFT) |
- (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_SHIFT) |
- (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_SHIFT) |
- (0xf << R300_WRITE_ENA_SHIFT) ) << 0) |
- (((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_SHIFT) |
- (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_SHIFT) |
- (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_SHIFT) |
- (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_SHIFT) |
- (0xf << R300_WRITE_ENA_SHIFT) ) << 16) ) );
- OUT_BATCH_REGSEQ(R300_VAP_OUTPUT_VTX_FMT_0, 2);
- OUT_BATCH(R300_VAP_OUTPUT_VTX_FMT_0__POS_PRESENT);
- OUT_BATCH(R300_VAP_OUTPUT_VTX_FMT_1__4_COMPONENTS);
- END_BATCH();
-}
-
-static GLboolean validate_buffers(struct r300_context *r300,
- struct radeon_bo *src_bo,
- struct radeon_bo *dst_bo)
-{
- int ret;
-
- radeon_cs_space_reset_bos(r300->radeon.cmdbuf.cs);
-
- ret = radeon_cs_space_check_with_bo(r300->radeon.cmdbuf.cs,
- src_bo, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0);
- if (ret)
- return GL_FALSE;
-
- ret = radeon_cs_space_check_with_bo(r300->radeon.cmdbuf.cs,
- dst_bo, 0, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT);
- if (ret)
- return GL_FALSE;
-
- return GL_TRUE;
-}
-
-/**
- * Calculate texcoords for given image region.
- * Output values are [minx, maxx, miny, maxy]
- */
-static void calc_tex_coords(float img_width, float img_height,
- float x, float y,
- float reg_width, float reg_height,
- unsigned flip_y, float *buf)
-{
- buf[0] = x / img_width;
- buf[1] = buf[0] + reg_width / img_width;
- buf[2] = y / img_height;
- buf[3] = buf[2] + reg_height / img_height;
- if (flip_y)
- {
- buf[2] = 1.0 - buf[2];
- buf[3] = 1.0 - buf[3];
- }
-}
-
-static void emit_draw_packet(struct r300_context *r300,
- unsigned src_width, unsigned src_height,
- unsigned src_x_offset, unsigned src_y_offset,
- unsigned dst_x_offset, unsigned dst_y_offset,
- unsigned reg_width, unsigned reg_height,
- unsigned flip_y)
-{
- float texcoords[4];
-
- calc_tex_coords(src_width, src_height,
- src_x_offset, src_y_offset,
- reg_width, reg_height,
- flip_y, texcoords);
-
- float verts[] = { dst_x_offset, dst_y_offset,
- texcoords[0], texcoords[2],
- dst_x_offset, dst_y_offset + reg_height,
- texcoords[0], texcoords[3],
- dst_x_offset + reg_width, dst_y_offset + reg_height,
- texcoords[1], texcoords[3],
- dst_x_offset + reg_width, dst_y_offset,
- texcoords[1], texcoords[2] };
-
- BATCH_LOCALS(&r300->radeon);
-
- BEGIN_BATCH(19);
- OUT_BATCH_PACKET3(R300_PACKET3_3D_DRAW_IMMD_2, 16);
- OUT_BATCH(R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_EMBEDDED |
- (4 << 16) | R300_VAP_VF_CNTL__PRIM_QUADS);
- OUT_BATCH_TABLE(verts, 16);
- END_BATCH();
-}
-
-static void other_stuff(struct r300_context *r300)
-{
- BATCH_LOCALS(&r300->radeon);
-
- BEGIN_BATCH(13);
- OUT_BATCH_REGVAL(R300_GA_POLY_MODE,
- R300_GA_POLY_MODE_FRONT_PTYPE_TRI | R300_GA_POLY_MODE_BACK_PTYPE_TRI);
- OUT_BATCH_REGVAL(R300_SU_CULL_MODE, R300_FRONT_FACE_CCW);
- OUT_BATCH_REGVAL(R300_FG_FOG_BLEND, 0);
- OUT_BATCH_REGVAL(R300_FG_ALPHA_FUNC, 0);
- OUT_BATCH_REGSEQ(R300_RB3D_CBLEND, 2);
- OUT_BATCH(0x0);
- OUT_BATCH(0x0);
- OUT_BATCH_REGVAL(R300_ZB_CNTL, 0);
- END_BATCH();
- if (r300->options.hw_tcl_enabled) {
- BEGIN_BATCH(2);
- OUT_BATCH_REGVAL(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE);
- END_BATCH();
- }
-}
-
-static void emit_cb_setup(struct r300_context *r300,
- struct radeon_bo *bo,
- intptr_t offset,
- gl_format mesa_format,
- unsigned pitch,
- unsigned width,
- unsigned height)
-{
- BATCH_LOCALS(&r300->radeon);
-
- unsigned x1, y1, x2, y2;
- x1 = 0;
- y1 = 0;
- x2 = width - 1;
- y2 = height - 1;
-
- if (r300->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV515) {
- x1 += R300_SCISSORS_OFFSET;
- y1 += R300_SCISSORS_OFFSET;
- x2 += R300_SCISSORS_OFFSET;
- y2 += R300_SCISSORS_OFFSET;
- }
-
- r300_emit_cb_setup(r300, bo, offset, mesa_format,
- _mesa_get_format_bytes(mesa_format),
- _mesa_format_row_stride(mesa_format, pitch));
-
- BEGIN_BATCH_NO_AUTOSTATE(5);
- OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL, 2);
- OUT_BATCH((x1 << R300_SCISSORS_X_SHIFT)|(y1 << R300_SCISSORS_Y_SHIFT));
- OUT_BATCH((x2 << R300_SCISSORS_X_SHIFT)|(y2 << R300_SCISSORS_Y_SHIFT));
- OUT_BATCH_REGVAL(R300_RB3D_CCTL, 0);
- END_BATCH();
-}
-
-unsigned r300_check_blit(gl_format dst_format)
-{
- switch (dst_format) {
- case MESA_FORMAT_RGB565:
- case MESA_FORMAT_ARGB1555:
- case MESA_FORMAT_RGBA8888:
- case MESA_FORMAT_RGBA8888_REV:
- case MESA_FORMAT_ARGB8888:
- case MESA_FORMAT_ARGB8888_REV:
- case MESA_FORMAT_XRGB8888:
- break;
- default:
- return 0;
- }
-
- if (_mesa_get_format_bits(dst_format, GL_DEPTH_BITS) > 0)
- return 0;
-
- return 1;
-}
-
-/**
- * Copy a region of [@a width x @a height] pixels from source buffer
- * to destination buffer.
- * @param[in] r300 r300 context
- * @param[in] src_bo source radeon buffer object
- * @param[in] src_offset offset of the source image in the @a src_bo
- * @param[in] src_mesaformat source image format
- * @param[in] src_pitch aligned source image width
- * @param[in] src_width source image width
- * @param[in] src_height source image height
- * @param[in] src_x_offset x offset in the source image
- * @param[in] src_y_offset y offset in the source image
- * @param[in] dst_bo destination radeon buffer object
- * @param[in] dst_offset offset of the destination image in the @a dst_bo
- * @param[in] dst_mesaformat destination image format
- * @param[in] dst_pitch aligned destination image width
- * @param[in] dst_width destination image width
- * @param[in] dst_height destination image height
- * @param[in] dst_x_offset x offset in the destination image
- * @param[in] dst_y_offset y offset in the destination image
- * @param[in] width region width
- * @param[in] height region height
- * @param[in] flip_y set if y coords of the source image need to be flipped
- */
-unsigned r300_blit(struct gl_context *ctx,
- struct radeon_bo *src_bo,
- intptr_t src_offset,
- gl_format src_mesaformat,
- unsigned src_pitch,
- unsigned src_width,
- unsigned src_height,
- unsigned src_x_offset,
- unsigned src_y_offset,
- struct radeon_bo *dst_bo,
- intptr_t dst_offset,
- gl_format dst_mesaformat,
- unsigned dst_pitch,
- unsigned dst_width,
- unsigned dst_height,
- unsigned dst_x_offset,
- unsigned dst_y_offset,
- unsigned reg_width,
- unsigned reg_height,
- unsigned flip_y)
-{
- r300ContextPtr r300 = R300_CONTEXT(ctx);
-
- if (!r300_check_blit(dst_mesaformat))
- return 0;
-
- /* Make sure that colorbuffer has even width - hw limitation */
- if (dst_pitch % 2 > 0)
- ++dst_pitch;
-
- /* Need to clamp the region size to make sure
- * we don't read outside of the source buffer
- * or write outside of the destination buffer.
- */
- if (reg_width + src_x_offset > src_width)
- reg_width = src_width - src_x_offset;
- if (reg_height + src_y_offset > src_height)
- reg_height = src_height - src_y_offset;
- if (reg_width + dst_x_offset > dst_width)
- reg_width = dst_width - dst_x_offset;
- if (reg_height + dst_y_offset > dst_height)
- reg_height = dst_height - dst_y_offset;
-
- if (src_bo == dst_bo) {
- return 0;
- }
-
- if (src_offset % 32 || dst_offset % 32) {
- return GL_FALSE;
- }
-
- if (0) {
- fprintf(stderr, "src: size [%d x %d], pitch %d, "
- "offset [%d x %d], format %s, bo %p\n",
- src_width, src_height, src_pitch,
- src_x_offset, src_y_offset,
- _mesa_get_format_name(src_mesaformat),
- src_bo);
- fprintf(stderr, "dst: pitch %d, offset[%d x %d], format %s, bo %p\n",
- dst_pitch, dst_x_offset, dst_y_offset,
- _mesa_get_format_name(dst_mesaformat), dst_bo);
- fprintf(stderr, "region: %d x %d\n", reg_width, reg_height);
- }
-
- /* Flush is needed to make sure that source buffer has correct data */
- radeonFlush(r300->radeon.glCtx);
-
- if (!validate_buffers(r300, src_bo, dst_bo))
- return 0;
-
- rcommonEnsureCmdBufSpace(&r300->radeon, 200, __FUNCTION__);
-
- other_stuff(r300);
-
- r300_emit_tx_setup(r300, src_mesaformat, src_bo, src_offset, src_width, src_height, src_pitch);
-
- if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) {
- r500_emit_fp_setup(r300, &r300->blit.fp_code.code.r500, dst_mesaformat);
- r500_emit_rs_setup(r300);
- } else {
- r300_emit_fp_setup(r300, &r300->blit.fp_code.code.r300, dst_mesaformat);
- r300_emit_rs_setup(r300);
- }
-
- if (r300->options.hw_tcl_enabled)
- emit_pvs_setup(r300, r300->blit.vp_code.body.d, 2);
-
- emit_vap_setup(r300);
-
- emit_cb_setup(r300, dst_bo, dst_offset, dst_mesaformat, dst_pitch, dst_width, dst_height);
-
- emit_draw_packet(r300, src_width, src_height,
- src_x_offset, src_y_offset,
- dst_x_offset, dst_y_offset,
- reg_width, reg_height,
- flip_y);
-
- r300EmitCacheFlush(r300);
-
- radeonFlush(r300->radeon.glCtx);
-
- return 1;
-}
+++ /dev/null
-/*
- * Copyright (C) 2009 Maciej Cencora <m.cencora@gmail.com>
- *
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial
- * portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
- * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
- * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
- * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-
-#ifndef R300_BLIT_H
-#define R300_BLIT_H
-
-void r300_blit_init(struct r300_context *r300);
-
-unsigned r300_check_blit(gl_format mesa_format);
-
-unsigned r300_blit(struct gl_context *ctx,
- struct radeon_bo *src_bo,
- intptr_t src_offset,
- gl_format src_mesaformat,
- unsigned src_pitch,
- unsigned src_width,
- unsigned src_height,
- unsigned src_x_offset,
- unsigned src_y_offset,
- struct radeon_bo *dst_bo,
- intptr_t dst_offset,
- gl_format dst_mesaformat,
- unsigned dst_pitch,
- unsigned dst_width,
- unsigned dst_height,
- unsigned dst_x_offset,
- unsigned dst_y_offset,
- unsigned reg_width,
- unsigned reg_height,
- unsigned flip_y);
-
-#endif // R300_BLIT_H
+++ /dev/null
-/*
-Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
-
-The Weather Channel (TM) funded Tungsten Graphics to develop the
-initial release of the Radeon 8500 driver under the XFree86 license.
-This notice must be preserved.
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-**************************************************************************/
-
-/**
- * \file
- *
- * \author Nicolai Haehnle <prefect_@gmx.net>
- */
-
-#include "main/glheader.h"
-#include "main/state.h"
-#include "main/imports.h"
-#include "main/macros.h"
-#include "main/context.h"
-#include "main/simple_list.h"
-
-#include "drm.h"
-#include "radeon_drm.h"
-
-#include "r300_context.h"
-#include "r300_reg.h"
-#include "r300_cmdbuf.h"
-#include "r300_emit.h"
-#include "radeon_bocs_wrapper.h"
-#include "radeon_mipmap_tree.h"
-#include "radeon_queryobj.h"
-
-/** # of dwords reserved for additional instructions that may need to be written
- * during flushing.
- */
-#define SPACE_FOR_FLUSHING 4
-
-static unsigned packet0_count(r300ContextPtr r300, uint32_t *pkt)
-{
- if (r300->radeon.radeonScreen->kernel_mm) {
- return ((((*pkt) >> 16) & 0x3FFF) + 1);
- } else {
- drm_r300_cmd_header_t *t = (drm_r300_cmd_header_t*)pkt;
- return t->packet0.count;
- }
-}
-
-#define vpu_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->vpu.count)
-#define r500fp_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->r500fp.count)
-
-static int check_vpu(struct gl_context *ctx, struct radeon_state_atom *atom)
-{
- r300ContextPtr r300 = R300_CONTEXT(ctx);
- int cnt;
- int extra = 1;
- cnt = vpu_count(atom->cmd);
-
- if (r300->radeon.radeonScreen->kernel_mm) {
- extra = 3;
- }
-
- return cnt ? (cnt * 4) + extra : 0;
-}
-
-static int check_vpp(struct gl_context *ctx, struct radeon_state_atom *atom)
-{
- r300ContextPtr r300 = R300_CONTEXT(ctx);
- int cnt;
- int extra = 1;
-
- if (r300->radeon.radeonScreen->kernel_mm) {
- cnt = r300->selected_vp->code.constants.Count * 4;
- extra = 3;
- } else {
- cnt = vpu_count(atom->cmd);
- extra = 1;
- }
-
- return cnt ? (cnt * 4) + extra : 0;
-}
-
-void r300_emit_vpu(struct r300_context *r300,
- uint32_t *data,
- unsigned len,
- uint32_t addr)
-{
- BATCH_LOCALS(&r300->radeon);
-
- BEGIN_BATCH_NO_AUTOSTATE(3 + len);
- OUT_BATCH_REGVAL(R300_VAP_PVS_VECTOR_INDX_REG, addr);
- OUT_BATCH(CP_PACKET0(R300_VAP_PVS_UPLOAD_DATA, len-1) | RADEON_ONE_REG_WR);
- OUT_BATCH_TABLE(data, len);
- END_BATCH();
-}
-
-static void emit_vpu_state(struct gl_context *ctx, struct radeon_state_atom * atom)
-{
- r300ContextPtr r300 = R300_CONTEXT(ctx);
- drm_r300_cmd_header_t cmd;
- uint32_t addr;
-
- cmd.u = atom->cmd[0];
- addr = (cmd.vpu.adrhi << 8) | cmd.vpu.adrlo;
-
- r300_emit_vpu(r300, &atom->cmd[1], vpu_count(atom->cmd) * 4, addr);
-}
-
-static void emit_vpp_state(struct gl_context *ctx, struct radeon_state_atom * atom)
-{
- r300ContextPtr r300 = R300_CONTEXT(ctx);
- drm_r300_cmd_header_t cmd;
- uint32_t addr;
-
- cmd.u = atom->cmd[0];
- addr = (cmd.vpu.adrhi << 8) | cmd.vpu.adrlo;
-
- r300_emit_vpu(r300, &atom->cmd[1], r300->selected_vp->code.constants.Count * 4, addr);
-}
-
-void r500_emit_fp(struct r300_context *r300,
- uint32_t *data,
- unsigned len,
- uint32_t addr,
- unsigned type,
- unsigned clamp)
-{
- BATCH_LOCALS(&r300->radeon);
-
- addr |= (type << 16);
- addr |= (clamp << 17);
-
- BEGIN_BATCH_NO_AUTOSTATE(len + 3);
- OUT_BATCH(CP_PACKET0(R500_GA_US_VECTOR_INDEX, 0));
- OUT_BATCH(addr);
- OUT_BATCH(CP_PACKET0(R500_GA_US_VECTOR_DATA, len-1) | RADEON_ONE_REG_WR);
- OUT_BATCH_TABLE(data, len);
- END_BATCH();
-}
-
-static void emit_r500fp_atom(struct gl_context *ctx, struct radeon_state_atom * atom)
-{
- r300ContextPtr r300 = R300_CONTEXT(ctx);
- drm_r300_cmd_header_t cmd;
- uint32_t addr, count;
- int type, clamp;
-
- cmd.u = atom->cmd[0];
- addr = ((cmd.r500fp.adrhi_flags & 1) << 8) | cmd.r500fp.adrlo;
- type = !!(cmd.r500fp.adrhi_flags & R500FP_CONSTANT_TYPE);
- clamp = !!(cmd.r500fp.adrhi_flags & R500FP_CONSTANT_CLAMP);
-
- if (type) {
- count = r500fp_count(atom->cmd) * 4;
- } else {
- count = r500fp_count(atom->cmd) * 6;
- }
-
- r500_emit_fp(r300, &atom->cmd[1], count, addr, type, clamp);
-}
-
-static int check_tex_offsets(struct gl_context *ctx, struct radeon_state_atom * atom)
-{
- r300ContextPtr r300 = R300_CONTEXT(ctx);
- int numtmus = packet0_count(r300, r300->hw.tex.offset.cmd);
- int dw = 0, i;
- if (atom->cmd[0] == CP_PACKET2) {
- return dw;
- }
- for(i = 0; i < numtmus; ++i) {
- radeonTexObj *t = r300->hw.textures[i];
- if (!t && !r300->radeon.radeonScreen->kernel_mm) {
- dw += 0;
- } else if (t && t->image_override && !t->bo) {
- if (!r300->radeon.radeonScreen->kernel_mm)
- dw += 2;
- } else
- dw += 4;
- }
- return dw;
-}
-
-static void emit_tex_offsets(struct gl_context *ctx, struct radeon_state_atom * atom)
-{
- r300ContextPtr r300 = R300_CONTEXT(ctx);
- BATCH_LOCALS(&r300->radeon);
- int numtmus = packet0_count(r300, r300->hw.tex.offset.cmd);
- int i;
-
- for(i = 0; i < numtmus; ++i) {
- radeonTexObj *t = r300->hw.textures[i];
- if (t && !t->image_override) {
- BEGIN_BATCH_NO_AUTOSTATE(4);
- OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1);
- OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, get_base_teximage_offset(t),
- RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
- END_BATCH();
- } else if (!t) {
- /* Texture unit hasn't a texture bound.
- * We assign the current color buffer as a fakery to make
- * KIL work on KMS (without it, the CS checker will complain).
- */
- if (r300->radeon.radeonScreen->kernel_mm) {
- struct radeon_renderbuffer *rrb = radeon_get_colorbuffer(&r300->radeon);
- if (rrb && rrb->bo) {
- BEGIN_BATCH_NO_AUTOSTATE(4);
- OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1);
- OUT_BATCH_RELOC(0, rrb->bo, 0,
- RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
- END_BATCH();
- }
- }
- } else { /* override cases */
- if (t->bo) {
- BEGIN_BATCH_NO_AUTOSTATE(4);
- OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1);
- OUT_BATCH_RELOC(t->tile_bits, t->bo, 0,
- RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
- END_BATCH();
- } else if (!r300->radeon.radeonScreen->kernel_mm) {
- BEGIN_BATCH_NO_AUTOSTATE(2);
- OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1);
- OUT_BATCH(t->override_offset);
- END_BATCH();
- } else {
- /* Texture unit hasn't a texture bound nothings to do */
- }
- }
- }
-}
-
-void r300_emit_scissor(struct gl_context *ctx)
-{
- r300ContextPtr r300 = R300_CONTEXT(ctx);
- BATCH_LOCALS(&r300->radeon);
- unsigned x1, y1, x2, y2;
- struct radeon_renderbuffer *rrb;
-
- if (!r300->radeon.radeonScreen->driScreen->dri2.enabled) {
- return;
- }
- rrb = radeon_get_colorbuffer(&r300->radeon);
- if (!rrb || !rrb->bo) {
- fprintf(stderr, "no rrb\n");
- return;
- }
- if (r300->radeon.state.scissor.enabled) {
- x1 = r300->radeon.state.scissor.rect.x1;
- y1 = r300->radeon.state.scissor.rect.y1;
- x2 = r300->radeon.state.scissor.rect.x2;
- y2 = r300->radeon.state.scissor.rect.y2;
- } else {
- x1 = 0;
- y1 = 0;
- x2 = rrb->base.Width - 1;
- y2 = rrb->base.Height - 1;
- }
- if (r300->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV515) {
- x1 += R300_SCISSORS_OFFSET;
- y1 += R300_SCISSORS_OFFSET;
- x2 += R300_SCISSORS_OFFSET;
- y2 += R300_SCISSORS_OFFSET;
- }
- BEGIN_BATCH_NO_AUTOSTATE(3);
- OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL, 2);
- OUT_BATCH((x1 << R300_SCISSORS_X_SHIFT)|(y1 << R300_SCISSORS_Y_SHIFT));
- OUT_BATCH((x2 << R300_SCISSORS_X_SHIFT)|(y2 << R300_SCISSORS_Y_SHIFT));
- END_BATCH();
-}
-static int check_cb_offset(struct gl_context *ctx, struct radeon_state_atom * atom)
-{
- r300ContextPtr r300 = R300_CONTEXT(ctx);
- uint32_t dw = 6 + 3 + 16;
- if (r300->radeon.radeonScreen->kernel_mm)
- dw += 2;
- if (!r300->radeon.radeonScreen->driScreen->dri2.enabled) {
- dw -= 3 + 16;
- }
- return dw;
-}
-
-static void emit_scissor(struct r300_context *r300,
- unsigned width,
- unsigned height)
-{
- int i;
- BATCH_LOCALS(&r300->radeon);
- if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) {
- BEGIN_BATCH_NO_AUTOSTATE(3);
- OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL, 2);
- OUT_BATCH(0);
- OUT_BATCH(((width - 1) << R300_SCISSORS_X_SHIFT) |
- ((height - 1) << R300_SCISSORS_Y_SHIFT));
- END_BATCH();
- BEGIN_BATCH_NO_AUTOSTATE(16);
- for (i = 0; i < 4; i++) {
- OUT_BATCH_REGSEQ(R300_SC_CLIPRECT_TL_0 + (i * 8), 2);
- OUT_BATCH((0 << R300_CLIPRECT_X_SHIFT) | (0 << R300_CLIPRECT_Y_SHIFT));
- OUT_BATCH(((width - 1) << R300_CLIPRECT_X_SHIFT) | ((height - 1) << R300_CLIPRECT_Y_SHIFT));
- }
- OUT_BATCH_REGSEQ(R300_SC_CLIP_RULE, 1);
- OUT_BATCH(0xAAAA);
- OUT_BATCH_REGSEQ(R300_SC_SCREENDOOR, 1);
- OUT_BATCH(0xffffff);
- END_BATCH();
- } else {
- BEGIN_BATCH_NO_AUTOSTATE(3);
- OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL, 2);
- OUT_BATCH((R300_SCISSORS_OFFSET << R300_SCISSORS_X_SHIFT) |
- (R300_SCISSORS_OFFSET << R300_SCISSORS_Y_SHIFT));
- OUT_BATCH(((width + R300_SCISSORS_OFFSET - 1) << R300_SCISSORS_X_SHIFT) |
- ((height + R300_SCISSORS_OFFSET - 1) << R300_SCISSORS_Y_SHIFT));
- END_BATCH();
- BEGIN_BATCH_NO_AUTOSTATE(16);
- for (i = 0; i < 4; i++) {
- OUT_BATCH_REGSEQ(R300_SC_CLIPRECT_TL_0 + (i * 8), 2);
- OUT_BATCH((R300_SCISSORS_OFFSET << R300_CLIPRECT_X_SHIFT) | (R300_SCISSORS_OFFSET << R300_CLIPRECT_Y_SHIFT));
- OUT_BATCH(((R300_SCISSORS_OFFSET + width - 1) << R300_CLIPRECT_X_SHIFT) |
- ((R300_SCISSORS_OFFSET + height - 1) << R300_CLIPRECT_Y_SHIFT));
- }
- OUT_BATCH_REGSEQ(R300_SC_CLIP_RULE, 1);
- OUT_BATCH(0xAAAA);
- OUT_BATCH_REGSEQ(R300_SC_SCREENDOOR, 1);
- OUT_BATCH(0xffffff);
- END_BATCH();
- }
-}
-
-void r300_emit_cb_setup(struct r300_context *r300,
- struct radeon_bo *bo,
- uint32_t offset,
- GLuint format,
- unsigned cpp,
- unsigned pitch)
-{
- BATCH_LOCALS(&r300->radeon);
- uint32_t cbpitch = pitch / cpp;
- uint32_t dw = 6;
-
- assert(offset % 32 == 0);
-
- switch (format) {
- case MESA_FORMAT_SL8:
- case MESA_FORMAT_A8:
- case MESA_FORMAT_L8:
- case MESA_FORMAT_I8:
- cbpitch |= R300_COLOR_FORMAT_I8;
- break;
- case MESA_FORMAT_RGB565:
- case MESA_FORMAT_RGB565_REV:
- cbpitch |= R300_COLOR_FORMAT_RGB565;
- break;
- case MESA_FORMAT_ARGB4444:
- case MESA_FORMAT_ARGB4444_REV:
- cbpitch |= R300_COLOR_FORMAT_ARGB4444;
- break;
- case MESA_FORMAT_RGBA5551:
- case MESA_FORMAT_ARGB1555:
- case MESA_FORMAT_ARGB1555_REV:
- cbpitch |= R300_COLOR_FORMAT_ARGB1555;
- break;
- case MESA_FORMAT_RGBA8888:
- case MESA_FORMAT_RGBA8888_REV:
- case MESA_FORMAT_XRGB8888:
- case MESA_FORMAT_ARGB8888:
- case MESA_FORMAT_XRGB8888_REV:
- case MESA_FORMAT_ARGB8888_REV:
- case MESA_FORMAT_SRGBA8:
- case MESA_FORMAT_SARGB8:
- cbpitch |= R300_COLOR_FORMAT_ARGB8888;
- break;
- default:
- _mesa_problem(r300->radeon.glCtx, "unexpected format in emit_cb_offset()");
- break;
- }
-
- if (bo->flags & RADEON_BO_FLAGS_MACRO_TILE)
- cbpitch |= R300_COLOR_TILE_ENABLE;
-
- if (r300->radeon.radeonScreen->kernel_mm)
- dw += 2;
-
- BEGIN_BATCH_NO_AUTOSTATE(dw);
- OUT_BATCH_REGSEQ(R300_RB3D_COLOROFFSET0, 1);
- OUT_BATCH_RELOC(offset, bo, offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
- OUT_BATCH_REGSEQ(R300_RB3D_COLORPITCH0, 1);
- if (!r300->radeon.radeonScreen->kernel_mm)
- OUT_BATCH(cbpitch);
- else
- OUT_BATCH_RELOC(cbpitch, bo, cbpitch, 0, RADEON_GEM_DOMAIN_VRAM, 0);
- END_BATCH();
-}
-
-static void emit_cb_offset_atom(struct gl_context *ctx, struct radeon_state_atom * atom)
-{
- r300ContextPtr r300 = R300_CONTEXT(ctx);
- struct radeon_renderbuffer *rrb;
- uint32_t offset = r300->radeon.state.color.draw_offset;
-
- rrb = radeon_get_colorbuffer(&r300->radeon);
- if (!rrb || !rrb->bo) {
- fprintf(stderr, "no rrb\n");
- return;
- }
-
- if (RADEON_DEBUG & RADEON_STATE)
- fprintf(stderr,"rrb is %p %d %dx%d\n", rrb, offset, rrb->base.Width, rrb->base.Height);
-
- r300_emit_cb_setup(r300, rrb->bo, offset, rrb->base.Format, rrb->cpp, rrb->pitch);
-
- if (r300->radeon.radeonScreen->driScreen->dri2.enabled) {
- emit_scissor(r300, rrb->base.Width, rrb->base.Height);
- }
-}
-
-static int check_zb_offset(struct gl_context *ctx, struct radeon_state_atom * atom)
-{
- r300ContextPtr r300 = R300_CONTEXT(ctx);
- uint32_t dw;
- dw = 6;
- if (r300->radeon.radeonScreen->kernel_mm)
- dw += 2;
- return dw;
-}
-
-static void emit_zb_offset(struct gl_context *ctx, struct radeon_state_atom * atom)
-{
- r300ContextPtr r300 = R300_CONTEXT(ctx);
- BATCH_LOCALS(&r300->radeon);
- struct radeon_renderbuffer *rrb;
- uint32_t zbpitch;
- uint32_t dw = atom->check(ctx, atom);
-
- rrb = radeon_get_depthbuffer(&r300->radeon);
- if (!rrb)
- return;
-
- zbpitch = (rrb->pitch / rrb->cpp);
- if (!r300->radeon.radeonScreen->kernel_mm) {
- if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) {
- zbpitch |= R300_DEPTHMACROTILE_ENABLE;
- }
- if (rrb->bo->flags & RADEON_BO_FLAGS_MICRO_TILE){
- zbpitch |= R300_DEPTHMICROTILE_TILED;
- }
- }
-
- BEGIN_BATCH_NO_AUTOSTATE(dw);
- OUT_BATCH_REGSEQ(R300_ZB_DEPTHOFFSET, 1);
- OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
- OUT_BATCH_REGSEQ(R300_ZB_DEPTHPITCH, 1);
- if (!r300->radeon.radeonScreen->kernel_mm)
- OUT_BATCH(zbpitch);
- else
- OUT_BATCH_RELOC(cbpitch, rrb->bo, zbpitch, 0, RADEON_GEM_DOMAIN_VRAM, 0);
- END_BATCH();
-}
-
-static void emit_zstencil_format(struct gl_context *ctx, struct radeon_state_atom * atom)
-{
- r300ContextPtr r300 = R300_CONTEXT(ctx);
- BATCH_LOCALS(&r300->radeon);
- struct radeon_renderbuffer *rrb;
- uint32_t format = 0;
-
- rrb = radeon_get_depthbuffer(&r300->radeon);
- if (!rrb)
- format = 0;
- else {
- if (rrb->cpp == 2)
- format = R300_DEPTHFORMAT_16BIT_INT_Z;
- else if (rrb->cpp == 4)
- format = R300_DEPTHFORMAT_24BIT_INT_Z_8BIT_STENCIL;
- }
-
- BEGIN_BATCH_NO_AUTOSTATE(atom->cmd_size);
- OUT_BATCH(atom->cmd[0]);
- atom->cmd[1] &= ~0xf;
- atom->cmd[1] |= format;
- OUT_BATCH(atom->cmd[1]);
- OUT_BATCH(atom->cmd[2]);
- OUT_BATCH(atom->cmd[3]);
- OUT_BATCH(atom->cmd[4]);
- END_BATCH();
-}
-
-static int check_never(struct gl_context *ctx, struct radeon_state_atom *atom)
-{
- return 0;
-}
-
-static int check_always(struct gl_context *ctx, struct radeon_state_atom *atom)
-{
- return atom->cmd_size;
-}
-
-static int check_variable(struct gl_context *ctx, struct radeon_state_atom *atom)
-{
- r300ContextPtr r300 = R300_CONTEXT(ctx);
- int cnt;
- if (atom->cmd[0] == CP_PACKET2) {
- return 0;
- }
- cnt = packet0_count(r300, atom->cmd);
- return cnt ? cnt + 1 : 0;
-}
-
-static int check_r500fp(struct gl_context *ctx, struct radeon_state_atom *atom)
-{
- int cnt;
- r300ContextPtr r300 = R300_CONTEXT(ctx);
- int extra = 1;
- cnt = r500fp_count(atom->cmd);
- if (r300->radeon.radeonScreen->kernel_mm)
- extra = 3;
-
- return cnt ? (cnt * 6) + extra : 0;
-}
-
-static int check_r500fp_const(struct gl_context *ctx, struct radeon_state_atom *atom)
-{
- int cnt;
- r300ContextPtr r300 = R300_CONTEXT(ctx);
- int extra = 1;
- cnt = r500fp_count(atom->cmd);
- if (r300->radeon.radeonScreen->kernel_mm)
- extra = 3;
-
- cnt = r500fp_count(atom->cmd);
- return cnt ? (cnt * 4) + extra : 0;
-}
-
-#define ALLOC_STATE( ATOM, CHK, SZ, IDX ) \
- do { \
- r300->hw.ATOM.cmd_size = (SZ); \
- r300->hw.ATOM.cmd = (uint32_t*)CALLOC((SZ) * sizeof(uint32_t)); \
- r300->hw.ATOM.name = #ATOM; \
- r300->hw.ATOM.idx = (IDX); \
- r300->hw.ATOM.check = check_##CHK; \
- r300->hw.ATOM.dirty = GL_FALSE; \
- r300->radeon.hw.max_state_size += (SZ); \
- insert_at_tail(&r300->radeon.hw.atomlist, &r300->hw.ATOM); \
- } while (0)
-/**
- * Allocate memory for the command buffer and initialize the state atom
- * list. Note that the initial hardware state is set by r300InitState().
- */
-void r300InitCmdBuf(r300ContextPtr r300)
-{
- int mtu;
- int has_tcl;
- int is_r500 = 0;
-
- has_tcl = r300->options.hw_tcl_enabled;
-
- if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515)
- is_r500 = 1;
-
- r300->radeon.hw.max_state_size = 2 + 2; /* reserve extra space for WAIT_IDLE and tex cache flush */
-
- mtu = r300->radeon.glCtx->Const.MaxTextureUnits;
- if (RADEON_DEBUG & RADEON_TEXTURE) {
- fprintf(stderr, "Using %d maximum texture units..\n", mtu);
- }
-
- /* Setup the atom linked list */
- make_empty_list(&r300->radeon.hw.atomlist);
- r300->radeon.hw.atomlist.name = "atom-list";
-
- /* Initialize state atoms */
- ALLOC_STATE(vpt, always, R300_VPT_CMDSIZE, 0);
- r300->hw.vpt.cmd[R300_VPT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_SE_VPORT_XSCALE, 6);
- ALLOC_STATE(vap_cntl, always, R300_VAP_CNTL_SIZE, 0);
- r300->hw.vap_cntl.cmd[R300_VAP_CNTL_FLUSH] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PVS_STATE_FLUSH_REG, 1);
- r300->hw.vap_cntl.cmd[R300_VAP_CNTL_FLUSH_1] = 0;
- r300->hw.vap_cntl.cmd[R300_VAP_CNTL_CMD] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CNTL, 1);
- if (is_r500 && !r300->radeon.radeonScreen->kernel_mm) {
- ALLOC_STATE(vap_index_offset, always, 2, 0);
- r300->hw.vap_index_offset.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_VAP_INDEX_OFFSET, 1);
- r300->hw.vap_index_offset.cmd[1] = 0;
- }
- ALLOC_STATE(vte, always, 3, 0);
- r300->hw.vte.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SE_VTE_CNTL, 2);
- ALLOC_STATE(vap_vf_max_vtx_indx, always, 3, 0);
- r300->hw.vap_vf_max_vtx_indx.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_VF_MAX_VTX_INDX, 2);
- ALLOC_STATE(vap_cntl_status, always, 2, 0);
- r300->hw.vap_cntl_status.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CNTL_STATUS, 1);
- ALLOC_STATE(vir[0], variable, R300_VIR_CMDSIZE, 0);
- r300->hw.vir[0].cmd[R300_VIR_CMD_0] =
- cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PROG_STREAM_CNTL_0, 1);
- ALLOC_STATE(vir[1], variable, R300_VIR_CMDSIZE, 1);
- r300->hw.vir[1].cmd[R300_VIR_CMD_0] =
- cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PROG_STREAM_CNTL_EXT_0, 1);
- ALLOC_STATE(vic, always, R300_VIC_CMDSIZE, 0);
- r300->hw.vic.cmd[R300_VIC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_VTX_STATE_CNTL, 2);
- ALLOC_STATE(vap_psc_sgn_norm_cntl, always, 2, 0);
- r300->hw.vap_psc_sgn_norm_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PSC_SGN_NORM_CNTL, SGN_NORM_ZERO_CLAMP_MINUS_ONE);
-
- if (has_tcl) {
- ALLOC_STATE(vap_clip_cntl, always, 2, 0);
- r300->hw.vap_clip_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CLIP_CNTL, 1);
- ALLOC_STATE(vap_clip, always, 5, 0);
- r300->hw.vap_clip.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_GB_VERT_CLIP_ADJ, 4);
- ALLOC_STATE(vap_pvs_vtx_timeout_reg, always, 2, 0);
- r300->hw.vap_pvs_vtx_timeout_reg.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, VAP_PVS_VTX_TIMEOUT_REG, 1);
- }
-
- ALLOC_STATE(vof, always, R300_VOF_CMDSIZE, 0);
- r300->hw.vof.cmd[R300_VOF_CMD_0] =
- cmdpacket0(r300->radeon.radeonScreen, R300_VAP_OUTPUT_VTX_FMT_0, 2);
-
- if (has_tcl) {
- ALLOC_STATE(pvs, always, R300_PVS_CMDSIZE, 0);
- r300->hw.pvs.cmd[R300_PVS_CMD_0] =
- cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PVS_CODE_CNTL_0, 3);
- }
-
- ALLOC_STATE(gb_enable, always, 2, 0);
- r300->hw.gb_enable.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GB_ENABLE, 1);
- if (!r300->radeon.radeonScreen->driScreen->dri2.enabled) {
- ALLOC_STATE(gb_misc, always, R300_GB_MISC_CMDSIZE, 0);
- } else {
- ALLOC_STATE(gb_misc, never, R300_GB_MISC_CMDSIZE, 0);
- }
- r300->hw.gb_misc.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GB_MSPOS0, 3);
- ALLOC_STATE(gb_misc2, always, R300_GB_MISC2_CMDSIZE, 0);
- r300->hw.gb_misc2.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, 0x401C, 2);
- ALLOC_STATE(txe, always, R300_TXE_CMDSIZE, 0);
- r300->hw.txe.cmd[R300_TXE_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_ENABLE, 1);
- ALLOC_STATE(ga_point_s0, always, 5, 0);
- r300->hw.ga_point_s0.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_S0, 4);
- ALLOC_STATE(ga_triangle_stipple, always, 2, 0);
- r300->hw.ga_triangle_stipple.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_TRIANGLE_STIPPLE, 1);
- ALLOC_STATE(ps, always, R300_PS_CMDSIZE, 0);
- r300->hw.ps.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_SIZE, 1);
- ALLOC_STATE(ga_point_minmax, always, 4, 0);
- r300->hw.ga_point_minmax.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_MINMAX, 3);
- ALLOC_STATE(lcntl, always, 2, 0);
- r300->hw.lcntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_LINE_CNTL, 1);
- ALLOC_STATE(ga_line_stipple, always, 4, 0);
- r300->hw.ga_line_stipple.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_LINE_STIPPLE_VALUE, 3);
- if (!r300->radeon.radeonScreen->driScreen->dri2.enabled) {
- ALLOC_STATE(shade, always, 2, 0);
- } else {
- ALLOC_STATE(shade, never, 2, 0);
- }
- r300->hw.shade.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_ENHANCE, 1);
- ALLOC_STATE(shade2, always, 4, 0);
- r300->hw.shade2.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, 0x4278, 3);
- ALLOC_STATE(polygon_mode, always, 4, 0);
- r300->hw.polygon_mode.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POLY_MODE, 3);
- ALLOC_STATE(fogp, always, 3, 0);
- r300->hw.fogp.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_FOG_SCALE, 2);
- ALLOC_STATE(zbias_cntl, always, 2, 0);
- r300->hw.zbias_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_TEX_WRAP, 1);
- ALLOC_STATE(zbs, always, R300_ZBS_CMDSIZE, 0);
- r300->hw.zbs.cmd[R300_ZBS_CMD_0] =
- cmdpacket0(r300->radeon.radeonScreen, R300_SU_POLY_OFFSET_FRONT_SCALE, 4);
- ALLOC_STATE(occlusion_cntl, always, 2, 0);
- r300->hw.occlusion_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_POLY_OFFSET_ENABLE, 1);
- ALLOC_STATE(cul, always, R300_CUL_CMDSIZE, 0);
- r300->hw.cul.cmd[R300_CUL_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_CULL_MODE, 1);
- ALLOC_STATE(su_depth_scale, always, 3, 0);
- r300->hw.su_depth_scale.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_DEPTH_SCALE, 2);
- ALLOC_STATE(rc, always, R300_RC_CMDSIZE, 0);
- r300->hw.rc.cmd[R300_RC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_COUNT, 2);
- if (is_r500) {
- ALLOC_STATE(ri, variable, R500_RI_CMDSIZE, 0);
- r300->hw.ri.cmd[R300_RI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_RS_IP_0, 16);
- ALLOC_STATE(rr, variable, R300_RR_CMDSIZE, 0);
- r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_RS_INST_0, 1);
- } else {
- ALLOC_STATE(ri, variable, R300_RI_CMDSIZE, 0);
- r300->hw.ri.cmd[R300_RI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_IP_0, 8);
- ALLOC_STATE(rr, variable, R300_RR_CMDSIZE, 0);
- r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_INST_0, 1);
- }
- ALLOC_STATE(sc_hyperz, always, 3, 0);
- r300->hw.sc_hyperz.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SC_HYPERZ, 2);
- ALLOC_STATE(sc_screendoor, always, 2, 0);
- r300->hw.sc_screendoor.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SC_SCREENDOOR, 1);
- ALLOC_STATE(us_out_fmt, always, 6, 0);
- r300->hw.us_out_fmt.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_OUT_FMT, 5);
-
- if (is_r500) {
- ALLOC_STATE(fp, always, R500_FP_CMDSIZE, 0);
- r300->hw.fp.cmd[R500_FP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_US_CONFIG, 2);
- r300->hw.fp.cmd[R500_FP_CNTL] = R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO;
- r300->hw.fp.cmd[R500_FP_CMD_1] = cmdpacket0(r300->radeon.radeonScreen, R500_US_CODE_ADDR, 3);
- r300->hw.fp.cmd[R500_FP_CMD_2] = cmdpacket0(r300->radeon.radeonScreen, R500_US_FC_CTRL, 1);
- r300->hw.fp.cmd[R500_FP_FC_CNTL] = 0; /* FIXME when we add flow control */
-
- ALLOC_STATE(r500fp, r500fp, R500_FPI_CMDSIZE, 0);
- r300->hw.r500fp.cmd[R300_FPI_CMD_0] =
- cmdr500fp(r300->radeon.radeonScreen, 0, 0, 0, 0);
- if (r300->radeon.radeonScreen->kernel_mm)
- r300->hw.r500fp.emit = emit_r500fp_atom;
-
- ALLOC_STATE(r500fp_const, r500fp_const, R500_FPP_CMDSIZE, 0);
- r300->hw.r500fp_const.cmd[R300_FPI_CMD_0] =
- cmdr500fp(r300->radeon.radeonScreen, 0, 0, 1, 0);
- if (r300->radeon.radeonScreen->kernel_mm)
- r300->hw.r500fp_const.emit = emit_r500fp_atom;
- } else {
- ALLOC_STATE(fp, always, R300_FP_CMDSIZE, 0);
- r300->hw.fp.cmd[R300_FP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_CONFIG, 3);
- r300->hw.fp.cmd[R300_FP_CMD_1] = cmdpacket0(r300->radeon.radeonScreen, R300_US_CODE_ADDR_0, 4);
-
- ALLOC_STATE(fpt, variable, R300_FPT_CMDSIZE, 0);
- r300->hw.fpt.cmd[R300_FPT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_TEX_INST_0, 0);
-
- ALLOC_STATE(fpi[0], variable, R300_FPI_CMDSIZE, 0);
- r300->hw.fpi[0].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_RGB_INST_0, 1);
- ALLOC_STATE(fpi[1], variable, R300_FPI_CMDSIZE, 1);
- r300->hw.fpi[1].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_RGB_ADDR_0, 1);
- ALLOC_STATE(fpi[2], variable, R300_FPI_CMDSIZE, 2);
- r300->hw.fpi[2].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_ALPHA_INST_0, 1);
- ALLOC_STATE(fpi[3], variable, R300_FPI_CMDSIZE, 3);
- r300->hw.fpi[3].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_ALPHA_ADDR_0, 1);
- ALLOC_STATE(fpp, variable, R300_FPP_CMDSIZE, 0);
- r300->hw.fpp.cmd[R300_FPP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_PFS_PARAM_0_X, 0);
- }
- ALLOC_STATE(fogs, always, R300_FOGS_CMDSIZE, 0);
- r300->hw.fogs.cmd[R300_FOGS_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_FOG_BLEND, 1);
- ALLOC_STATE(fogc, always, R300_FOGC_CMDSIZE, 0);
- r300->hw.fogc.cmd[R300_FOGC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_FOG_COLOR_R, 3);
- ALLOC_STATE(at, always, R300_AT_CMDSIZE, 0);
- r300->hw.at.cmd[R300_AT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_ALPHA_FUNC, 2);
- ALLOC_STATE(fg_depth_src, always, 2, 0);
- r300->hw.fg_depth_src.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_DEPTH_SRC, 1);
- ALLOC_STATE(rb3d_cctl, always, 2, 0);
- r300->hw.rb3d_cctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_CCTL, 1);
- ALLOC_STATE(bld, always, R300_BLD_CMDSIZE, 0);
- r300->hw.bld.cmd[R300_BLD_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_CBLEND, 2);
- ALLOC_STATE(cmk, always, R300_CMK_CMDSIZE, 0);
- r300->hw.cmk.cmd[R300_CMK_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, RB3D_COLOR_CHANNEL_MASK, 1);
- if (is_r500) {
- ALLOC_STATE(blend_color, always, 3, 0);
- r300->hw.blend_color.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_RB3D_CONSTANT_COLOR_AR, 2);
- } else {
- ALLOC_STATE(blend_color, always, 2, 0);
- r300->hw.blend_color.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_BLEND_COLOR, 1);
- }
- ALLOC_STATE(rop, always, 2, 0);
- r300->hw.rop.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_ROPCNTL, 1);
- ALLOC_STATE(cb, cb_offset, R300_CB_CMDSIZE, 0);
- r300->hw.cb.emit = &emit_cb_offset_atom;
- ALLOC_STATE(rb3d_dither_ctl, always, 10, 0);
- r300->hw.rb3d_dither_ctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_DITHER_CTL, 9);
- ALLOC_STATE(rb3d_aaresolve_ctl, always, 2, 0);
- r300->hw.rb3d_aaresolve_ctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_AARESOLVE_CTL, 1);
- if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV350) {
- ALLOC_STATE(rb3d_discard_src_pixel_lte_threshold, always, 3, 0);
- } else {
- ALLOC_STATE(rb3d_discard_src_pixel_lte_threshold, never, 3, 0);
- }
- r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD, 2);
- ALLOC_STATE(zs, always, R300_ZS_CMDSIZE, 0);
- r300->hw.zs.cmd[R300_ZS_CMD_0] =
- cmdpacket0(r300->radeon.radeonScreen, R300_ZB_CNTL, 3);
- if (is_r500) {
- if (r300->radeon.radeonScreen->kernel_mm)
- ALLOC_STATE(zsb, always, R300_ZSB_CMDSIZE, 0);
- else
- ALLOC_STATE(zsb, never, R300_ZSB_CMDSIZE, 0);
- r300->hw.zsb.cmd[R300_ZSB_CMD_0] =
- cmdpacket0(r300->radeon.radeonScreen, R500_ZB_STENCILREFMASK_BF, 1);
- }
-
- ALLOC_STATE(zstencil_format, always, 5, 0);
- r300->hw.zstencil_format.cmd[0] =
- cmdpacket0(r300->radeon.radeonScreen, R300_ZB_FORMAT, 4);
- r300->hw.zstencil_format.emit = emit_zstencil_format;
-
- ALLOC_STATE(zb, zb_offset, R300_ZB_CMDSIZE, 0);
- r300->hw.zb.emit = emit_zb_offset;
- ALLOC_STATE(zb_depthclearvalue, always, 2, 0);
- r300->hw.zb_depthclearvalue.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_DEPTHCLEARVALUE, 1);
- ALLOC_STATE(zb_zmask, always, 3, 0);
- r300->hw.zb_zmask.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_ZMASK_OFFSET, 2);
- ALLOC_STATE(zb_hiz_offset, always, 2, 0);
- r300->hw.zb_hiz_offset.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_HIZ_OFFSET, 1);
- ALLOC_STATE(zb_hiz_pitch, always, 2, 0);
- r300->hw.zb_hiz_pitch.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_HIZ_PITCH, 1);
-
- /* VPU only on TCL */
- if (has_tcl) {
- int i;
- ALLOC_STATE(vpi, vpu, R300_VPI_CMDSIZE, 0);
- r300->hw.vpi.cmd[0] =
- cmdvpu(r300->radeon.radeonScreen, R300_PVS_CODE_START, 0);
- if (r300->radeon.radeonScreen->kernel_mm)
- r300->hw.vpi.emit = emit_vpu_state;
-
- if (is_r500) {
- ALLOC_STATE(vpp, vpp, R300_VPP_CMDSIZE, 0);
- r300->hw.vpp.cmd[0] =
- cmdvpu(r300->radeon.radeonScreen, R500_PVS_CONST_START, 0);
- if (r300->radeon.radeonScreen->kernel_mm)
- r300->hw.vpp.emit = emit_vpp_state;
-
- ALLOC_STATE(vps, vpu, R300_VPS_CMDSIZE, 0);
- r300->hw.vps.cmd[0] =
- cmdvpu(r300->radeon.radeonScreen, R500_POINT_VPORT_SCALE_OFFSET, 1);
- if (r300->radeon.radeonScreen->kernel_mm)
- r300->hw.vps.emit = emit_vpu_state;
-
- for (i = 0; i < 6; i++) {
- ALLOC_STATE(vpucp[i], vpu, R300_VPUCP_CMDSIZE, 0);
- r300->hw.vpucp[i].cmd[0] =
- cmdvpu(r300->radeon.radeonScreen,
- R500_PVS_UCP_START + i, 1);
- if (r300->radeon.radeonScreen->kernel_mm)
- r300->hw.vpucp[i].emit = emit_vpu_state;
- }
- } else {
- ALLOC_STATE(vpp, vpp, R300_VPP_CMDSIZE, 0);
- r300->hw.vpp.cmd[0] =
- cmdvpu(r300->radeon.radeonScreen, R300_PVS_CONST_START, 0);
- if (r300->radeon.radeonScreen->kernel_mm)
- r300->hw.vpp.emit = emit_vpp_state;
-
- ALLOC_STATE(vps, vpu, R300_VPS_CMDSIZE, 0);
- r300->hw.vps.cmd[0] =
- cmdvpu(r300->radeon.radeonScreen, R300_POINT_VPORT_SCALE_OFFSET, 1);
- if (r300->radeon.radeonScreen->kernel_mm)
- r300->hw.vps.emit = emit_vpu_state;
-
- for (i = 0; i < 6; i++) {
- ALLOC_STATE(vpucp[i], vpu, R300_VPUCP_CMDSIZE, 0);
- r300->hw.vpucp[i].cmd[0] =
- cmdvpu(r300->radeon.radeonScreen,
- R300_PVS_UCP_START + i, 1);
- if (r300->radeon.radeonScreen->kernel_mm)
- r300->hw.vpucp[i].emit = emit_vpu_state;
- }
- }
- }
-
- /* Textures */
- ALLOC_STATE(tex.filter, variable, mtu + 1, 0);
- r300->hw.tex.filter.cmd[R300_TEX_CMD_0] =
- cmdpacket0(r300->radeon.radeonScreen, R300_TX_FILTER0_0, 0);
-
- ALLOC_STATE(tex.filter_1, variable, mtu + 1, 0);
- r300->hw.tex.filter_1.cmd[R300_TEX_CMD_0] =
- cmdpacket0(r300->radeon.radeonScreen, R300_TX_FILTER1_0, 0);
-
- ALLOC_STATE(tex.size, variable, mtu + 1, 0);
- r300->hw.tex.size.cmd[R300_TEX_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_SIZE_0, 0);
-
- ALLOC_STATE(tex.format, variable, mtu + 1, 0);
- r300->hw.tex.format.cmd[R300_TEX_CMD_0] =
- cmdpacket0(r300->radeon.radeonScreen, R300_TX_FORMAT_0, 0);
-
- ALLOC_STATE(tex.pitch, variable, mtu + 1, 0);
- r300->hw.tex.pitch.cmd[R300_TEX_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_FORMAT2_0, 0);
-
- ALLOC_STATE(tex.offset, tex_offsets, 1, 0);
- r300->hw.tex.offset.cmd[R300_TEX_CMD_0] =
- cmdpacket0(r300->radeon.radeonScreen, R300_TX_OFFSET_0, 0);
- r300->hw.tex.offset.emit = &emit_tex_offsets;
-
- ALLOC_STATE(tex.chroma_key, variable, mtu + 1, 0);
- r300->hw.tex.chroma_key.cmd[R300_TEX_CMD_0] =
- cmdpacket0(r300->radeon.radeonScreen, R300_TX_CHROMA_KEY_0, 0);
-
- ALLOC_STATE(tex.border_color, variable, mtu + 1, 0);
- r300->hw.tex.border_color.cmd[R300_TEX_CMD_0] =
- cmdpacket0(r300->radeon.radeonScreen, R300_TX_BORDER_COLOR_0, 0);
-
- radeon_init_query_stateobj(&r300->radeon, R300_QUERYOBJ_CMDSIZE);
- if (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV530) {
- r300->radeon.query.queryobj.cmd[R300_QUERYOBJ_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, RV530_FG_ZBREG_DEST, 1);
- r300->radeon.query.queryobj.cmd[R300_QUERYOBJ_DATA_0] = RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL;
- } else {
- r300->radeon.query.queryobj.cmd[R300_QUERYOBJ_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_REG_DEST, 1);
- r300->radeon.query.queryobj.cmd[R300_QUERYOBJ_DATA_0] = R300_RASTER_PIPE_SELECT_ALL;
- }
- r300->radeon.query.queryobj.cmd[R300_QUERYOBJ_CMD_1] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_ZPASS_DATA, 1);
- r300->radeon.query.queryobj.cmd[R300_QUERYOBJ_DATA_1] = 0;
-
- r300->radeon.hw.is_dirty = GL_TRUE;
- r300->radeon.hw.all_dirty = GL_TRUE;
-
- rcommonInitCmdBuf(&r300->radeon);
-}
+++ /dev/null
-/*
-Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
-
-The Weather Channel (TM) funded Tungsten Graphics to develop the
-initial release of the Radeon 8500 driver under the XFree86 license.
-This notice must be preserved.
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-**************************************************************************/
-
-/**
- * \file
- *
- * \author Nicolai Haehnle <prefect_@gmx.net>
- */
-
-#ifndef __R300_CMDBUF_H__
-#define __R300_CMDBUF_H__
-
-#include "r300_context.h"
-
-#define CACHE_FLUSH_BUFSZ (4*2)
-#define PRE_EMIT_STATE_BUFSZ (2+2)
-#define AOS_BUFSZ(nr) (3+(nr >>1)*3 + (nr&1)*2 + (nr*2))
-#define FIREAOS_BUFSZ (3)
-#define SCISSORS_BUFSZ (3)
-
-void r300InitCmdBuf(r300ContextPtr r300);
-void r300_emit_scissor(struct gl_context *ctx);
-
-void r300_emit_vpu(struct r300_context *ctx,
- uint32_t *data,
- unsigned len,
- uint32_t addr);
-
-void r500_emit_fp(struct r300_context *r300,
- uint32_t *data,
- unsigned len,
- uint32_t addr,
- unsigned type,
- unsigned clamp);
-
-void r300_emit_cb_setup(struct r300_context *r300,
- struct radeon_bo *bo,
- uint32_t offset,
- GLuint format,
- unsigned cpp,
- unsigned pitch);
-
-#endif /* __R300_CMDBUF_H__ */
+++ /dev/null
-/*
-Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
-
-The Weather Channel (TM) funded Tungsten Graphics to develop the
-initial release of the Radeon 8500 driver under the XFree86 license.
-This notice must be preserved.
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-**************************************************************************/
-
-/**
- * \file
- *
- * \author Keith Whitwell <keith@tungstengraphics.com>
- *
- * \author Nicolai Haehnle <prefect_@gmx.net>
- */
-
-#include <stdbool.h>
-#include "main/glheader.h"
-#include "main/api_arrayelt.h"
-#include "main/context.h"
-#include "main/simple_list.h"
-#include "main/imports.h"
-#include "main/extensions.h"
-#include "main/bufferobj.h"
-#include "main/texobj.h"
-#include "main/mfeatures.h"
-
-#include "swrast/swrast.h"
-#include "swrast_setup/swrast_setup.h"
-#include "vbo/vbo.h"
-
-#include "tnl/tnl.h"
-#include "tnl/t_pipeline.h"
-
-#include "drivers/common/driverfuncs.h"
-#include "drivers/common/meta.h"
-
-#include "r300_context.h"
-#include "radeon_span.h"
-#include "r300_blit.h"
-#include "r300_cmdbuf.h"
-#include "r300_state.h"
-#include "r300_tex.h"
-#include "r300_emit.h"
-#include "r300_render.h"
-#include "r300_swtcl.h"
-#include "radeon_bocs_wrapper.h"
-#include "radeon_buffer_objects.h"
-#include "radeon_queryobj.h"
-
-#include "utils.h"
-#include "xmlpool.h" /* for symbolic values of enum-type options */
-
-
-static const struct tnl_pipeline_stage *r300_pipeline[] = {
- /* Catch any t&l fallbacks
- */
- &_tnl_vertex_transform_stage,
- &_tnl_normal_transform_stage,
- &_tnl_lighting_stage,
- &_tnl_fog_coordinate_stage,
- &_tnl_texgen_stage,
- &_tnl_texture_transform_stage,
- &_tnl_point_attenuation_stage,
- &_tnl_vertex_program_stage,
- &_tnl_render_stage,
- 0,
-};
-
-static void r300_get_lock(radeonContextPtr rmesa)
-{
- drm_radeon_sarea_t *sarea = rmesa->sarea;
-
- if (sarea->ctx_owner != rmesa->dri.hwContext) {
- sarea->ctx_owner = rmesa->dri.hwContext;
- if (!rmesa->radeonScreen->kernel_mm)
- radeon_bo_legacy_texture_age(rmesa->radeonScreen->bom);
- }
-}
-
-static void r300_vtbl_emit_cs_header(struct radeon_cs *cs, radeonContextPtr rmesa)
-{
- /* please flush pipe do all pending work */
- radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
- R300_SC_SCREENDOOR, 1));
- radeon_cs_write_dword(cs, 0x0);
- radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
- R300_SC_SCREENDOOR, 1));
- radeon_cs_write_dword(cs, 0x00FFFFFF);
- radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
- R300_SC_HYPERZ, 1));
- radeon_cs_write_dword(cs, 0x0);
- radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
- R300_US_CONFIG, 1));
- radeon_cs_write_dword(cs, 0x0);
- radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
- R300_ZB_CNTL, 1));
- radeon_cs_write_dword(cs, 0x0);
- radeon_cs_write_dword(cs, cmdwait(rmesa->radeonScreen, R300_WAIT_3D));
- radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
- R300_RB3D_DSTCACHE_CTLSTAT, 1));
- radeon_cs_write_dword(cs, R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
- radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
- R300_ZB_ZCACHE_CTLSTAT, 1));
- radeon_cs_write_dword(cs, R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE);
- radeon_cs_write_dword(cs, cmdwait(rmesa->radeonScreen,
- R300_WAIT_3D | R300_WAIT_3D_CLEAN));
-}
-
-static void r300_vtbl_pre_emit_atoms(radeonContextPtr radeon)
-{
- BATCH_LOCALS(radeon);
-
- cp_wait(radeon, R300_WAIT_3D | R300_WAIT_3D_CLEAN);
- BEGIN_BATCH_NO_AUTOSTATE(2);
- OUT_BATCH_REGVAL(R300_TX_INVALTAGS, R300_TX_FLUSH);
- END_BATCH();
- end_3d(radeon);
-}
-
-static void r300_fallback(struct gl_context *ctx, GLuint bit, GLboolean mode)
-{
- r300ContextPtr r300 = R300_CONTEXT(ctx);
- if (mode)
- r300->radeon.Fallback |= bit;
- else
- r300->radeon.Fallback &= ~bit;
-
- r300SwitchFallback(ctx, R300_FALLBACK_RADEON_COMMON, mode);
-}
-
-static void r300_emit_query_finish(radeonContextPtr radeon)
-{
- r300ContextPtr r300 = (r300ContextPtr)radeon;
- struct radeon_query_object *query = radeon->query.current;
- BATCH_LOCALS(radeon);
-
- BEGIN_BATCH_NO_AUTOSTATE(3 * 2 *r300->radeon.radeonScreen->num_gb_pipes + 2);
- switch (r300->radeon.radeonScreen->num_gb_pipes) {
- case 4:
- OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_3);
- OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
- OUT_BATCH_RELOC(0, query->bo, query->curr_offset+3*sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0);
- case 3:
- OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_2);
- OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
- OUT_BATCH_RELOC(0, query->bo, query->curr_offset+2*sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0);
- case 2:
- if (r300->radeon.radeonScreen->chip_family <= CHIP_FAMILY_RV380) {
- OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_3);
- } else {
- OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_1);
- }
- OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
- OUT_BATCH_RELOC(0, query->bo, query->curr_offset+1*sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0);
- case 1:
- default:
- OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_0);
- OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
- OUT_BATCH_RELOC(0, query->bo, query->curr_offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
- break;
- }
- OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_ALL);
- END_BATCH();
- query->curr_offset += r300->radeon.radeonScreen->num_gb_pipes * sizeof(uint32_t);
- assert(query->curr_offset < RADEON_QUERY_PAGE_SIZE);
- query->emitted_begin = GL_FALSE;
-}
-
-static void rv530_emit_query_finish_single_z(radeonContextPtr radeon)
-{
- BATCH_LOCALS(radeon);
- struct radeon_query_object *query = radeon->query.current;
-
- BEGIN_BATCH_NO_AUTOSTATE(8);
- OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
- OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
- OUT_BATCH_RELOC(0, query->bo, query->curr_offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
- OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
- END_BATCH();
-
- query->curr_offset += sizeof(uint32_t);
- assert(query->curr_offset < RADEON_QUERY_PAGE_SIZE);
- query->emitted_begin = GL_FALSE;
-}
-
-static void rv530_emit_query_finish_double_z(radeonContextPtr radeon)
-{
- BATCH_LOCALS(radeon);
- struct radeon_query_object *query = radeon->query.current;
-
- BEGIN_BATCH_NO_AUTOSTATE(14);
- OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
- OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
- OUT_BATCH_RELOC(0, query->bo, query->curr_offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
- OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_1);
- OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
- OUT_BATCH_RELOC(0, query->bo, query->curr_offset + sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0);
- OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
- END_BATCH();
-
- query->curr_offset += 2 * sizeof(uint32_t);
- assert(query->curr_offset < RADEON_QUERY_PAGE_SIZE);
- query->emitted_begin = GL_FALSE;
-}
-
-static void r300_init_vtbl(radeonContextPtr radeon)
-{
- radeon->vtbl.get_lock = r300_get_lock;
- radeon->vtbl.update_viewport_offset = r300UpdateViewportOffset;
- radeon->vtbl.emit_cs_header = r300_vtbl_emit_cs_header;
- radeon->vtbl.swtcl_flush = r300_swtcl_flush;
- radeon->vtbl.pre_emit_atoms = r300_vtbl_pre_emit_atoms;
- radeon->vtbl.fallback = r300_fallback;
- if (radeon->radeonScreen->chip_family == CHIP_FAMILY_RV530) {
- if (radeon->radeonScreen->num_z_pipes == 2)
- radeon->vtbl.emit_query_finish = rv530_emit_query_finish_double_z;
- else
- radeon->vtbl.emit_query_finish = rv530_emit_query_finish_single_z;
- } else
- radeon->vtbl.emit_query_finish = r300_emit_query_finish;
-
- radeon->vtbl.check_blit = r300_check_blit;
- radeon->vtbl.blit = r300_blit;
-
- if (radeon->radeonScreen->chip_family >= CHIP_FAMILY_RV515) {
- radeon->vtbl.is_format_renderable = r500IsFormatRenderable;
- } else {
- radeon->vtbl.is_format_renderable = r300IsFormatRenderable;
- }
-}
-
-static void r300InitConstValues(struct gl_context *ctx, radeonScreenPtr screen)
-{
- r300ContextPtr r300 = R300_CONTEXT(ctx);
-
- ctx->Const.MaxTextureImageUnits =
- driQueryOptioni(&r300->radeon.optionCache, "texture_image_units");
- ctx->Const.MaxTextureCoordUnits =
- driQueryOptioni(&r300->radeon.optionCache, "texture_coord_units");
- ctx->Const.MaxTextureUnits = MIN2(ctx->Const.MaxTextureImageUnits,
- ctx->Const.MaxTextureCoordUnits);
- ctx->Const.MaxCombinedTextureImageUnits =
- ctx->Const.MaxVertexTextureImageUnits +
- ctx->Const.MaxTextureImageUnits;
-
-
- ctx->Const.MaxTextureMaxAnisotropy = 16.0;
- ctx->Const.MaxTextureLodBias = 16.0;
-
- if (screen->chip_family >= CHIP_FAMILY_RV515) {
- ctx->Const.MaxTextureLevels = 13;
- ctx->Const.MaxCubeTextureLevels = 13;
- ctx->Const.MaxTextureRectSize = 4096;
- ctx->Const.MaxRenderbufferSize = 4096;
- }
- else {
- ctx->Const.MaxTextureLevels = 12;
- ctx->Const.MaxCubeTextureLevels = 12;
- ctx->Const.MaxTextureRectSize = 2048;
- ctx->Const.MaxRenderbufferSize = 2048;
- }
-
- ctx->Const.MinPointSize = 1.0;
- ctx->Const.MinPointSizeAA = 1.0;
- ctx->Const.MaxPointSize = R300_POINTSIZE_MAX;
- ctx->Const.MaxPointSizeAA = R300_POINTSIZE_MAX;
-
- ctx->Const.MinLineWidth = 1.0;
- ctx->Const.MinLineWidthAA = 1.0;
- ctx->Const.MaxLineWidth = R300_LINESIZE_MAX;
- ctx->Const.MaxLineWidthAA = R300_LINESIZE_MAX;
-
- ctx->Const.MaxDrawBuffers = 1;
- ctx->Const.MaxColorAttachments = 1;
-
- if (r300->options.hw_tcl_enabled) {
- ctx->Const.VertexProgram.MaxNativeInstructions = 255;
- ctx->Const.VertexProgram.MaxNativeAluInstructions = 255;
- ctx->Const.VertexProgram.MaxNativeAttribs = 16;
- ctx->Const.VertexProgram.MaxNativeTemps = 32;
- ctx->Const.VertexProgram.MaxNativeParameters = 256;
- ctx->Const.VertexProgram.MaxNativeAddressRegs = 1;
- }
-
- if (screen->chip_family >= CHIP_FAMILY_RV515) {
- ctx->Const.FragmentProgram.MaxNativeTemps = R500_PFS_NUM_TEMP_REGS;
- ctx->Const.FragmentProgram.MaxNativeAttribs = 11; /* copy i915... */
-
- /* The hardware limits are higher than this,
- * but the non-KMS DRM interface artificially limits us
- * to this many instructions.
- *
- * We could of course work around it in the KMS path,
- * but it would be a mess, so it seems wiser
- * to leave it as is. Going forward, the Gallium driver
- * will not be subject to these limitations.
- */
- ctx->Const.FragmentProgram.MaxNativeParameters = 255;
- ctx->Const.FragmentProgram.MaxNativeAluInstructions = 255;
- ctx->Const.FragmentProgram.MaxNativeTexInstructions = 255;
- ctx->Const.FragmentProgram.MaxNativeInstructions = 255;
- ctx->Const.FragmentProgram.MaxNativeTexIndirections = 255;
- ctx->Const.FragmentProgram.MaxNativeAddressRegs = 0;
- } else {
- ctx->Const.FragmentProgram.MaxNativeTemps = R300_PFS_NUM_TEMP_REGS;
- ctx->Const.FragmentProgram.MaxNativeAttribs = 11; /* copy i915... */
- ctx->Const.FragmentProgram.MaxNativeParameters = R300_PFS_NUM_CONST_REGS;
- ctx->Const.FragmentProgram.MaxNativeAluInstructions = R300_PFS_MAX_ALU_INST;
- ctx->Const.FragmentProgram.MaxNativeTexInstructions = R300_PFS_MAX_TEX_INST;
- ctx->Const.FragmentProgram.MaxNativeInstructions = R300_PFS_MAX_ALU_INST + R300_PFS_MAX_TEX_INST;
- ctx->Const.FragmentProgram.MaxNativeTexIndirections = R300_PFS_MAX_TEX_INDIRECT;
- ctx->Const.FragmentProgram.MaxNativeAddressRegs = 0;
- }
-
-}
-
-static void r300ParseOptions(r300ContextPtr r300, radeonScreenPtr screen)
-{
- struct r300_options options = { 0 };
-
- driParseConfigFiles(&r300->radeon.optionCache, &screen->optionCache,
- screen->driScreen->myNum, "r300");
-
- r300->radeon.initialMaxAnisotropy = driQueryOptionf(&r300->radeon.optionCache, "def_max_anisotropy");
-
- options.stencil_two_side_disabled = driQueryOptionb(&r300->radeon.optionCache, "disable_stencil_two_side");
- options.s3tc_force_enabled = driQueryOptionb(&r300->radeon.optionCache, "force_s3tc_enable");
- options.s3tc_force_disabled = driQueryOptionb(&r300->radeon.optionCache, "disable_s3tc");
-
- if (!(screen->chip_flags & RADEON_CHIPSET_TCL) || driQueryOptioni(&r300->radeon.optionCache, "tcl_mode") == DRI_CONF_TCL_SW)
- options.hw_tcl_enabled = 0;
- else
- options.hw_tcl_enabled = 1;
-
- options.conformance_mode = !driQueryOptionb(&r300->radeon.optionCache, "disable_lowimpact_fallback");
-
- r300->options = options;
-}
-
-static void r300InitGLExtensions(struct gl_context *ctx)
-{
- r300ContextPtr r300 = R300_CONTEXT(ctx);
-
- ctx->Extensions.ARB_depth_texture = true;
- ctx->Extensions.ARB_fragment_program = true;
- ctx->Extensions.ARB_shadow = true;
- ctx->Extensions.ARB_shadow_ambient = true;
- ctx->Extensions.ARB_texture_border_clamp = true;
- ctx->Extensions.ARB_texture_cube_map = true;
- ctx->Extensions.ARB_texture_env_combine = true;
- ctx->Extensions.ARB_texture_env_crossbar = true;
- ctx->Extensions.ARB_texture_env_dot3 = true;
- ctx->Extensions.ARB_vertex_program = true;
- ctx->Extensions.EXT_blend_color = true;
- ctx->Extensions.EXT_blend_equation_separate = true;
- ctx->Extensions.EXT_blend_func_separate = true;
- ctx->Extensions.EXT_blend_minmax = true;
- ctx->Extensions.EXT_fog_coord = true;
- ctx->Extensions.EXT_gpu_program_parameters = true;
- ctx->Extensions.EXT_point_parameters = true;
- ctx->Extensions.EXT_provoking_vertex = true;
- ctx->Extensions.EXT_secondary_color = true;
- ctx->Extensions.EXT_shadow_funcs = true;
- ctx->Extensions.EXT_texture_env_dot3 = true;
- ctx->Extensions.EXT_texture_filter_anisotropic = true;
- ctx->Extensions.EXT_texture_mirror_clamp = true;
- ctx->Extensions.EXT_texture_sRGB = true;
- ctx->Extensions.EXT_vertex_array_bgra = true;
- ctx->Extensions.ATI_separate_stencil = true;
- ctx->Extensions.ATI_texture_env_combine3 = true;
- ctx->Extensions.ATI_texture_mirror_once = true;
- ctx->Extensions.MESA_pack_invert = true;
- ctx->Extensions.MESA_ycbcr_texture = true;
- ctx->Extensions.NV_blend_square = true;
- ctx->Extensions.NV_texture_rectangle = true;
- ctx->Extensions.NV_vertex_program = true;
-#if FEATURE_OES_EGL_image
- ctx->Extensions.OES_EGL_image = true;
-#endif
-
- if (r300->radeon.radeonScreen->kernel_mm) {
- ctx->Extensions.EXT_framebuffer_blit = true;
- ctx->Extensions.EXT_framebuffer_object = true;
- }
-
- ctx->Extensions.EXT_stencil_two_side =
- !r300->options.stencil_two_side_disabled;
-
- if (r300->options.s3tc_force_disabled) {
- ctx->Extensions.EXT_texture_compression_s3tc = false;
- } else if (ctx->Mesa_DXTn || r300->options.s3tc_force_enabled) {
- ctx->Extensions.EXT_texture_compression_s3tc = true;
- ctx->Extensions.S3_s3tc = true;
- }
-
- ctx->Extensions.ARB_occlusion_query =
- r300->radeon.radeonScreen->drmSupportsOcclusionQueries;
-
- ctx->Extensions.ARB_half_float_vertex =
- (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_R420);
-
- ctx->Extensions.EXT_packed_depth_stencil =
- (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515);
-}
-
-static void r300InitIoctlFuncs(struct dd_function_table *functions)
-{
- functions->Clear = _mesa_meta_Clear;
- functions->Finish = radeonFinish;
- functions->Flush = radeonFlush;
-}
-
-/* Create the device specific rendering context.
- */
-GLboolean r300CreateContext(gl_api api,
- const struct gl_config * glVisual,
- __DRIcontext * driContextPriv,
- void *sharedContextPrivate)
-{
- __DRIscreen *sPriv = driContextPriv->driScreenPriv;
- radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private);
- struct dd_function_table functions;
- r300ContextPtr r300;
- struct gl_context *ctx;
-
- assert(glVisual);
- assert(driContextPriv);
- assert(screen);
-
- r300 = (r300ContextPtr) CALLOC(sizeof(*r300));
- if (!r300)
- return GL_FALSE;
-
- r300ParseOptions(r300, screen);
-
- r300->radeon.radeonScreen = screen;
- r300_init_vtbl(&r300->radeon);
-
- _mesa_init_driver_functions(&functions);
- r300InitIoctlFuncs(&functions);
- r300InitStateFuncs(&r300->radeon, &functions);
- r300InitTextureFuncs(&r300->radeon, &functions);
- r300InitShaderFuncs(&functions);
- radeonInitQueryObjFunctions(&functions);
- radeonInitBufferObjectFuncs(&functions);
-
- if (!radeonInitContext(&r300->radeon, &functions,
- glVisual, driContextPriv,
- sharedContextPrivate)) {
- FREE(r300);
- return GL_FALSE;
- }
-
- ctx = r300->radeon.glCtx;
-
- r300->fallback = 0;
- if (r300->options.hw_tcl_enabled)
- ctx->VertexProgram._MaintainTnlProgram = GL_TRUE;
-
- ctx->FragmentProgram._MaintainTexEnvProgram = GL_TRUE;
-
- r300InitConstValues(ctx, screen);
-
- _mesa_set_mvp_with_dp4( ctx, GL_TRUE );
-
- /* Initialize the software rasterizer and helper modules.
- */
- _swrast_CreateContext(ctx);
- _vbo_CreateContext(ctx);
- _tnl_CreateContext(ctx);
- _swsetup_CreateContext(ctx);
- _swsetup_Wakeup(ctx);
-
- /* Install the customized pipeline:
- */
- _tnl_destroy_pipeline(ctx);
- _tnl_install_pipeline(ctx, r300_pipeline);
- TNL_CONTEXT(ctx)->Driver.RunPipeline = _tnl_run_pipeline;
-
- /* Configure swrast and TNL to match hardware characteristics:
- */
- _swrast_allow_pixel_fog(ctx, GL_FALSE);
- _swrast_allow_vertex_fog(ctx, GL_TRUE);
- _tnl_allow_pixel_fog(ctx, GL_FALSE);
- _tnl_allow_vertex_fog(ctx, GL_TRUE);
-
- if (r300->options.hw_tcl_enabled) {
- r300InitDraw(ctx);
- } else {
- r300InitSwtcl(ctx);
- }
-
- r300_blit_init(r300);
- radeon_fbo_init(&r300->radeon);
- radeonInitSpanFuncs( ctx );
- r300InitCmdBuf(r300);
- r300InitState(r300);
- r300InitShaderFunctions(r300);
-
- r300InitGLExtensions(ctx);
-
- return GL_TRUE;
-}
-
+++ /dev/null
-/*
-Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
-
-The Weather Channel (TM) funded Tungsten Graphics to develop the
-initial release of the Radeon 8500 driver under the XFree86 license.
-This notice must be preserved.
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-**************************************************************************/
-
-/**
- * \file
- *
- * \author Keith Whitwell <keith@tungstengraphics.com>
- * \author Nicolai Haehnle <prefect_@gmx.net>
- */
-
-#ifndef __R300_CONTEXT_H__
-#define __R300_CONTEXT_H__
-
-#include "drm.h"
-#include "radeon_drm.h"
-#include "dri_util.h"
-#include "radeon_common.h"
-
-#include "main/mtypes.h"
-#include "program/prog_instruction.h"
-#include "compiler/radeon_code.h"
-
-struct r300_context;
-typedef struct r300_context r300ContextRec;
-typedef struct r300_context *r300ContextPtr;
-
-
-#include "r300_vertprog.h"
-
-
-/* The blit width for texture uploads
- */
-#define R300_BLIT_WIDTH_BYTES 1024
-#define R300_MAX_TEXTURE_UNITS 8
-
-
-
-#define R300_VPT_CMD_0 0
-#define R300_VPT_XSCALE 1
-#define R300_VPT_XOFFSET 2
-#define R300_VPT_YSCALE 3
-#define R300_VPT_YOFFSET 4
-#define R300_VPT_ZSCALE 5
-#define R300_VPT_ZOFFSET 6
-#define R300_VPT_CMDSIZE 7
-
-#define R300_VIR_CMD_0 0 /* vir is variable size (at least 1) */
-#define R300_VIR_CNTL_0 1
-#define R300_VIR_CNTL_1 2
-#define R300_VIR_CNTL_2 3
-#define R300_VIR_CNTL_3 4
-#define R300_VIR_CNTL_4 5
-#define R300_VIR_CNTL_5 6
-#define R300_VIR_CNTL_6 7
-#define R300_VIR_CNTL_7 8
-#define R300_VIR_CMDSIZE 9
-
-#define R300_VIC_CMD_0 0
-#define R300_VIC_CNTL_0 1
-#define R300_VIC_CNTL_1 2
-#define R300_VIC_CMDSIZE 3
-
-#define R300_VOF_CMD_0 0
-#define R300_VOF_CNTL_0 1
-#define R300_VOF_CNTL_1 2
-#define R300_VOF_CMDSIZE 3
-
-#define R300_PVS_CMD_0 0
-#define R300_PVS_CNTL_1 1
-#define R300_PVS_CNTL_2 2
-#define R300_PVS_CNTL_3 3
-#define R300_PVS_CMDSIZE 4
-
-#define R300_GB_MISC_CMD_0 0
-#define R300_GB_MISC_MSPOS_0 1
-#define R300_GB_MISC_MSPOS_1 2
-#define R300_GB_MISC_TILE_CONFIG 3
-#define R300_GB_MISC_CMDSIZE 4
-#define R300_GB_MISC2_CMD_0 0
-#define R300_GB_MISC2_SELECT 1
-#define R300_GB_MISC2_AA_CONFIG 2
-#define R300_GB_MISC2_CMDSIZE 3
-
-#define R300_TXE_CMD_0 0
-#define R300_TXE_ENABLE 1
-#define R300_TXE_CMDSIZE 2
-
-#define R300_PS_CMD_0 0
-#define R300_PS_POINTSIZE 1
-#define R300_PS_CMDSIZE 2
-
-#define R300_ZBS_CMD_0 0
-#define R300_ZBS_T_FACTOR 1
-#define R300_ZBS_T_CONSTANT 2
-#define R300_ZBS_W_FACTOR 3
-#define R300_ZBS_W_CONSTANT 4
-#define R300_ZBS_CMDSIZE 5
-
-#define R300_CUL_CMD_0 0
-#define R300_CUL_CULL 1
-#define R300_CUL_CMDSIZE 2
-
-#define R300_RC_CMD_0 0
-#define R300_RC_CNTL_0 1
-#define R300_RC_CNTL_1 2
-#define R300_RC_CMDSIZE 3
-
-#define R300_RI_CMD_0 0
-#define R300_RI_INTERP_0 1
-#define R300_RI_INTERP_1 2
-#define R300_RI_INTERP_2 3
-#define R300_RI_INTERP_3 4
-#define R300_RI_INTERP_4 5
-#define R300_RI_INTERP_5 6
-#define R300_RI_INTERP_6 7
-#define R300_RI_INTERP_7 8
-#define R300_RI_CMDSIZE 9
-
-#define R500_RI_CMDSIZE 17
-
-#define R300_RR_CMD_0 0 /* rr is variable size (at least 1) */
-#define R300_RR_INST_0 1
-#define R300_RR_INST_1 2
-#define R300_RR_INST_2 3
-#define R300_RR_INST_3 4
-#define R300_RR_INST_4 5
-#define R300_RR_INST_5 6
-#define R300_RR_INST_6 7
-#define R300_RR_INST_7 8
-#define R300_RR_CMDSIZE 9
-
-#define R300_FP_CMD_0 0
-#define R300_FP_CNTL0 1
-#define R300_FP_CNTL1 2
-#define R300_FP_CNTL2 3
-#define R300_FP_CMD_1 4
-#define R300_FP_NODE0 5
-#define R300_FP_NODE1 6
-#define R300_FP_NODE2 7
-#define R300_FP_NODE3 8
-#define R300_FP_CMDSIZE 9
-
-#define R500_FP_CMD_0 0
-#define R500_FP_CNTL 1
-#define R500_FP_PIXSIZE 2
-#define R500_FP_CMD_1 3
-#define R500_FP_CODE_ADDR 4
-#define R500_FP_CODE_RANGE 5
-#define R500_FP_CODE_OFFSET 6
-#define R500_FP_CMD_2 7
-#define R500_FP_FC_CNTL 8
-#define R500_FP_CMDSIZE 9
-
-#define R300_FPT_CMD_0 0
-#define R300_FPT_INSTR_0 1
-#define R300_FPT_CMDSIZE 65
-
-#define R300_FPI_CMD_0 0
-#define R300_FPI_INSTR_0 1
-#define R300_FPI_CMDSIZE 65
-/* R500 has space for 512 instructions - 6 dwords per instruction */
-#define R500_FPI_CMDSIZE (512*6+1)
-
-#define R300_FPP_CMD_0 0
-#define R300_FPP_PARAM_0 1
-#define R300_FPP_CMDSIZE (32*4+1)
-/* R500 has spcae for 256 constants - 4 dwords per constant */
-#define R500_FPP_CMDSIZE (256*4+1)
-
-#define R300_FOGS_CMD_0 0
-#define R300_FOGS_STATE 1
-#define R300_FOGS_CMDSIZE 2
-
-#define R300_FOGC_CMD_0 0
-#define R300_FOGC_R 1
-#define R300_FOGC_G 2
-#define R300_FOGC_B 3
-#define R300_FOGC_CMDSIZE 4
-
-#define R300_FOGP_CMD_0 0
-#define R300_FOGP_SCALE 1
-#define R300_FOGP_START 2
-#define R300_FOGP_CMDSIZE 3
-
-#define R300_AT_CMD_0 0
-#define R300_AT_ALPHA_TEST 1
-#define R300_AT_UNKNOWN 2
-#define R300_AT_CMDSIZE 3
-
-#define R300_BLD_CMD_0 0
-#define R300_BLD_CBLEND 1
-#define R300_BLD_ABLEND 2
-#define R300_BLD_CMDSIZE 3
-
-#define R300_CMK_CMD_0 0
-#define R300_CMK_COLORMASK 1
-#define R300_CMK_CMDSIZE 2
-
-#define R300_CB_CMD_0 0
-#define R300_CB_OFFSET 1
-#define R300_CB_CMD_1 2
-#define R300_CB_PITCH 3
-#define R300_CB_CMDSIZE 4
-
-#define R300_ZS_CMD_0 0
-#define R300_ZS_CNTL_0 1
-#define R300_ZS_CNTL_1 2
-#define R300_ZS_CNTL_2 3
-#define R300_ZS_CMDSIZE 4
-
-#define R300_ZSB_CMD_0 0
-#define R300_ZSB_CNTL_0 1
-#define R300_ZSB_CMDSIZE 2
-
-#define R300_ZB_CMD_0 0
-#define R300_ZB_OFFSET 1
-#define R300_ZB_PITCH 2
-#define R300_ZB_CMDSIZE 3
-
-#define R300_VAP_CNTL_FLUSH 0
-#define R300_VAP_CNTL_FLUSH_1 1
-#define R300_VAP_CNTL_CMD 2
-#define R300_VAP_CNTL_INSTR 3
-#define R300_VAP_CNTL_SIZE 4
-
-#define R300_VPI_CMD_0 0
-#define R300_VPI_INSTR_0 1
-#define R300_VPI_CMDSIZE 1025 /* 256 16 byte instructions */
-
-#define R300_VPP_CMD_0 0
-#define R300_VPP_PARAM_0 1
-#define R300_VPP_CMDSIZE 1025 /* 256 4-component parameters */
-
-#define R300_VPUCP_CMD_0 0
-#define R300_VPUCP_X 1
-#define R300_VPUCP_Y 2
-#define R300_VPUCP_Z 3
-#define R300_VPUCP_W 4
-#define R300_VPUCP_CMDSIZE 5 /* 256 4-component parameters */
-
-#define R300_VPS_CMD_0 0
-#define R300_VPS_ZERO_0 1
-#define R300_VPS_ZERO_1 2
-#define R300_VPS_POINTSIZE 3
-#define R300_VPS_ZERO_3 4
-#define R300_VPS_CMDSIZE 5
-
- /* the layout is common for all fields inside tex */
-#define R300_TEX_CMD_0 0
-#define R300_TEX_VALUE_0 1
-/* We don't really use this, instead specify mtu+1 dynamically
-#define R300_TEX_CMDSIZE (MAX_TEXTURE_UNITS+1)
-*/
-
-#define R300_QUERYOBJ_CMD_0 0
-#define R300_QUERYOBJ_DATA_0 1
-#define R300_QUERYOBJ_CMD_1 2
-#define R300_QUERYOBJ_DATA_1 3
-#define R300_QUERYOBJ_CMDSIZE 4
-
-/**
- * Cache for hardware register state.
- */
-struct r300_hw_state {
- struct radeon_state_atom vpt; /* viewport (1D98) */
- struct radeon_state_atom vap_cntl;
- struct radeon_state_atom vap_index_offset; /* 0x208c r5xx only */
- struct radeon_state_atom vof; /* VAP output format register 0x2090 */
- struct radeon_state_atom vte; /* (20B0) */
- struct radeon_state_atom vap_vf_max_vtx_indx; /* Maximum Vertex Indx Clamp (2134) */
- struct radeon_state_atom vap_cntl_status;
- struct radeon_state_atom vir[2]; /* vap input route (2150/21E0) */
- struct radeon_state_atom vic; /* vap input control (2180) */
- struct radeon_state_atom vap_psc_sgn_norm_cntl; /* Programmable Stream Control Signed Normalize Control (21DC) */
- struct radeon_state_atom vap_clip_cntl;
- struct radeon_state_atom vap_clip;
- struct radeon_state_atom vap_pvs_vtx_timeout_reg; /* Vertex timeout register (2288) */
- struct radeon_state_atom pvs; /* pvs_cntl (22D0) */
- struct radeon_state_atom gb_enable; /* (4008) */
- struct radeon_state_atom gb_misc; /* Multisampling position shifts ? (4010) */
- struct radeon_state_atom gb_misc2; /* Multisampling position shifts ? (4010) */
- struct radeon_state_atom ga_point_s0; /* S Texture Coordinate of Vertex 0 for Point texture stuffing (LLC) (4200) */
- struct radeon_state_atom ga_triangle_stipple; /* (4214) */
- struct radeon_state_atom ps; /* pointsize (421C) */
- struct radeon_state_atom ga_point_minmax; /* (4230) */
- struct radeon_state_atom lcntl; /* line control */
- struct radeon_state_atom ga_line_stipple; /* (4260) */
- struct radeon_state_atom shade;
- struct radeon_state_atom shade2;
- struct radeon_state_atom polygon_mode;
- struct radeon_state_atom fogp; /* fog parameters (4294) */
- struct radeon_state_atom ga_soft_reset; /* (429C) */
- struct radeon_state_atom zbias_cntl;
- struct radeon_state_atom zbs; /* zbias (42A4) */
- struct radeon_state_atom occlusion_cntl;
- struct radeon_state_atom cul; /* cull cntl (42B8) */
- struct radeon_state_atom su_depth_scale; /* (42C0) */
- struct radeon_state_atom rc; /* rs control (4300) */
- struct radeon_state_atom ri; /* rs interpolators (4310) */
- struct radeon_state_atom rr; /* rs route (4330) */
- struct radeon_state_atom sc_hyperz; /* (43A4) */
- struct radeon_state_atom sc_screendoor; /* (43E8) */
- struct radeon_state_atom fp; /* fragment program cntl + nodes (4600) */
- struct radeon_state_atom fpt; /* texi - (4620) */
- struct radeon_state_atom us_out_fmt; /* (46A4) */
- struct radeon_state_atom r500fp; /* r500 fp instructions */
- struct radeon_state_atom r500fp_const; /* r500 fp constants */
- struct radeon_state_atom fpi[4]; /* fp instructions (46C0/47C0/48C0/49C0) */
- struct radeon_state_atom fogs; /* fog state (4BC0) */
- struct radeon_state_atom fogc; /* fog color (4BC8) */
- struct radeon_state_atom at; /* alpha test (4BD4) */
- struct radeon_state_atom fg_depth_src; /* (4BD8) */
- struct radeon_state_atom fpp; /* 0x4C00 and following */
- struct radeon_state_atom rb3d_cctl; /* (4E00) */
- struct radeon_state_atom bld; /* blending (4E04) */
- struct radeon_state_atom cmk; /* colormask (4E0C) */
- struct radeon_state_atom blend_color; /* constant blend color */
- struct radeon_state_atom rop; /* ropcntl */
- struct radeon_state_atom cb; /* colorbuffer (4E28) */
- struct radeon_state_atom rb3d_dither_ctl; /* (4E50) */
- struct radeon_state_atom rb3d_aaresolve_ctl; /* (4E88) */
- struct radeon_state_atom rb3d_discard_src_pixel_lte_threshold; /* (4E88) I saw it only written on RV350 hardware.. */
- struct radeon_state_atom zs; /* zstencil control (4F00) */
- struct radeon_state_atom zsb; /* zstencil bf */
- struct radeon_state_atom zstencil_format;
- struct radeon_state_atom zb; /* z buffer (4F20) */
- struct radeon_state_atom zb_depthclearvalue; /* (4F28) */
- struct radeon_state_atom zb_zmask; /* (4F30) */
- struct radeon_state_atom zb_hiz_offset; /* (4F44) */
- struct radeon_state_atom zb_hiz_pitch; /* (4F54) */
-
- struct radeon_state_atom vpi; /* vp instructions */
- struct radeon_state_atom vpp; /* vp parameters */
- struct radeon_state_atom vps; /* vertex point size (?) */
- struct radeon_state_atom vpucp[6]; /* vp user clip plane - 6 */
- /* 8 texture units */
- /* the state is grouped by function and not by
- texture unit. This makes single unit updates
- really awkward - we are much better off
- updating the whole thing at once */
- struct {
- struct radeon_state_atom filter;
- struct radeon_state_atom filter_1;
- struct radeon_state_atom size;
- struct radeon_state_atom format;
- struct radeon_state_atom pitch;
- struct radeon_state_atom offset;
- struct radeon_state_atom chroma_key;
- struct radeon_state_atom border_color;
- } tex;
- struct radeon_state_atom txe; /* tex enable (4104) */
- radeonTexObj *textures[R300_MAX_TEXTURE_UNITS];
-};
-
-/**
- * State cache
- */
-
-/* Vertex shader state */
-
-#define COLOR_IS_RGBA
-#define TAG(x) r300##x
-#include "tnl_dd/t_dd_vertex.h"
-#undef TAG
-
-struct r300_vertex_program_key {
- GLbitfield FpReads;
- GLuint FogAttr;
- GLuint WPosAttr;
-};
-
-struct r300_vertex_program {
- struct gl_vertex_program *Base;
- struct r300_vertex_program *next;
-
- struct r300_vertex_program_key key;
- struct r300_vertex_program_code code;
-
- GLboolean error;
-};
-
-struct r300_vertex_program_cont {
- /* This is the unmodified vertex program mesa provided us with.
- * We need to keep it unchanged because we may need to create another
- * hw specific vertex program based on this.
- */
- struct gl_vertex_program mesa_program;
- /* This is the list of hw specific vertex programs derived from mesa_program */
- struct r300_vertex_program *progs;
-};
-
-
-/**
-* Store everything about a fragment program that is needed
-* to render with that program.
-*/
-struct r300_fragment_program {
- GLboolean error;
- struct r300_fragment_program *next;
- struct r300_fragment_program_external_state state;
-
- struct rX00_fragment_program_code code;
- GLbitfield InputsRead;
-
- /* attribute that we are sending the WPOS in */
- gl_frag_attrib wpos_attr;
- /* attribute that we are sending the fog coordinate in */
- gl_frag_attrib fog_attr;
-};
-
-struct r300_fragment_program_cont {
- /* This is the unmodified fragment program mesa provided us with.
- * We need to keep it unchanged because we may need to create another
- * hw specific fragment program based on this.
- */
- struct gl_fragment_program Base;
- /* This is the list of hw specific fragment programs derived from Base */
- struct r300_fragment_program *progs;
-};
-
-
-#define R300_MAX_AOS_ARRAYS 16
-
-
-/* r300_swtcl.c
- */
-struct r300_swtcl_info {
- /*
- * Offset of the 4UB color data within a hardware (swtcl) vertex.
- */
- GLuint coloroffset;
-
- /**
- * Offset of the 3UB specular color data within a hardware (swtcl) vertex.
- */
- GLuint specoffset;
-};
-
-struct r300_vtable {
- void (* SetupRSUnit)(struct gl_context *ctx);
- void (* SetupFragmentShaderTextures)(struct gl_context *ctx, int *tmu_mappings);
- void (* SetupPixelShader)(struct gl_context *ctx);
-};
-
-struct r300_vertex_buffer {
- struct vertex_attribute {
- /* generic */
- GLubyte element;
- GLuint stride;
- GLuint dwords;
- GLubyte size; /* number of components */
- GLboolean is_named_bo;
- struct radeon_bo *bo;
- GLint bo_offset;
-
- /* hw specific */
- uint32_t data_type:4;
- uint32_t dst_loc:5;
- uint32_t _signed:1;
- uint32_t normalize:1;
- uint32_t swizzle:12;
- uint32_t write_mask:4;
- } attribs[VERT_ATTRIB_MAX];
-
- GLubyte num_attribs;
-};
-
-struct r300_index_buffer {
- struct radeon_bo *bo;
- int bo_offset;
-
- GLboolean is_32bit;
- GLuint count;
-};
-
-
-/**
- * \brief R300 context structure.
- */
-struct r300_context {
- struct radeon_context radeon; /* parent class, must be first */
-
- struct r300_vtable vtbl;
-
- struct r300_hw_state hw;
-
- struct r300_vertex_program *selected_vp;
- struct r300_fragment_program *selected_fp;
-
- /* Vertex buffers
- */
- GLvector4f dummy_attrib[_TNL_ATTRIB_MAX];
- GLvector4f *temp_attrib[_TNL_ATTRIB_MAX];
-
- struct r300_options {
- uint32_t conformance_mode:1;
- uint32_t hw_tcl_enabled:1;
- uint32_t s3tc_force_enabled:1;
- uint32_t s3tc_force_disabled:1;
- uint32_t stencil_two_side_disabled:1;
- } options;
-
- struct r300_swtcl_info swtcl;
- struct r300_vertex_buffer vbuf;
- struct r300_index_buffer ind_buf;
-
- uint32_t fallback;
-
- struct {
- struct r300_vertex_program_code vp_code;
- struct rX00_fragment_program_code fp_code;
- } blit;
-
- DECLARE_RENDERINPUTS(render_inputs_bitset);
-};
-
-#define R300_CONTEXT(ctx) ((r300ContextPtr)(ctx->DriverCtx))
-
-extern void r300DestroyContext(__DRIcontext * driContextPriv);
-extern GLboolean r300CreateContext(gl_api api,
- const struct gl_config * glVisual,
- __DRIcontext * driContextPriv,
- void *sharedContextPrivate);
-
-extern void r300InitShaderFuncs(struct dd_function_table *functions);
-
-extern void r300InitShaderFunctions(r300ContextPtr r300);
-
-extern void r300InitDraw(struct gl_context *ctx);
-
-#define r300PackFloat32 radeonPackFloat32
-#define r300PackFloat24 radeonPackFloat24
-
-#endif /* __R300_CONTEXT_H__ */
+++ /dev/null
-/**************************************************************************
- *
- * Copyright 2009 Maciej Cencora
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sub license, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial portions
- * of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHOR(S) AND/OR ITS SUPPLIERS BE LIABLE FOR
- * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- **************************************************************************/
-
-#include <stdlib.h>
-
-#include "main/glheader.h"
-#include "main/context.h"
-#include "main/state.h"
-#include "main/enums.h"
-#include "main/simple_list.h"
-
-#include "r300_reg.h"
-#include "r300_context.h"
-#include "r300_emit.h"
-#include "r300_render.h"
-#include "r300_state.h"
-#include "r300_tex.h"
-#include "r300_cmdbuf.h"
-
-#include "radeon_buffer_objects.h"
-#include "radeon_common_context.h"
-
-#include "tnl/tnl.h"
-#include "tnl/t_vp_build.h"
-#include "vbo/vbo_context.h"
-
-
-static int getTypeSize(GLenum type)
-{
- switch (type) {
- case GL_DOUBLE:
- return sizeof(GLdouble);
- case GL_HALF_FLOAT:
- return sizeof(GLhalfARB);
- case GL_FLOAT:
- return sizeof(GLfloat);
- case GL_INT:
- return sizeof(GLint);
- case GL_UNSIGNED_INT:
- return sizeof(GLuint);
- case GL_SHORT:
- return sizeof(GLshort);
- case GL_UNSIGNED_SHORT:
- return sizeof(GLushort);
- case GL_BYTE:
- return sizeof(GLbyte);
- case GL_UNSIGNED_BYTE:
- return sizeof(GLubyte);
- default:
- assert(0);
- return 0;
- }
-}
-
-static void r300FixupIndexBuffer(struct gl_context *ctx, const struct _mesa_index_buffer *mesa_ind_buf)
-{
- r300ContextPtr r300 = R300_CONTEXT(ctx);
- GLvoid *src_ptr;
- GLuint *out;
- int i;
- GLboolean mapped_named_bo = GL_FALSE;
-
- if (mesa_ind_buf->obj->Name && !mesa_ind_buf->obj->Pointer) {
- ctx->Driver.MapBufferRange(ctx, 0, mesa_ind_buf->obj->Size,
- GL_MAP_READ_BIT, mesa_ind_buf->obj);
- mapped_named_bo = GL_TRUE;
- assert(mesa_ind_buf->obj->Pointer != NULL);
- }
- src_ptr = ADD_POINTERS(mesa_ind_buf->obj->Pointer, mesa_ind_buf->ptr);
-
- radeon_print(RADEON_FALLBACKS, RADEON_IMPORTANT,
- "%s: Fixing index buffer format. type %d\n",
- __func__, mesa_ind_buf->type);
-
- if (mesa_ind_buf->type == GL_UNSIGNED_BYTE) {
- GLuint size = sizeof(GLushort) * ((mesa_ind_buf->count + 1) & ~1);
- GLubyte *in = (GLubyte *)src_ptr;
-
- radeonAllocDmaRegion(&r300->radeon, &r300->ind_buf.bo, &r300->ind_buf.bo_offset, size, 4);
- radeon_bo_map(r300->ind_buf.bo, 1);
- assert(r300->ind_buf.bo->ptr != NULL);
- out = (GLuint *)ADD_POINTERS(r300->ind_buf.bo->ptr, r300->ind_buf.bo_offset);
-
- for (i = 0; i + 1 < mesa_ind_buf->count; i += 2) {
- *out++ = in[i] | in[i + 1] << 16;
- }
-
- if (i < mesa_ind_buf->count) {
- *out++ = in[i];
- }
- radeon_bo_unmap(r300->ind_buf.bo);
-#if MESA_BIG_ENDIAN
- } else { /* if (mesa_ind_buf->type == GL_UNSIGNED_SHORT) */
- GLushort *in = (GLushort *)src_ptr;
- GLuint size = sizeof(GLushort) * ((mesa_ind_buf->count + 1) & ~1);
-
- radeonAllocDmaRegion(&r300->radeon, &r300->ind_buf.bo,
- &r300->ind_buf.bo_offset, size, 4);
-
- radeon_bo_map(r300->ind_buf.bo, 1);
- assert(r300->ind_buf.bo->ptr != NULL);
- out = (GLuint *)ADD_POINTERS(r300->ind_buf.bo->ptr, r300->ind_buf.bo_offset);
-
- for (i = 0; i + 1 < mesa_ind_buf->count; i += 2) {
- *out++ = in[i] | in[i + 1] << 16;
- }
-
- if (i < mesa_ind_buf->count) {
- *out++ = in[i];
- }
- radeon_bo_unmap(r300->ind_buf.bo);
-#endif
- }
-
- r300->ind_buf.is_32bit = GL_FALSE;
- r300->ind_buf.count = mesa_ind_buf->count;
-
- if (mapped_named_bo) {
- ctx->Driver.UnmapBuffer(ctx, mesa_ind_buf->obj);
- }
-}
-
-
-static void r300SetupIndexBuffer(struct gl_context *ctx, const struct _mesa_index_buffer *mesa_ind_buf)
-{
- r300ContextPtr r300 = R300_CONTEXT(ctx);
-
- if (!mesa_ind_buf) {
- r300->ind_buf.bo = NULL;
- return;
- }
- radeon_print(RADEON_RENDER, RADEON_TRACE, "%s\n", __func__);
-
-#if MESA_BIG_ENDIAN
- if (mesa_ind_buf->type == GL_UNSIGNED_INT) {
-#else
- if (mesa_ind_buf->type != GL_UNSIGNED_BYTE) {
-#endif
- const GLvoid *src_ptr;
- GLvoid *dst_ptr;
- GLboolean mapped_named_bo = GL_FALSE;
-
- if (mesa_ind_buf->obj->Name && !mesa_ind_buf->obj->Pointer) {
- ctx->Driver.MapBufferRange(ctx, 0,
- mesa_ind_buf->obj->Size,
- GL_MAP_READ_BIT,
- mesa_ind_buf->obj);
- assert(mesa_ind_buf->obj->Pointer != NULL);
- mapped_named_bo = GL_TRUE;
- }
-
- src_ptr = ADD_POINTERS(mesa_ind_buf->obj->Pointer, mesa_ind_buf->ptr);
-
- const GLuint size = mesa_ind_buf->count * getTypeSize(mesa_ind_buf->type);
-
- radeonAllocDmaRegion(&r300->radeon, &r300->ind_buf.bo, &r300->ind_buf.bo_offset, size, 4);
-
- radeon_bo_map(r300->ind_buf.bo, 1);
- assert(r300->ind_buf.bo->ptr != NULL);
- dst_ptr = ADD_POINTERS(r300->ind_buf.bo->ptr, r300->ind_buf.bo_offset);
- memcpy(dst_ptr, src_ptr, size);
-
- radeon_bo_unmap(r300->ind_buf.bo);
- r300->ind_buf.is_32bit = (mesa_ind_buf->type == GL_UNSIGNED_INT);
- r300->ind_buf.count = mesa_ind_buf->count;
-
- if (mapped_named_bo) {
- ctx->Driver.UnmapBuffer(ctx, mesa_ind_buf->obj);
- }
- } else {
- r300FixupIndexBuffer(ctx, mesa_ind_buf);
- }
-}
-
-#define CONVERT( TYPE, MACRO ) do { \
- GLuint i, j, sz; \
- sz = input->Size; \
- if (input->Normalized) { \
- for (i = 0; i < count; i++) { \
- const TYPE *in = (TYPE *)src_ptr; \
- for (j = 0; j < sz; j++) { \
- *dst_ptr++ = MACRO(*in); \
- in++; \
- } \
- src_ptr += stride; \
- } \
- } else { \
- for (i = 0; i < count; i++) { \
- const TYPE *in = (TYPE *)src_ptr; \
- for (j = 0; j < sz; j++) { \
- *dst_ptr++ = (GLfloat)(*in); \
- in++; \
- } \
- src_ptr += stride; \
- } \
- } \
-} while (0)
-
-/**
- * Convert attribute data type to float
- * If the attribute uses named buffer object replace the bo with newly allocated bo
- */
-static void r300ConvertAttrib(struct gl_context *ctx, int count, const struct gl_client_array *input, struct vertex_attribute *attr)
-{
- r300ContextPtr r300 = R300_CONTEXT(ctx);
- const GLvoid *src_ptr;
- GLboolean mapped_named_bo = GL_FALSE;
- GLfloat *dst_ptr;
- GLuint stride;
-
- stride = (input->StrideB == 0) ? getTypeSize(input->Type) * input->Size : input->StrideB;
-
- /* Convert value for first element only */
- if (input->StrideB == 0)
- count = 1;
-
- if (input->BufferObj->Name) {
- if (!input->BufferObj->Pointer) {
- ctx->Driver.MapBufferRange(ctx, 0, input->BufferObj->Size,
- GL_MAP_READ_BIT, input->BufferObj);
- mapped_named_bo = GL_TRUE;
- }
-
- src_ptr = ADD_POINTERS(input->BufferObj->Pointer, input->Ptr);
- } else {
- src_ptr = input->Ptr;
- }
-
- radeonAllocDmaRegion(&r300->radeon, &attr->bo, &attr->bo_offset, sizeof(GLfloat) * input->Size * count, 32);
- radeon_bo_map(attr->bo, 1);
- dst_ptr = (GLfloat *)ADD_POINTERS(attr->bo->ptr, attr->bo_offset);
-
- radeon_print(RADEON_FALLBACKS, RADEON_IMPORTANT,
- "%s: Converting vertex attributes, attribute data format %x,"
- "stride %d, components %d\n"
- , __FUNCTION__, input->Type
- , stride, input->Size);
-
- assert(src_ptr != NULL);
-
- switch (input->Type) {
- case GL_DOUBLE:
- CONVERT(GLdouble, (GLfloat));
- break;
- case GL_UNSIGNED_INT:
- CONVERT(GLuint, UINT_TO_FLOAT);
- break;
- case GL_INT:
- CONVERT(GLint, INT_TO_FLOAT);
- break;
- case GL_UNSIGNED_SHORT:
- CONVERT(GLushort, USHORT_TO_FLOAT);
- break;
- case GL_SHORT:
- CONVERT(GLshort, SHORT_TO_FLOAT);
- break;
- case GL_UNSIGNED_BYTE:
- assert(input->Format != GL_BGRA);
- CONVERT(GLubyte, UBYTE_TO_FLOAT);
- break;
- case GL_BYTE:
- CONVERT(GLbyte, BYTE_TO_FLOAT);
- break;
- default:
- assert(0);
- break;
- }
-
- radeon_bo_unmap(attr->bo);
- if (mapped_named_bo) {
- ctx->Driver.UnmapBuffer(ctx, input->BufferObj);
- }
-}
-
-static void r300AlignDataToDword(struct gl_context *ctx, const struct gl_client_array *input, int count, struct vertex_attribute *attr)
-{
- r300ContextPtr r300 = R300_CONTEXT(ctx);
- const int dst_stride = (input->StrideB + 3) & ~3;
- const int size = getTypeSize(input->Type) * input->Size * count;
- GLboolean mapped_named_bo = GL_FALSE;
-
- radeonAllocDmaRegion(&r300->radeon, &attr->bo, &attr->bo_offset, size, 32);
-
- radeon_bo_map(attr->bo, 1);
-
- if (!input->BufferObj->Pointer) {
- ctx->Driver.MapBufferRange(ctx, 0, input->BufferObj->Size,
- GL_MAP_READ_BIT, input->BufferObj);
- mapped_named_bo = GL_TRUE;
- }
-
- radeon_print(RADEON_FALLBACKS, RADEON_IMPORTANT, "%s. Vertex alignment doesn't match hw requirements.\n", __func__);
-
- {
- GLvoid *src_ptr = ADD_POINTERS(input->BufferObj->Pointer, input->Ptr);
- GLvoid *dst_ptr = ADD_POINTERS(attr->bo->ptr, attr->bo_offset);
- int i;
-
- for (i = 0; i < count; ++i) {
- memcpy(dst_ptr, src_ptr, input->StrideB);
- src_ptr += input->StrideB;
- dst_ptr += dst_stride;
- }
- }
-
- if (mapped_named_bo) {
- ctx->Driver.UnmapBuffer(ctx, input->BufferObj);
- }
-
- radeon_bo_unmap(attr->bo);
- attr->stride = dst_stride;
-}
-
-static void r300TranslateAttrib(struct gl_context *ctx, GLuint attr, int count, const struct gl_client_array *input)
-{
- r300ContextPtr r300 = R300_CONTEXT(ctx);
- struct r300_vertex_buffer *vbuf = &r300->vbuf;
- struct vertex_attribute r300_attr = { 0 };
- GLenum type;
- GLuint stride;
-
- radeon_print(RADEON_RENDER, RADEON_TRACE, "%s\n", __func__);
- stride = (input->StrideB == 0) ? getTypeSize(input->Type) * input->Size : input->StrideB;
-
- if (input->Type == GL_DOUBLE || input->Type == GL_UNSIGNED_INT || input->Type == GL_INT ||
-#if MESA_BIG_ENDIAN
- getTypeSize(input->Type) != 4 ||
-#endif
- stride < 4) {
-
- type = GL_FLOAT;
-
- if (input->StrideB == 0) {
- r300_attr.stride = 0;
- } else {
- r300_attr.stride = sizeof(GLfloat) * input->Size;
- }
- r300_attr.dwords = input->Size;
- r300_attr.is_named_bo = GL_FALSE;
- } else {
- type = input->Type;
- r300_attr.dwords = (getTypeSize(type) * input->Size + 3)/ 4;
- if (!input->BufferObj->Name) {
-
- if (input->StrideB == 0) {
- r300_attr.stride = 0;
- } else {
- r300_attr.stride = (getTypeSize(type) * input->Size + 3) & ~3;
- }
-
- r300_attr.is_named_bo = GL_FALSE;
- }
- }
-
- r300_attr.size = input->Size;
- r300_attr.element = attr;
- r300_attr.dst_loc = vbuf->num_attribs;
-
- switch (type) {
- case GL_FLOAT:
- switch (input->Size) {
- case 1: r300_attr.data_type = R300_DATA_TYPE_FLOAT_1; break;
- case 2: r300_attr.data_type = R300_DATA_TYPE_FLOAT_2; break;
- case 3: r300_attr.data_type = R300_DATA_TYPE_FLOAT_3; break;
- case 4: r300_attr.data_type = R300_DATA_TYPE_FLOAT_4; break;
- }
- r300_attr._signed = 0;
- r300_attr.normalize = 0;
- break;
- case GL_HALF_FLOAT:
- switch (input->Size) {
- case 1:
- case 2:
- r300_attr.data_type = R300_DATA_TYPE_FLT16_2;
- break;
- case 3:
- case 4:
- r300_attr.data_type = R300_DATA_TYPE_FLT16_4;
- break;
- }
- break;
- case GL_SHORT:
- r300_attr._signed = 1;
- r300_attr.normalize = input->Normalized;
- switch (input->Size) {
- case 1:
- case 2:
- r300_attr.data_type = R300_DATA_TYPE_SHORT_2;
- break;
- case 3:
- case 4:
- r300_attr.data_type = R300_DATA_TYPE_SHORT_4;
- break;
- }
- break;
- case GL_BYTE:
- r300_attr._signed = 1;
- r300_attr.normalize = input->Normalized;
- r300_attr.data_type = R300_DATA_TYPE_BYTE;
- break;
- case GL_UNSIGNED_SHORT:
- r300_attr._signed = 0;
- r300_attr.normalize = input->Normalized;
- switch (input->Size) {
- case 1:
- case 2:
- r300_attr.data_type = R300_DATA_TYPE_SHORT_2;
- break;
- case 3:
- case 4:
- r300_attr.data_type = R300_DATA_TYPE_SHORT_4;
- break;
- }
- break;
- case GL_UNSIGNED_BYTE:
- r300_attr._signed = 0;
- r300_attr.normalize = input->Normalized;
- if (input->Format == GL_BGRA)
- r300_attr.data_type = R300_DATA_TYPE_D3DCOLOR;
- else
- r300_attr.data_type = R300_DATA_TYPE_BYTE;
- break;
-
- default:
- case GL_DOUBLE:
- case GL_INT:
- case GL_UNSIGNED_INT:
- assert(0);
- break;
- }
-
- switch (input->Size) {
- case 4:
- r300_attr.swizzle = SWIZZLE_XYZW;
- break;
- case 3:
- r300_attr.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_ONE);
- break;
- case 2:
- r300_attr.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_ZERO, SWIZZLE_ONE);
- break;
- case 1:
- r300_attr.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_ZERO, SWIZZLE_ZERO, SWIZZLE_ONE);
- break;
- }
-
- r300_attr.write_mask = MASK_XYZW;
-
- vbuf->attribs[vbuf->num_attribs] = r300_attr;
- ++vbuf->num_attribs;
-}
-
-static void r300SetVertexFormat(struct gl_context *ctx, const struct gl_client_array *arrays[], int count)
-{
- r300ContextPtr r300 = R300_CONTEXT(ctx);
- struct r300_vertex_buffer *vbuf = &r300->vbuf;
- radeon_print(RADEON_RENDER, RADEON_VERBOSE, "%s\n", __func__);
- {
- int i, tmp;
-
- tmp = r300->selected_vp->code.InputsRead;
- i = 0;
- vbuf->num_attribs = 0;
- while (tmp) {
- /* find first enabled bit */
- while (!(tmp & 1)) {
- tmp >>= 1;
- ++i;
- }
-
- r300TranslateAttrib(ctx, i, count, arrays[i]);
-
- tmp >>= 1;
- ++i;
- }
- }
-
- r300SwitchFallback(ctx, R300_FALLBACK_AOS_LIMIT, vbuf->num_attribs > R300_MAX_AOS_ARRAYS);
- if (r300->fallback)
- return;
-}
-
-static void r300AllocDmaRegions(struct gl_context *ctx, const struct gl_client_array *input[], int count)
-{
- r300ContextPtr r300 = R300_CONTEXT(ctx);
- struct r300_vertex_buffer *vbuf = &r300->vbuf;
- GLuint stride;
- int ret;
- int i, index;
- radeon_print(RADEON_RENDER, RADEON_VERBOSE,
- "%s: count %d num_attribs %d\n",
- __func__, count, vbuf->num_attribs);
-
- for (index = 0; index < vbuf->num_attribs; index++) {
- struct radeon_aos *aos = &r300->radeon.tcl.aos[index];
- i = vbuf->attribs[index].element;
-
- stride = (input[i]->StrideB == 0) ? getTypeSize(input[i]->Type) * input[i]->Size : input[i]->StrideB;
-
- if (input[i]->Type == GL_DOUBLE || input[i]->Type == GL_UNSIGNED_INT || input[i]->Type == GL_INT ||
-#if MESA_BIG_ENDIAN
- getTypeSize(input[i]->Type) != 4 ||
-#endif
- stride < 4) {
-
- r300ConvertAttrib(ctx, count, input[i], &vbuf->attribs[index]);
- } else {
- if (input[i]->BufferObj->Name) {
- if (stride % 4 != 0 || (intptr_t)input[i]->Ptr % 4 != 0) {
- r300AlignDataToDword(ctx, input[i], count, &vbuf->attribs[index]);
- vbuf->attribs[index].is_named_bo = GL_FALSE;
- } else {
- vbuf->attribs[index].stride = input[i]->StrideB;
- vbuf->attribs[index].bo_offset = (intptr_t) input[i]->Ptr;
- vbuf->attribs[index].bo = get_radeon_buffer_object(input[i]->BufferObj)->bo;
- vbuf->attribs[index].is_named_bo = GL_TRUE;
- }
- } else {
-
- int size;
- int local_count = count;
- uint32_t *dst;
-
- if (input[i]->StrideB == 0) {
- size = getTypeSize(input[i]->Type) * input[i]->Size;
- local_count = 1;
- } else {
- size = getTypeSize(input[i]->Type) * input[i]->Size * local_count;
- }
-
- radeonAllocDmaRegion(&r300->radeon, &vbuf->attribs[index].bo, &vbuf->attribs[index].bo_offset, size, 32);
- radeon_bo_map(vbuf->attribs[index].bo, 1);
- assert(vbuf->attribs[index].bo->ptr != NULL);
- dst = (uint32_t *)ADD_POINTERS(vbuf->attribs[index].bo->ptr, vbuf->attribs[index].bo_offset);
- switch (vbuf->attribs[index].dwords) {
- case 1: radeonEmitVec4(dst, input[i]->Ptr, input[i]->StrideB, local_count); break;
- case 2: radeonEmitVec8(dst, input[i]->Ptr, input[i]->StrideB, local_count); break;
- case 3: radeonEmitVec12(dst, input[i]->Ptr, input[i]->StrideB, local_count); break;
- case 4: radeonEmitVec16(dst, input[i]->Ptr, input[i]->StrideB, local_count); break;
- default: assert(0); break;
- }
- radeon_bo_unmap(vbuf->attribs[index].bo);
-
- }
- }
-
- aos->count = vbuf->attribs[index].stride == 0 ? 1 : count;
- aos->stride = vbuf->attribs[index].stride / sizeof(float);
- aos->components = vbuf->attribs[index].dwords;
- aos->bo = vbuf->attribs[index].bo;
- aos->offset = vbuf->attribs[index].bo_offset;
-
- if (vbuf->attribs[index].is_named_bo) {
- radeon_cs_space_add_persistent_bo(r300->radeon.cmdbuf.cs, r300->vbuf.attribs[index].bo, RADEON_GEM_DOMAIN_GTT, 0);
- }
- }
-
- r300->radeon.tcl.aos_count = vbuf->num_attribs;
- ret = radeon_cs_space_check_with_bo(r300->radeon.cmdbuf.cs, first_elem(&r300->radeon.dma.reserved)->bo, RADEON_GEM_DOMAIN_GTT, 0);
- r300SwitchFallback(ctx, R300_FALLBACK_INVALID_BUFFERS, ret);
-
-}
-
-static void r300FreeData(struct gl_context *ctx)
-{
- /* Need to zero tcl.aos[n].bo and tcl.elt_dma_bo
- * to prevent double unref in radeonReleaseArrays
- * called during context destroy
- */
- radeon_print(RADEON_RENDER, RADEON_VERBOSE, "%s\n", __func__);
- r300ContextPtr r300 = R300_CONTEXT(ctx);
- {
- int i;
-
- for (i = 0; i < r300->vbuf.num_attribs; i++) {
- if (!r300->vbuf.attribs[i].is_named_bo) {
- radeon_bo_unref(r300->vbuf.attribs[i].bo);
- }
- r300->radeon.tcl.aos[i].bo = NULL;
- }
- }
-
- {
- if (r300->ind_buf.bo != NULL) {
- radeon_bo_unref(r300->ind_buf.bo);
- }
- }
-}
-
-static GLuint r300PredictTryDrawPrimsSize(struct gl_context *ctx,
- GLuint nr_prims, const struct _mesa_prim *prim)
-{
- struct r300_context *r300 = R300_CONTEXT(ctx);
- struct r300_vertex_buffer *vbuf = &r300->vbuf;
- GLboolean flushed;
- GLuint dwords;
- GLuint state_size;
- int i;
- GLuint extra_prims = 0;
-
- /* Check for primitive splitting. */
- for (i = 0; i < nr_prims; ++i) {
- const GLuint num_verts = r300NumVerts(r300, prim[i].count, prim[i].mode);
- extra_prims += num_verts/(65535 - 32);
- }
- nr_prims += extra_prims;
-
- dwords = 2*CACHE_FLUSH_BUFSZ;
- dwords += PRE_EMIT_STATE_BUFSZ;
- dwords += (AOS_BUFSZ(vbuf->num_attribs)
- + SCISSORS_BUFSZ*2
- + FIREAOS_BUFSZ )*nr_prims;
-
- state_size = radeonCountStateEmitSize(&r300->radeon);
- flushed = rcommonEnsureCmdBufSpace(&r300->radeon,
- dwords + state_size,
- __FUNCTION__);
- if (flushed)
- dwords += radeonCountStateEmitSize(&r300->radeon);
- else
- dwords += state_size;
-
- radeon_print(RADEON_RENDER, RADEON_VERBOSE, "%s: total prediction size is %d.\n", __FUNCTION__, dwords);
- return dwords;
-}
-
-static GLboolean r300TryDrawPrims(struct gl_context *ctx,
- const struct gl_client_array *arrays[],
- const struct _mesa_prim *prim,
- GLuint nr_prims,
- const struct _mesa_index_buffer *ib,
- GLuint min_index,
- GLuint max_index )
-{
- struct r300_context *r300 = R300_CONTEXT(ctx);
- GLuint i;
-
- radeon_print(RADEON_RENDER, RADEON_NORMAL, "%s: %u (%d-%d) cs begin at %d\n",
- __FUNCTION__, nr_prims, min_index, max_index, r300->radeon.cmdbuf.cs->cdw );
-
- if (ctx->NewState)
- _mesa_update_state( ctx );
-
- if (r300->options.hw_tcl_enabled)
- _tnl_UpdateFixedFunctionProgram(ctx);
-
- r300UpdateShaders(r300);
-
- r300SwitchFallback(ctx, R300_FALLBACK_INVALID_BUFFERS, !r300ValidateBuffers(ctx));
-
- r300SetVertexFormat(ctx, arrays, max_index + 1);
-
- if (r300->fallback)
- return GL_FALSE;
-
- r300SetupVAP(ctx, r300->selected_vp->code.InputsRead, r300->selected_vp->code.OutputsWritten);
-
- r300UpdateShaderStates(r300);
-
- /* ensure we have the cmd buf space in advance to cover
- * the state + DMA AOS pointers */
- GLuint emit_end = r300PredictTryDrawPrimsSize(ctx, nr_prims, prim)
- + r300->radeon.cmdbuf.cs->cdw;
-
- r300SetupIndexBuffer(ctx, ib);
-
- r300AllocDmaRegions(ctx, arrays, max_index + 1);
-
- if (r300->fallback)
- return GL_FALSE;
-
- r300EmitCacheFlush(r300);
- radeonEmitState(&r300->radeon);
-
- for (i = 0; i < nr_prims; ++i) {
- r300RunRenderPrimitive(ctx, prim[i].start, prim[i].start + prim[i].count, prim[i].mode);
- }
-
- r300EmitCacheFlush(r300);
-
- r300FreeData(ctx);
-
- radeon_print(RADEON_RENDER, RADEON_VERBOSE, "%s: %u (%d-%d) cs ending at %d\n",
- __FUNCTION__, nr_prims, min_index, max_index, r300->radeon.cmdbuf.cs->cdw );
-
- if (emit_end < r300->radeon.cmdbuf.cs->cdw)
- WARN_ONCE("Rendering was %d commands larger than predicted size."
- " We might overflow command buffer.\n", r300->radeon.cmdbuf.cs->cdw - emit_end);
-
- return GL_TRUE;
-}
-
-static void r300DrawPrims(struct gl_context *ctx,
- const struct gl_client_array *arrays[],
- const struct _mesa_prim *prim,
- GLuint nr_prims,
- const struct _mesa_index_buffer *ib,
- GLboolean index_bounds_valid,
- GLuint min_index,
- GLuint max_index)
-{
- GLboolean retval;
- struct r300_context *r300 = R300_CONTEXT(ctx);
- radeonContextPtr radeon = &r300->radeon;
-
- radeon_prepare_render(radeon);
-
- /* This check should get folded into just the places that
- * min/max index are really needed.
- */
- if (!index_bounds_valid) {
- vbo_get_minmax_index(ctx, prim, ib, &min_index, &max_index);
- }
-
- if (min_index) {
- radeon_print(RADEON_FALLBACKS, RADEON_IMPORTANT,
- "%s: Rebasing primitives. %p nr_prims %d min_index %u max_index %u\n",
- __func__, prim, nr_prims, min_index, max_index);
- vbo_rebase_prims( ctx, arrays, prim, nr_prims, ib, min_index, max_index, r300DrawPrims );
- return;
- }
-
- /* Make an attempt at drawing */
- retval = r300TryDrawPrims(ctx, arrays, prim, nr_prims, ib, min_index, max_index);
-
- /* If failed run tnl pipeline - it should take care of fallbacks */
- if (!retval)
- _tnl_draw_prims(ctx, arrays, prim, nr_prims, ib, min_index, max_index);
-}
-
-void r300InitDraw(struct gl_context *ctx)
-{
- struct vbo_context *vbo = vbo_context(ctx);
-
- vbo->draw_prims = r300DrawPrims;
-}
+++ /dev/null
-/*
-Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
-
-The Weather Channel (TM) funded Tungsten Graphics to develop the
-initial release of the Radeon 8500 driver under the XFree86 license.
-This notice must be preserved.
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-**************************************************************************/
-
-/**
- * \file
- *
- * \author Keith Whitwell <keith@tungstengraphics.com>
- * \author Maciej Cencora <m.cencora@gmail.com>
- */
-
-#include "main/glheader.h"
-#include "main/mtypes.h"
-#include "main/colormac.h"
-#include "main/imports.h"
-#include "main/macros.h"
-
-#include "swrast_setup/swrast_setup.h"
-#include "tnl/tnl.h"
-#include "tnl/t_context.h"
-
-#include "r300_context.h"
-#include "r300_emit.h"
-
-
-GLuint r300VAPInputCntl0(struct gl_context * ctx, GLuint InputsRead)
-{
- /* No idea what this value means. I have seen other values written to
- * this register... */
- return 0x5555;
-}
-
-GLuint r300VAPInputCntl1(struct gl_context * ctx, GLuint InputsRead)
-{
- GLuint i, vic_1 = 0;
-
- if (InputsRead & (1 << VERT_ATTRIB_POS))
- vic_1 |= R300_INPUT_CNTL_POS;
-
- if (InputsRead & (1 << VERT_ATTRIB_NORMAL))
- vic_1 |= R300_INPUT_CNTL_NORMAL;
-
- if (InputsRead & (1 << VERT_ATTRIB_COLOR0))
- vic_1 |= R300_INPUT_CNTL_COLOR;
-
- for (i = 0; i < ctx->Const.MaxTextureUnits; i++)
- if (InputsRead & (1 << (VERT_ATTRIB_TEX0 + i))) {
- vic_1 |= R300_INPUT_CNTL_TC0 << i;
- }
-
- return vic_1;
-}
-
-GLuint r300VAPOutputCntl0(struct gl_context * ctx, GLuint vp_writes)
-{
- GLuint ret = 0;
-
- if (vp_writes & (1 << VERT_RESULT_HPOS))
- ret |= R300_VAP_OUTPUT_VTX_FMT_0__POS_PRESENT;
-
- if (vp_writes & (1 << VERT_RESULT_COL0))
- ret |= R300_VAP_OUTPUT_VTX_FMT_0__COLOR_0_PRESENT;
-
- if (vp_writes & (1 << VERT_RESULT_COL1))
- ret |= R300_VAP_OUTPUT_VTX_FMT_0__COLOR_1_PRESENT;
-
- /* Two sided lighting works only if all 4 colors are written */
- if (vp_writes & (1 << VERT_RESULT_BFC0) || vp_writes & (1 << VERT_RESULT_BFC1))
- ret |= R300_VAP_OUTPUT_VTX_FMT_0__COLOR_0_PRESENT | R300_VAP_OUTPUT_VTX_FMT_0__COLOR_1_PRESENT |
- R300_VAP_OUTPUT_VTX_FMT_0__COLOR_2_PRESENT | R300_VAP_OUTPUT_VTX_FMT_0__COLOR_3_PRESENT;
-
- if (vp_writes & (1 << VERT_RESULT_PSIZ))
- ret |= R300_VAP_OUTPUT_VTX_FMT_0__PT_SIZE_PRESENT;
-
- return ret;
-}
-
-GLuint r300VAPOutputCntl1(struct gl_context * ctx, GLuint vp_writes)
-{
- GLuint i, ret = 0, first_free_texcoord = 0;
-
- for (i = 0; i < ctx->Const.MaxTextureUnits; i++) {
- if (vp_writes & (1 << (VERT_RESULT_TEX0 + i))) {
- ret |= (4 << (3 * first_free_texcoord));
- ++first_free_texcoord;
- }
- }
-
- if (first_free_texcoord > 8) {
- fprintf(stderr, "\tout of free texcoords\n");
- exit(-1);
- }
-
- return ret;
-}
-
-void r300EmitCacheFlush(r300ContextPtr rmesa)
-{
- BATCH_LOCALS(&rmesa->radeon);
-
- BEGIN_BATCH_NO_AUTOSTATE(4);
- OUT_BATCH_REGVAL(R300_RB3D_DSTCACHE_CTLSTAT,
- R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS |
- R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
- OUT_BATCH_REGVAL(R300_ZB_ZCACHE_CTLSTAT,
- R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE |
- R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE);
- END_BATCH();
- COMMIT_BATCH();
-}
+++ /dev/null
-/*
- * Copyright (C) 2005 Vladimir Dergachev.
- *
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial
- * portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
- * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
- * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
- * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-
-/*
- * Authors:
- * Vladimir Dergachev <volodya@mindspring.com>
- * Nicolai Haehnle <prefect_@gmx.net>
- * Aapo Tahkola <aet@rasterburn.org>
- * Ben Skeggs <darktama@iinet.net.au>
- * Jerome Glisse <j.glisse@gmail.com>
- */
-
-/* This files defines functions for accessing R300 hardware.
- */
-#ifndef __R300_EMIT_H__
-#define __R300_EMIT_H__
-
-#include "main/glheader.h"
-#include "r300_context.h"
-#include "r300_cmdbuf.h"
-
-static INLINE uint32_t cmdpacket0(struct radeon_screen *rscrn,
- int reg, int count)
-{
- if (!rscrn->kernel_mm) {
- drm_r300_cmd_header_t cmd;
-
- cmd.u = 0;
- cmd.packet0.cmd_type = R300_CMD_PACKET0;
- cmd.packet0.count = count;
- cmd.packet0.reghi = ((unsigned int)reg & 0xFF00) >> 8;
- cmd.packet0.reglo = ((unsigned int)reg & 0x00FF);
-
- return cmd.u;
- }
- if (count) {
- return CP_PACKET0(reg, count - 1);
- }
- return CP_PACKET2;
-}
-
-static INLINE uint32_t cmdvpu(struct radeon_screen *rscrn, int addr, int count)
-{
- drm_r300_cmd_header_t cmd;
-
- cmd.u = 0;
- cmd.vpu.cmd_type = R300_CMD_VPU;
- cmd.vpu.count = count;
- cmd.vpu.adrhi = ((unsigned int)addr & 0xFF00) >> 8;
- cmd.vpu.adrlo = ((unsigned int)addr & 0x00FF);
-
- return cmd.u;
-}
-
-static INLINE uint32_t cmdr500fp(struct radeon_screen *rscrn,
- int addr, int count, int type, int clamp)
-{
- drm_r300_cmd_header_t cmd;
-
- cmd.u = 0;
- cmd.r500fp.cmd_type = R300_CMD_R500FP;
- cmd.r500fp.count = count;
- cmd.r500fp.adrhi_flags = ((unsigned int)addr & 0x100) >> 8;
- cmd.r500fp.adrhi_flags |= type ? R500FP_CONSTANT_TYPE : 0;
- cmd.r500fp.adrhi_flags |= clamp ? R500FP_CONSTANT_CLAMP : 0;
- cmd.r500fp.adrlo = ((unsigned int)addr & 0x00FF);
-
- return cmd.u;
-}
-
-static INLINE uint32_t cmdpacket3(struct radeon_screen *rscrn, int packet)
-{
- drm_r300_cmd_header_t cmd;
-
- cmd.u = 0;
- cmd.packet3.cmd_type = R300_CMD_PACKET3;
- cmd.packet3.packet = packet;
-
- return cmd.u;
-}
-
-static INLINE uint32_t cmdcpdelay(struct radeon_screen *rscrn,
- unsigned short count)
-{
- drm_r300_cmd_header_t cmd;
-
- cmd.u = 0;
-
- cmd.delay.cmd_type = R300_CMD_CP_DELAY;
- cmd.delay.count = count;
-
- return cmd.u;
-}
-
-static INLINE uint32_t cmdwait(struct radeon_screen *rscrn,
- unsigned char flags)
-{
- drm_r300_cmd_header_t cmd;
-
- cmd.u = 0;
- cmd.wait.cmd_type = R300_CMD_WAIT;
- cmd.wait.flags = flags;
-
- return cmd.u;
-}
-
-static INLINE uint32_t cmdpacify(struct radeon_screen *rscrn)
-{
- drm_r300_cmd_header_t cmd;
-
- cmd.u = 0;
- cmd.header.cmd_type = R300_CMD_END3D;
-
- return cmd.u;
-}
-
-/**
- * Write the header of a packet3 to the command buffer.
- * Outputs 2 dwords and expects (num_extra+1) additional dwords afterwards.
- */
-#define OUT_BATCH_PACKET3(packet, num_extra) do {\
- if (!b_l_rmesa->radeonScreen->kernel_mm) { \
- OUT_BATCH(cmdpacket3(b_l_rmesa->radeonScreen,\
- R300_CMD_PACKET3_RAW)); \
- } else b_l_rmesa->cmdbuf.cs->section_cdw++;\
- OUT_BATCH(CP_PACKET3((packet), (num_extra))); \
- } while(0)
-
-/**
- * Must be sent to switch to 2d commands
- */
-void static INLINE end_3d(radeonContextPtr radeon)
-{
- BATCH_LOCALS(radeon);
-
- if (!radeon->radeonScreen->kernel_mm) {
- BEGIN_BATCH_NO_AUTOSTATE(1);
- OUT_BATCH(cmdpacify(radeon->radeonScreen));
- END_BATCH();
- }
-}
-
-void static INLINE cp_delay(r300ContextPtr rmesa, unsigned short count)
-{
- BATCH_LOCALS(&rmesa->radeon);
-
- if (!rmesa->radeon.radeonScreen->kernel_mm) {
- BEGIN_BATCH_NO_AUTOSTATE(1);
- OUT_BATCH(cmdcpdelay(rmesa->radeon.radeonScreen, count));
- END_BATCH();
- }
-}
-
-void static INLINE cp_wait(radeonContextPtr radeon, unsigned char flags)
-{
- BATCH_LOCALS(radeon);
- uint32_t wait_until;
-
- if (!radeon->radeonScreen->kernel_mm) {
- BEGIN_BATCH_NO_AUTOSTATE(1);
- OUT_BATCH(cmdwait(radeon->radeonScreen, flags));
- END_BATCH();
- } else {
- switch(flags) {
- case R300_WAIT_2D:
- wait_until = (1 << 14);
- break;
- case R300_WAIT_3D:
- wait_until = (1 << 15);
- break;
- case R300_NEW_WAIT_2D_3D:
- wait_until = (1 << 14) | (1 << 15);
- break;
- case R300_NEW_WAIT_2D_2D_CLEAN:
- wait_until = (1 << 14) | (1 << 16) | (1 << 18);
- break;
- case R300_NEW_WAIT_3D_3D_CLEAN:
- wait_until = (1 << 15) | (1 << 17) | (1 << 18);
- break;
- case R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN:
- wait_until = (1 << 14) | (1 << 16) | (1 << 18);
- wait_until |= (1 << 15) | (1 << 17) | (1 << 18);
- break;
- default:
- return;
- }
- BEGIN_BATCH_NO_AUTOSTATE(2);
- OUT_BATCH(CP_PACKET0(RADEON_WAIT_UNTIL, 0));
- OUT_BATCH(wait_until);
- END_BATCH();
- }
-}
-
-extern int r300PrimitiveType(r300ContextPtr rmesa, int prim);
-extern int r300NumVerts(r300ContextPtr rmesa, int num_verts, int prim);
-
-extern void r300EmitCacheFlush(r300ContextPtr rmesa);
-
-extern GLuint r300VAPInputCntl0(struct gl_context * ctx, GLuint InputsRead);
-extern GLuint r300VAPInputCntl1(struct gl_context * ctx, GLuint InputsRead);
-extern GLuint r300VAPOutputCntl0(struct gl_context * ctx, GLuint vp_writes);
-extern GLuint r300VAPOutputCntl1(struct gl_context * ctx, GLuint vp_writes);
-
-#endif
+++ /dev/null
-/*
- * Copyright (C) 2009 Maciej Cencora <m.cencora@gmail.com>
- *
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial
- * portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
- * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
- * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
- * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-
-/**
- * \file
- *
- * Fragment program compiler. Perform transformations on the intermediate
- * representation until the program is in a form where we can translate
- * it more or less directly into machine-readable form.
- *
- * \author Ben Skeggs <darktama@iinet.net.au>
- * \author Jerome Glisse <j.glisse@gmail.com>
- */
-
-#include "r300_fragprog_common.h"
-
-#include "program/prog_print.h"
-
-#include "compiler/radeon_compiler.h"
-
-#include "radeon_mesa_to_rc.h"
-
-
-static GLuint build_dts(GLuint depthmode)
-{
- switch(depthmode) {
- default:
- case GL_LUMINANCE: return RC_SWIZZLE_XYZZ;
- case GL_INTENSITY: return RC_SWIZZLE_XYZW;
- case GL_ALPHA: return RC_SWIZZLE_WWWW;
- }
-}
-
-static GLuint build_func(GLuint comparefunc)
-{
- return comparefunc - GL_NEVER;
-}
-
-/**
- * Collect all external state that is relevant for compiling the given
- * fragment program.
- */
-static void build_state(
- r300ContextPtr r300,
- struct gl_fragment_program *fp,
- struct r300_fragment_program_external_state *state)
-{
- int unit;
-
- memset(state, 0, sizeof(*state));
-
- for(unit = 0; unit < 16; ++unit) {
- if (fp->Base.ShadowSamplers & (1 << unit)) {
- struct gl_texture_object* tex = r300->radeon.glCtx->Texture.Unit[unit]._Current;
-
- state->unit[unit].texture_swizzle = build_dts(tex->Sampler.DepthMode);
- state->unit[unit].texture_compare_func = build_func(tex->Sampler.CompareFunc);
- }
- }
-}
-
-
-/**
- * Transform the program to support fragment.position.
- *
- * Introduce a small fragment at the start of the program that will be
- * the only code that directly reads the FRAG_ATTRIB_WPOS input.
- * All other code pieces that reference that input will be rewritten
- * to read from a newly allocated temporary.
- *
- */
-static void insert_WPOS_trailer(struct r300_fragment_program_compiler *compiler, struct r300_fragment_program * fp)
-{
- int i;
-
- fp->wpos_attr = FRAG_ATTRIB_MAX;
- if (!(compiler->Base.Program.InputsRead & FRAG_BIT_WPOS)) {
- return;
- }
-
- for (i = FRAG_ATTRIB_TEX0; i <= FRAG_ATTRIB_TEX7; ++i)
- {
- if (!(compiler->Base.Program.InputsRead & (1 << i))) {
- fp->wpos_attr = i;
- break;
- }
- }
-
- /* No free texcoord found, fall-back to software rendering */
- if (fp->wpos_attr == FRAG_ATTRIB_MAX)
- {
- compiler->Base.Error = 1;
- return;
- }
-
- rc_transform_fragment_wpos(&compiler->Base, FRAG_ATTRIB_WPOS, fp->wpos_attr, GL_FALSE);
-}
-
-/**
- * Rewrite fragment.fogcoord to use a texture coordinate slot.
- * Note that fogcoord is forced into an X001 pattern, and this enforcement
- * is done here.
- *
- * See also the counterpart rewriting for vertex programs.
- */
-static void rewriteFog(struct r300_fragment_program_compiler *compiler, struct r300_fragment_program * fp)
-{
- struct rc_src_register src;
- int i;
-
- fp->fog_attr = FRAG_ATTRIB_MAX;
- if (!(compiler->Base.Program.InputsRead & FRAG_BIT_FOGC)) {
- return;
- }
-
- for (i = FRAG_ATTRIB_TEX0; i <= FRAG_ATTRIB_TEX7; ++i)
- {
- if (!(compiler->Base.Program.InputsRead & (1 << i))) {
- fp->fog_attr = i;
- break;
- }
- }
-
- /* No free texcoord found, fall-back to software rendering */
- if (fp->fog_attr == FRAG_ATTRIB_MAX)
- {
- compiler->Base.Error = 1;
- return;
- }
-
- memset(&src, 0, sizeof(src));
- src.File = RC_FILE_INPUT;
- src.Index = fp->fog_attr;
- src.Swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_ZERO, SWIZZLE_ZERO, SWIZZLE_ONE);
- rc_move_input(&compiler->Base, FRAG_ATTRIB_FOGC, src);
-}
-
-
-/**
- * Reserve hardware temporary registers for the program inputs.
- *
- * @note This allocation is performed explicitly, because the order of inputs
- * is determined by the RS hardware.
- */
-static void allocate_hw_inputs(
- struct r300_fragment_program_compiler * c,
- void (*allocate)(void * data, unsigned input, unsigned hwreg),
- void * mydata)
-{
- GLuint InputsRead = c->Base.Program.InputsRead;
- int i;
- GLuint hwindex = 0;
-
- /* Primary colour */
- if (InputsRead & FRAG_BIT_COL0)
- allocate(mydata, FRAG_ATTRIB_COL0, hwindex++);
- InputsRead &= ~FRAG_BIT_COL0;
-
- /* Secondary color */
- if (InputsRead & FRAG_BIT_COL1)
- allocate(mydata, FRAG_ATTRIB_COL1, hwindex++);
- InputsRead &= ~FRAG_BIT_COL1;
-
- /* Texcoords */
- for (i = 0; i < 8; i++) {
- if (InputsRead & (FRAG_BIT_TEX0 << i))
- allocate(mydata, FRAG_ATTRIB_TEX0+i, hwindex++);
- }
- InputsRead &= ~FRAG_BITS_TEX_ANY;
-
- /* Fogcoords treated as a texcoord */
- if (InputsRead & FRAG_BIT_FOGC)
- allocate(mydata, FRAG_ATTRIB_FOGC, hwindex++);
- InputsRead &= ~FRAG_BIT_FOGC;
-
- /* fragment position treated as a texcoord */
- if (InputsRead & FRAG_BIT_WPOS)
- allocate(mydata, FRAG_ATTRIB_WPOS, hwindex++);
- InputsRead &= ~FRAG_BIT_WPOS;
-
- /* Anything else */
- if (InputsRead)
- rc_error(&c->Base, "Don't know how to handle inputs 0x%x\n", InputsRead);
-}
-
-
-static void translate_fragment_program(struct gl_context *ctx, struct r300_fragment_program_cont *cont, struct r300_fragment_program *fp)
-{
- r300ContextPtr r300 = R300_CONTEXT(ctx);
- struct r300_fragment_program_compiler compiler;
-
- memset(&compiler, 0, sizeof(compiler));
- rc_init(&compiler.Base);
- compiler.Base.Debug = (RADEON_DEBUG & RADEON_PIXEL) ? GL_TRUE : GL_FALSE;
-
- compiler.code = &fp->code;
- compiler.state = fp->state;
- compiler.enable_shadow_ambient = GL_TRUE;
- compiler.Base.is_r500 = (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) ? GL_TRUE : GL_FALSE;
- compiler.Base.disable_optimizations = 0;
- compiler.Base.has_half_swizzles = 1;
- compiler.Base.max_temp_regs = (compiler.Base.is_r500) ? 128 : 32;
- compiler.Base.max_constants = compiler.Base.is_r500 ? 256 : 32;
- compiler.Base.max_alu_insts = compiler.Base.is_r500 ? 512 : 64;
- compiler.Base.max_tex_insts = compiler.Base.is_r500 ? 512 : 32;
- compiler.OutputDepth = FRAG_RESULT_DEPTH;
- memset(compiler.OutputColor, 0, 4 * sizeof(unsigned));
- compiler.OutputColor[0] = FRAG_RESULT_COLOR;
- compiler.AllocateHwInputs = &allocate_hw_inputs;
-
- if (compiler.Base.Debug) {
- fflush(stderr);
- printf("Fragment Program: Initial program:\n");
- _mesa_print_program(&cont->Base.Base);
- fflush(stderr);
- }
-
- radeon_mesa_to_rc_program(&compiler.Base, &cont->Base.Base);
-
- insert_WPOS_trailer(&compiler, fp);
-
- rewriteFog(&compiler, fp);
-
- r3xx_compile_fragment_program(&compiler);
-
- if (compiler.Base.is_r500) {
- /* We need to support the non-KMS DRM interface, which
- * artificially limits the number of instructions and
- * constants which are available to us.
- *
- * See also the comment in r300_context.c where we
- * set the MAX_NATIVE_xxx values.
- */
- if (fp->code.code.r500.inst_end >= 255 || fp->code.constants.Count > 255)
- rc_error(&compiler.Base, "Program is too big (upgrade to r300g to avoid this limitation).\n");
- }
-
- fp->error = compiler.Base.Error;
-
- fp->InputsRead = compiler.Base.Program.InputsRead;
-
- /* Clear the fog/wpos_attr if code accessing these
- * attributes has been removed during compilation
- */
- if (fp->fog_attr != FRAG_ATTRIB_MAX) {
- if (!(fp->InputsRead & (1 << fp->fog_attr)))
- fp->fog_attr = FRAG_ATTRIB_MAX;
- }
-
- if (fp->wpos_attr != FRAG_ATTRIB_MAX) {
- if (!(fp->InputsRead & (1 << fp->wpos_attr)))
- fp->wpos_attr = FRAG_ATTRIB_MAX;
- }
-
- rc_destroy(&compiler.Base);
-}
-
-struct r300_fragment_program *r300SelectAndTranslateFragmentShader(struct gl_context *ctx)
-{
- r300ContextPtr r300 = R300_CONTEXT(ctx);
- struct r300_fragment_program_cont *fp_list;
- struct r300_fragment_program *fp;
- struct r300_fragment_program_external_state state;
-
- fp_list = (struct r300_fragment_program_cont *)ctx->FragmentProgram._Current;
- build_state(r300, ctx->FragmentProgram._Current, &state);
-
- fp = fp_list->progs;
- while (fp) {
- if (memcmp(&fp->state, &state, sizeof(state)) == 0) {
- return r300->selected_fp = fp;
- }
- fp = fp->next;
- }
-
- fp = calloc(1, sizeof(struct r300_fragment_program));
-
- fp->state = state;
-
- fp->next = fp_list->progs;
- fp_list->progs = fp;
-
- translate_fragment_program(ctx, fp_list, fp);
-
- return r300->selected_fp = fp;
-}
+++ /dev/null
-/*
- * Copyright (C) 2009 Maciej Cencora <m.cencora@gmail.com>
- *
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial
- * portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
- * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
- * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
- * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-
-#ifndef __R300_FRAGPROG_COMMON_H_
-#define __R300_FRAGPROG_COMMON_H_
-
-#include "main/mtypes.h"
-
-#include "r300_context.h"
-
-struct r300_fragment_program *r300SelectAndTranslateFragmentShader(struct gl_context *ctx);
-
-#endif
+++ /dev/null
-/**************************************************************************
-
-Copyright (C) 2004-2005 Nicolai Haehnle et al.
-
-Permission is hereby granted, free of charge, to any person obtaining a
-copy of this software and associated documentation files (the "Software"),
-to deal in the Software without restriction, including without limitation
-on the rights to use, copy, modify, merge, publish, distribute, sub
-license, and/or sell copies of the Software, and to permit persons to whom
-the Software is furnished to do so, subject to the following conditions:
-
-The above copyright notice and this permission notice (including the next
-paragraph) shall be included in all copies or substantial portions of the
-Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
-THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
-DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
-USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-**************************************************************************/
-
-/* *INDENT-OFF* */
-
-#ifndef _R300_REG_H
-#define _R300_REG_H
-
-#define R300_MC_INIT_MISC_LAT_TIMER 0x180
-# define R300_MC_MISC__MC_CPR_INIT_LAT_SHIFT 0
-# define R300_MC_MISC__MC_VF_INIT_LAT_SHIFT 4
-# define R300_MC_MISC__MC_DISP0R_INIT_LAT_SHIFT 8
-# define R300_MC_MISC__MC_DISP1R_INIT_LAT_SHIFT 12
-# define R300_MC_MISC__MC_FIXED_INIT_LAT_SHIFT 16
-# define R300_MC_MISC__MC_E2R_INIT_LAT_SHIFT 20
-# define R300_MC_MISC__MC_SAME_PAGE_PRIO_SHIFT 24
-# define R300_MC_MISC__MC_GLOBW_INIT_LAT_SHIFT 28
-
-
-#define R300_MC_INIT_GFX_LAT_TIMER 0x154
-# define R300_MC_MISC__MC_G3D0R_INIT_LAT_SHIFT 0
-# define R300_MC_MISC__MC_G3D1R_INIT_LAT_SHIFT 4
-# define R300_MC_MISC__MC_G3D2R_INIT_LAT_SHIFT 8
-# define R300_MC_MISC__MC_G3D3R_INIT_LAT_SHIFT 12
-# define R300_MC_MISC__MC_TX0R_INIT_LAT_SHIFT 16
-# define R300_MC_MISC__MC_TX1R_INIT_LAT_SHIFT 20
-# define R300_MC_MISC__MC_GLOBR_INIT_LAT_SHIFT 24
-# define R300_MC_MISC__MC_GLOBW_FULL_LAT_SHIFT 28
-
-/*
- * This file contains registers and constants for the R300. They have been
- * found mostly by examining command buffers captured using glxtest, as well
- * as by extrapolating some known registers and constants from the R200.
- * I am fairly certain that they are correct unless stated otherwise
- * in comments.
- */
-
-#define R300_SE_VPORT_XSCALE 0x1D98
-#define R300_SE_VPORT_XOFFSET 0x1D9C
-#define R300_SE_VPORT_YSCALE 0x1DA0
-#define R300_SE_VPORT_YOFFSET 0x1DA4
-#define R300_SE_VPORT_ZSCALE 0x1DA8
-#define R300_SE_VPORT_ZOFFSET 0x1DAC
-
-#define R300_VAP_PORT_IDX0 0x2040
-/*
- * Vertex Array Processing (VAP) Control
- */
-#define R300_VAP_CNTL 0x2080
-# define R300_PVS_NUM_SLOTS_SHIFT 0
-# define R300_PVS_NUM_CNTLRS_SHIFT 4
-# define R300_PVS_NUM_FPUS_SHIFT 8
-# define R300_VF_MAX_VTX_NUM_SHIFT 18
-# define R300_GL_CLIP_SPACE_DEF (0 << 22)
-# define R300_DX_CLIP_SPACE_DEF (1 << 22)
-# define R500_TCL_STATE_OPTIMIZATION (1 << 23)
-
-/* This register is written directly and also starts data section
- * in many 3d CP_PACKET3's
- */
-#define R300_VAP_VF_CNTL 0x2084
-# define R300_VAP_VF_CNTL__PRIM_TYPE__SHIFT 0
-# define R300_VAP_VF_CNTL__PRIM_NONE (0<<0)
-# define R300_VAP_VF_CNTL__PRIM_POINTS (1<<0)
-# define R300_VAP_VF_CNTL__PRIM_LINES (2<<0)
-# define R300_VAP_VF_CNTL__PRIM_LINE_STRIP (3<<0)
-# define R300_VAP_VF_CNTL__PRIM_TRIANGLES (4<<0)
-# define R300_VAP_VF_CNTL__PRIM_TRIANGLE_FAN (5<<0)
-# define R300_VAP_VF_CNTL__PRIM_TRIANGLE_STRIP (6<<0)
-# define R300_VAP_VF_CNTL__PRIM_LINE_LOOP (12<<0)
-# define R300_VAP_VF_CNTL__PRIM_QUADS (13<<0)
-# define R300_VAP_VF_CNTL__PRIM_QUAD_STRIP (14<<0)
-# define R300_VAP_VF_CNTL__PRIM_POLYGON (15<<0)
-
-# define R300_VAP_VF_CNTL__PRIM_WALK__SHIFT 4
- /* State based - direct writes to registers trigger vertex
- generation */
-# define R300_VAP_VF_CNTL__PRIM_WALK_STATE_BASED (0<<4)
-# define R300_VAP_VF_CNTL__PRIM_WALK_INDICES (1<<4)
-# define R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_LIST (2<<4)
-# define R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_EMBEDDED (3<<4)
-
- /* I don't think I saw these three used.. */
-# define R300_VAP_VF_CNTL__COLOR_ORDER__SHIFT 6
-# define R300_VAP_VF_CNTL__TCL_OUTPUT_CTL_ENA__SHIFT 9
-# define R300_VAP_VF_CNTL__PROG_STREAM_ENA__SHIFT 10
-
- /* index size - when not set the indices are assumed to be 16 bit */
-# define R300_VAP_VF_CNTL__INDEX_SIZE_32bit (1<<11)
- /* number of vertices */
-# define R300_VAP_VF_CNTL__NUM_VERTICES__SHIFT 16
-
-#define R500_VAP_INDEX_OFFSET 0x208c
-
-#define R300_VAP_OUTPUT_VTX_FMT_0 0x2090
-# define R300_VAP_OUTPUT_VTX_FMT_0__POS_PRESENT (1<<0)
-# define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_0_PRESENT (1<<1)
-# define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_1_PRESENT (1<<2)
-# define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_2_PRESENT (1<<3)
-# define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_3_PRESENT (1<<4)
-# define R300_VAP_OUTPUT_VTX_FMT_0__PT_SIZE_PRESENT (1<<16)
-
-#define R300_VAP_OUTPUT_VTX_FMT_1 0x2094
- /* each of the following is 3 bits wide, specifies number
- of components */
-# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_0_COMP_CNT_SHIFT 0
-# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_1_COMP_CNT_SHIFT 3
-# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_2_COMP_CNT_SHIFT 6
-# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_3_COMP_CNT_SHIFT 9
-# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_4_COMP_CNT_SHIFT 12
-# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_5_COMP_CNT_SHIFT 15
-# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_6_COMP_CNT_SHIFT 18
-# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_7_COMP_CNT_SHIFT 21
-# define R300_VAP_OUTPUT_VTX_FMT_1__NOT_PRESENT 0
-# define R300_VAP_OUTPUT_VTX_FMT_1__1_COMPONENT 1
-# define R300_VAP_OUTPUT_VTX_FMT_1__2_COMPONENTS 2
-# define R300_VAP_OUTPUT_VTX_FMT_1__3_COMPONENTS 3
-# define R300_VAP_OUTPUT_VTX_FMT_1__4_COMPONENTS 4
-
-#define R300_SE_VTE_CNTL 0x20b0
-# define R300_VPORT_X_SCALE_ENA (1 << 0)
-# define R300_VPORT_X_OFFSET_ENA (1 << 1)
-# define R300_VPORT_Y_SCALE_ENA (1 << 2)
-# define R300_VPORT_Y_OFFSET_ENA (1 << 3)
-# define R300_VPORT_Z_SCALE_ENA (1 << 4)
-# define R300_VPORT_Z_OFFSET_ENA (1 << 5)
-# define R300_VTX_XY_FMT (1 << 8)
-# define R300_VTX_Z_FMT (1 << 9)
-# define R300_VTX_W0_FMT (1 << 10)
-# define R300_SERIAL_PROC_ENA (1 << 11)
-
-/* BEGIN: Vertex data assembly - lots of uncertainties */
-
-/* gap */
-
-/* Maximum Vertex Indx Clamp */
-#define R300_VAP_VF_MAX_VTX_INDX 0x2134
-/* Minimum Vertex Indx Clamp */
-#define R300_VAP_VF_MIN_VTX_INDX 0x2138
-
-/** Vertex assembler/processor control status */
-#define R300_VAP_CNTL_STATUS 0x2140
-/* No swap at all (default) */
-# define R300_VC_NO_SWAP (0 << 0)
-/* 16-bit swap: 0xAABBCCDD becomes 0xBBAADDCC */
-# define R300_VC_16BIT_SWAP (1 << 0)
-/* 32-bit swap: 0xAABBCCDD becomes 0xDDCCBBAA */
-# define R300_VC_32BIT_SWAP (2 << 0)
-/* Half-dword swap: 0xAABBCCDD becomes 0xCCDDAABB */
-# define R300_VC_HALF_DWORD_SWAP (3 << 0)
-/* The TCL engine will not be used (as it is logically or even physically removed) */
-# define R300_VAP_TCL_BYPASS (1 << 8)
-/* Read only flag if TCL engine is busy. */
-# define R300_VAP_PVS_BUSY (1 << 11)
-/* TODO: gap for MAX_MPS */
-/* Read only flag if the vertex store is busy. */
-# define R300_VAP_VS_BUSY (1 << 24)
-/* Read only flag if the reciprocal engine is busy. */
-# define R300_VAP_RCP_BUSY (1 << 25)
-/* Read only flag if the viewport transform engine is busy. */
-# define R300_VAP_VTE_BUSY (1 << 26)
-/* Read only flag if the memory interface unit is busy. */
-# define R300_VAP_MUI_BUSY (1 << 27)
-/* Read only flag if the vertex cache is busy. */
-# define R300_VAP_VC_BUSY (1 << 28)
-/* Read only flag if the vertex fetcher is busy. */
-# define R300_VAP_VF_BUSY (1 << 29)
-/* Read only flag if the register pipeline is busy. */
-# define R300_VAP_REGPIPE_BUSY (1 << 30)
-/* Read only flag if the VAP engine is busy. */
-# define R300_VAP_VAP_BUSY (1 << 31)
-
-/* gap */
-
-/* Where do we get our vertex data?
- *
- * Vertex data either comes either from immediate mode registers or from
- * vertex arrays.
- * There appears to be no mixed mode (though we can force the pitch of
- * vertex arrays to 0, effectively reusing the same element over and over
- * again).
- *
- * Immediate mode is controlled by the INPUT_CNTL registers. I am not sure
- * if these registers influence vertex array processing.
- *
- * Vertex arrays are controlled via the 3D_LOAD_VBPNTR packet3.
- *
- * In both cases, vertex attributes are then passed through INPUT_ROUTE.
- *
- * Beginning with INPUT_ROUTE_0_0 is a list of WORDs that route vertex data
- * into the vertex processor's input registers.
- * The first word routes the first input, the second word the second, etc.
- * The corresponding input is routed into the register with the given index.
- * The list is ended by a word with INPUT_ROUTE_END set.
- *
- * Always set COMPONENTS_4 in immediate mode.
- */
-
-#define R300_VAP_PROG_STREAM_CNTL_0 0x2150
-# define R300_DATA_TYPE_0_SHIFT 0
-# define R300_DATA_TYPE_FLOAT_1 0
-# define R300_DATA_TYPE_FLOAT_2 1
-# define R300_DATA_TYPE_FLOAT_3 2
-# define R300_DATA_TYPE_FLOAT_4 3
-# define R300_DATA_TYPE_BYTE 4
-# define R300_DATA_TYPE_D3DCOLOR 5
-# define R300_DATA_TYPE_SHORT_2 6
-# define R300_DATA_TYPE_SHORT_4 7
-# define R300_DATA_TYPE_VECTOR_3_TTT 8
-# define R300_DATA_TYPE_VECTOR_3_EET 9
-# define R300_DATA_TYPE_FLT16_2 11
-# define R300_DATA_TYPE_FLT16_4 12
-
-# define R300_SKIP_DWORDS_SHIFT 4
-# define R300_DST_VEC_LOC_SHIFT 8
-# define R300_LAST_VEC (1 << 13)
-# define R300_SIGNED (1 << 14)
-# define R300_NORMALIZE (1 << 15)
-# define R300_DATA_TYPE_1_SHIFT 16
-#define R300_VAP_PROG_STREAM_CNTL_1 0x2154
-#define R300_VAP_PROG_STREAM_CNTL_2 0x2158
-#define R300_VAP_PROG_STREAM_CNTL_3 0x215C
-#define R300_VAP_PROG_STREAM_CNTL_4 0x2160
-#define R300_VAP_PROG_STREAM_CNTL_5 0x2164
-#define R300_VAP_PROG_STREAM_CNTL_6 0x2168
-#define R300_VAP_PROG_STREAM_CNTL_7 0x216C
-/* gap */
-
-/* Notes:
- * - always set up to produce at least two attributes:
- * if vertex program uses only position, fglrx will set normal, too
- * - INPUT_CNTL_0_COLOR and INPUT_CNTL_COLOR bits are always equal.
- */
-#define R300_VAP_VTX_STATE_CNTL 0x2180
-# define R300_COLOR_0_ASSEMBLY_SHIFT 0
-# define R300_SEL_COLOR 0
-# define R300_SEL_USER_COLOR_0 1
-# define R300_SEL_USER_COLOR_1 2
-# define R300_COLOR_1_ASSEMBLY_SHIFT 2
-# define R300_COLOR_2_ASSEMBLY_SHIFT 4
-# define R300_COLOR_3_ASSEMBLY_SHIFT 6
-# define R300_COLOR_4_ASSEMBLY_SHIFT 8
-# define R300_COLOR_5_ASSEMBLY_SHIFT 10
-# define R300_COLOR_6_ASSEMBLY_SHIFT 12
-# define R300_COLOR_7_ASSEMBLY_SHIFT 14
-# define R300_UPDATE_USER_COLOR_0_ENA (1 << 16)
-
-/*
- * Each bit in this field applies to the corresponding vector in the VSM
- * memory (i.e. Bit 0 applies to VECTOR_0 (POSITION), etc.). If the bit
- * is set, then the corresponding 4-Dword Vector is output into the Vertex Stream.
- */
-#define R300_VAP_VSM_VTX_ASSM 0x2184
-# define R300_INPUT_CNTL_POS 0x00000001
-# define R300_INPUT_CNTL_NORMAL 0x00000002
-# define R300_INPUT_CNTL_COLOR 0x00000004
-# define R300_INPUT_CNTL_TC0 0x00000400
-# define R300_INPUT_CNTL_TC1 0x00000800
-# define R300_INPUT_CNTL_TC2 0x00001000 /* GUESS */
-# define R300_INPUT_CNTL_TC3 0x00002000 /* GUESS */
-# define R300_INPUT_CNTL_TC4 0x00004000 /* GUESS */
-# define R300_INPUT_CNTL_TC5 0x00008000 /* GUESS */
-# define R300_INPUT_CNTL_TC6 0x00010000 /* GUESS */
-# define R300_INPUT_CNTL_TC7 0x00020000 /* GUESS */
-
-/* Programmable Stream Control Signed Normalize Control */
-#define R300_VAP_PSC_SGN_NORM_CNTL 0x21dc
-# define SGN_NORM_ZERO 0
-# define SGN_NORM_ZERO_CLAMP_MINUS_ONE 1
-# define SGN_NORM_NO_ZERO 2
-
-/* gap */
-
-/* Words parallel to INPUT_ROUTE_0; All words that are active in INPUT_ROUTE_0
- * are set to a swizzling bit pattern, other words are 0.
- *
- * In immediate mode, the pattern is always set to xyzw. In vertex array
- * mode, the swizzling pattern is e.g. used to set zw components in texture
- * coordinates with only tweo components.
- */
-#define R300_VAP_PROG_STREAM_CNTL_EXT_0 0x21e0
-# define R300_SWIZZLE0_SHIFT 0
-# define R300_SWIZZLE_SELECT_X_SHIFT 0
-# define R300_SWIZZLE_SELECT_Y_SHIFT 3
-# define R300_SWIZZLE_SELECT_Z_SHIFT 6
-# define R300_SWIZZLE_SELECT_W_SHIFT 9
-
-# define R300_SWIZZLE_SELECT_X 0
-# define R300_SWIZZLE_SELECT_Y 1
-# define R300_SWIZZLE_SELECT_Z 2
-# define R300_SWIZZLE_SELECT_W 3
-# define R300_SWIZZLE_SELECT_FP_ZERO 4
-# define R300_SWIZZLE_SELECT_FP_ONE 5
-/* alternate forms for r300_emit.c */
-# define R300_INPUT_ROUTE_SELECT_X 0
-# define R300_INPUT_ROUTE_SELECT_Y 1
-# define R300_INPUT_ROUTE_SELECT_Z 2
-# define R300_INPUT_ROUTE_SELECT_W 3
-# define R300_INPUT_ROUTE_SELECT_ZERO 4
-# define R300_INPUT_ROUTE_SELECT_ONE 5
-
-# define R300_WRITE_ENA_SHIFT 12
-# define R300_WRITE_ENA_X 1
-# define R300_WRITE_ENA_Y 2
-# define R300_WRITE_ENA_Z 4
-# define R300_WRITE_ENA_W 8
-# define R300_SWIZZLE1_SHIFT 16
-#define R300_VAP_PROG_STREAM_CNTL_EXT_1 0x21e4
-#define R300_VAP_PROG_STREAM_CNTL_EXT_2 0x21e8
-#define R300_VAP_PROG_STREAM_CNTL_EXT_3 0x21ec
-#define R300_VAP_PROG_STREAM_CNTL_EXT_4 0x21f0
-#define R300_VAP_PROG_STREAM_CNTL_EXT_5 0x21f4
-#define R300_VAP_PROG_STREAM_CNTL_EXT_6 0x21f8
-#define R300_VAP_PROG_STREAM_CNTL_EXT_7 0x21fc
-
-/* END: Vertex data assembly */
-
-/* gap */
-
-/* BEGIN: Upload vertex program and data */
-
-/*
- * The programmable vertex shader unit has a memory bank of unknown size
- * that can be written to in 16 byte units by writing the address into
- * UPLOAD_ADDRESS, followed by data in UPLOAD_DATA (multiples of 4 DWORDs).
- *
- * Pointers into the memory bank are always in multiples of 16 bytes.
- *
- * The memory bank is divided into areas with fixed meaning.
- *
- * Starting at address UPLOAD_PROGRAM: Vertex program instructions.
- * Native limits reported by drivers from ATI suggest size 256 (i.e. 4KB),
- * whereas the difference between known addresses suggests size 512.
- *
- * Starting at address UPLOAD_PARAMETERS: Vertex program parameters.
- * Native reported limits and the VPI layout suggest size 256, whereas
- * difference between known addresses suggests size 512.
- *
- * At address UPLOAD_POINTSIZE is a vector (0, 0, ps, 0), where ps is the
- * floating point pointsize. The exact purpose of this state is uncertain,
- * as there is also the R300_RE_POINTSIZE register.
- *
- * Multiple vertex programs and parameter sets can be loaded at once,
- * which could explain the size discrepancy.
- */
-#define R300_VAP_PVS_VECTOR_INDX_REG 0x2200
-# define R300_PVS_CODE_START 0
-# define R300_MAX_PVS_CODE_LINES 256
-# define R500_MAX_PVS_CODE_LINES 1024
-# define R300_PVS_CONST_START 512
-# define R500_PVS_CONST_START 1024
-# define R300_MAX_PVS_CONST_VECS 256
-# define R500_MAX_PVS_CONST_VECS 1024
-# define R300_PVS_UCP_START 1024
-# define R500_PVS_UCP_START 1536
-# define R300_POINT_VPORT_SCALE_OFFSET 1030
-# define R500_POINT_VPORT_SCALE_OFFSET 1542
-# define R300_POINT_GEN_TEX_OFFSET 1031
-# define R500_POINT_GEN_TEX_OFFSET 1543
-
-/*
- * These are obsolete defines form r300_context.h, but they might give some
- * clues when investigating the addresses further...
- */
-#if 0
-#define VSF_DEST_PROGRAM 0x0
-#define VSF_DEST_MATRIX0 0x200
-#define VSF_DEST_MATRIX1 0x204
-#define VSF_DEST_MATRIX2 0x208
-#define VSF_DEST_VECTOR0 0x20c
-#define VSF_DEST_VECTOR1 0x20d
-#define VSF_DEST_UNKNOWN1 0x400
-#define VSF_DEST_UNKNOWN2 0x406
-#endif
-
-/* gap */
-
-#define R300_VAP_PVS_UPLOAD_DATA 0x2208
-
-/* END: Upload vertex program and data */
-
-/* gap */
-
-/* I do not know the purpose of this register. However, I do know that
- * it is set to 221C_CLEAR for clear operations and to 221C_NORMAL
- * for normal rendering.
- *
- * 2007-11-05: This register is the user clip plane control register, but there
- * also seems to be a rendering mode control; the NORMAL/CLEAR defines.
- *
- * See bug #9871. http://bugs.freedesktop.org/attachment.cgi?id=10672&action=view
- */
-#define R300_VAP_CLIP_CNTL 0x221C
-# define R300_VAP_UCP_ENABLE_0 (1 << 0)
-# define R300_VAP_UCP_ENABLE_1 (1 << 1)
-# define R300_VAP_UCP_ENABLE_2 (1 << 2)
-# define R300_VAP_UCP_ENABLE_3 (1 << 3)
-# define R300_VAP_UCP_ENABLE_4 (1 << 4)
-# define R300_VAP_UCP_ENABLE_5 (1 << 5)
-# define R300_PS_UCP_MODE_DIST_COP (0 << 14)
-# define R300_PS_UCP_MODE_RADIUS_COP (1 << 14)
-# define R300_PS_UCP_MODE_RADIUS_COP_CLIP (2 << 14)
-# define R300_PS_UCP_MODE_CLIP_AS_TRIFAN (3 << 14)
-# define R300_CLIP_DISABLE (1 << 16)
-# define R300_UCP_CULL_ONLY_ENABLE (1 << 17)
-# define R300_BOUNDARY_EDGE_FLAG_ENABLE (1 << 18)
-# define R500_COLOR2_IS_TEXTURE (1 << 20)
-# define R500_COLOR3_IS_TEXTURE (1 << 21)
-
-/* These seem to be per-pixel and per-vertex X and Y clipping planes. The first
- * plane is per-pixel and the second plane is per-vertex.
- *
- * This was determined by experimentation alone but I believe it is correct.
- *
- * These registers are called X_QUAD0_1_FL to X_QUAD0_4_FL by glxtest.
- */
-#define R300_VAP_GB_VERT_CLIP_ADJ 0x2220
-#define R300_VAP_GB_VERT_DISC_ADJ 0x2224
-#define R300_VAP_GB_HORZ_CLIP_ADJ 0x2228
-#define R300_VAP_GB_HORZ_DISC_ADJ 0x222c
-
-#define R300_VAP_PVS_FLOW_CNTL_ADDRS_0 0x2230
-#define R300_PVS_FC_ACT_ADRS(x) ((x) << 0)
-#define R300_PVS_FC_LOOP_CNT_JMP_INST(x) ((x) << 8)
-#define R300_PVS_FC_LAST_INST(x) ((x) << 16)
-#define R300_PVS_FC_RTN_INST(x) ((x) << 24)
-
-/* gap */
-
-/* Sometimes, END_OF_PKT and 0x2284=0 are the only commands sent between
- * rendering commands and overwriting vertex program parameters.
- * Therefore, I suspect writing zero to 0x2284 synchronizes the engine and
- * avoids bugs caused by still running shaders reading bad data from memory.
- */
-#define R300_VAP_PVS_STATE_FLUSH_REG 0x2284
-
-/* This register is used to define the number of core clocks to wait for a
- * vertex to be received by the VAP input controller (while the primitive
- * path is backed up) before forcing any accumulated vertices to be submitted
- * to the vertex processing path.
- */
-#define VAP_PVS_VTX_TIMEOUT_REG 0x2288
-# define R300_2288_R300 0x00750000 /* -- nh */
-# define R300_2288_RV350 0x0000FFFF /* -- Vladimir */
-
-#define R300_VAP_PVS_FLOW_CNTL_LOOP_INDEX_0 0x2290
-#define R300_PVS_FC_LOOP_INIT_VAL(x) ((x) << 0)
-#define R300_PVS_FC_LOOP_STEP_VAL(x) ((x) << 8)
-
-/* gap */
-
-/* Addresses are relative to the vertex program instruction area of the
- * memory bank. PROGRAM_END points to the last instruction of the active
- * program
- *
- * The meaning of the two UNKNOWN fields is obviously not known. However,
- * experiments so far have shown that both *must* point to an instruction
- * inside the vertex program, otherwise the GPU locks up.
- *
- * fglrx usually sets CNTL_3_UNKNOWN to the end of the program and
- * R300_PVS_CNTL_1_POS_END_SHIFT points to instruction where last write to
- * position takes place.
- *
- * Most likely this is used to ignore rest of the program in cases
- * where group of verts arent visible. For some reason this "section"
- * is sometimes accepted other instruction that have no relationship with
- * position calculations.
- */
-#define R300_VAP_PVS_CODE_CNTL_0 0x22D0
-# define R300_PVS_FIRST_INST_SHIFT 0
-# define R300_PVS_XYZW_VALID_INST_SHIFT 10
-# define R300_PVS_LAST_INST_SHIFT 20
-/* Addresses are relative to the vertex program parameters area. */
-#define R300_VAP_PVS_CONST_CNTL 0x22D4
-# define R300_PVS_CONST_BASE_OFFSET_SHIFT 0
-# define R300_PVS_MAX_CONST_ADDR_SHIFT 16
-#define R300_VAP_PVS_CODE_CNTL_1 0x22D8
-# define R300_PVS_LAST_VTX_SRC_INST_SHIFT 0
-#define R300_VAP_PVS_FLOW_CNTL_OPC 0x22DC
-#define R300_VAP_PVS_FC_OPC_JUMP(x) (1 << (2 * (x)))
-#define R300_VAP_PVS_FC_OPC_LOOP(x) (2 << (2 * (x)))
-#define R300_VAP_PVS_FC_OPC_JSR(x) (3 << (2 * (x)))
-
-/* The entire range from 0x2300 to 0x2AC inclusive seems to be used for
- * immediate vertices
- */
-#define R300_VAP_VTX_COLOR_R 0x2464
-#define R300_VAP_VTX_COLOR_G 0x2468
-#define R300_VAP_VTX_COLOR_B 0x246C
-#define R300_VAP_VTX_POS_0_X_1 0x2490 /* used for glVertex2*() */
-#define R300_VAP_VTX_POS_0_Y_1 0x2494
-#define R300_VAP_VTX_COLOR_PKD 0x249C /* RGBA */
-#define R300_VAP_VTX_POS_0_X_2 0x24A0 /* used for glVertex3*() */
-#define R300_VAP_VTX_POS_0_Y_2 0x24A4
-#define R300_VAP_VTX_POS_0_Z_2 0x24A8
-/* write 0 to indicate end of packet? */
-#define R300_VAP_VTX_END_OF_PKT 0x24AC
-
-#define R500_VAP_PVS_FLOW_CNTL_ADDRS_LW_0 0x2500
-#define R500_PVS_FC_ACT_ADRS(x) ((x) << 0)
-#define R500_PVS_FC_LOOP_CNT_JMP_INST(x) ((x) << 16)
-
-#define R500_VAP_PVS_FLOW_CNTL_ADDRS_UW_0 0x2504
-#define R500_PVS_FC_LAST_INST(x) ((x) << 0)
-#define R500_PVS_FC_RTN_INST(x) ((x) << 16)
-
-/* gap */
-
-/* These are values from r300_reg/r300_reg.h - they are known to be correct
- * and are here so we can use one register file instead of several
- * - Vladimir
- */
-#define R300_GB_VAP_RASTER_VTX_FMT_0 0x4000
-# define R300_GB_VAP_RASTER_VTX_FMT_0__POS_PRESENT (1<<0)
-# define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_0_PRESENT (1<<1)
-# define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_1_PRESENT (1<<2)
-# define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_2_PRESENT (1<<3)
-# define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_3_PRESENT (1<<4)
-# define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_SPACE (0xf<<5)
-# define R300_GB_VAP_RASTER_VTX_FMT_0__PT_SIZE_PRESENT (0x1<<16)
-
-#define R300_GB_VAP_RASTER_VTX_FMT_1 0x4004
- /* each of the following is 3 bits wide, specifies number
- of components */
-# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_0_COMP_CNT_SHIFT 0
-# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_1_COMP_CNT_SHIFT 3
-# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_2_COMP_CNT_SHIFT 6
-# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_3_COMP_CNT_SHIFT 9
-# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_4_COMP_CNT_SHIFT 12
-# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_5_COMP_CNT_SHIFT 15
-# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_6_COMP_CNT_SHIFT 18
-# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_7_COMP_CNT_SHIFT 21
-
-/* UNK30 seems to enables point to quad transformation on textures
- * (or something closely related to that).
- * This bit is rather fatal at the time being due to lackings at pixel
- * shader side
- * Specifies top of Raster pipe specific enable controls.
- */
-#define R300_GB_ENABLE 0x4008
-# define R300_GB_POINT_STUFF_DISABLE (0 << 0)
-# define R300_GB_POINT_STUFF_ENABLE (1 << 0) /* Specifies if points will have stuffed texture coordinates. */
-# define R300_GB_LINE_STUFF_DISABLE (0 << 1)
-# define R300_GB_LINE_STUFF_ENABLE (1 << 1) /* Specifies if lines will have stuffed texture coordinates. */
-# define R300_GB_TRIANGLE_STUFF_DISABLE (0 << 2)
-# define R300_GB_TRIANGLE_STUFF_ENABLE (1 << 2) /* Specifies if triangles will have stuffed texture coordinates. */
-# define R300_GB_STENCIL_AUTO_DISABLE (0 << 4)
-# define R300_GB_STENCIL_AUTO_ENABLE (1 << 4) /* Enable stencil auto inc/dec based on triangle cw/ccw, force into dzy low bit. */
-# define R300_GB_STENCIL_AUTO_FORCE (2 << 4) /* Force 0 into dzy low bit. */
-
- /* each of the following is 2 bits wide */
-#define R300_GB_TEX_REPLICATE 0 /* Replicate VAP source texture coordinates (S,T,[R,Q]). */
-#define R300_GB_TEX_ST 1 /* Stuff with source texture coordinates (S,T). */
-#define R300_GB_TEX_STR 2 /* Stuff with source texture coordinates (S,T,R). */
-# define R300_GB_TEX0_SOURCE_SHIFT 16
-# define R300_GB_TEX1_SOURCE_SHIFT 18
-# define R300_GB_TEX2_SOURCE_SHIFT 20
-# define R300_GB_TEX3_SOURCE_SHIFT 22
-# define R300_GB_TEX4_SOURCE_SHIFT 24
-# define R300_GB_TEX5_SOURCE_SHIFT 26
-# define R300_GB_TEX6_SOURCE_SHIFT 28
-# define R300_GB_TEX7_SOURCE_SHIFT 30
-
-/* MSPOS - positions for multisample antialiasing (?) */
-#define R300_GB_MSPOS0 0x4010
- /* shifts - each of the fields is 4 bits */
-# define R300_GB_MSPOS0__MS_X0_SHIFT 0
-# define R300_GB_MSPOS0__MS_Y0_SHIFT 4
-# define R300_GB_MSPOS0__MS_X1_SHIFT 8
-# define R300_GB_MSPOS0__MS_Y1_SHIFT 12
-# define R300_GB_MSPOS0__MS_X2_SHIFT 16
-# define R300_GB_MSPOS0__MS_Y2_SHIFT 20
-# define R300_GB_MSPOS0__MSBD0_Y 24
-# define R300_GB_MSPOS0__MSBD0_X 28
-
-#define R300_GB_MSPOS1 0x4014
-# define R300_GB_MSPOS1__MS_X3_SHIFT 0
-# define R300_GB_MSPOS1__MS_Y3_SHIFT 4
-# define R300_GB_MSPOS1__MS_X4_SHIFT 8
-# define R300_GB_MSPOS1__MS_Y4_SHIFT 12
-# define R300_GB_MSPOS1__MS_X5_SHIFT 16
-# define R300_GB_MSPOS1__MS_Y5_SHIFT 20
-# define R300_GB_MSPOS1__MSBD1 24
-
-/* Specifies the graphics pipeline configuration for rasterization. */
-#define R300_GB_TILE_CONFIG 0x4018
-# define R300_GB_TILE_DISABLE (0 << 0)
-# define R300_GB_TILE_ENABLE (1 << 0)
-# define R300_GB_TILE_PIPE_COUNT_RV300 (0 << 1) /* RV350 (1 pipe, 1 ctx) */
-# define R300_GB_TILE_PIPE_COUNT_R300 (3 << 1) /* R300 (2 pipes, 1 ctx) */
-# define R300_GB_TILE_PIPE_COUNT_R420_3P (6 << 1) /* R420-3P (3 pipes, 1 ctx) */
-# define R300_GB_TILE_PIPE_COUNT_R420 (7 << 1) /* R420 (4 pipes, 1 ctx) */
-# define R300_GB_TILE_SIZE_8 (0 << 4)
-# define R300_GB_TILE_SIZE_16 (1 << 4)
-# define R300_GB_TILE_SIZE_32 (2 << 4)
-# define R300_GB_SUPER_SIZE_1 (0 << 6)
-# define R300_GB_SUPER_SIZE_2 (1 << 6)
-# define R300_GB_SUPER_SIZE_4 (2 << 6)
-# define R300_GB_SUPER_SIZE_8 (3 << 6)
-# define R300_GB_SUPER_SIZE_16 (4 << 6)
-# define R300_GB_SUPER_SIZE_32 (5 << 6)
-# define R300_GB_SUPER_SIZE_64 (6 << 6)
-# define R300_GB_SUPER_SIZE_128 (7 << 6)
-# define R300_GB_SUPER_X_SHIFT 9 /* 3 bits wide */
-# define R300_GB_SUPER_Y_SHIFT 12 /* 3 bits wide */
-# define R300_GB_SUPER_TILE_A (0 << 15)
-# define R300_GB_SUPER_TILE_B (1 << 15)
-# define R300_GB_SUBPIXEL_1_12 (0 << 16)
-# define R300_GB_SUBPIXEL_1_16 (1 << 16)
-# define GB_TILE_CONFIG_QUADS_PER_RAS_4 (0 << 17)
-# define GB_TILE_CONFIG_QUADS_PER_RAS_8 (1 << 17)
-# define GB_TILE_CONFIG_QUADS_PER_RAS_16 (2 << 17)
-# define GB_TILE_CONFIG_QUADS_PER_RAS_32 (3 << 17)
-# define GB_TILE_CONFIG_BB_SCAN_INTERCEPT (0 << 19)
-# define GB_TILE_CONFIG_BB_SCAN_BOUND_BOX (1 << 19)
-# define GB_TILE_CONFIG_ALT_SCAN_EN_LR (0 << 20)
-# define GB_TILE_CONFIG_ALT_SCAN_EN_LRL (1 << 20)
-# define GB_TILE_CONFIG_ALT_OFFSET (0 << 21)
-# define GB_TILE_CONFIG_SUBPRECISION (0 << 22)
-# define GB_TILE_CONFIG_ALT_TILING_DEF (0 << 23)
-# define GB_TILE_CONFIG_ALT_TILING_3_2 (1 << 23)
-# define GB_TILE_CONFIG_Z_EXTENDED_24_1 (0 << 24)
-# define GB_TILE_CONFIG_Z_EXTENDED_S25_1 (1 << 24)
-
-/* Specifies the sizes of the various FIFO`s in the sc/rs/us. This register must be the first one written */
-#define R300_GB_FIFO_SIZE 0x4024
- /* each of the following is 2 bits wide */
-#define R300_GB_FIFO_SIZE_32 0
-#define R300_GB_FIFO_SIZE_64 1
-#define R300_GB_FIFO_SIZE_128 2
-#define R300_GB_FIFO_SIZE_256 3
-# define R300_SC_IFIFO_SIZE_SHIFT 0
-# define R300_SC_TZFIFO_SIZE_SHIFT 2
-# define R300_SC_BFIFO_SIZE_SHIFT 4
-
-# define R300_US_OFIFO_SIZE_SHIFT 12
-# define R300_US_WFIFO_SIZE_SHIFT 14
- /* the following use the same constants as above, but meaning is
- is times 2 (i.e. instead of 32 words it means 64 */
-# define R300_RS_TFIFO_SIZE_SHIFT 6
-# define R300_RS_CFIFO_SIZE_SHIFT 8
-# define R300_US_RAM_SIZE_SHIFT 10
- /* watermarks, 3 bits wide */
-# define R300_RS_HIGHWATER_COL_SHIFT 16
-# define R300_RS_HIGHWATER_TEX_SHIFT 19
-# define R300_OFIFO_HIGHWATER_SHIFT 22 /* two bits only */
-# define R300_CUBE_FIFO_HIGHWATER_COL_SHIFT 24
-
-#define GB_Z_PEQ_CONFIG 0x4028
-# define GB_Z_PEQ_CONFIG_Z_PEQ_SIZE_4_4 (0 << 0)
-# define GB_Z_PEQ_CONFIG_Z_PEQ_SIZE_8_8 (1 << 0)
-
-/* Specifies various polygon specific selects (fog, depth, perspective). */
-#define R300_GB_SELECT 0x401c
-# define R300_GB_FOG_SELECT_C0A (0 << 0)
-# define R300_GB_FOG_SELECT_C1A (1 << 0)
-# define R300_GB_FOG_SELECT_C2A (2 << 0)
-# define R300_GB_FOG_SELECT_C3A (3 << 0)
-# define R300_GB_FOG_SELECT_1_1_W (4 << 0)
-# define R300_GB_FOG_SELECT_Z (5 << 0)
-# define R300_GB_DEPTH_SELECT_Z (0 << 3)
-# define R300_GB_DEPTH_SELECT_1_1_W (1 << 3)
-# define R300_GB_W_SELECT_1_W (0 << 4)
-# define R300_GB_W_SELECT_1 (1 << 4)
-# define R300_GB_FOG_STUFF_DISABLE (0 << 5)
-# define R300_GB_FOG_STUFF_ENABLE (1 << 5)
-# define R300_GB_FOG_STUFF_TEX_SHIFT 6
-# define R300_GB_FOG_STUFF_TEX_MASK 0x000003c0
-# define R300_GB_FOG_STUFF_COMP_SHIFT 10
-# define R300_GB_FOG_STUFF_COMP_MASK 0x00000c00
-
-/* Specifies the graphics pipeline configuration for antialiasing. */
-#define GB_AA_CONFIG 0x4020
-# define GB_AA_CONFIG_AA_DISABLE (0 << 0)
-# define GB_AA_CONFIG_AA_ENABLE (1 << 0)
-# define GB_AA_CONFIG_NUM_AA_SUBSAMPLES_2 (0 << 1)
-# define GB_AA_CONFIG_NUM_AA_SUBSAMPLES_3 (1 << 1)
-# define GB_AA_CONFIG_NUM_AA_SUBSAMPLES_4 (2 << 1)
-# define GB_AA_CONFIG_NUM_AA_SUBSAMPLES_6 (3 << 1)
-
-/* Selects which of 4 pipes are active. */
-#define GB_PIPE_SELECT 0x402c
-# define GB_PIPE_SELECT_PIPE0_ID_SHIFT 0
-# define GB_PIPE_SELECT_PIPE1_ID_SHIFT 2
-# define GB_PIPE_SELECT_PIPE2_ID_SHIFT 4
-# define GB_PIPE_SELECT_PIPE3_ID_SHIFT 6
-# define GB_PIPE_SELECT_PIPE_MASK_SHIFT 8
-# define GB_PIPE_SELECT_MAX_PIPE 12
-# define GB_PIPE_SELECT_BAD_PIPES 14
-# define GB_PIPE_SELECT_CONFIG_PIPES 18
-
-
-/* Specifies the sizes of the various FIFO`s in the sc/rs. */
-#define GB_FIFO_SIZE1 0x4070
-/* High water mark for SC input fifo */
-# define GB_FIFO_SIZE1_SC_HIGHWATER_IFIFO_SHIFT 0
-# define GB_FIFO_SIZE1_SC_HIGHWATER_IFIFO_MASK 0x0000003f
-/* High water mark for SC input fifo (B) */
-# define GB_FIFO_SIZE1_SC_HIGHWATER_BFIFO_SHIFT 6
-# define GB_FIFO_SIZE1_SC_HIGHWATER_BFIFO_MASK 0x00000fc0
-/* High water mark for RS colors' fifo */
-# define GB_FIFO_SIZE1_SC_HIGHWATER_COL_SHIFT 12
-# define GB_FIFO_SIZE1_SC_HIGHWATER_COL_MASK 0x0003f000
-/* High water mark for RS textures' fifo */
-# define GB_FIFO_SIZE1_SC_HIGHWATER_TEX_SHIFT 18
-# define GB_FIFO_SIZE1_SC_HIGHWATER_TEX_MASK 0x00fc0000
-
-/* This table specifies the source location and format for up to 16 texture
- * addresses (i[0]:i[15]) and four colors (c[0]:c[3])
- */
-#define R500_RS_IP_0 0x4074
-#define R500_RS_IP_1 0x4078
-#define R500_RS_IP_2 0x407C
-#define R500_RS_IP_3 0x4080
-#define R500_RS_IP_4 0x4084
-#define R500_RS_IP_5 0x4088
-#define R500_RS_IP_6 0x408C
-#define R500_RS_IP_7 0x4090
-#define R500_RS_IP_8 0x4094
-#define R500_RS_IP_9 0x4098
-#define R500_RS_IP_10 0x409C
-#define R500_RS_IP_11 0x40A0
-#define R500_RS_IP_12 0x40A4
-#define R500_RS_IP_13 0x40A8
-#define R500_RS_IP_14 0x40AC
-#define R500_RS_IP_15 0x40B0
-#define R500_RS_IP_PTR_K0 62
-#define R500_RS_IP_PTR_K1 63
-#define R500_RS_IP_TEX_PTR_S_SHIFT 0
-#define R500_RS_IP_TEX_PTR_T_SHIFT 6
-#define R500_RS_IP_TEX_PTR_R_SHIFT 12
-#define R500_RS_IP_TEX_PTR_Q_SHIFT 18
-#define R500_RS_IP_COL_PTR_SHIFT 24
-#define R500_RS_IP_COL_FMT_SHIFT 27
-# define R500_RS_COL_PTR(x) ((x) << 24)
-# define R500_RS_COL_FMT(x) ((x) << 27)
-/* gap */
-#define R500_RS_IP_OFFSET_DIS (0 << 31)
-#define R500_RS_IP_OFFSET_EN (1 << 31)
-
-/* gap */
-
-/* Zero to flush caches. */
-#define R300_TX_INVALTAGS 0x4100
-#define R300_TX_FLUSH 0x0
-
-/* The upper enable bits are guessed, based on fglrx reported limits. */
-#define R300_TX_ENABLE 0x4104
-# define R300_TX_ENABLE_0 (1 << 0)
-# define R300_TX_ENABLE_1 (1 << 1)
-# define R300_TX_ENABLE_2 (1 << 2)
-# define R300_TX_ENABLE_3 (1 << 3)
-# define R300_TX_ENABLE_4 (1 << 4)
-# define R300_TX_ENABLE_5 (1 << 5)
-# define R300_TX_ENABLE_6 (1 << 6)
-# define R300_TX_ENABLE_7 (1 << 7)
-# define R300_TX_ENABLE_8 (1 << 8)
-# define R300_TX_ENABLE_9 (1 << 9)
-# define R300_TX_ENABLE_10 (1 << 10)
-# define R300_TX_ENABLE_11 (1 << 11)
-# define R300_TX_ENABLE_12 (1 << 12)
-# define R300_TX_ENABLE_13 (1 << 13)
-# define R300_TX_ENABLE_14 (1 << 14)
-# define R300_TX_ENABLE_15 (1 << 15)
-
-#define R500_TX_FILTER_4 0x4110
-# define R500_TX_WEIGHT_1_SHIFT (0)
-# define R500_TX_WEIGHT_0_SHIFT (11)
-# define R500_TX_WEIGHT_PAIR (1<<22)
-# define R500_TX_PHASE_SHIFT (23)
-# define R500_TX_DIRECTION_HORIZONTAL (0<<27)
-# define R500_TX_DIRECTION_VERITCAL (1<<27)
-
-/* S Texture Coordinate of Vertex 0 for Point texture stuffing (LLC) */
-#define R300_GA_POINT_S0 0x4200
-
-/* T Texture Coordinate of Vertex 0 for Point texture stuffing (LLC) */
-#define R300_GA_POINT_T0 0x4204
-
-/* S Texture Coordinate of Vertex 2 for Point texture stuffing (URC) */
-#define R300_GA_POINT_S1 0x4208
-
-/* T Texture Coordinate of Vertex 2 for Point texture stuffing (URC) */
-#define R300_GA_POINT_T1 0x420c
-
-/* Specifies amount to shift integer position of vertex (screen space) before
- * converting to float for triangle stipple.
- */
-#define R300_GA_TRIANGLE_STIPPLE 0x4214
-# define R300_GA_TRIANGLE_STIPPLE_X_SHIFT_SHIFT 0
-# define R300_GA_TRIANGLE_STIPPLE_X_SHIFT_MASK 0x0000000f
-# define R300_GA_TRIANGLE_STIPPLE_Y_SHIFT_SHIFT 16
-# define R300_GA_TRIANGLE_STIPPLE_Y_SHIFT_MASK 0x000f0000
-
-/* The pointsize is given in multiples of 6. The pointsize can be enormous:
- * Clear() renders a single point that fills the entire framebuffer.
- * 1/2 Height of point; fixed (16.0), subpixel format (1/12 or 1/16, even if in
- * 8b precision).
- */
-#define R300_GA_POINT_SIZE 0x421C
-# define R300_POINTSIZE_Y_SHIFT 0
-# define R300_POINTSIZE_Y_MASK 0x0000ffff
-# define R300_POINTSIZE_X_SHIFT 16
-# define R300_POINTSIZE_X_MASK 0xffff0000
-# define R300_POINTSIZE_MAX (R300_POINTSIZE_Y_MASK / 6)
-
-/* Blue fill color */
-#define R500_GA_FILL_R 0x4220
-
-/* Blue fill color */
-#define R500_GA_FILL_G 0x4224
-
-/* Blue fill color */
-#define R500_GA_FILL_B 0x4228
-
-/* Alpha fill color */
-#define R500_GA_FILL_A 0x422c
-
-
-/* Specifies maximum and minimum point & sprite sizes for per vertex size
- * specification. The lower part (15:0) is MIN and (31:16) is max.
- */
-#define R300_GA_POINT_MINMAX 0x4230
-# define R300_GA_POINT_MINMAX_MIN_SHIFT 0
-# define R300_GA_POINT_MINMAX_MIN_MASK (0xFFFF << 0)
-# define R300_GA_POINT_MINMAX_MAX_SHIFT 16
-# define R300_GA_POINT_MINMAX_MAX_MASK (0xFFFF << 16)
-
-/* 1/2 width of line, in subpixels (1/12 or 1/16 only, even in 8b
- * subprecision); (16.0) fixed format.
- *
- * The line width is given in multiples of 6.
- * In default mode lines are classified as vertical lines.
- * HO: horizontal
- * VE: vertical or horizontal
- * HO & VE: no classification
- */
-#define R300_GA_LINE_CNTL 0x4234
-# define R300_GA_LINE_CNTL_WIDTH_SHIFT 0
-# define R300_GA_LINE_CNTL_WIDTH_MASK 0x0000ffff
-# define R300_GA_LINE_CNTL_END_TYPE_HOR (0 << 16)
-# define R300_GA_LINE_CNTL_END_TYPE_VER (1 << 16)
-# define R300_GA_LINE_CNTL_END_TYPE_SQR (2 << 16) /* horizontal or vertical depending upon slope */
-# define R300_GA_LINE_CNTL_END_TYPE_COMP (3 << 16) /* Computed (perpendicular to slope) */
-# define R500_GA_LINE_CNTL_SORT_NO (0 << 18)
-# define R500_GA_LINE_CNTL_SORT_MINX_MINY (1 << 18)
-/** TODO: looks wrong */
-# define R300_LINESIZE_MAX (R300_GA_LINE_CNTL_WIDTH_MASK / 6)
-/** TODO: looks wrong */
-# define R300_LINE_CNT_HO (1 << 16)
-/** TODO: looks wrong */
-# define R300_LINE_CNT_VE (1 << 17)
-
-/* Line Stipple configuration information. */
-#define R300_GA_LINE_STIPPLE_CONFIG 0x4238
-# define R300_GA_LINE_STIPPLE_CONFIG_LINE_RESET_NO (0 << 0)
-# define R300_GA_LINE_STIPPLE_CONFIG_LINE_RESET_LINE (1 << 0)
-# define R300_GA_LINE_STIPPLE_CONFIG_LINE_RESET_PACKET (2 << 0)
-# define R300_GA_LINE_STIPPLE_CONFIG_STIPPLE_SCALE_SHIFT 2
-# define R300_GA_LINE_STIPPLE_CONFIG_STIPPLE_SCALE_MASK 0xfffffffc
-
-/* Used to load US instructions and constants */
-#define R500_GA_US_VECTOR_INDEX 0x4250
-# define R500_GA_US_VECTOR_INDEX_SHIFT 0
-# define R500_GA_US_VECTOR_INDEX_MASK 0x000000ff
-# define R500_GA_US_VECTOR_INDEX_TYPE_INSTR (0 << 16)
-# define R500_GA_US_VECTOR_INDEX_TYPE_CONST (1 << 16)
-# define R500_GA_US_VECTOR_INDEX_CLAMP_NO (0 << 17)
-# define R500_GA_US_VECTOR_INDEX_CLAMP_CONST (1 << 17)
-
-/* Data register for loading US instructions and constants */
-#define R500_GA_US_VECTOR_DATA 0x4254
-
-/* Specifies color properties and mappings of textures. */
-#define R500_GA_COLOR_CONTROL_PS3 0x4258
-# define R500_TEX0_SHADING_PS3_SOLID (0 << 0)
-# define R500_TEX0_SHADING_PS3_FLAT (1 << 0)
-# define R500_TEX0_SHADING_PS3_GOURAUD (2 << 0)
-# define R500_TEX1_SHADING_PS3_SOLID (0 << 2)
-# define R500_TEX1_SHADING_PS3_FLAT (1 << 2)
-# define R500_TEX1_SHADING_PS3_GOURAUD (2 << 2)
-# define R500_TEX2_SHADING_PS3_SOLID (0 << 4)
-# define R500_TEX2_SHADING_PS3_FLAT (1 << 4)
-# define R500_TEX2_SHADING_PS3_GOURAUD (2 << 4)
-# define R500_TEX3_SHADING_PS3_SOLID (0 << 6)
-# define R500_TEX3_SHADING_PS3_FLAT (1 << 6)
-# define R500_TEX3_SHADING_PS3_GOURAUD (2 << 6)
-# define R500_TEX4_SHADING_PS3_SOLID (0 << 8)
-# define R500_TEX4_SHADING_PS3_FLAT (1 << 8)
-# define R500_TEX4_SHADING_PS3_GOURAUD (2 << 8)
-# define R500_TEX5_SHADING_PS3_SOLID (0 << 10)
-# define R500_TEX5_SHADING_PS3_FLAT (1 << 10)
-# define R500_TEX5_SHADING_PS3_GOURAUD (2 << 10)
-# define R500_TEX6_SHADING_PS3_SOLID (0 << 12)
-# define R500_TEX6_SHADING_PS3_FLAT (1 << 12)
-# define R500_TEX6_SHADING_PS3_GOURAUD (2 << 12)
-# define R500_TEX7_SHADING_PS3_SOLID (0 << 14)
-# define R500_TEX7_SHADING_PS3_FLAT (1 << 14)
-# define R500_TEX7_SHADING_PS3_GOURAUD (2 << 14)
-# define R500_TEX8_SHADING_PS3_SOLID (0 << 16)
-# define R500_TEX8_SHADING_PS3_FLAT (1 << 16)
-# define R500_TEX8_SHADING_PS3_GOURAUD (2 << 16)
-# define R500_TEX9_SHADING_PS3_SOLID (0 << 18)
-# define R500_TEX9_SHADING_PS3_FLAT (1 << 18)
-# define R500_TEX9_SHADING_PS3_GOURAUD (2 << 18)
-# define R500_TEX10_SHADING_PS3_SOLID (0 << 20)
-# define R500_TEX10_SHADING_PS3_FLAT (1 << 20)
-# define R500_TEX10_SHADING_PS3_GOURAUD (2 << 20)
-# define R500_COLOR0_TEX_OVERRIDE_NO (0 << 22)
-# define R500_COLOR0_TEX_OVERRIDE_TEX_0 (1 << 22)
-# define R500_COLOR0_TEX_OVERRIDE_TEX_1 (2 << 22)
-# define R500_COLOR0_TEX_OVERRIDE_TEX_2 (3 << 22)
-# define R500_COLOR0_TEX_OVERRIDE_TEX_3 (4 << 22)
-# define R500_COLOR0_TEX_OVERRIDE_TEX_4 (5 << 22)
-# define R500_COLOR0_TEX_OVERRIDE_TEX_5 (6 << 22)
-# define R500_COLOR0_TEX_OVERRIDE_TEX_6 (7 << 22)
-# define R500_COLOR0_TEX_OVERRIDE_TEX_7 (8 << 22)
-# define R500_COLOR0_TEX_OVERRIDE_TEX_8_C2 (9 << 22)
-# define R500_COLOR0_TEX_OVERRIDE_TEX_9_C3 (10 << 22)
-# define R500_COLOR1_TEX_OVERRIDE_NO (0 << 26)
-# define R500_COLOR1_TEX_OVERRIDE_TEX_0 (1 << 26)
-# define R500_COLOR1_TEX_OVERRIDE_TEX_1 (2 << 26)
-# define R500_COLOR1_TEX_OVERRIDE_TEX_2 (3 << 26)
-# define R500_COLOR1_TEX_OVERRIDE_TEX_3 (4 << 26)
-# define R500_COLOR1_TEX_OVERRIDE_TEX_4 (5 << 26)
-# define R500_COLOR1_TEX_OVERRIDE_TEX_5 (6 << 26)
-# define R500_COLOR1_TEX_OVERRIDE_TEX_6 (7 << 26)
-# define R500_COLOR1_TEX_OVERRIDE_TEX_7 (8 << 26)
-# define R500_COLOR1_TEX_OVERRIDE_TEX_8_C2 (9 << 26)
-# define R500_COLOR1_TEX_OVERRIDE_TEX_9_C3 (10 << 26)
-
-/* Returns idle status of various G3D block, captured when GA_IDLE written or
- * when hard or soft reset asserted.
- */
-#define R500_GA_IDLE 0x425c
-# define R500_GA_IDLE_PIPE3_Z_IDLE (0 << 0)
-# define R500_GA_IDLE_PIPE2_Z_IDLE (0 << 1)
-# define R500_GA_IDLE_PIPE3_CD_IDLE (0 << 2)
-# define R500_GA_IDLE_PIPE2_CD_IDLE (0 << 3)
-# define R500_GA_IDLE_PIPE3_FG_IDLE (0 << 4)
-# define R500_GA_IDLE_PIPE2_FG_IDLE (0 << 5)
-# define R500_GA_IDLE_PIPE3_US_IDLE (0 << 6)
-# define R500_GA_IDLE_PIPE2_US_IDLE (0 << 7)
-# define R500_GA_IDLE_PIPE3_SC_IDLE (0 << 8)
-# define R500_GA_IDLE_PIPE2_SC_IDLE (0 << 9)
-# define R500_GA_IDLE_PIPE3_RS_IDLE (0 << 10)
-# define R500_GA_IDLE_PIPE2_RS_IDLE (0 << 11)
-# define R500_GA_IDLE_PIPE1_Z_IDLE (0 << 12)
-# define R500_GA_IDLE_PIPE0_Z_IDLE (0 << 13)
-# define R500_GA_IDLE_PIPE1_CD_IDLE (0 << 14)
-# define R500_GA_IDLE_PIPE0_CD_IDLE (0 << 15)
-# define R500_GA_IDLE_PIPE1_FG_IDLE (0 << 16)
-# define R500_GA_IDLE_PIPE0_FG_IDLE (0 << 17)
-# define R500_GA_IDLE_PIPE1_US_IDLE (0 << 18)
-# define R500_GA_IDLE_PIPE0_US_IDLE (0 << 19)
-# define R500_GA_IDLE_PIPE1_SC_IDLE (0 << 20)
-# define R500_GA_IDLE_PIPE0_SC_IDLE (0 << 21)
-# define R500_GA_IDLE_PIPE1_RS_IDLE (0 << 22)
-# define R500_GA_IDLE_PIPE0_RS_IDLE (0 << 23)
-# define R500_GA_IDLE_SU_IDLE (0 << 24)
-# define R500_GA_IDLE_GA_IDLE (0 << 25)
-# define R500_GA_IDLE_GA_UNIT2_IDLE (0 << 26)
-
-/* Current value of stipple accumulator. */
-#define R300_GA_LINE_STIPPLE_VALUE 0x4260
-
-/* S Texture Coordinate Value for Vertex 0 of Line (stuff textures -- i.e. AA) */
-#define R300_GA_LINE_S0 0x4264
-/* S Texture Coordinate Value for Vertex 1 of Lines (V2 of parallelogram -- stuff textures -- i.e. AA) */
-#define R300_GA_LINE_S1 0x4268
-
-/* GA Input fifo high water marks */
-#define R500_GA_FIFO_CNTL 0x4270
-# define R500_GA_FIFO_CNTL_VERTEX_FIFO_MASK 0x00000007
-# define R500_GA_FIFO_CNTL_VERTEX_FIFO_SHIFT 0
-# define R500_GA_FIFO_CNTL_VERTEX_INDEX_MASK 0x00000038
-# define R500_GA_FIFO_CNTL_VERTEX_INDEX_SHIFT 3
-# define R500_GA_FIFO_CNTL_VERTEX_REG_MASK 0x00003fc0
-# define R500_GA_FIFO_CNTL_VERTEX_REG_SHIFT 6
-
-/* GA enhance/tweaks */
-#define R300_GA_ENHANCE 0x4274
-# define R300_GA_ENHANCE_DEADLOCK_CNTL_NO_EFFECT (0 << 0)
-# define R300_GA_ENHANCE_DEADLOCK_CNTL_PREVENT_TCL (1 << 0) /* Prevents TCL interface from deadlocking on GA side. */
-# define R300_GA_ENHANCE_FASTSYNC_CNTL_NO_EFFECT (0 << 1)
-# define R300_GA_ENHANCE_FASTSYNC_CNTL_ENABLE (1 << 1) /* Enables high-performance register/primitive switching. */
-# define R500_GA_ENHANCE_REG_READWRITE_NO_EFFECT (0 << 2) /* R520+ only */
-# define R500_GA_ENHANCE_REG_READWRITE_ENABLE (1 << 2) /* R520+ only, Enables GA support of simultaneous register reads and writes. */
-# define R500_GA_ENHANCE_REG_NOSTALL_NO_EFFECT (0 << 3)
-# define R500_GA_ENHANCE_REG_NOSTALL_ENABLE (1 << 3) /* Enables GA support of no-stall reads for register read back. */
-
-#define R300_GA_COLOR_CONTROL 0x4278
-# define R300_GA_COLOR_CONTROL_RGB0_SHADING_SOLID (0 << 0)
-# define R300_GA_COLOR_CONTROL_RGB0_SHADING_FLAT (1 << 0)
-# define R300_GA_COLOR_CONTROL_RGB0_SHADING_GOURAUD (2 << 0)
-# define R300_GA_COLOR_CONTROL_ALPHA0_SHADING_SOLID (0 << 2)
-# define R300_GA_COLOR_CONTROL_ALPHA0_SHADING_FLAT (1 << 2)
-# define R300_GA_COLOR_CONTROL_ALPHA0_SHADING_GOURAUD (2 << 2)
-# define R300_GA_COLOR_CONTROL_RGB1_SHADING_SOLID (0 << 4)
-# define R300_GA_COLOR_CONTROL_RGB1_SHADING_FLAT (1 << 4)
-# define R300_GA_COLOR_CONTROL_RGB1_SHADING_GOURAUD (2 << 4)
-# define R300_GA_COLOR_CONTROL_ALPHA1_SHADING_SOLID (0 << 6)
-# define R300_GA_COLOR_CONTROL_ALPHA1_SHADING_FLAT (1 << 6)
-# define R300_GA_COLOR_CONTROL_ALPHA1_SHADING_GOURAUD (2 << 6)
-# define R300_GA_COLOR_CONTROL_RGB2_SHADING_SOLID (0 << 8)
-# define R300_GA_COLOR_CONTROL_RGB2_SHADING_FLAT (1 << 8)
-# define R300_GA_COLOR_CONTROL_RGB2_SHADING_GOURAUD (2 << 8)
-# define R300_GA_COLOR_CONTROL_ALPHA2_SHADING_SOLID (0 << 10)
-# define R300_GA_COLOR_CONTROL_ALPHA2_SHADING_FLAT (1 << 10)
-# define R300_GA_COLOR_CONTROL_ALPHA2_SHADING_GOURAUD (2 << 10)
-# define R300_GA_COLOR_CONTROL_RGB3_SHADING_SOLID (0 << 12)
-# define R300_GA_COLOR_CONTROL_RGB3_SHADING_FLAT (1 << 12)
-# define R300_GA_COLOR_CONTROL_RGB3_SHADING_GOURAUD (2 << 12)
-# define R300_GA_COLOR_CONTROL_ALPHA3_SHADING_SOLID (0 << 14)
-# define R300_GA_COLOR_CONTROL_ALPHA3_SHADING_FLAT (1 << 14)
-# define R300_GA_COLOR_CONTROL_ALPHA3_SHADING_GOURAUD (2 << 14)
-# define R300_GA_COLOR_CONTROL_PROVOKING_VERTEX_FIRST (0 << 16)
-# define R300_GA_COLOR_CONTROL_PROVOKING_VERTEX_SECOND (1 << 16)
-# define R300_GA_COLOR_CONTROL_PROVOKING_VERTEX_THIRD (2 << 16)
-# define R300_GA_COLOR_CONTROL_PROVOKING_VERTEX_LAST (3 << 16)
-
-/** TODO: might be candidate for removal */
-# define R300_RE_SHADE_MODEL_SMOOTH ( \
- R300_GA_COLOR_CONTROL_RGB0_SHADING_GOURAUD | R300_GA_COLOR_CONTROL_ALPHA0_SHADING_GOURAUD | \
- R300_GA_COLOR_CONTROL_RGB1_SHADING_GOURAUD | R300_GA_COLOR_CONTROL_ALPHA1_SHADING_GOURAUD | \
- R300_GA_COLOR_CONTROL_RGB2_SHADING_GOURAUD | R300_GA_COLOR_CONTROL_ALPHA2_SHADING_GOURAUD | \
- R300_GA_COLOR_CONTROL_RGB3_SHADING_GOURAUD | R300_GA_COLOR_CONTROL_ALPHA3_SHADING_GOURAUD)
-/** TODO: might be candidate for removal, the GOURAUD stuff also looks buggy to me */
-# define R300_RE_SHADE_MODEL_FLAT ( \
- R300_GA_COLOR_CONTROL_RGB0_SHADING_FLAT | R300_GA_COLOR_CONTROL_ALPHA0_SHADING_FLAT | \
- R300_GA_COLOR_CONTROL_RGB1_SHADING_FLAT | R300_GA_COLOR_CONTROL_ALPHA1_SHADING_GOURAUD | \
- R300_GA_COLOR_CONTROL_RGB2_SHADING_FLAT | R300_GA_COLOR_CONTROL_ALPHA2_SHADING_FLAT | \
- R300_GA_COLOR_CONTROL_RGB3_SHADING_FLAT | R300_GA_COLOR_CONTROL_ALPHA3_SHADING_GOURAUD)
-
-/* Specifies red & green components of fill color -- S312 format -- Backwards comp. */
-#define R300_GA_SOLID_RG 0x427c
-# define GA_SOLID_RG_COLOR_GREEN_SHIFT 0
-# define GA_SOLID_RG_COLOR_GREEN_MASK 0x0000ffff
-# define GA_SOLID_RG_COLOR_RED_SHIFT 16
-# define GA_SOLID_RG_COLOR_RED_MASK 0xffff0000
-/* Specifies blue & alpha components of fill color -- S312 format -- Backwards comp. */
-#define R300_GA_SOLID_BA 0x4280
-# define GA_SOLID_BA_COLOR_ALPHA_SHIFT 0
-# define GA_SOLID_BA_COLOR_ALPHA_MASK 0x0000ffff
-# define GA_SOLID_BA_COLOR_BLUE_SHIFT 16
-# define GA_SOLID_BA_COLOR_BLUE_MASK 0xffff0000
-
-/* Polygon Mode
- * Dangerous
- */
-#define R300_GA_POLY_MODE 0x4288
-# define R300_GA_POLY_MODE_DISABLE (0 << 0)
-# define R300_GA_POLY_MODE_DUAL (1 << 0) /* send 2 sets of 3 polys with specified poly type */
-/* reserved */
-# define R300_GA_POLY_MODE_FRONT_PTYPE_POINT (0 << 4)
-# define R300_GA_POLY_MODE_FRONT_PTYPE_LINE (1 << 4)
-# define R300_GA_POLY_MODE_FRONT_PTYPE_TRI (2 << 4)
-/* reserved */
-# define R300_GA_POLY_MODE_BACK_PTYPE_POINT (0 << 7)
-# define R300_GA_POLY_MODE_BACK_PTYPE_LINE (1 << 7)
-# define R300_GA_POLY_MODE_BACK_PTYPE_TRI (2 << 7)
-/* reserved */
-
-/* Specifies the rouding mode for geometry & color SPFP to FP conversions. */
-#define R300_GA_ROUND_MODE 0x428c
-# define R300_GA_ROUND_MODE_GEOMETRY_ROUND_TRUNC (0 << 0)
-# define R300_GA_ROUND_MODE_GEOMETRY_ROUND_NEAREST (1 << 0)
-# define R300_GA_ROUND_MODE_COLOR_ROUND_TRUNC (0 << 2)
-# define R300_GA_ROUND_MODE_COLOR_ROUND_NEAREST (1 << 2)
-# define R300_GA_ROUND_MODE_RGB_CLAMP_RGB (0 << 4)
-# define R300_GA_ROUND_MODE_RGB_CLAMP_FP20 (1 << 4)
-# define R300_GA_ROUND_MODE_ALPHA_CLAMP_RGB (0 << 5)
-# define R300_GA_ROUND_MODE_ALPHA_CLAMP_FP20 (1 << 5)
-# define R500_GA_ROUND_MODE_GEOMETRY_MASK_SHIFT 6
-# define R500_GA_ROUND_MODE_GEOMETRY_MASK_MASK 0x000003c0
-
-/* Specifies x & y offsets for vertex data after conversion to FP.
- * Offsets are in S15 format (subpixels -- 1/12 or 1/16, even in 8b
- * subprecision).
- */
-#define R300_GA_OFFSET 0x4290
-# define R300_GA_OFFSET_X_OFFSET_SHIFT 0
-# define R300_GA_OFFSET_X_OFFSET_MASK 0x0000ffff
-# define R300_GA_OFFSET_Y_OFFSET_SHIFT 16
-# define R300_GA_OFFSET_Y_OFFSET_MASK 0xffff0000
-
-/* Specifies the scale to apply to fog. */
-#define R300_GA_FOG_SCALE 0x4294
-/* Specifies the offset to apply to fog. */
-#define R300_GA_FOG_OFFSET 0x4298
-/* Specifies number of cycles to assert reset, and also causes RB3D soft reset to assert. */
-#define R300_GA_SOFT_RESET 0x429c
-
-/* Not sure why there are duplicate of factor and constant values.
- * My best guess so far is that there are seperate zbiases for test and write.
- * Ordering might be wrong.
- * Some of the tests indicate that fgl has a fallback implementation of zbias
- * via pixel shaders.
- */
-#define R300_SU_TEX_WRAP 0x42A0
-#define R300_SU_POLY_OFFSET_FRONT_SCALE 0x42A4
-#define R300_SU_POLY_OFFSET_FRONT_OFFSET 0x42A8
-#define R300_SU_POLY_OFFSET_BACK_SCALE 0x42AC
-#define R300_SU_POLY_OFFSET_BACK_OFFSET 0x42B0
-
-/* This register needs to be set to (1<<1) for RV350 to correctly
- * perform depth test (see --vb-triangles in r300_demo)
- * Don't know about other chips. - Vladimir
- * This is set to 3 when GL_POLYGON_OFFSET_FILL is on.
- * My guess is that there are two bits for each zbias primitive
- * (FILL, LINE, POINT).
- * One to enable depth test and one for depth write.
- * Yet this doesnt explain why depth writes work ...
- */
-#define R300_SU_POLY_OFFSET_ENABLE 0x42B4
-# define R300_FRONT_ENABLE (1 << 0)
-# define R300_BACK_ENABLE (1 << 1)
-# define R300_PARA_ENABLE (1 << 2)
-
-#define R300_SU_CULL_MODE 0x42B8
-# define R300_CULL_FRONT (1 << 0)
-# define R300_CULL_BACK (1 << 1)
-# define R300_FRONT_FACE_CCW (0 << 2)
-# define R300_FRONT_FACE_CW (1 << 2)
-
-/* SU Depth Scale value */
-#define R300_SU_DEPTH_SCALE 0x42c0
-/* SU Depth Offset value */
-#define R300_SU_DEPTH_OFFSET 0x42c4
-
-#define R300_SU_REG_DEST 0x42c8
-# define R300_RASTER_PIPE_SELECT_0 (1 << 0)
-# define R300_RASTER_PIPE_SELECT_1 (1 << 1)
-# define R300_RASTER_PIPE_SELECT_2 (1 << 2)
-# define R300_RASTER_PIPE_SELECT_3 (1 << 3)
-# define R300_RASTER_PIPE_SELECT_ALL 0xf
-
-
-/* BEGIN: Rasterization / Interpolators - many guesses */
-
-/*
- * TC_CNT is the number of incoming texture coordinate sets (i.e. it depends
- * on the vertex program, *not* the fragment program)
- */
-#define R300_RS_COUNT 0x4300
-# define R300_IT_COUNT_SHIFT 0
-# define R300_IT_COUNT_MASK 0x0000007f
-# define R300_IC_COUNT_SHIFT 7
-# define R300_IC_COUNT_MASK 0x00000780
-# define R300_W_ADDR_SHIFT 12
-# define R300_W_ADDR_MASK 0x0003f000
-# define R300_HIRES_DIS (0 << 18)
-# define R300_HIRES_EN (1 << 18)
-
-#define R300_RS_INST_COUNT 0x4304
-# define R300_RS_INST_COUNT_SHIFT 0
-# define R300_RS_INST_COUNT_MASK 0x0000000f
-# define R300_RS_TX_OFFSET_SHIFT 5
-# define R300_RS_TX_OFFSET_MASK 0x000000e0
-
-/* gap */
-
-/* Only used for texture coordinates.
- * Use the source field to route texture coordinate input from the
- * vertex program to the desired interpolator. Note that the source
- * field is relative to the outputs the vertex program *actually*
- * writes. If a vertex program only writes texcoord[1], this will
- * be source index 0.
- * Set INTERP_USED on all interpolators that produce data used by
- * the fragment program. INTERP_USED looks like a swizzling mask,
- * but I haven't seen it used that way.
- *
- * Note: The _UNKNOWN constants are always set in their respective
- * register. I don't know if this is necessary.
- */
-#define R300_RS_IP_0 0x4310
-#define R300_RS_IP_1 0x4314
-#define R300_RS_IP_2 0x4318
-#define R300_RS_IP_3 0x431C
-# define R300_RS_INTERP_SRC_SHIFT 2 /* TODO: check for removal */
-# define R300_RS_INTERP_SRC_MASK (7 << 2) /* TODO: check for removal */
-# define R300_RS_TEX_PTR(x) ((x) << 0)
-# define R300_RS_COL_PTR(x) ((x) << 6)
-# define R300_RS_COL_FMT(x) ((x) << 9)
-# define R300_RS_COL_FMT_RGBA 0
-# define R300_RS_COL_FMT_RGB0 1
-# define R300_RS_COL_FMT_RGB1 2
-# define R300_RS_COL_FMT_000A 4
-# define R300_RS_COL_FMT_0000 5
-# define R300_RS_COL_FMT_0001 6
-# define R300_RS_COL_FMT_111A 8
-# define R300_RS_COL_FMT_1110 9
-# define R300_RS_COL_FMT_1111 10
-# define R300_RS_SEL_S(x) ((x) << 13)
-# define R300_RS_SEL_T(x) ((x) << 16)
-# define R300_RS_SEL_R(x) ((x) << 19)
-# define R300_RS_SEL_Q(x) ((x) << 22)
-# define R300_RS_SEL_C0 0
-# define R300_RS_SEL_C1 1
-# define R300_RS_SEL_C2 2
-# define R300_RS_SEL_C3 3
-# define R300_RS_SEL_K0 4
-# define R300_RS_SEL_K1 5
-
-
-/* */
-#define R500_RS_INST_0 0x4320
-#define R500_RS_INST_1 0x4324
-#define R500_RS_INST_2 0x4328
-#define R500_RS_INST_3 0x432c
-#define R500_RS_INST_4 0x4330
-#define R500_RS_INST_5 0x4334
-#define R500_RS_INST_6 0x4338
-#define R500_RS_INST_7 0x433c
-#define R500_RS_INST_8 0x4340
-#define R500_RS_INST_9 0x4344
-#define R500_RS_INST_10 0x4348
-#define R500_RS_INST_11 0x434c
-#define R500_RS_INST_12 0x4350
-#define R500_RS_INST_13 0x4354
-#define R500_RS_INST_14 0x4358
-#define R500_RS_INST_15 0x435c
-#define R500_RS_INST_TEX_ID_SHIFT 0
-#define R500_RS_INST_TEX_CN_WRITE (1 << 4)
-#define R500_RS_INST_TEX_ADDR_SHIFT 5
-#define R500_RS_INST_COL_ID_SHIFT 12
-#define R500_RS_INST_COL_CN_NO_WRITE (0 << 16)
-#define R500_RS_INST_COL_CN_WRITE (1 << 16)
-#define R500_RS_INST_COL_CN_WRITE_FBUFFER (2 << 16)
-#define R500_RS_INST_COL_CN_WRITE_BACKFACE (3 << 16)
-#define R500_RS_INST_COL_ADDR_SHIFT 18
-#define R500_RS_INST_TEX_ADJ (1 << 25)
-#define R500_RS_INST_W_CN (1 << 26)
-#define R500_RS_INST_TEX_ID(x) ((x) << R500_RS_INST_TEX_ID_SHIFT)
-#define R500_RS_INST_TEX_ADDR(x) ((x) << R500_RS_INST_TEX_ADDR_SHIFT)
-#define R500_RS_INST_COL_ID(x) ((x) << R500_RS_INST_COL_ID_SHIFT)
-#define R500_RS_INST_COL_ADDR(x) ((x) << R500_RS_INST_COL_ADDR_SHIFT)
-
-/* These DWORDs control how vertex data is routed into fragment program
- * registers, after interpolators.
- */
-#define R300_RS_INST_0 0x4330
-#define R300_RS_INST_1 0x4334
-#define R300_RS_INST_2 0x4338
-#define R300_RS_INST_3 0x433C /* GUESS */
-#define R300_RS_INST_4 0x4340 /* GUESS */
-#define R300_RS_INST_5 0x4344 /* GUESS */
-#define R300_RS_INST_6 0x4348 /* GUESS */
-#define R300_RS_INST_7 0x434C /* GUESS */
-# define R300_RS_INST_TEX_ID(x) ((x) << 0)
-# define R300_RS_INST_TEX_CN_WRITE (1 << 3)
-# define R300_RS_INST_TEX_ADDR_SHIFT 6
-# define R300_RS_INST_TEX_ADDR(x) ((x) << R300_RS_INST_TEX_ADDR_SHIFT)
-# define R300_RS_INST_COL_ID(x) ((x) << 11)
-# define R300_RS_INST_COL_CN_WRITE (1 << 14)
-# define R300_RS_INST_COL_ADDR_SHIFT 17
-# define R300_RS_INST_COL_ADDR(x) ((x) << R300_RS_INST_COL_ADDR_SHIFT)
-# define R300_RS_INST_TEX_ADJ (1 << 22)
-# define R300_RS_COL_BIAS_UNUSED_SHIFT 23
-
-/* END: Rasterization / Interpolators - many guesses */
-
-/* Hierarchical Z Enable */
-#define R300_SC_HYPERZ 0x43a4
-# define R300_SC_HYPERZ_DISABLE (0 << 0)
-# define R300_SC_HYPERZ_ENABLE (1 << 0)
-# define R300_SC_HYPERZ_MIN (0 << 1)
-# define R300_SC_HYPERZ_MAX (1 << 1)
-# define R300_SC_HYPERZ_ADJ_256 (0 << 2)
-# define R300_SC_HYPERZ_ADJ_128 (1 << 2)
-# define R300_SC_HYPERZ_ADJ_64 (2 << 2)
-# define R300_SC_HYPERZ_ADJ_32 (3 << 2)
-# define R300_SC_HYPERZ_ADJ_16 (4 << 2)
-# define R300_SC_HYPERZ_ADJ_8 (5 << 2)
-# define R300_SC_HYPERZ_ADJ_4 (6 << 2)
-# define R300_SC_HYPERZ_ADJ_2 (7 << 2)
-# define R300_SC_HYPERZ_HZ_Z0MIN_NO (0 << 5)
-# define R300_SC_HYPERZ_HZ_Z0MIN (1 << 5)
-# define R300_SC_HYPERZ_HZ_Z0MAX_NO (0 << 6)
-# define R300_SC_HYPERZ_HZ_Z0MAX (1 << 6)
-
-#define R300_SC_EDGERULE 0x43a8
-
-/* BEGIN: Scissors and cliprects */
-
-/* There are four clipping rectangles. Their corner coordinates are inclusive.
- * Every pixel is assigned a number from 0 and 15 by setting bits 0-3 depending
- * on whether the pixel is inside cliprects 0-3, respectively. For example,
- * if a pixel is inside cliprects 0 and 1, but outside 2 and 3, it is assigned
- * the number 3 (binary 0011).
- * Iff the bit corresponding to the pixel's number in RE_CLIPRECT_CNTL is set,
- * the pixel is rasterized.
- *
- * In addition to this, there is a scissors rectangle. Only pixels inside the
- * scissors rectangle are drawn. (coordinates are inclusive)
- *
- * For some reason, the top-left corner of the framebuffer is at (1440, 1440)
- * for the purpose of clipping and scissors.
- */
-#define R300_SC_CLIPRECT_TL_0 0x43B0
-#define R300_SC_CLIPRECT_BR_0 0x43B4
-#define R300_SC_CLIPRECT_TL_1 0x43B8
-#define R300_SC_CLIPRECT_BR_1 0x43BC
-#define R300_SC_CLIPRECT_TL_2 0x43C0
-#define R300_SC_CLIPRECT_BR_2 0x43C4
-#define R300_SC_CLIPRECT_TL_3 0x43C8
-#define R300_SC_CLIPRECT_BR_3 0x43CC
-# define R300_CLIPRECT_OFFSET 1440
-# define R300_CLIPRECT_MASK 0x1FFF
-# define R300_CLIPRECT_X_SHIFT 0
-# define R300_CLIPRECT_X_MASK (0x1FFF << 0)
-# define R300_CLIPRECT_Y_SHIFT 13
-# define R300_CLIPRECT_Y_MASK (0x1FFF << 13)
-#define R300_SC_CLIP_RULE 0x43D0
-# define R300_CLIP_OUT (1 << 0)
-# define R300_CLIP_0 (1 << 1)
-# define R300_CLIP_1 (1 << 2)
-# define R300_CLIP_10 (1 << 3)
-# define R300_CLIP_2 (1 << 4)
-# define R300_CLIP_20 (1 << 5)
-# define R300_CLIP_21 (1 << 6)
-# define R300_CLIP_210 (1 << 7)
-# define R300_CLIP_3 (1 << 8)
-# define R300_CLIP_30 (1 << 9)
-# define R300_CLIP_31 (1 << 10)
-# define R300_CLIP_310 (1 << 11)
-# define R300_CLIP_32 (1 << 12)
-# define R300_CLIP_320 (1 << 13)
-# define R300_CLIP_321 (1 << 14)
-# define R300_CLIP_3210 (1 << 15)
-
-/* gap */
-
-#define R300_SC_SCISSORS_TL 0x43E0
-#define R300_SC_SCISSORS_BR 0x43E4
-# define R300_SCISSORS_OFFSET 1440
-# define R300_SCISSORS_X_SHIFT 0
-# define R300_SCISSORS_X_MASK (0x1FFF << 0)
-# define R300_SCISSORS_Y_SHIFT 13
-# define R300_SCISSORS_Y_MASK (0x1FFF << 13)
-
-/* Screen door sample mask */
-#define R300_SC_SCREENDOOR 0x43e8
-
-/* END: Scissors and cliprects */
-
-/* BEGIN: Texture specification */
-
-/*
- * The texture specification dwords are grouped by meaning and not by texture
- * unit. This means that e.g. the offset for texture image unit N is found in
- * register TX_OFFSET_0 + (4*N)
- */
-#define R300_TX_FILTER0_0 0x4400
-#define R300_TX_FILTER0_1 0x4404
-#define R300_TX_FILTER0_2 0x4408
-#define R300_TX_FILTER0_3 0x440c
-#define R300_TX_FILTER0_4 0x4410
-#define R300_TX_FILTER0_5 0x4414
-#define R300_TX_FILTER0_6 0x4418
-#define R300_TX_FILTER0_7 0x441c
-#define R300_TX_FILTER0_8 0x4420
-#define R300_TX_FILTER0_9 0x4424
-#define R300_TX_FILTER0_10 0x4428
-#define R300_TX_FILTER0_11 0x442c
-#define R300_TX_FILTER0_12 0x4430
-#define R300_TX_FILTER0_13 0x4434
-#define R300_TX_FILTER0_14 0x4438
-#define R300_TX_FILTER0_15 0x443c
-# define R300_TX_REPEAT 0
-# define R300_TX_MIRRORED 1
-# define R300_TX_CLAMP_TO_EDGE 2
-# define R300_TX_MIRROR_ONCE_TO_EDGE 3
-# define R300_TX_CLAMP 4
-# define R300_TX_MIRROR_ONCE 5
-# define R300_TX_CLAMP_TO_BORDER 6
-# define R300_TX_MIRROR_ONCE_TO_BORDER 7
-# define R300_TX_WRAP_S_SHIFT 0
-# define R300_TX_WRAP_S_MASK (7 << 0)
-# define R300_TX_WRAP_T_SHIFT 3
-# define R300_TX_WRAP_T_MASK (7 << 3)
-# define R300_TX_WRAP_R_SHIFT 6
-# define R300_TX_WRAP_R_MASK (7 << 6)
-# define R300_TX_MAG_FILTER_4 (0 << 9)
-# define R300_TX_MAG_FILTER_NEAREST (1 << 9)
-# define R300_TX_MAG_FILTER_LINEAR (2 << 9)
-# define R300_TX_MAG_FILTER_ANISO (3 << 9)
-# define R300_TX_MAG_FILTER_MASK (3 << 9)
-# define R300_TX_MIN_FILTER_NEAREST (1 << 11)
-# define R300_TX_MIN_FILTER_LINEAR (2 << 11)
-# define R300_TX_MIN_FILTER_ANISO (3 << 11)
-# define R300_TX_MIN_FILTER_MASK (3 << 11)
-# define R300_TX_MIN_FILTER_MIP_NONE (0 << 13)
-# define R300_TX_MIN_FILTER_MIP_NEAREST (1 << 13)
-# define R300_TX_MIN_FILTER_MIP_LINEAR (2 << 13)
-# define R300_TX_MIN_FILTER_MIP_MASK (3 << 13)
-# define R300_TX_MAX_ANISO_1_TO_1 (0 << 21)
-# define R300_TX_MAX_ANISO_2_TO_1 (1 << 21)
-# define R300_TX_MAX_ANISO_4_TO_1 (2 << 21)
-# define R300_TX_MAX_ANISO_8_TO_1 (3 << 21)
-# define R300_TX_MAX_ANISO_16_TO_1 (4 << 21)
-# define R300_TX_MAX_ANISO_MASK (7 << 21)
-
-#define R300_TX_FILTER1_0 0x4440
-# define R300_CHROMA_KEY_MODE_DISABLE 0
-# define R300_CHROMA_KEY_FORCE 1
-# define R300_CHROMA_KEY_BLEND 2
-# define R300_MC_ROUND_NORMAL (0<<2)
-# define R300_MC_ROUND_MPEG4 (1<<2)
-# define R300_LOD_BIAS_SHIFT 3
-# define R300_LOD_BIAS_MASK 0x1ff8
-# define R300_EDGE_ANISO_EDGE_DIAG (0<<13)
-# define R300_EDGE_ANISO_EDGE_ONLY (1<<13)
-# define R300_MC_COORD_TRUNCATE_DISABLE (0<<14)
-# define R300_MC_COORD_TRUNCATE_MPEG (1<<14)
-# define R300_TX_TRI_PERF_0_8 (0<<15)
-# define R300_TX_TRI_PERF_1_8 (1<<15)
-# define R300_TX_TRI_PERF_1_4 (2<<15)
-# define R300_TX_TRI_PERF_3_8 (3<<15)
-# define R300_ANISO_THRESHOLD_MASK (7<<17)
-
-# define R500_MACRO_SWITCH (1<<22)
-# define R500_BORDER_FIX (1<<31)
-
-#define R300_TX_SIZE_0 0x4480
-# define R300_TX_WIDTHMASK_SHIFT 0
-# define R300_TX_WIDTHMASK_MASK (2047 << 0)
-# define R300_TX_HEIGHTMASK_SHIFT 11
-# define R300_TX_HEIGHTMASK_MASK (2047 << 11)
-# define R300_TX_DEPTHMASK_SHIFT 22
-# define R300_TX_DEPTHMASK_MASK (0xf << 22)
-# define R300_TX_MAX_MIP_LEVEL_SHIFT 26
-# define R300_TX_MAX_MIP_LEVEL_MASK (0xf << 26)
-# define R300_TX_SIZE_PROJECTED (1<<30)
-# define R300_TX_SIZE_TXPITCH_EN (1<<31)
-#define R300_TX_FORMAT_0 0x44C0
- /* The interpretation of the format word by Wladimir van der Laan */
- /* The X, Y, Z and W refer to the layout of the components.
- They are given meanings as R, G, B and Alpha by the swizzle
- specification */
-# define R300_TX_FORMAT_X8 0x0
-# define R500_TX_FORMAT_X1 0x0 // bit set in format 2
-# define R300_TX_FORMAT_X16 0x1
-# define R500_TX_FORMAT_X1_REV 0x0 // bit set in format 2
-# define R300_TX_FORMAT_Y4X4 0x2
-# define R300_TX_FORMAT_Y8X8 0x3
-# define R300_TX_FORMAT_Y16X16 0x4
-# define R300_TX_FORMAT_Z3Y3X2 0x5
-# define R300_TX_FORMAT_Z5Y6X5 0x6
-# define R300_TX_FORMAT_Z6Y5X5 0x7
-# define R300_TX_FORMAT_Z11Y11X10 0x8
-# define R300_TX_FORMAT_Z10Y11X11 0x9
-# define R300_TX_FORMAT_W4Z4Y4X4 0xA
-# define R300_TX_FORMAT_W1Z5Y5X5 0xB
-# define R300_TX_FORMAT_W8Z8Y8X8 0xC
-# define R300_TX_FORMAT_W2Z10Y10X10 0xD
-# define R300_TX_FORMAT_W16Z16Y16X16 0xE
-# define R300_TX_FORMAT_DXT1 0xF
-# define R300_TX_FORMAT_DXT3 0x10
-# define R300_TX_FORMAT_DXT5 0x11
-# define R300_TX_FORMAT_D3DMFT_CxV8U8 0x12 /* no swizzle */
-# define R300_TX_FORMAT_A8R8G8B8 0x13 /* no swizzle */
-# define R300_TX_FORMAT_B8G8_B8G8 0x14 /* no swizzle */
-# define R300_TX_FORMAT_G8R8_G8B8 0x15 /* no swizzle */
-
- /* These two values are wrong, but they're the only values that
- * produce any even vaguely correct results. Can r300 only do 16-bit
- * depth textures?
- */
-# define R300_TX_FORMAT_X24_Y8 0x1e
-# define R300_TX_FORMAT_X32 0x1e
-
- /* 0x16 - some 16 bit green format.. ?? */
-# define R300_TX_FORMAT_3D (1 << 25)
-# define R300_TX_FORMAT_CUBIC_MAP (2 << 25)
-
-# define R300_TX_FORMAT_GAMMA (1 << 21)
-
- /* gap */
- /* Floating point formats */
- /* Note - hardware supports both 16 and 32 bit floating point */
-# define R300_TX_FORMAT_FL_I16 0x18
-# define R300_TX_FORMAT_FL_I16A16 0x19
-# define R300_TX_FORMAT_FL_R16G16B16A16 0x1A
-# define R300_TX_FORMAT_FL_I32 0x1B
-# define R300_TX_FORMAT_FL_I32A32 0x1C
-# define R300_TX_FORMAT_FL_R32G32B32A32 0x1D
- /* alpha modes, convenience mostly */
- /* if you have alpha, pick constant appropriate to the
- number of channels (1 for I8, 2 for I8A8, 4 for R8G8B8A8, etc */
-# define R300_TX_FORMAT_ALPHA_1CH 0x000
-# define R300_TX_FORMAT_ALPHA_2CH 0x200
-# define R300_TX_FORMAT_ALPHA_4CH 0x600
-# define R300_TX_FORMAT_ALPHA_NONE 0xA00
- /* Swizzling */
- /* constants */
-# define R300_TX_FORMAT_X 0
-# define R300_TX_FORMAT_Y 1
-# define R300_TX_FORMAT_Z 2
-# define R300_TX_FORMAT_W 3
-# define R300_TX_FORMAT_ZERO 4
-# define R300_TX_FORMAT_ONE 5
- /* 2.0*Z, everything above 1.0 is set to 0.0 */
-# define R300_TX_FORMAT_CUT_Z 6
- /* 2.0*W, everything above 1.0 is set to 0.0 */
-# define R300_TX_FORMAT_CUT_W 7
-
-# define R300_TX_FORMAT_B_SHIFT 18
-# define R300_TX_FORMAT_G_SHIFT 15
-# define R300_TX_FORMAT_R_SHIFT 12
-# define R300_TX_FORMAT_A_SHIFT 9
- /* Convenience macro to take care of layout and swizzling */
-# define R300_EASY_TX_FORMAT(B, G, R, A, FMT) ( \
- ((R300_TX_FORMAT_##B)<<R300_TX_FORMAT_B_SHIFT) \
- | ((R300_TX_FORMAT_##G)<<R300_TX_FORMAT_G_SHIFT) \
- | ((R300_TX_FORMAT_##R)<<R300_TX_FORMAT_R_SHIFT) \
- | ((R300_TX_FORMAT_##A)<<R300_TX_FORMAT_A_SHIFT) \
- | (R300_TX_FORMAT_##FMT) \
- )
- /* These can be ORed with result of R300_EASY_TX_FORMAT()
- We don't really know what they do. Take values from a
- constant color ? */
-# define R300_TX_FORMAT_CONST_X (1<<5)
-# define R300_TX_FORMAT_CONST_Y (2<<5)
-# define R300_TX_FORMAT_CONST_Z (4<<5)
-# define R300_TX_FORMAT_CONST_W (8<<5)
-
-# define R300_TX_FORMAT_YUV_MODE 0x00800000
-
-#define R300_TX_FORMAT2_0 0x4500 /* obvious missing in gap */
-# define R300_TX_PITCHMASK_SHIFT 0
-# define R300_TX_PITCHMASK_MASK (2047 << 0)
-# define R500_TXFORMAT_MSB (1 << 14)
-# define R500_TXWIDTH_BIT11 (1 << 15)
-# define R500_TXHEIGHT_BIT11 (1 << 16)
-# define R500_POW2FIX2FLT (1 << 17)
-# define R500_SEL_FILTER4_TC0 (0 << 18)
-# define R500_SEL_FILTER4_TC1 (1 << 18)
-# define R500_SEL_FILTER4_TC2 (2 << 18)
-# define R500_SEL_FILTER4_TC3 (3 << 18)
-
-#define R300_TX_OFFSET_0 0x4540
-#define R300_TX_OFFSET_1 0x4544
-#define R300_TX_OFFSET_2 0x4548
-#define R300_TX_OFFSET_3 0x454C
-#define R300_TX_OFFSET_4 0x4550
-#define R300_TX_OFFSET_5 0x4554
-#define R300_TX_OFFSET_6 0x4558
-#define R300_TX_OFFSET_7 0x455C
- /* BEGIN: Guess from R200 */
-# define R300_TXO_ENDIAN_NO_SWAP (0 << 0)
-# define R300_TXO_ENDIAN_BYTE_SWAP (1 << 0)
-# define R300_TXO_ENDIAN_WORD_SWAP (2 << 0)
-# define R300_TXO_ENDIAN_HALFDW_SWAP (3 << 0)
-# define R300_TXO_MACRO_TILE (1 << 2)
-# define R300_TXO_MICRO_TILE_LINEAR (0 << 3)
-# define R300_TXO_MICRO_TILE (1 << 3)
-# define R300_TXO_MICRO_TILE_SQUARE (2 << 3)
-# define R300_TXO_OFFSET_MASK 0xffffffe0
-# define R300_TXO_OFFSET_SHIFT 5
- /* END: Guess from R200 */
-
-/* 32 bit chroma key */
-#define R300_TX_CHROMA_KEY_0 0x4580
-#define R300_TX_CHROMA_KEY_1 0x4584
-#define R300_TX_CHROMA_KEY_2 0x4588
-#define R300_TX_CHROMA_KEY_3 0x458c
-#define R300_TX_CHROMA_KEY_4 0x4590
-#define R300_TX_CHROMA_KEY_5 0x4594
-#define R300_TX_CHROMA_KEY_6 0x4598
-#define R300_TX_CHROMA_KEY_7 0x459c
-#define R300_TX_CHROMA_KEY_8 0x45a0
-#define R300_TX_CHROMA_KEY_9 0x45a4
-#define R300_TX_CHROMA_KEY_10 0x45a8
-#define R300_TX_CHROMA_KEY_11 0x45ac
-#define R300_TX_CHROMA_KEY_12 0x45b0
-#define R300_TX_CHROMA_KEY_13 0x45b4
-#define R300_TX_CHROMA_KEY_14 0x45b8
-#define R300_TX_CHROMA_KEY_15 0x45bc
-/* ff00ff00 == { 0, 1.0, 0, 1.0 } */
-
-/* Border Color */
-#define R300_TX_BORDER_COLOR_0 0x45c0
-#define R300_TX_BORDER_COLOR_1 0x45c4
-#define R300_TX_BORDER_COLOR_2 0x45c8
-#define R300_TX_BORDER_COLOR_3 0x45cc
-#define R300_TX_BORDER_COLOR_4 0x45d0
-#define R300_TX_BORDER_COLOR_5 0x45d4
-#define R300_TX_BORDER_COLOR_6 0x45d8
-#define R300_TX_BORDER_COLOR_7 0x45dc
-#define R300_TX_BORDER_COLOR_8 0x45e0
-#define R300_TX_BORDER_COLOR_9 0x45e4
-#define R300_TX_BORDER_COLOR_10 0x45e8
-#define R300_TX_BORDER_COLOR_11 0x45ec
-#define R300_TX_BORDER_COLOR_12 0x45f0
-#define R300_TX_BORDER_COLOR_13 0x45f4
-#define R300_TX_BORDER_COLOR_14 0x45f8
-#define R300_TX_BORDER_COLOR_15 0x45fc
-
-
-/* END: Texture specification */
-
-/* BEGIN: Fragment program instruction set */
-
-/* Fragment programs are written directly into register space.
- * There are separate instruction streams for texture instructions and ALU
- * instructions.
- * In order to synchronize these streams, the program is divided into up
- * to 4 nodes. Each node begins with a number of TEX operations, followed
- * by a number of ALU operations.
- * The first node can have zero TEX ops, all subsequent nodes must have at
- * least
- * one TEX ops.
- * All nodes must have at least one ALU op.
- *
- * The index of the last node is stored in PFS_CNTL_0: A value of 0 means
- * 1 node, a value of 3 means 4 nodes.
- * The total amount of instructions is defined in PFS_CNTL_2. The offsets are
- * offsets into the respective instruction streams, while *_END points to the
- * last instruction relative to this offset.
- */
-#define R300_US_CONFIG 0x4600
-# define R300_PFS_CNTL_LAST_NODES_SHIFT 0
-# define R300_PFS_CNTL_LAST_NODES_MASK (3 << 0)
-# define R300_PFS_CNTL_FIRST_NODE_HAS_TEX (1 << 3)
-#define R300_US_PIXSIZE 0x4604
-/* There is an unshifted value here which has so far always been equal to the
- * index of the highest used temporary register.
- */
-#define R300_US_CODE_OFFSET 0x4608
-# define R300_PFS_CNTL_ALU_OFFSET_SHIFT 0
-# define R300_PFS_CNTL_ALU_OFFSET_MASK (63 << 0)
-# define R300_PFS_CNTL_ALU_END_SHIFT 6
-# define R300_PFS_CNTL_ALU_END_MASK (63 << 6)
-# define R300_PFS_CNTL_TEX_OFFSET_SHIFT 13
-# define R300_PFS_CNTL_TEX_OFFSET_MASK (31 << 13)
-# define R300_PFS_CNTL_TEX_END_SHIFT 18
-# define R300_PFS_CNTL_TEX_END_MASK (31 << 18)
-# define R400_PFS_CNTL_TEX_OFFSET_MSB_SHIFT 24
-# define R400_PFS_CNTL_TEX_OFFSET_MSB_MASK (0xf << 24)
-# define R400_PFS_CNTL_TEX_END_MSB_SHIFT 28
-# define R400_PFS_CNTL_TEX_END_MSB_MASK (0xf << 28)
-
-/* gap */
-
-/* Nodes are stored backwards. The last active node is always stored in
- * PFS_NODE_3.
- * Example: In a 2-node program, NODE_0 and NODE_1 are set to 0. The
- * first node is stored in NODE_2, the second node is stored in NODE_3.
- *
- * Offsets are relative to the master offset from PFS_CNTL_2.
- */
-#define R300_US_CODE_ADDR_0 0x4610
-#define R300_US_CODE_ADDR_1 0x4614
-#define R300_US_CODE_ADDR_2 0x4618
-#define R300_US_CODE_ADDR_3 0x461C
-# define R300_ALU_START_SHIFT 0
-# define R300_ALU_START_MASK (63 << 0)
-# define R300_ALU_SIZE_SHIFT 6
-# define R300_ALU_SIZE_MASK (63 << 6)
-# define R300_TEX_START_SHIFT 12
-# define R300_TEX_START_MASK (31 << 12)
-# define R300_TEX_SIZE_SHIFT 17
-# define R300_TEX_SIZE_MASK (31 << 17)
-# define R300_RGBA_OUT (1 << 22)
-# define R300_W_OUT (1 << 23)
-# define R400_TEX_START_MSB_SHIFT 24
-# define R400_TEX_START_MSG_MASK (0xf << 24)
-# define R400_TEX_SIZE_MSB_SHIFT 28
-# define R400_TEX_SIZE_MSG_MASK (0xf << 28)
-
-/* TEX
- * As far as I can tell, texture instructions cannot write into output
- * registers directly. A subsequent ALU instruction is always necessary,
- * even if it's just MAD o0, r0, 1, 0
- */
-#define R300_US_TEX_INST_0 0x4620
-# define R300_SRC_ADDR_SHIFT 0
-# define R300_SRC_ADDR_MASK (31 << 0)
-# define R300_DST_ADDR_SHIFT 6
-# define R300_DST_ADDR_MASK (31 << 6)
-# define R300_TEX_ID_SHIFT 11
-# define R300_TEX_ID_MASK (15 << 11)
-# define R300_TEX_INST_SHIFT 15
-# define R300_TEX_OP_NOP 0
-# define R300_TEX_OP_LD 1
-# define R300_TEX_OP_KIL 2
-# define R300_TEX_OP_TXP 3
-# define R300_TEX_OP_TXB 4
-# define R300_TEX_INST_MASK (7 << 15)
-# define R400_SRC_ADDR_EXT_BIT (1 << 19)
-# define R400_DST_ADDR_EXT_BIT (1 << 20)
-
-/* Output format from the unfied shader */
-#define R300_US_OUT_FMT 0x46A4
-# define R300_US_OUT_FMT_C4_8 (0 << 0)
-# define R300_US_OUT_FMT_C4_10 (1 << 0)
-# define R300_US_OUT_FMT_C4_10_GAMMA (2 << 0)
-# define R300_US_OUT_FMT_C_16 (3 << 0)
-# define R300_US_OUT_FMT_C2_16 (4 << 0)
-# define R300_US_OUT_FMT_C4_16 (5 << 0)
-# define R300_US_OUT_FMT_C_16_MPEG (6 << 0)
-# define R300_US_OUT_FMT_C2_16_MPEG (7 << 0)
-# define R300_US_OUT_FMT_C2_4 (8 << 0)
-# define R300_US_OUT_FMT_C_3_3_2 (9 << 0)
-# define R300_US_OUT_FMT_C_6_5_6 (10 << 0)
-# define R300_US_OUT_FMT_C_11_11_10 (11 << 0)
-# define R300_US_OUT_FMT_C_10_11_11 (12 << 0)
-# define R300_US_OUT_FMT_C_2_10_10_10 (13 << 0)
-/* reserved */
-# define R300_US_OUT_FMT_UNUSED (15 << 0)
-# define R300_US_OUT_FMT_C_16_FP (16 << 0)
-# define R300_US_OUT_FMT_C2_16_FP (17 << 0)
-# define R300_US_OUT_FMT_C4_16_FP (18 << 0)
-# define R300_US_OUT_FMT_C_32_FP (19 << 0)
-# define R300_US_OUT_FMT_C2_32_FP (20 << 0)
-# define R300_US_OUT_FMT_C4_32_FP (20 << 0)
-
-/* ALU
- * The ALU instructions register blocks are enumerated according to the order
- * in which fglrx. I assume there is space for 64 instructions, since
- * each block has space for a maximum of 64 DWORDs, and this matches reported
- * native limits.
- *
- * The basic functional block seems to be one MAD for each color and alpha,
- * and an adder that adds all components after the MUL.
- * - ADD, MUL, MAD etc.: use MAD with appropriate neutral operands
- * - DP4: Use OUTC_DP4, OUTA_DP4
- * - DP3: Use OUTC_DP3, OUTA_DP4, appropriate alpha operands
- * - DPH: Use OUTC_DP4, OUTA_DP4, appropriate alpha operands
- * - CMPH: If ARG2 > 0.5, return ARG0, else return ARG1
- * - CMP: If ARG2 < 0, return ARG1, else return ARG0
- * - FLR: use FRC+MAD
- * - XPD: use MAD+MAD
- * - SGE, SLT: use MAD+CMP
- * - RSQ: use ABS modifier for argument
- * - Use OUTC_REPL_ALPHA to write results of an alpha-only operation
- * (e.g. RCP) into color register
- * - apparently, there's no quick DST operation
- * - fglrx set FPI2_UNKNOWN_31 on a "MAD fragment.color, tmp0, tmp1, tmp2"
- * - fglrx set FPI2_UNKNOWN_31 on a "MAX r2, r1, c0"
- * - fglrx once set FPI0_UNKNOWN_31 on a "FRC r1, r1"
- *
- * Operand selection
- * First stage selects three sources from the available registers and
- * constant parameters. This is defined in INSTR1 (color) and INSTR3 (alpha).
- * fglrx sorts the three source fields: Registers before constants,
- * lower indices before higher indices; I do not know whether this is
- * necessary.
- *
- * fglrx fills unused sources with "read constant 0"
- * According to specs, you cannot select more than two different constants.
- *
- * Second stage selects the operands from the sources. This is defined in
- * INSTR0 (color) and INSTR2 (alpha). You can also select the special constants
- * zero and one.
- * Swizzling and negation happens in this stage, as well.
- *
- * Important: Color and alpha seem to be mostly separate, i.e. their sources
- * selection appears to be fully independent (the register storage is probably
- * physically split into a color and an alpha section).
- * However (because of the apparent physical split), there is some interaction
- * WRT swizzling. If, for example, you want to load an R component into an
- * Alpha operand, this R component is taken from a *color* source, not from
- * an alpha source. The corresponding register doesn't even have to appear in
- * the alpha sources list. (I hope this all makes sense to you)
- *
- * Destination selection
- * The destination register index is in FPI1 (color) and FPI3 (alpha)
- * together with enable bits.
- * There are separate enable bits for writing into temporary registers
- * (DSTC_REG_* /DSTA_REG) and program output registers (DSTC_OUTPUT_*
- * /DSTA_OUTPUT). You can write to both at once, or not write at all (the
- * same index must be used for both).
- *
- * Note: There is a special form for LRP
- * - Argument order is the same as in ARB_fragment_program.
- * - Operation is MAD
- * - ARG1 is set to ARGC_SRC1C_LRP/ARGC_SRC1A_LRP
- * - Set FPI0/FPI2_SPECIAL_LRP
- * Arbitrary LRP (including support for swizzling) requires vanilla MAD+MAD
- */
-#define R300_US_ALU_RGB_ADDR_0 0x46C0
-# define R300_ALU_SRC0C_SHIFT 0
-# define R300_ALU_SRC0C_MASK (31 << 0)
-# define R300_ALU_SRC0C_CONST (1 << 5)
-# define R300_ALU_SRC1C_SHIFT 6
-# define R300_ALU_SRC1C_MASK (31 << 6)
-# define R300_ALU_SRC1C_CONST (1 << 11)
-# define R300_ALU_SRC2C_SHIFT 12
-# define R300_ALU_SRC2C_MASK (31 << 12)
-# define R300_ALU_SRC2C_CONST (1 << 17)
-# define R300_ALU_SRC_MASK 0x0003ffff
-# define R300_ALU_DSTC_SHIFT 18
-# define R300_ALU_DSTC_MASK (31 << 18)
-# define R300_ALU_DSTC_REG_MASK_SHIFT 23
-# define R300_ALU_DSTC_REG_X (1 << 23)
-# define R300_ALU_DSTC_REG_Y (1 << 24)
-# define R300_ALU_DSTC_REG_Z (1 << 25)
-# define R300_ALU_DSTC_OUTPUT_MASK_SHIFT 26
-# define R300_ALU_DSTC_OUTPUT_X (1 << 26)
-# define R300_ALU_DSTC_OUTPUT_Y (1 << 27)
-# define R300_ALU_DSTC_OUTPUT_Z (1 << 28)
-# define R300_RGB_TARGET(x) ((x) << 29)
-
-#define R300_US_ALU_ALPHA_ADDR_0 0x47C0
-# define R300_ALU_SRC0A_SHIFT 0
-# define R300_ALU_SRC0A_MASK (31 << 0)
-# define R300_ALU_SRC0A_CONST (1 << 5)
-# define R300_ALU_SRC1A_SHIFT 6
-# define R300_ALU_SRC1A_MASK (31 << 6)
-# define R300_ALU_SRC1A_CONST (1 << 11)
-# define R300_ALU_SRC2A_SHIFT 12
-# define R300_ALU_SRC2A_MASK (31 << 12)
-# define R300_ALU_SRC2A_CONST (1 << 17)
-# define R300_ALU_SRC_MASK 0x0003ffff
-# define R300_ALU_DSTA_SHIFT 18
-# define R300_ALU_DSTA_MASK (31 << 18)
-# define R300_ALU_DSTA_REG (1 << 23)
-# define R300_ALU_DSTA_OUTPUT (1 << 24)
-# define R300_ALU_DSTA_DEPTH (1 << 27)
-# define R300_ALPHA_TARGET(x) ((x) << 25)
-
-#define R300_US_ALU_RGB_INST_0 0x48C0
-# define R300_ALU_ARGC_SRC0C_XYZ 0
-# define R300_ALU_ARGC_SRC0C_XXX 1
-# define R300_ALU_ARGC_SRC0C_YYY 2
-# define R300_ALU_ARGC_SRC0C_ZZZ 3
-# define R300_ALU_ARGC_SRC1C_XYZ 4
-# define R300_ALU_ARGC_SRC1C_XXX 5
-# define R300_ALU_ARGC_SRC1C_YYY 6
-# define R300_ALU_ARGC_SRC1C_ZZZ 7
-# define R300_ALU_ARGC_SRC2C_XYZ 8
-# define R300_ALU_ARGC_SRC2C_XXX 9
-# define R300_ALU_ARGC_SRC2C_YYY 10
-# define R300_ALU_ARGC_SRC2C_ZZZ 11
-# define R300_ALU_ARGC_SRC0A 12
-# define R300_ALU_ARGC_SRC1A 13
-# define R300_ALU_ARGC_SRC2A 14
-# define R300_ALU_ARGC_SRCP_XYZ 15
-# define R300_ALU_ARGC_SRCP_XXX 16
-# define R300_ALU_ARGC_SRCP_YYY 17
-# define R300_ALU_ARGC_SRCP_ZZZ 18
-# define R300_ALU_ARGC_SRCP_WWW 19
-# define R300_ALU_ARGC_ZERO 20
-# define R300_ALU_ARGC_ONE 21
-# define R300_ALU_ARGC_HALF 22
-# define R300_ALU_ARGC_SRC0C_YZX 23
-# define R300_ALU_ARGC_SRC1C_YZX 24
-# define R300_ALU_ARGC_SRC2C_YZX 25
-# define R300_ALU_ARGC_SRC0C_ZXY 26
-# define R300_ALU_ARGC_SRC1C_ZXY 27
-# define R300_ALU_ARGC_SRC2C_ZXY 28
-# define R300_ALU_ARGC_SRC0CA_WZY 29
-# define R300_ALU_ARGC_SRC1CA_WZY 30
-# define R300_ALU_ARGC_SRC2CA_WZY 31
-
-# define R300_ALU_ARG0C_SHIFT 0
-# define R300_ALU_ARG0C_MASK (31 << 0)
-# define R300_ALU_ARG0C_NOP (0 << 5)
-# define R300_ALU_ARG0C_NEG (1 << 5)
-# define R300_ALU_ARG0C_ABS (2 << 5)
-# define R300_ALU_ARG0C_NAB (3 << 5)
-# define R300_ALU_ARG1C_SHIFT 7
-# define R300_ALU_ARG1C_MASK (31 << 7)
-# define R300_ALU_ARG1C_NOP (0 << 12)
-# define R300_ALU_ARG1C_NEG (1 << 12)
-# define R300_ALU_ARG1C_ABS (2 << 12)
-# define R300_ALU_ARG1C_NAB (3 << 12)
-# define R300_ALU_ARG2C_SHIFT 14
-# define R300_ALU_ARG2C_MASK (31 << 14)
-# define R300_ALU_ARG2C_NOP (0 << 19)
-# define R300_ALU_ARG2C_NEG (1 << 19)
-# define R300_ALU_ARG2C_ABS (2 << 19)
-# define R300_ALU_ARG2C_NAB (3 << 19)
-# define R300_ALU_SRCP_1_MINUS_2_SRC0 (0 << 21)
-# define R300_ALU_SRCP_SRC1_MINUS_SRC0 (1 << 21)
-# define R300_ALU_SRCP_SRC1_PLUS_SRC0 (2 << 21)
-# define R300_ALU_SRCP_1_MINUS_SRC0 (3 << 21)
-
-# define R300_ALU_OUTC_MAD (0 << 23)
-# define R300_ALU_OUTC_DP3 (1 << 23)
-# define R300_ALU_OUTC_DP4 (2 << 23)
-# define R300_ALU_OUTC_D2A (3 << 23)
-# define R300_ALU_OUTC_MIN (4 << 23)
-# define R300_ALU_OUTC_MAX (5 << 23)
-# define R300_ALU_OUTC_CND (7 << 23)
-# define R300_ALU_OUTC_CMP (8 << 23)
-# define R300_ALU_OUTC_FRC (9 << 23)
-# define R300_ALU_OUTC_REPL_ALPHA (10 << 23)
-
-# define R300_ALU_OUTC_MOD_NOP (0 << 27)
-# define R300_ALU_OUTC_MOD_MUL2 (1 << 27)
-# define R300_ALU_OUTC_MOD_MUL4 (2 << 27)
-# define R300_ALU_OUTC_MOD_MUL8 (3 << 27)
-# define R300_ALU_OUTC_MOD_DIV2 (4 << 27)
-# define R300_ALU_OUTC_MOD_DIV4 (5 << 27)
-# define R300_ALU_OUTC_MOD_DIV8 (6 << 27)
-
-# define R300_ALU_OUTC_CLAMP (1 << 30)
-# define R300_ALU_INSERT_NOP (1 << 31)
-
-#define R300_US_ALU_ALPHA_INST_0 0x49C0
-# define R300_ALU_ARGA_SRC0C_X 0
-# define R300_ALU_ARGA_SRC0C_Y 1
-# define R300_ALU_ARGA_SRC0C_Z 2
-# define R300_ALU_ARGA_SRC1C_X 3
-# define R300_ALU_ARGA_SRC1C_Y 4
-# define R300_ALU_ARGA_SRC1C_Z 5
-# define R300_ALU_ARGA_SRC2C_X 6
-# define R300_ALU_ARGA_SRC2C_Y 7
-# define R300_ALU_ARGA_SRC2C_Z 8
-# define R300_ALU_ARGA_SRC0A 9
-# define R300_ALU_ARGA_SRC1A 10
-# define R300_ALU_ARGA_SRC2A 11
-# define R300_ALU_ARGA_SRCP_X 12
-# define R300_ALU_ARGA_SRCP_Y 13
-# define R300_ALU_ARGA_SRCP_Z 14
-# define R300_ALU_ARGA_SRCP_W 15
-
-# define R300_ALU_ARGA_ZERO 16
-# define R300_ALU_ARGA_ONE 17
-# define R300_ALU_ARGA_HALF 18
-# define R300_ALU_ARG0A_SHIFT 0
-# define R300_ALU_ARG0A_MASK (31 << 0)
-# define R300_ALU_ARG0A_NOP (0 << 5)
-# define R300_ALU_ARG0A_NEG (1 << 5)
-# define R300_ALU_ARG0A_ABS (2 << 5)
-# define R300_ALU_ARG0A_NAB (3 << 5)
-# define R300_ALU_ARG1A_SHIFT 7
-# define R300_ALU_ARG1A_MASK (31 << 7)
-# define R300_ALU_ARG1A_NOP (0 << 12)
-# define R300_ALU_ARG1A_NEG (1 << 12)
-# define R300_ALU_ARG1A_ABS (2 << 12)
-# define R300_ALU_ARG1A_NAB (3 << 12)
-# define R300_ALU_ARG2A_SHIFT 14
-# define R300_ALU_ARG2A_MASK (31 << 14)
-# define R300_ALU_ARG2A_NOP (0 << 19)
-# define R300_ALU_ARG2A_NEG (1 << 19)
-# define R300_ALU_ARG2A_ABS (2 << 19)
-# define R300_ALU_ARG2A_NAB (3 << 19)
-# define R300_ALU_SRCP_1_MINUS_2_SRC0 (0 << 21)
-# define R300_ALU_SRCP_SRC1_MINUS_SRC0 (1 << 21)
-# define R300_ALU_SRCP_SRC1_PLUS_SRC0 (2 << 21)
-# define R300_ALU_SRCP_1_MINUS_SRC0 (3 << 21)
-
-# define R300_ALU_OUTA_MAD (0 << 23)
-# define R300_ALU_OUTA_DP4 (1 << 23)
-# define R300_ALU_OUTA_MIN (2 << 23)
-# define R300_ALU_OUTA_MAX (3 << 23)
-# define R300_ALU_OUTA_CND (5 << 23)
-# define R300_ALU_OUTA_CMP (6 << 23)
-# define R300_ALU_OUTA_FRC (7 << 23)
-# define R300_ALU_OUTA_EX2 (8 << 23)
-# define R300_ALU_OUTA_LG2 (9 << 23)
-# define R300_ALU_OUTA_RCP (10 << 23)
-# define R300_ALU_OUTA_RSQ (11 << 23)
-
-# define R300_ALU_OUTA_MOD_NOP (0 << 27)
-# define R300_ALU_OUTA_MOD_MUL2 (1 << 27)
-# define R300_ALU_OUTA_MOD_MUL4 (2 << 27)
-# define R300_ALU_OUTA_MOD_MUL8 (3 << 27)
-# define R300_ALU_OUTA_MOD_DIV2 (4 << 27)
-# define R300_ALU_OUTA_MOD_DIV4 (5 << 27)
-# define R300_ALU_OUTA_MOD_DIV8 (6 << 27)
-
-# define R300_ALU_OUTA_CLAMP (1 << 30)
-/* END: Fragment program instruction set */
-
-/* R4xx extended fragment shader registers. */
-#define R400_US_ALU_EXT_ADDR_0 0x4ac0 /* up to 63 (0x4bbc) */
-# define R400_ADDR_EXT_RGB_MSB_BIT(x) (1 << (x))
-# define R400_ADDRD_EXT_RGB_MSB_BIT 0x08
-# define R400_ADDR_EXT_A_MSB_BIT(x) (1 << ((x) + 4))
-# define R400_ADDRD_EXT_A_MSB_BIT 0x80
-
-#define R400_US_CODE_BANK 0x46b8
-# define R400_BANK_SHIFT 0
-# define R400_BANK_MASK 0xf
-# define R400_R390_MODE_ENABLE (1 << 4)
-#define R400_US_CODE_EXT 0x46bc
-# define R400_ALU_OFFSET_MSB_SHIFT 0
-# define R400_ALU_OFFSET_MSB_MASK (0x7 << 0)
-# define R400_ALU_SIZE_MSB_SHIFT 3
-# define R400_ALU_SIZE_MSB_MASK (0x7 << 3)
-# define R400_ALU_START0_MSB_SHIFT 6
-# define R400_ALU_START0_MSB_MASK (0x7 << 6)
-# define R400_ALU_SIZE0_MSB_SHIFT 9
-# define R400_ALU_SIZE0_MSB_MASK (0x7 << 9)
-# define R400_ALU_START1_MSB_SHIFT 12
-# define R400_ALU_START1_MSB_MASK (0x7 << 12)
-# define R400_ALU_SIZE1_MSB_SHIFT 15
-# define R400_ALU_SIZE1_MSB_MASK (0x7 << 15)
-# define R400_ALU_START2_MSB_SHIFT 18
-# define R400_ALU_START2_MSB_MASK (0x7 << 18)
-# define R400_ALU_SIZE2_MSB_SHIFT 21
-# define R400_ALU_SIZE2_MSB_MASK (0x7 << 21)
-# define R400_ALU_START3_MSB_SHIFT 24
-# define R400_ALU_START3_MSB_MASK (0x7 << 24)
-# define R400_ALU_SIZE3_MSB_SHIFT 27
-# define R400_ALU_SIZE3_MSB_MASK (0x7 << 27)
-/* END: R4xx extended fragment shader registers. */
-
-/* Fog: Fog Blending Enable */
-#define R300_FG_FOG_BLEND 0x4bc0
-# define R300_FG_FOG_BLEND_DISABLE (0 << 0)
-# define R300_FG_FOG_BLEND_ENABLE (1 << 0)
-# define R300_FG_FOG_BLEND_FN_LINEAR (0 << 1)
-# define R300_FG_FOG_BLEND_FN_EXP (1 << 1)
-# define R300_FG_FOG_BLEND_FN_EXP2 (2 << 1)
-# define R300_FG_FOG_BLEND_FN_CONSTANT (3 << 1)
-# define R300_FG_FOG_BLEND_FN_MASK (3 << 1)
-
-/* Fog: Red Component of Fog Color */
-#define R300_FG_FOG_COLOR_R 0x4bc8
-/* Fog: Green Component of Fog Color */
-#define R300_FG_FOG_COLOR_G 0x4bcc
-/* Fog: Blue Component of Fog Color */
-#define R300_FG_FOG_COLOR_B 0x4bd0
-# define R300_FG_FOG_COLOR_MASK 0x000003ff
-
-/* Fog: Constant Factor for Fog Blending */
-#define R300_FG_FOG_FACTOR 0x4bc4
-# define FG_FOG_FACTOR_MASK 0x000003ff
-
-/* Fog: Alpha function */
-#define R300_FG_ALPHA_FUNC 0x4bd4
-# define R300_FG_ALPHA_FUNC_VAL_MASK 0x000000ff
-# define R300_FG_ALPHA_FUNC_NEVER (0 << 8)
-# define R300_FG_ALPHA_FUNC_LESS (1 << 8)
-# define R300_FG_ALPHA_FUNC_EQUAL (2 << 8)
-# define R300_FG_ALPHA_FUNC_LE (3 << 8)
-# define R300_FG_ALPHA_FUNC_GREATER (4 << 8)
-# define R300_FG_ALPHA_FUNC_NOTEQUAL (5 << 8)
-# define R300_FG_ALPHA_FUNC_GE (6 << 8)
-# define R300_FG_ALPHA_FUNC_ALWAYS (7 << 8)
-# define R300_ALPHA_TEST_OP_MASK (7 << 8)
-# define R300_FG_ALPHA_FUNC_DISABLE (0 << 11)
-# define R300_FG_ALPHA_FUNC_ENABLE (1 << 11)
-
-# define R500_FG_ALPHA_FUNC_10BIT (0 << 12)
-# define R500_FG_ALPHA_FUNC_8BIT (1 << 12)
-
-# define R300_FG_ALPHA_FUNC_MASK_DISABLE (0 << 16)
-# define R300_FG_ALPHA_FUNC_MASK_ENABLE (1 << 16)
-# define R300_FG_ALPHA_FUNC_CFG_2_OF_4 (0 << 17)
-# define R300_FG_ALPHA_FUNC_CFG_3_OF_6 (1 << 17)
-
-# define R300_FG_ALPHA_FUNC_DITH_DISABLE (0 << 20)
-# define R300_FG_ALPHA_FUNC_DITH_ENABLE (1 << 20)
-
-# define R500_FG_ALPHA_FUNC_OFFSET_DISABLE (0 << 24)
-# define R500_FG_ALPHA_FUNC_OFFSET_ENABLE (1 << 24) /* Not supported in R520 */
-# define R500_FG_ALPHA_FUNC_DISC_ZERO_MASK_DISABLE (0 << 25)
-# define R500_FG_ALPHA_FUNC_DISC_ZERO_MASK_ENABLE (1 << 25)
-
-# define R500_FG_ALPHA_FUNC_FP16_DISABLE (0 << 28)
-# define R500_FG_ALPHA_FUNC_FP16_ENABLE (1 << 28)
-
-
-/* Fog: Where does the depth come from? */
-#define R300_FG_DEPTH_SRC 0x4bd8
-# define R300_FG_DEPTH_SRC_SCAN (0 << 0)
-# define R300_FG_DEPTH_SRC_SHADER (1 << 0)
-
-/* Fog: Alpha Compare Value */
-#define R500_FG_ALPHA_VALUE 0x4be0
-# define R500_FG_ALPHA_VALUE_MASK 0x0000ffff
-
-#define RV530_FG_ZBREG_DEST 0x4be8
-# define RV530_FG_ZBREG_DEST_PIPE_SELECT_0 (1 << 0)
-# define RV530_FG_ZBREG_DEST_PIPE_SELECT_1 (1 << 1)
-# define RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL (3 << 0)
-
-/* gap */
-
-/* Fragment program parameters in 7.16 floating point */
-#define R300_PFS_PARAM_0_X 0x4C00
-#define R300_PFS_PARAM_0_Y 0x4C04
-#define R300_PFS_PARAM_0_Z 0x4C08
-#define R300_PFS_PARAM_0_W 0x4C0C
-/* last consts */
-#define R300_PFS_PARAM_31_X 0x4DF0
-#define R300_PFS_PARAM_31_Y 0x4DF4
-#define R300_PFS_PARAM_31_Z 0x4DF8
-#define R300_PFS_PARAM_31_W 0x4DFC
-
-/* Unpipelined. */
-#define R300_RB3D_CCTL 0x4e00
-# define R300_RB3D_CCTL_NUM_MULTIWRITES_1_BUFFER (0 << 5)
-# define R300_RB3D_CCTL_NUM_MULTIWRITES_2_BUFFERS (1 << 5)
-# define R300_RB3D_CCTL_NUM_MULTIWRITES_3_BUFFERS (2 << 5)
-# define R300_RB3D_CCTL_NUM_MULTIWRITES_4_BUFFERS (3 << 5)
-# define R300_RB3D_CCTL_CLRCMP_FLIPE_DISABLE (0 << 7)
-# define R300_RB3D_CCTL_CLRCMP_FLIPE_ENABLE (1 << 7)
-# define R300_RB3D_CCTL_AA_COMPRESSION_DISABLE (0 << 9)
-# define R300_RB3D_CCTL_AA_COMPRESSION_ENABLE (1 << 9)
-# define R300_RB3D_CCTL_CMASK_DISABLE (0 << 10)
-# define R300_RB3D_CCTL_CMASK_ENABLE (1 << 10)
-/* reserved */
-# define R300_RB3D_CCTL_INDEPENDENT_COLOR_CHANNEL_MASK_DISABLE (0 << 12)
-# define R300_RB3D_CCTL_INDEPENDENT_COLOR_CHANNEL_MASK_ENABLE (1 << 12)
-# define R300_RB3D_CCTL_WRITE_COMPRESSION_ENABLE (0 << 13)
-# define R300_RB3D_CCTL_WRITE_COMPRESSION_DISABLE (1 << 13)
-# define R300_RB3D_CCTL_INDEPENDENT_COLORFORMAT_ENABLE_DISABLE (0 << 14)
-# define R300_RB3D_CCTL_INDEPENDENT_COLORFORMAT_ENABLE_ENABLE (1 << 14)
-
-
-/* Notes:
- * - AFAIK fglrx always sets BLEND_UNKNOWN when blending is used in
- * the application
- * - AFAIK fglrx always sets BLEND_NO_SEPARATE when CBLEND and ABLEND
- * are set to the same
- * function (both registers are always set up completely in any case)
- * - Most blend flags are simply copied from R200 and not tested yet
- */
-#define R300_RB3D_CBLEND 0x4E04
-#define R300_RB3D_ABLEND 0x4E08
-/* the following only appear in CBLEND */
-# define R300_ALPHA_BLEND_ENABLE (1 << 0)
-# define R300_SEPARATE_ALPHA_ENABLE (1 << 1)
-# define R300_READ_ENABLE (1 << 2)
-# define R300_DISCARD_SRC_PIXELS_DIS (0 << 3)
-# define R300_DISCARD_SRC_PIXELS_SRC_ALPHA_0 (1 << 3)
-# define R300_DISCARD_SRC_PIXELS_SRC_COLOR_0 (2 << 3)
-# define R300_DISCARD_SRC_PIXELS_SRC_ALPHA_COLOR_0 (3 << 3)
-# define R300_DISCARD_SRC_PIXELS_SRC_ALPHA_1 (4 << 3)
-# define R300_DISCARD_SRC_PIXELS_SRC_COLOR_1 (5 << 3)
-# define R300_DISCARD_SRC_PIXELS_SRC_ALPHA_COLOR_1 (6 << 3)
-
-/* the following are shared between CBLEND and ABLEND */
-# define R300_FCN_MASK (3 << 12)
-# define R300_COMB_FCN_ADD_CLAMP (0 << 12)
-# define R300_COMB_FCN_ADD_NOCLAMP (1 << 12)
-# define R300_COMB_FCN_SUB_CLAMP (2 << 12)
-# define R300_COMB_FCN_SUB_NOCLAMP (3 << 12)
-# define R300_COMB_FCN_MIN (4 << 12)
-# define R300_COMB_FCN_MAX (5 << 12)
-# define R300_COMB_FCN_RSUB_CLAMP (6 << 12)
-# define R300_COMB_FCN_RSUB_NOCLAMP (7 << 12)
-# define R300_BLEND_GL_ZERO (32)
-# define R300_BLEND_GL_ONE (33)
-# define R300_BLEND_GL_SRC_COLOR (34)
-# define R300_BLEND_GL_ONE_MINUS_SRC_COLOR (35)
-# define R300_BLEND_GL_DST_COLOR (36)
-# define R300_BLEND_GL_ONE_MINUS_DST_COLOR (37)
-# define R300_BLEND_GL_SRC_ALPHA (38)
-# define R300_BLEND_GL_ONE_MINUS_SRC_ALPHA (39)
-# define R300_BLEND_GL_DST_ALPHA (40)
-# define R300_BLEND_GL_ONE_MINUS_DST_ALPHA (41)
-# define R300_BLEND_GL_SRC_ALPHA_SATURATE (42)
-# define R300_BLEND_GL_CONST_COLOR (43)
-# define R300_BLEND_GL_ONE_MINUS_CONST_COLOR (44)
-# define R300_BLEND_GL_CONST_ALPHA (45)
-# define R300_BLEND_GL_ONE_MINUS_CONST_ALPHA (46)
-# define R300_BLEND_MASK (63)
-# define R300_SRC_BLEND_SHIFT (16)
-# define R300_DST_BLEND_SHIFT (24)
-
-/* Constant color used by the blender. Pipelined through the blender.
- * Note: For R520, this field is ignored, use RB3D_CONSTANT_COLOR_GB__BLUE,
- * RB3D_CONSTANT_COLOR_GB__GREEN, etc. instead.
- */
-#define R300_RB3D_BLEND_COLOR 0x4E10
-
-
-/* 3D Color Channel Mask. If all the channels used in the current color format
- * are disabled, then the cb will discard all the incoming quads. Pipelined
- * through the blender.
- */
-#define RB3D_COLOR_CHANNEL_MASK 0x4E0C
-# define RB3D_COLOR_CHANNEL_MASK_BLUE_MASK0 (1 << 0)
-# define RB3D_COLOR_CHANNEL_MASK_GREEN_MASK0 (1 << 1)
-# define RB3D_COLOR_CHANNEL_MASK_RED_MASK0 (1 << 2)
-# define RB3D_COLOR_CHANNEL_MASK_ALPHA_MASK0 (1 << 3)
-# define RB3D_COLOR_CHANNEL_MASK_BLUE_MASK1 (1 << 4)
-# define RB3D_COLOR_CHANNEL_MASK_GREEN_MASK1 (1 << 5)
-# define RB3D_COLOR_CHANNEL_MASK_RED_MASK1 (1 << 6)
-# define RB3D_COLOR_CHANNEL_MASK_ALPHA_MASK1 (1 << 7)
-# define RB3D_COLOR_CHANNEL_MASK_BLUE_MASK2 (1 << 8)
-# define RB3D_COLOR_CHANNEL_MASK_GREEN_MASK2 (1 << 9)
-# define RB3D_COLOR_CHANNEL_MASK_RED_MASK2 (1 << 10)
-# define RB3D_COLOR_CHANNEL_MASK_ALPHA_MASK2 (1 << 11)
-# define RB3D_COLOR_CHANNEL_MASK_BLUE_MASK3 (1 << 12)
-# define RB3D_COLOR_CHANNEL_MASK_GREEN_MASK3 (1 << 13)
-# define RB3D_COLOR_CHANNEL_MASK_RED_MASK3 (1 << 14)
-# define RB3D_COLOR_CHANNEL_MASK_ALPHA_MASK3 (1 << 15)
-
-/* Clear color that is used when the color mask is set to 00. Unpipelined.
- * Program this register with a 32-bit value in ARGB8888 or ARGB2101010
- * formats, ignoring the fields.
- */
-#define RB3D_COLOR_CLEAR_VALUE 0x4e14
-
-/* gap */
-
-/* Color Compare Color. Stalls the 2d/3d datapath until it is idle. */
-#define RB3D_CLRCMP_CLR 0x4e20
-
-/* Color Compare Mask. Stalls the 2d/3d datapath until it is idle. */
-#define RB3D_CLRCMP_MSK 0x4e24
-
-/* Color Buffer Address Offset of multibuffer 0. Unpipelined. */
-#define R300_RB3D_COLOROFFSET0 0x4E28
-# define R300_COLOROFFSET_MASK 0xFFFFFFE0
-/* Color Buffer Address Offset of multibuffer 1. Unpipelined. */
-#define R300_RB3D_COLOROFFSET1 0x4E2C
-/* Color Buffer Address Offset of multibuffer 2. Unpipelined. */
-#define R300_RB3D_COLOROFFSET2 0x4E30
-/* Color Buffer Address Offset of multibuffer 3. Unpipelined. */
-#define R300_RB3D_COLOROFFSET3 0x4E34
-
-/* Color buffer format and tiling control for all the multibuffers and the
- * pitch of multibuffer 0 to 3. Unpipelined. The cache must be empty before any
- * of the registers are changed.
- *
- * Bit 16: Larger tiles
- * Bit 17: 4x2 tiles
- * Bit 18: Extremely weird tile like, but some pixels duplicated?
- */
-#define R300_RB3D_COLORPITCH0 0x4E38
-# define R300_COLORPITCH_MASK 0x00003FFE
-# define R300_COLOR_TILE_DISABLE (0 << 16)
-# define R300_COLOR_TILE_ENABLE (1 << 16)
-# define R300_COLOR_MICROTILE_DISABLE (0 << 17)
-# define R300_COLOR_MICROTILE_ENABLE (1 << 17)
-# define R300_COLOR_MICROTILE_ENABLE_SQUARE (2 << 17) /* Only available in 16-bit */
-# define R300_COLOR_ENDIAN_NO_SWAP (0 << 19)
-# define R300_COLOR_ENDIAN_WORD_SWAP (1 << 19)
-# define R300_COLOR_ENDIAN_DWORD_SWAP (2 << 19)
-# define R300_COLOR_ENDIAN_HALF_DWORD_SWAP (3 << 19)
-# define R500_COLOR_FORMAT_ARGB10101010 (0 << 21)
-# define R500_COLOR_FORMAT_UV1010 (1 << 21)
-# define R500_COLOR_FORMAT_CI8 (2 << 21) /* 2D only */
-# define R300_COLOR_FORMAT_ARGB1555 (3 << 21)
-# define R300_COLOR_FORMAT_RGB565 (4 << 21)
-# define R500_COLOR_FORMAT_ARGB2101010 (5 << 21)
-# define R300_COLOR_FORMAT_ARGB8888 (6 << 21)
-# define R300_COLOR_FORMAT_ARGB32323232 (7 << 21)
-/* reserved */
-# define R300_COLOR_FORMAT_I8 (9 << 21)
-# define R300_COLOR_FORMAT_ARGB16161616 (10 << 21)
-# define R300_COLOR_FORMAT_VYUY (11 << 21)
-# define R300_COLOR_FORMAT_YVYU (12 << 21)
-# define R300_COLOR_FORMAT_UV88 (13 << 21)
-# define R500_COLOR_FORMAT_I10 (14 << 21)
-# define R300_COLOR_FORMAT_ARGB4444 (15 << 21)
-#define R300_RB3D_COLORPITCH1 0x4E3C
-#define R300_RB3D_COLORPITCH2 0x4E40
-#define R300_RB3D_COLORPITCH3 0x4E44
-
-/* gap */
-
-/* Destination Color Buffer Cache Control/Status. If the cb is in e2 mode, then
- * a flush or free will not occur upon a write to this register, but a sync
- * will be immediately sent if one is requested. If both DC_FLUSH and DC_FREE
- * are zero but DC_FINISH is one, then a sync will be sent immediately -- the
- * cb will not wait for all the previous operations to complete before sending
- * the sync. Unpipelined except when DC_FINISH and DC_FREE are both set to
- * zero.
- *
- * Set to 0A before 3D operations, set to 02 afterwards.
- */
-#define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c
-# define R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_NO_EFFECT (0 << 0)
-# define R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_NO_EFFECT_1 (1 << 0)
-# define R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D (2 << 0)
-# define R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D_1 (3 << 0)
-# define R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_NO_EFFECT (0 << 2)
-# define R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_NO_EFFECT_1 (1 << 2)
-# define R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS (2 << 2)
-# define R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS_1 (3 << 2)
-# define R300_RB3D_DSTCACHE_CTLSTAT_DC_FINISH_NO_SIGNAL (0 << 4)
-# define R300_RB3D_DSTCACHE_CTLSTAT_DC_FINISH_SIGNAL (1 << 4)
-
-#define R300_RB3D_DITHER_CTL 0x4E50
-# define R300_RB3D_DITHER_CTL_DITHER_MODE_TRUNCATE (0 << 0)
-# define R300_RB3D_DITHER_CTL_DITHER_MODE_ROUND (1 << 0)
-# define R300_RB3D_DITHER_CTL_DITHER_MODE_LUT (2 << 0)
-/* reserved */
-# define R300_RB3D_DITHER_CTL_ALPHA_DITHER_MODE_TRUNCATE (0 << 2)
-# define R300_RB3D_DITHER_CTL_ALPHA_DITHER_MODE_ROUND (1 << 2)
-# define R300_RB3D_DITHER_CTL_ALPHA_DITHER_MODE_LUT (2 << 2)
-/* reserved */
-
-/* Resolve buffer destination address. The cache must be empty before changing
- * this register if the cb is in resolve mode. Unpipelined
- */
-#define R300_RB3D_AARESOLVE_OFFSET 0x4e80
-# define R300_RB3D_AARESOLVE_OFFSET_SHIFT 5
-# define R300_RB3D_AARESOLVE_OFFSET_MASK 0xffffffe0 /* At least according to the calculations of Christoph Brill */
-
-/* Resolve Buffer Pitch and Tiling Control. The cache must be empty before
- * changing this register if the cb is in resolve mode. Unpipelined
- */
-#define R300_RB3D_AARESOLVE_PITCH 0x4e84
-# define R300_RB3D_AARESOLVE_PITCH_SHIFT 1
-# define R300_RB3D_AARESOLVE_PITCH_MASK 0x00003ffe /* At least according to the calculations of Christoph Brill */
-
-/* Resolve Buffer Control. Unpipelined */
-#define R300_RB3D_AARESOLVE_CTL 0x4e88
-# define R300_RB3D_AARESOLVE_CTL_AARESOLVE_MODE_NORMAL (0 << 0)
-# define R300_RB3D_AARESOLVE_CTL_AARESOLVE_MODE_RESOLVE (1 << 0)
-# define R300_RB3D_AARESOLVE_CTL_AARESOLVE_GAMMA_10 (0 << 1)
-# define R300_RB3D_AARESOLVE_CTL_AARESOLVE_GAMMA_22 (1 << 1)
-# define R300_RB3D_AARESOLVE_CTL_AARESOLVE_ALPHA_SAMPLE0 (0 << 2)
-# define R300_RB3D_AARESOLVE_CTL_AARESOLVE_ALPHA_AVERAGE (1 << 2)
-
-
-/* Discard src pixels less than or equal to threshold. */
-#define R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD 0x4ea0
-/* Discard src pixels greater than or equal to threshold. */
-#define R500_RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD 0x4ea4
-# define R500_RB3D_DISCARD_SRC_PIXEL_THRESHOLD_BLUE_SHIFT 0
-# define R500_RB3D_DISCARD_SRC_PIXEL_THRESHOLD_BLUE_MASK 0x000000ff
-# define R500_RB3D_DISCARD_SRC_PIXEL_THRESHOLD_GREEN_SHIFT 8
-# define R500_RB3D_DISCARD_SRC_PIXEL_THRESHOLD_GREEN_MASK 0x0000ff00
-# define R500_RB3D_DISCARD_SRC_PIXEL_THRESHOLD_RED_SHIFT 16
-# define R500_RB3D_DISCARD_SRC_PIXEL_THRESHOLD_RED_MASK 0x00ff0000
-# define R500_RB3D_DISCARD_SRC_PIXEL_THRESHOLD_ALPHA_SHIFT 24
-# define R500_RB3D_DISCARD_SRC_PIXEL_THRESHOLD_ALPHA_MASK 0xff000000
-
-/* 3D ROP Control. Stalls the 2d/3d datapath until it is idle. */
-#define R300_RB3D_ROPCNTL 0x4e18
-# define R300_RB3D_ROPCNTL_ROP_ENABLE 0x00000004
-# define R300_RB3D_ROPCNTL_ROP_MASK (15 << 8)
-# define R300_RB3D_ROPCNTL_ROP_SHIFT 8
-
-/* Color Compare Flip. Stalls the 2d/3d datapath until it is idle. */
-#define R300_RB3D_CLRCMP_FLIPE 0x4e1c
-
-/* Sets the fifo sizes */
-#define R500_RB3D_FIFO_SIZE 0x4ef4
-# define R500_RB3D_FIFO_SIZE_OP_FIFO_SIZE_FULL (0 << 0)
-# define R500_RB3D_FIFO_SIZE_OP_FIFO_SIZE_HALF (1 << 0)
-# define R500_RB3D_FIFO_SIZE_OP_FIFO_SIZE_QUATER (2 << 0)
-# define R500_RB3D_FIFO_SIZE_OP_FIFO_SIZE_EIGTHS (3 << 0)
-
-/* Constant color used by the blender. Pipelined through the blender. */
-#define R500_RB3D_CONSTANT_COLOR_AR 0x4ef8
-# define R500_RB3D_CONSTANT_COLOR_AR_RED_MASK 0x0000ffff
-# define R500_RB3D_CONSTANT_COLOR_AR_RED_SHIFT 0
-# define R500_RB3D_CONSTANT_COLOR_AR_ALPHA_MASK 0xffff0000
-# define R500_RB3D_CONSTANT_COLOR_AR_ALPHA_SHIFT 16
-
-/* Constant color used by the blender. Pipelined through the blender. */
-#define R500_RB3D_CONSTANT_COLOR_GB 0x4efc
-# define R500_RB3D_CONSTANT_COLOR_AR_BLUE_MASK 0x0000ffff
-# define R500_RB3D_CONSTANT_COLOR_AR_BLUE_SHIFT 0
-# define R500_RB3D_CONSTANT_COLOR_AR_GREEN_MASK 0xffff0000
-# define R500_RB3D_CONSTANT_COLOR_AR_GREEN_SHIFT 16
-
-/* gap */
-/* There seems to be no "write only" setting, so use Z-test = ALWAYS
- * for this.
- * Bit (1<<8) is the "test" bit. so plain write is 6 - vd
- */
-#define R300_ZB_CNTL 0x4F00
-# define R300_STENCIL_ENABLE (1 << 0)
-# define R300_Z_ENABLE (1 << 1)
-# define R300_Z_WRITE_ENABLE (1 << 2)
-# define R300_Z_SIGNED_COMPARE (1 << 3)
-# define R300_STENCIL_FRONT_BACK (1 << 4)
-# define R400_ZSIGNED_MAGNITUDE (1 << 5)
-# define R500_STENCIL_REFMASK_FRONT_BACK (1 << 6)
-
-#define R300_ZB_ZSTENCILCNTL 0x4f04
- /* functions */
-# define R300_ZS_NEVER 0
-# define R300_ZS_LESS 1
-# define R300_ZS_LEQUAL 2
-# define R300_ZS_EQUAL 3
-# define R300_ZS_GEQUAL 4
-# define R300_ZS_GREATER 5
-# define R300_ZS_NOTEQUAL 6
-# define R300_ZS_ALWAYS 7
-# define R300_ZS_MASK 7
- /* operations */
-# define R300_ZS_KEEP 0
-# define R300_ZS_ZERO 1
-# define R300_ZS_REPLACE 2
-# define R300_ZS_INCR 3
-# define R300_ZS_DECR 4
-# define R300_ZS_INVERT 5
-# define R300_ZS_INCR_WRAP 6
-# define R300_ZS_DECR_WRAP 7
-# define R300_Z_FUNC_SHIFT 0
- /* front and back refer to operations done for front
- and back faces, i.e. separate stencil function support */
-# define R300_S_FRONT_FUNC_SHIFT 3
-# define R300_S_FRONT_SFAIL_OP_SHIFT 6
-# define R300_S_FRONT_ZPASS_OP_SHIFT 9
-# define R300_S_FRONT_ZFAIL_OP_SHIFT 12
-# define R300_S_BACK_FUNC_SHIFT 15
-# define R300_S_BACK_SFAIL_OP_SHIFT 18
-# define R300_S_BACK_ZPASS_OP_SHIFT 21
-# define R300_S_BACK_ZFAIL_OP_SHIFT 24
-
-#define R300_ZB_STENCILREFMASK 0x4f08
-# define R300_STENCILREF_SHIFT 0
-# define R300_STENCILREF_MASK 0x000000ff
-# define R300_STENCILMASK_SHIFT 8
-# define R300_STENCILMASK_MASK 0x0000ff00
-# define R300_STENCILWRITEMASK_SHIFT 16
-# define R300_STENCILWRITEMASK_MASK 0x00ff0000
-
-/* gap */
-
-#define R300_ZB_FORMAT 0x4f10
-# define R300_DEPTHFORMAT_16BIT_INT_Z (0 << 0)
-# define R300_DEPTHFORMAT_16BIT_13E3 (1 << 0)
-# define R300_DEPTHFORMAT_24BIT_INT_Z_8BIT_STENCIL (2 << 0)
-/* reserved up to (15 << 0) */
-# define R300_INVERT_13E3_LEADING_ONES (0 << 4)
-# define R300_INVERT_13E3_LEADING_ZEROS (1 << 4)
-
-#define R300_ZB_ZTOP 0x4F14
-# define R300_ZTOP_DISABLE (0 << 0)
-# define R300_ZTOP_ENABLE (1 << 0)
-
-/* gap */
-
-#define R300_ZB_ZCACHE_CTLSTAT 0x4f18
-# define R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_NO_EFFECT (0 << 0)
-# define R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE (1 << 0)
-# define R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_NO_EFFECT (0 << 1)
-# define R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE (1 << 1)
-# define R300_ZB_ZCACHE_CTLSTAT_ZC_BUSY_IDLE (0 << 31)
-# define R300_ZB_ZCACHE_CTLSTAT_ZC_BUSY_BUSY (1 << 31)
-
-#define R300_ZB_BW_CNTL 0x4f1c
-# define R300_HIZ_DISABLE (0 << 0)
-# define R300_HIZ_ENABLE (1 << 0)
-# define R300_HIZ_MIN (0 << 1)
-# define R300_HIZ_MAX (1 << 1)
-# define R300_FAST_FILL_DISABLE (0 << 2)
-# define R300_FAST_FILL_ENABLE (1 << 2)
-# define R300_RD_COMP_DISABLE (0 << 3)
-# define R300_RD_COMP_ENABLE (1 << 3)
-# define R300_WR_COMP_DISABLE (0 << 4)
-# define R300_WR_COMP_ENABLE (1 << 4)
-# define R300_ZB_CB_CLEAR_RMW (0 << 5)
-# define R300_ZB_CB_CLEAR_CACHE_LINEAR (1 << 5)
-# define R300_FORCE_COMPRESSED_STENCIL_VALUE_DISABLE (0 << 6)
-# define R300_FORCE_COMPRESSED_STENCIL_VALUE_ENABLE (1 << 6)
-
-# define R500_ZEQUAL_OPTIMIZE_ENABLE (0 << 7)
-# define R500_ZEQUAL_OPTIMIZE_DISABLE (1 << 7)
-# define R500_SEQUAL_OPTIMIZE_ENABLE (0 << 8)
-# define R500_SEQUAL_OPTIMIZE_DISABLE (1 << 8)
-
-# define R500_BMASK_ENABLE (0 << 10)
-# define R500_BMASK_DISABLE (1 << 10)
-# define R500_HIZ_EQUAL_REJECT_DISABLE (0 << 11)
-# define R500_HIZ_EQUAL_REJECT_ENABLE (1 << 11)
-# define R500_HIZ_FP_EXP_BITS_DISABLE (0 << 12)
-# define R500_HIZ_FP_EXP_BITS_1 (1 << 12)
-# define R500_HIZ_FP_EXP_BITS_2 (2 << 12)
-# define R500_HIZ_FP_EXP_BITS_3 (3 << 12)
-# define R500_HIZ_FP_EXP_BITS_4 (4 << 12)
-# define R500_HIZ_FP_EXP_BITS_5 (5 << 12)
-# define R500_HIZ_FP_INVERT_LEADING_ONES (0 << 15)
-# define R500_HIZ_FP_INVERT_LEADING_ZEROS (1 << 15)
-# define R500_TILE_OVERWRITE_RECOMPRESSION_ENABLE (0 << 16)
-# define R500_TILE_OVERWRITE_RECOMPRESSION_DISABLE (1 << 16)
-# define R500_CONTIGUOUS_6XAA_SAMPLES_ENABLE (0 << 17)
-# define R500_CONTIGUOUS_6XAA_SAMPLES_DISABLE (1 << 17)
-# define R500_PEQ_PACKING_DISABLE (0 << 18)
-# define R500_PEQ_PACKING_ENABLE (1 << 18)
-# define R500_COVERED_PTR_MASKING_DISABLE (0 << 18)
-# define R500_COVERED_PTR_MASKING_ENABLE (1 << 18)
-
-
-/* gap */
-
-/* Z Buffer Address Offset.
- * Bits 31 to 5 are used for aligned Z buffer address offset for macro tiles.
- */
-#define R300_ZB_DEPTHOFFSET 0x4f20
-
-/* Z Buffer Pitch and Endian Control */
-#define R300_ZB_DEPTHPITCH 0x4f24
-# define R300_DEPTHPITCH_MASK 0x00003FFC
-# define R300_DEPTHMACROTILE_DISABLE (0 << 16)
-# define R300_DEPTHMACROTILE_ENABLE (1 << 16)
-# define R300_DEPTHMICROTILE_LINEAR (0 << 17)
-# define R300_DEPTHMICROTILE_TILED (1 << 17)
-# define R300_DEPTHMICROTILE_TILED_SQUARE (2 << 17)
-# define R300_DEPTHENDIAN_NO_SWAP (0 << 18)
-# define R300_DEPTHENDIAN_WORD_SWAP (1 << 18)
-# define R300_DEPTHENDIAN_DWORD_SWAP (2 << 18)
-# define R300_DEPTHENDIAN_HALF_DWORD_SWAP (3 << 18)
-
-/* Z Buffer Clear Value */
-#define R300_ZB_DEPTHCLEARVALUE 0x4f28
-
-#define R300_ZB_ZMASK_OFFSET 0x4f30
-#define R300_ZB_ZMASK_PITCH 0x4f34
-#define R300_ZB_ZMASK_WRINDEX 0x4f38
-#define R300_ZB_ZMASK_DWORD 0x4f3c
-#define R300_ZB_ZMASK_RDINDEX 0x4f40
-
-/* Hierarchical Z Memory Offset */
-#define R300_ZB_HIZ_OFFSET 0x4f44
-
-/* Hierarchical Z Write Index */
-#define R300_ZB_HIZ_WRINDEX 0x4f48
-
-/* Hierarchical Z Data */
-#define R300_ZB_HIZ_DWORD 0x4f4c
-
-/* Hierarchical Z Read Index */
-#define R300_ZB_HIZ_RDINDEX 0x4f50
-
-/* Hierarchical Z Pitch */
-#define R300_ZB_HIZ_PITCH 0x4f54
-
-/* Z Buffer Z Pass Counter Data */
-#define R300_ZB_ZPASS_DATA 0x4f58
-
-/* Z Buffer Z Pass Counter Address */
-#define R300_ZB_ZPASS_ADDR 0x4f5c
-
-/* Depth buffer X and Y coordinate offset */
-#define R300_ZB_DEPTHXY_OFFSET 0x4f60
-# define R300_DEPTHX_OFFSET_SHIFT 1
-# define R300_DEPTHX_OFFSET_MASK 0x000007FE
-# define R300_DEPTHY_OFFSET_SHIFT 17
-# define R300_DEPTHY_OFFSET_MASK 0x07FE0000
-
-/* Sets the fifo sizes */
-#define R500_ZB_FIFO_SIZE 0x4fd0
-# define R500_OP_FIFO_SIZE_FULL (0 << 0)
-# define R500_OP_FIFO_SIZE_HALF (1 << 0)
-# define R500_OP_FIFO_SIZE_QUATER (2 << 0)
-# define R500_OP_FIFO_SIZE_EIGTHS (4 << 0)
-
-/* Stencil Reference Value and Mask for backfacing quads */
-/* R300_ZB_STENCILREFMASK handles front face */
-#define R500_ZB_STENCILREFMASK_BF 0x4fd4
-# define R500_STENCILREF_SHIFT 0
-# define R500_STENCILREF_MASK 0x000000ff
-# define R500_STENCILMASK_SHIFT 8
-# define R500_STENCILMASK_MASK 0x0000ff00
-# define R500_STENCILWRITEMASK_SHIFT 16
-# define R500_STENCILWRITEMASK_MASK 0x00ff0000
-
-/**
- * \defgroup R3XX_R5XX_PROGRAMMABLE_VERTEX_SHADER_DESCRIPTION R3XX-R5XX PROGRAMMABLE VERTEX SHADER DESCRIPTION
- *
- * The PVS_DST_MATH_INST is used to identify whether the instruction is a Vector
- * Engine instruction or a Math Engine instruction.
- */
-
-/*\{*/
-
-enum {
- /* R3XX */
- VECTOR_NO_OP = 0,
- VE_DOT_PRODUCT = 1,
- VE_MULTIPLY = 2,
- VE_ADD = 3,
- VE_MULTIPLY_ADD = 4,
- VE_DISTANCE_VECTOR = 5,
- VE_FRACTION = 6,
- VE_MAXIMUM = 7,
- VE_MINIMUM = 8,
- VE_SET_GREATER_THAN_EQUAL = 9,
- VE_SET_LESS_THAN = 10,
- VE_MULTIPLYX2_ADD = 11,
- VE_MULTIPLY_CLAMP = 12,
- VE_FLT2FIX_DX = 13,
- VE_FLT2FIX_DX_RND = 14,
- /* R5XX */
- VE_PRED_SET_EQ_PUSH = 15,
- VE_PRED_SET_GT_PUSH = 16,
- VE_PRED_SET_GTE_PUSH = 17,
- VE_PRED_SET_NEQ_PUSH = 18,
- VE_COND_WRITE_EQ = 19,
- VE_COND_WRITE_GT = 20,
- VE_COND_WRITE_GTE = 21,
- VE_COND_WRITE_NEQ = 22,
- VE_COND_MUX_EQ = 23,
- VE_COND_MUX_GT = 24,
- VE_COND_MUX_GTE = 25,
- VE_SET_GREATER_THAN = 26,
- VE_SET_EQUAL = 27,
- VE_SET_NOT_EQUAL = 28,
-};
-
-enum {
- /* R3XX */
- MATH_NO_OP = 0,
- ME_EXP_BASE2_DX = 1,
- ME_LOG_BASE2_DX = 2,
- ME_EXP_BASEE_FF = 3,
- ME_LIGHT_COEFF_DX = 4,
- ME_POWER_FUNC_FF = 5,
- ME_RECIP_DX = 6,
- ME_RECIP_FF = 7,
- ME_RECIP_SQRT_DX = 8,
- ME_RECIP_SQRT_FF = 9,
- ME_MULTIPLY = 10,
- ME_EXP_BASE2_FULL_DX = 11,
- ME_LOG_BASE2_FULL_DX = 12,
- ME_POWER_FUNC_FF_CLAMP_B = 13,
- ME_POWER_FUNC_FF_CLAMP_B1 = 14,
- ME_POWER_FUNC_FF_CLAMP_01 = 15,
- ME_SIN = 16,
- ME_COS = 17,
- /* R5XX */
- ME_LOG_BASE2_IEEE = 18,
- ME_RECIP_IEEE = 19,
- ME_RECIP_SQRT_IEEE = 20,
- ME_PRED_SET_EQ = 21,
- ME_PRED_SET_GT = 22,
- ME_PRED_SET_GTE = 23,
- ME_PRED_SET_NEQ = 24,
- ME_PRED_SET_CLR = 25,
- ME_PRED_SET_INV = 26,
- ME_PRED_SET_POP = 27,
- ME_PRED_SET_RESTORE = 28,
-};
-
-enum {
- /* R3XX */
- PVS_MACRO_OP_2CLK_MADD = 0,
- PVS_MACRO_OP_2CLK_M2X_ADD = 1,
-};
-
-enum {
- PVS_SRC_REG_TEMPORARY = 0, /* Intermediate Storage */
- PVS_SRC_REG_INPUT = 1, /* Input Vertex Storage */
- PVS_SRC_REG_CONSTANT = 2, /* Constant State Storage */
- PVS_SRC_REG_ALT_TEMPORARY = 3, /* Alternate Intermediate Storage */
-};
-
-enum {
- PVS_DST_REG_TEMPORARY = 0, /* Intermediate Storage */
- PVS_DST_REG_A0 = 1, /* Address Register Storage */
- PVS_DST_REG_OUT = 2, /* Output Memory. Used for all outputs */
- PVS_DST_REG_OUT_REPL_X = 3, /* Output Memory & Replicate X to all channels */
- PVS_DST_REG_ALT_TEMPORARY = 4, /* Alternate Intermediate Storage */
- PVS_DST_REG_INPUT = 5, /* Output Memory & Replicate X to all channels */
-};
-
-enum {
- PVS_SRC_SELECT_X = 0, /* Select X Component */
- PVS_SRC_SELECT_Y = 1, /* Select Y Component */
- PVS_SRC_SELECT_Z = 2, /* Select Z Component */
- PVS_SRC_SELECT_W = 3, /* Select W Component */
- PVS_SRC_SELECT_FORCE_0 = 4, /* Force Component to 0.0 */
- PVS_SRC_SELECT_FORCE_1 = 5, /* Force Component to 1.0 */
-};
-
-/* PVS Opcode & Destination Operand Description */
-
-enum {
- PVS_DST_OPCODE_MASK = 0x3f,
- PVS_DST_OPCODE_SHIFT = 0,
- PVS_DST_MATH_INST_MASK = 0x1,
- PVS_DST_MATH_INST_SHIFT = 6,
- PVS_DST_MACRO_INST_MASK = 0x1,
- PVS_DST_MACRO_INST_SHIFT = 7,
- PVS_DST_REG_TYPE_MASK = 0xf,
- PVS_DST_REG_TYPE_SHIFT = 8,
- PVS_DST_ADDR_MODE_1_MASK = 0x1,
- PVS_DST_ADDR_MODE_1_SHIFT = 12,
- PVS_DST_OFFSET_MASK = 0x7f,
- PVS_DST_OFFSET_SHIFT = 13,
- PVS_DST_WE_X_MASK = 0x1,
- PVS_DST_WE_X_SHIFT = 20,
- PVS_DST_WE_Y_MASK = 0x1,
- PVS_DST_WE_Y_SHIFT = 21,
- PVS_DST_WE_Z_MASK = 0x1,
- PVS_DST_WE_Z_SHIFT = 22,
- PVS_DST_WE_W_MASK = 0x1,
- PVS_DST_WE_W_SHIFT = 23,
- PVS_DST_VE_SAT_MASK = 0x1,
- PVS_DST_VE_SAT_SHIFT = 24,
- PVS_DST_ME_SAT_MASK = 0x1,
- PVS_DST_ME_SAT_SHIFT = 25,
- PVS_DST_PRED_ENABLE_MASK = 0x1,
- PVS_DST_PRED_ENABLE_SHIFT = 26,
- PVS_DST_PRED_SENSE_MASK = 0x1,
- PVS_DST_PRED_SENSE_SHIFT = 27,
- PVS_DST_DUAL_MATH_OP_MASK = 0x3,
- PVS_DST_DUAL_MATH_OP_SHIFT = 27,
- PVS_DST_ADDR_SEL_MASK = 0x3,
- PVS_DST_ADDR_SEL_SHIFT = 29,
- PVS_DST_ADDR_MODE_0_MASK = 0x1,
- PVS_DST_ADDR_MODE_0_SHIFT = 31,
-};
-
-/* PVS Source Operand Description */
-
-enum {
- PVS_SRC_REG_TYPE_MASK = 0x3,
- PVS_SRC_REG_TYPE_SHIFT = 0,
- SPARE_0_MASK = 0x1,
- SPARE_0_SHIFT = 2,
- PVS_SRC_ABS_XYZW_MASK = 0x1,
- PVS_SRC_ABS_XYZW_SHIFT = 3,
- PVS_SRC_ADDR_MODE_0_MASK = 0x1,
- PVS_SRC_ADDR_MODE_0_SHIFT = 4,
- PVS_SRC_OFFSET_MASK = 0xff,
- PVS_SRC_OFFSET_SHIFT = 5,
- PVS_SRC_SWIZZLE_X_MASK = 0x7,
- PVS_SRC_SWIZZLE_X_SHIFT = 13,
- PVS_SRC_SWIZZLE_Y_MASK = 0x7,
- PVS_SRC_SWIZZLE_Y_SHIFT = 16,
- PVS_SRC_SWIZZLE_Z_MASK = 0x7,
- PVS_SRC_SWIZZLE_Z_SHIFT = 19,
- PVS_SRC_SWIZZLE_W_MASK = 0x7,
- PVS_SRC_SWIZZLE_W_SHIFT = 22,
- PVS_SRC_MODIFIER_X_MASK = 0x1,
- PVS_SRC_MODIFIER_X_SHIFT = 25,
- PVS_SRC_MODIFIER_Y_MASK = 0x1,
- PVS_SRC_MODIFIER_Y_SHIFT = 26,
- PVS_SRC_MODIFIER_Z_MASK = 0x1,
- PVS_SRC_MODIFIER_Z_SHIFT = 27,
- PVS_SRC_MODIFIER_W_MASK = 0x1,
- PVS_SRC_MODIFIER_W_SHIFT = 28,
- PVS_SRC_ADDR_SEL_MASK = 0x3,
- PVS_SRC_ADDR_SEL_SHIFT = 29,
- PVS_SRC_ADDR_MODE_1_MASK = 0x0,
- PVS_SRC_ADDR_MODE_1_SHIFT = 32,
-};
-
-
-#define PVS_OP_DST_OPERAND(opcode, math_inst, macro_inst, reg_index, reg_writemask, reg_class) \
- (((opcode & PVS_DST_OPCODE_MASK) << PVS_DST_OPCODE_SHIFT) \
- | ((math_inst & PVS_DST_MATH_INST_MASK) << PVS_DST_MATH_INST_SHIFT) \
- | ((macro_inst & PVS_DST_MACRO_INST_MASK) << PVS_DST_MACRO_INST_SHIFT) \
- | ((reg_index & PVS_DST_OFFSET_MASK) << PVS_DST_OFFSET_SHIFT) \
- | ((reg_writemask & 0xf) << PVS_DST_WE_X_SHIFT) /* X Y Z W */ \
- | ((reg_class & PVS_DST_REG_TYPE_MASK) << PVS_DST_REG_TYPE_SHIFT))
-
-#define PVS_SRC_OPERAND(in_reg_index, comp_x, comp_y, comp_z, comp_w, reg_class, negate) \
- (((in_reg_index & PVS_SRC_OFFSET_MASK) << PVS_SRC_OFFSET_SHIFT) \
- | ((comp_x & PVS_SRC_SWIZZLE_X_MASK) << PVS_SRC_SWIZZLE_X_SHIFT) \
- | ((comp_y & PVS_SRC_SWIZZLE_Y_MASK) << PVS_SRC_SWIZZLE_Y_SHIFT) \
- | ((comp_z & PVS_SRC_SWIZZLE_Z_MASK) << PVS_SRC_SWIZZLE_Z_SHIFT) \
- | ((comp_w & PVS_SRC_SWIZZLE_W_MASK) << PVS_SRC_SWIZZLE_W_SHIFT) \
- | ((negate & 0xf) << PVS_SRC_MODIFIER_X_SHIFT) /* X Y Z W */ \
- | ((reg_class & PVS_SRC_REG_TYPE_MASK) << PVS_SRC_REG_TYPE_SHIFT))
-
-/*\}*/
-
-/* BEGIN: Packet 3 commands */
-
-/* A primitive emission dword. */
-#define R300_PRIM_TYPE_NONE (0 << 0)
-#define R300_PRIM_TYPE_POINT (1 << 0)
-#define R300_PRIM_TYPE_LINE (2 << 0)
-#define R300_PRIM_TYPE_LINE_STRIP (3 << 0)
-#define R300_PRIM_TYPE_TRI_LIST (4 << 0)
-#define R300_PRIM_TYPE_TRI_FAN (5 << 0)
-#define R300_PRIM_TYPE_TRI_STRIP (6 << 0)
-#define R300_PRIM_TYPE_TRI_TYPE2 (7 << 0)
-#define R300_PRIM_TYPE_RECT_LIST (8 << 0)
-#define R300_PRIM_TYPE_3VRT_POINT_LIST (9 << 0)
-#define R300_PRIM_TYPE_3VRT_LINE_LIST (10 << 0)
- /* GUESS (based on r200) */
-#define R300_PRIM_TYPE_POINT_SPRITES (11 << 0)
-#define R300_PRIM_TYPE_LINE_LOOP (12 << 0)
-#define R300_PRIM_TYPE_QUADS (13 << 0)
-#define R300_PRIM_TYPE_QUAD_STRIP (14 << 0)
-#define R300_PRIM_TYPE_POLYGON (15 << 0)
-#define R300_PRIM_TYPE_MASK 0xF
-#define R300_PRIM_WALK_IND (1 << 4)
-#define R300_PRIM_WALK_LIST (2 << 4)
-#define R300_PRIM_WALK_RING (3 << 4)
-#define R300_PRIM_WALK_MASK (3 << 4)
- /* GUESS (based on r200) */
-#define R300_PRIM_COLOR_ORDER_BGRA (0 << 6)
-#define R300_PRIM_COLOR_ORDER_RGBA (1 << 6)
-#define R300_PRIM_NUM_VERTICES_SHIFT 16
-#define R300_PRIM_NUM_VERTICES_MASK 0xffff
-
-
-
-/*
- * The R500 unified shader (US) registers come in banks of 512 each, one
- * for each instruction slot in the shader. You can't touch them directly.
- * R500_US_VECTOR_INDEX() sets the base instruction to modify; successive
- * writes to R500_GA_US_VECTOR_DATA autoincrement the index after the
- * instruction is fully specified.
- */
-#define R500_US_ALU_ALPHA_INST_0 0xa800
-# define R500_ALPHA_OP_MAD 0
-# define R500_ALPHA_OP_DP 1
-# define R500_ALPHA_OP_MIN 2
-# define R500_ALPHA_OP_MAX 3
-/* #define R500_ALPHA_OP_RESERVED 4 */
-# define R500_ALPHA_OP_CND 5
-# define R500_ALPHA_OP_CMP 6
-# define R500_ALPHA_OP_FRC 7
-# define R500_ALPHA_OP_EX2 8
-# define R500_ALPHA_OP_LN2 9
-# define R500_ALPHA_OP_RCP 10
-# define R500_ALPHA_OP_RSQ 11
-# define R500_ALPHA_OP_SIN 12
-# define R500_ALPHA_OP_COS 13
-# define R500_ALPHA_OP_MDH 14
-# define R500_ALPHA_OP_MDV 15
-# define R500_ALPHA_ADDRD(x) ((x) << 4)
-# define R500_ALPHA_ADDRD_REL (1 << 11)
-# define R500_ALPHA_SEL_A_SHIFT 12
-# define R500_ALPHA_SEL_A_SRC0 (0 << 12)
-# define R500_ALPHA_SEL_A_SRC1 (1 << 12)
-# define R500_ALPHA_SEL_A_SRC2 (2 << 12)
-# define R500_ALPHA_SEL_A_SRCP (3 << 12)
-# define R500_ALPHA_SWIZ_A_R (0 << 14)
-# define R500_ALPHA_SWIZ_A_G (1 << 14)
-# define R500_ALPHA_SWIZ_A_B (2 << 14)
-# define R500_ALPHA_SWIZ_A_A (3 << 14)
-# define R500_ALPHA_SWIZ_A_0 (4 << 14)
-# define R500_ALPHA_SWIZ_A_HALF (5 << 14)
-# define R500_ALPHA_SWIZ_A_1 (6 << 14)
-/* #define R500_ALPHA_SWIZ_A_UNUSED (7 << 14) */
-# define R500_ALPHA_MOD_A_NOP (0 << 17)
-# define R500_ALPHA_MOD_A_NEG (1 << 17)
-# define R500_ALPHA_MOD_A_ABS (2 << 17)
-# define R500_ALPHA_MOD_A_NAB (3 << 17)
-# define R500_ALPHA_SEL_B_SHIFT 19
-# define R500_ALPHA_SEL_B_SRC0 (0 << 19)
-# define R500_ALPHA_SEL_B_SRC1 (1 << 19)
-# define R500_ALPHA_SEL_B_SRC2 (2 << 19)
-# define R500_ALPHA_SEL_B_SRCP (3 << 19)
-# define R500_ALPHA_SWIZ_B_R (0 << 21)
-# define R500_ALPHA_SWIZ_B_G (1 << 21)
-# define R500_ALPHA_SWIZ_B_B (2 << 21)
-# define R500_ALPHA_SWIZ_B_A (3 << 21)
-# define R500_ALPHA_SWIZ_B_0 (4 << 21)
-# define R500_ALPHA_SWIZ_B_HALF (5 << 21)
-# define R500_ALPHA_SWIZ_B_1 (6 << 21)
-/* #define R500_ALPHA_SWIZ_B_UNUSED (7 << 21) */
-# define R500_ALPHA_MOD_B_NOP (0 << 24)
-# define R500_ALPHA_MOD_B_NEG (1 << 24)
-# define R500_ALPHA_MOD_B_ABS (2 << 24)
-# define R500_ALPHA_MOD_B_NAB (3 << 24)
-# define R500_ALPHA_OMOD_IDENTITY (0 << 26)
-# define R500_ALPHA_OMOD_MUL_2 (1 << 26)
-# define R500_ALPHA_OMOD_MUL_4 (2 << 26)
-# define R500_ALPHA_OMOD_MUL_8 (3 << 26)
-# define R500_ALPHA_OMOD_DIV_2 (4 << 26)
-# define R500_ALPHA_OMOD_DIV_4 (5 << 26)
-# define R500_ALPHA_OMOD_DIV_8 (6 << 26)
-# define R500_ALPHA_OMOD_DISABLE (7 << 26)
-# define R500_ALPHA_TARGET(x) ((x) << 29)
-# define R500_ALPHA_W_OMASK (1 << 31)
-#define R500_US_ALU_ALPHA_ADDR_0 0x9800
-# define R500_ALPHA_ADDR0(x) ((x) << 0)
-# define R500_ALPHA_ADDR0_CONST (1 << 8)
-# define R500_ALPHA_ADDR0_REL (1 << 9)
-# define R500_ALPHA_ADDR1(x) ((x) << 10)
-# define R500_ALPHA_ADDR1_CONST (1 << 18)
-# define R500_ALPHA_ADDR1_REL (1 << 19)
-# define R500_ALPHA_ADDR2(x) ((x) << 20)
-# define R500_ALPHA_ADDR2_CONST (1 << 28)
-# define R500_ALPHA_ADDR2_REL (1 << 29)
-# define R500_ALPHA_SRCP_OP_1_MINUS_2A0 (0 << 30)
-# define R500_ALPHA_SRCP_OP_A1_MINUS_A0 (1 << 30)
-# define R500_ALPHA_SRCP_OP_A1_PLUS_A0 (2 << 30)
-# define R500_ALPHA_SRCP_OP_1_MINUS_A0 (3 << 30)
-#define R500_US_ALU_RGBA_INST_0 0xb000
-# define R500_ALU_RGBA_OP_MAD (0 << 0)
-# define R500_ALU_RGBA_OP_DP3 (1 << 0)
-# define R500_ALU_RGBA_OP_DP4 (2 << 0)
-# define R500_ALU_RGBA_OP_D2A (3 << 0)
-# define R500_ALU_RGBA_OP_MIN (4 << 0)
-# define R500_ALU_RGBA_OP_MAX (5 << 0)
-/* #define R500_ALU_RGBA_OP_RESERVED (6 << 0) */
-# define R500_ALU_RGBA_OP_CND (7 << 0)
-# define R500_ALU_RGBA_OP_CMP (8 << 0)
-# define R500_ALU_RGBA_OP_FRC (9 << 0)
-# define R500_ALU_RGBA_OP_SOP (10 << 0)
-# define R500_ALU_RGBA_OP_MDH (11 << 0)
-# define R500_ALU_RGBA_OP_MDV (12 << 0)
-# define R500_ALU_RGBA_ADDRD(x) ((x) << 4)
-# define R500_ALU_RGBA_ADDRD_REL (1 << 11)
-# define R500_ALU_RGBA_SEL_C_SHIFT 12
-# define R500_ALU_RGBA_SEL_C_SRC0 (0 << 12)
-# define R500_ALU_RGBA_SEL_C_SRC1 (1 << 12)
-# define R500_ALU_RGBA_SEL_C_SRC2 (2 << 12)
-# define R500_ALU_RGBA_SEL_C_SRCP (3 << 12)
-# define R500_ALU_RGBA_R_SWIZ_R (0 << 14)
-# define R500_ALU_RGBA_R_SWIZ_G (1 << 14)
-# define R500_ALU_RGBA_R_SWIZ_B (2 << 14)
-# define R500_ALU_RGBA_R_SWIZ_A (3 << 14)
-# define R500_ALU_RGBA_R_SWIZ_0 (4 << 14)
-# define R500_ALU_RGBA_R_SWIZ_HALF (5 << 14)
-# define R500_ALU_RGBA_R_SWIZ_1 (6 << 14)
-/* #define R500_ALU_RGBA_R_SWIZ_UNUSED (7 << 14) */
-# define R500_ALU_RGBA_G_SWIZ_R (0 << 17)
-# define R500_ALU_RGBA_G_SWIZ_G (1 << 17)
-# define R500_ALU_RGBA_G_SWIZ_B (2 << 17)
-# define R500_ALU_RGBA_G_SWIZ_A (3 << 17)
-# define R500_ALU_RGBA_G_SWIZ_0 (4 << 17)
-# define R500_ALU_RGBA_G_SWIZ_HALF (5 << 17)
-# define R500_ALU_RGBA_G_SWIZ_1 (6 << 17)
-/* #define R500_ALU_RGBA_G_SWIZ_UNUSED (7 << 17) */
-# define R500_ALU_RGBA_B_SWIZ_R (0 << 20)
-# define R500_ALU_RGBA_B_SWIZ_G (1 << 20)
-# define R500_ALU_RGBA_B_SWIZ_B (2 << 20)
-# define R500_ALU_RGBA_B_SWIZ_A (3 << 20)
-# define R500_ALU_RGBA_B_SWIZ_0 (4 << 20)
-# define R500_ALU_RGBA_B_SWIZ_HALF (5 << 20)
-# define R500_ALU_RGBA_B_SWIZ_1 (6 << 20)
-/* #define R500_ALU_RGBA_B_SWIZ_UNUSED (7 << 20) */
-# define R500_ALU_RGBA_MOD_C_NOP (0 << 23)
-# define R500_ALU_RGBA_MOD_C_NEG (1 << 23)
-# define R500_ALU_RGBA_MOD_C_ABS (2 << 23)
-# define R500_ALU_RGBA_MOD_C_NAB (3 << 23)
-# define R500_ALU_RGBA_ALPHA_SEL_C_SHIFT 25
-# define R500_ALU_RGBA_ALPHA_SEL_C_SRC0 (0 << 25)
-# define R500_ALU_RGBA_ALPHA_SEL_C_SRC1 (1 << 25)
-# define R500_ALU_RGBA_ALPHA_SEL_C_SRC2 (2 << 25)
-# define R500_ALU_RGBA_ALPHA_SEL_C_SRCP (3 << 25)
-# define R500_ALU_RGBA_A_SWIZ_R (0 << 27)
-# define R500_ALU_RGBA_A_SWIZ_G (1 << 27)
-# define R500_ALU_RGBA_A_SWIZ_B (2 << 27)
-# define R500_ALU_RGBA_A_SWIZ_A (3 << 27)
-# define R500_ALU_RGBA_A_SWIZ_0 (4 << 27)
-# define R500_ALU_RGBA_A_SWIZ_HALF (5 << 27)
-# define R500_ALU_RGBA_A_SWIZ_1 (6 << 27)
-/* #define R500_ALU_RGBA_A_SWIZ_UNUSED (7 << 27) */
-# define R500_ALU_RGBA_ALPHA_MOD_C_NOP (0 << 30)
-# define R500_ALU_RGBA_ALPHA_MOD_C_NEG (1 << 30)
-# define R500_ALU_RGBA_ALPHA_MOD_C_ABS (2 << 30)
-# define R500_ALU_RGBA_ALPHA_MOD_C_NAB (3 << 30)
-#define R500_US_ALU_RGB_INST_0 0xa000
-# define R500_ALU_RGB_SEL_A_SHIFT 0
-# define R500_ALU_RGB_SEL_A_SRC0 (0 << 0)
-# define R500_ALU_RGB_SEL_A_SRC1 (1 << 0)
-# define R500_ALU_RGB_SEL_A_SRC2 (2 << 0)
-# define R500_ALU_RGB_SEL_A_SRCP (3 << 0)
-# define R500_ALU_RGB_R_SWIZ_A_R (0 << 2)
-# define R500_ALU_RGB_R_SWIZ_A_G (1 << 2)
-# define R500_ALU_RGB_R_SWIZ_A_B (2 << 2)
-# define R500_ALU_RGB_R_SWIZ_A_A (3 << 2)
-# define R500_ALU_RGB_R_SWIZ_A_0 (4 << 2)
-# define R500_ALU_RGB_R_SWIZ_A_HALF (5 << 2)
-# define R500_ALU_RGB_R_SWIZ_A_1 (6 << 2)
-/* #define R500_ALU_RGB_R_SWIZ_A_UNUSED (7 << 2) */
-# define R500_ALU_RGB_G_SWIZ_A_R (0 << 5)
-# define R500_ALU_RGB_G_SWIZ_A_G (1 << 5)
-# define R500_ALU_RGB_G_SWIZ_A_B (2 << 5)
-# define R500_ALU_RGB_G_SWIZ_A_A (3 << 5)
-# define R500_ALU_RGB_G_SWIZ_A_0 (4 << 5)
-# define R500_ALU_RGB_G_SWIZ_A_HALF (5 << 5)
-# define R500_ALU_RGB_G_SWIZ_A_1 (6 << 5)
-/* #define R500_ALU_RGB_G_SWIZ_A_UNUSED (7 << 5) */
-# define R500_ALU_RGB_B_SWIZ_A_R (0 << 8)
-# define R500_ALU_RGB_B_SWIZ_A_G (1 << 8)
-# define R500_ALU_RGB_B_SWIZ_A_B (2 << 8)
-# define R500_ALU_RGB_B_SWIZ_A_A (3 << 8)
-# define R500_ALU_RGB_B_SWIZ_A_0 (4 << 8)
-# define R500_ALU_RGB_B_SWIZ_A_HALF (5 << 8)
-# define R500_ALU_RGB_B_SWIZ_A_1 (6 << 8)
-/* #define R500_ALU_RGB_B_SWIZ_A_UNUSED (7 << 8) */
-# define R500_ALU_RGB_MOD_A_NOP (0 << 11)
-# define R500_ALU_RGB_MOD_A_NEG (1 << 11)
-# define R500_ALU_RGB_MOD_A_ABS (2 << 11)
-# define R500_ALU_RGB_MOD_A_NAB (3 << 11)
-# define R500_ALU_RGB_SEL_B_SHIFT 13
-# define R500_ALU_RGB_SEL_B_SRC0 (0 << 13)
-# define R500_ALU_RGB_SEL_B_SRC1 (1 << 13)
-# define R500_ALU_RGB_SEL_B_SRC2 (2 << 13)
-# define R500_ALU_RGB_SEL_B_SRCP (3 << 13)
-# define R500_ALU_RGB_R_SWIZ_B_R (0 << 15)
-# define R500_ALU_RGB_R_SWIZ_B_G (1 << 15)
-# define R500_ALU_RGB_R_SWIZ_B_B (2 << 15)
-# define R500_ALU_RGB_R_SWIZ_B_A (3 << 15)
-# define R500_ALU_RGB_R_SWIZ_B_0 (4 << 15)
-# define R500_ALU_RGB_R_SWIZ_B_HALF (5 << 15)
-# define R500_ALU_RGB_R_SWIZ_B_1 (6 << 15)
-/* #define R500_ALU_RGB_R_SWIZ_B_UNUSED (7 << 15) */
-# define R500_ALU_RGB_G_SWIZ_B_R (0 << 18)
-# define R500_ALU_RGB_G_SWIZ_B_G (1 << 18)
-# define R500_ALU_RGB_G_SWIZ_B_B (2 << 18)
-# define R500_ALU_RGB_G_SWIZ_B_A (3 << 18)
-# define R500_ALU_RGB_G_SWIZ_B_0 (4 << 18)
-# define R500_ALU_RGB_G_SWIZ_B_HALF (5 << 18)
-# define R500_ALU_RGB_G_SWIZ_B_1 (6 << 18)
-/* #define R500_ALU_RGB_G_SWIZ_B_UNUSED (7 << 18) */
-# define R500_ALU_RGB_B_SWIZ_B_R (0 << 21)
-# define R500_ALU_RGB_B_SWIZ_B_G (1 << 21)
-# define R500_ALU_RGB_B_SWIZ_B_B (2 << 21)
-# define R500_ALU_RGB_B_SWIZ_B_A (3 << 21)
-# define R500_ALU_RGB_B_SWIZ_B_0 (4 << 21)
-# define R500_ALU_RGB_B_SWIZ_B_HALF (5 << 21)
-# define R500_ALU_RGB_B_SWIZ_B_1 (6 << 21)
-/* #define R500_ALU_RGB_B_SWIZ_B_UNUSED (7 << 21) */
-# define R500_ALU_RGB_MOD_B_NOP (0 << 24)
-# define R500_ALU_RGB_MOD_B_NEG (1 << 24)
-# define R500_ALU_RGB_MOD_B_ABS (2 << 24)
-# define R500_ALU_RGB_MOD_B_NAB (3 << 24)
-# define R500_ALU_RGB_OMOD_IDENTITY (0 << 26)
-# define R500_ALU_RGB_OMOD_MUL_2 (1 << 26)
-# define R500_ALU_RGB_OMOD_MUL_4 (2 << 26)
-# define R500_ALU_RGB_OMOD_MUL_8 (3 << 26)
-# define R500_ALU_RGB_OMOD_DIV_2 (4 << 26)
-# define R500_ALU_RGB_OMOD_DIV_4 (5 << 26)
-# define R500_ALU_RGB_OMOD_DIV_8 (6 << 26)
-# define R500_ALU_RGB_OMOD_DISABLE (7 << 26)
-# define R500_ALU_RGB_TARGET(x) ((x) << 29)
-# define R500_ALU_RGB_WMASK (1 << 31)
-#define R500_US_ALU_RGB_ADDR_0 0x9000
-# define R500_RGB_ADDR0(x) ((x) << 0)
-# define R500_RGB_ADDR0_CONST (1 << 8)
-# define R500_RGB_ADDR0_REL (1 << 9)
-# define R500_RGB_ADDR1(x) ((x) << 10)
-# define R500_RGB_ADDR1_CONST (1 << 18)
-# define R500_RGB_ADDR1_REL (1 << 19)
-# define R500_RGB_ADDR2(x) ((x) << 20)
-# define R500_RGB_ADDR2_CONST (1 << 28)
-# define R500_RGB_ADDR2_REL (1 << 29)
-# define R500_RGB_SRCP_OP_1_MINUS_2RGB0 (0 << 30)
-# define R500_RGB_SRCP_OP_RGB1_MINUS_RGB0 (1 << 30)
-# define R500_RGB_SRCP_OP_RGB1_PLUS_RGB0 (2 << 30)
-# define R500_RGB_SRCP_OP_1_MINUS_RGB0 (3 << 30)
-#define R500_US_CMN_INST_0 0xb800
-# define R500_INST_TYPE_MASK (3 << 0)
-# define R500_INST_TYPE_ALU (0 << 0)
-# define R500_INST_TYPE_OUT (1 << 0)
-# define R500_INST_TYPE_FC (2 << 0)
-# define R500_INST_TYPE_TEX (3 << 0)
-# define R500_INST_TEX_SEM_WAIT (1 << 2)
-# define R500_INST_RGB_PRED_SEL_NONE (0 << 3)
-# define R500_INST_RGB_PRED_SEL_RGBA (1 << 3)
-# define R500_INST_RGB_PRED_SEL_RRRR (2 << 3)
-# define R500_INST_RGB_PRED_SEL_GGGG (3 << 3)
-# define R500_INST_RGB_PRED_SEL_BBBB (4 << 3)
-# define R500_INST_RGB_PRED_SEL_AAAA (5 << 3)
-# define R500_INST_RGB_PRED_INV (1 << 6)
-# define R500_INST_WRITE_INACTIVE (1 << 7)
-# define R500_INST_LAST (1 << 8)
-# define R500_INST_NOP (1 << 9)
-# define R500_INST_ALU_WAIT (1 << 10)
-# define R500_INST_RGB_WMASK_R (1 << 11)
-# define R500_INST_RGB_WMASK_G (1 << 12)
-# define R500_INST_RGB_WMASK_B (1 << 13)
-# define R500_INST_ALPHA_WMASK (1 << 14)
-# define R500_INST_RGB_OMASK_R (1 << 15)
-# define R500_INST_RGB_OMASK_G (1 << 16)
-# define R500_INST_RGB_OMASK_B (1 << 17)
-# define R500_INST_ALPHA_OMASK (1 << 18)
-# define R500_INST_RGB_CLAMP (1 << 19)
-# define R500_INST_ALPHA_CLAMP (1 << 20)
-# define R500_INST_ALU_RESULT_SEL (1 << 21)
-# define R500_INST_ALU_RESULT_SEL_RED (0 << 21)
-# define R500_INST_ALU_RESULT_SEL_ALPHA (1 << 21)
-# define R500_INST_ALPHA_PRED_INV (1 << 22)
-# define R500_INST_ALU_RESULT_OP_EQ (0 << 23)
-# define R500_INST_ALU_RESULT_OP_LT (1 << 23)
-# define R500_INST_ALU_RESULT_OP_GE (2 << 23)
-# define R500_INST_ALU_RESULT_OP_NE (3 << 23)
-# define R500_INST_ALPHA_PRED_SEL_NONE (0 << 25)
-# define R500_INST_ALPHA_PRED_SEL_RGBA (1 << 25)
-# define R500_INST_ALPHA_PRED_SEL_RRRR (2 << 25)
-# define R500_INST_ALPHA_PRED_SEL_GGGG (3 << 25)
-# define R500_INST_ALPHA_PRED_SEL_BBBB (4 << 25)
-# define R500_INST_ALPHA_PRED_SEL_AAAA (5 << 25)
-/* XXX next four are kind of guessed */
-# define R500_INST_STAT_WE_R (1 << 28)
-# define R500_INST_STAT_WE_G (1 << 29)
-# define R500_INST_STAT_WE_B (1 << 30)
-# define R500_INST_STAT_WE_A (1 << 31)
-
-/* note that these are 8 bit lengths, despite the offsets, at least for R500 */
-#define R500_US_CODE_ADDR 0x4630
-# define R500_US_CODE_START_ADDR(x) ((x) << 0)
-# define R500_US_CODE_END_ADDR(x) ((x) << 16)
-#define R500_US_CODE_OFFSET 0x4638
-# define R500_US_CODE_OFFSET_ADDR(x) ((x) << 0)
-#define R500_US_CODE_RANGE 0x4634
-# define R500_US_CODE_RANGE_ADDR(x) ((x) << 0)
-# define R500_US_CODE_RANGE_SIZE(x) ((x) << 16)
-#define R500_US_CONFIG 0x4600
-# define R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO (1 << 1)
-#define R500_US_FC_ADDR_0 0xa000
-# define R500_FC_BOOL_ADDR(x) ((x) << 0)
-# define R500_FC_INT_ADDR(x) ((x) << 8)
-# define R500_FC_JUMP_ADDR(x) ((x) << 16)
-# define R500_FC_JUMP_GLOBAL (1 << 31)
-#define R500_US_FC_BOOL_CONST 0x4620
-# define R500_FC_KBOOL(x) (x)
-#define R500_US_FC_CTRL 0x4624
-# define R500_FC_TEST_EN (1 << 30)
-# define R500_FC_FULL_FC_EN (1 << 31)
-#define R500_US_FC_INST_0 0x9800
-# define R500_FC_OP_JUMP (0 << 0)
-# define R500_FC_OP_LOOP (1 << 0)
-# define R500_FC_OP_ENDLOOP (2 << 0)
-# define R500_FC_OP_REP (3 << 0)
-# define R500_FC_OP_ENDREP (4 << 0)
-# define R500_FC_OP_BREAKLOOP (5 << 0)
-# define R500_FC_OP_BREAKREP (6 << 0)
-# define R500_FC_OP_CONTINUE (7 << 0)
-# define R500_FC_B_ELSE (1 << 4)
-# define R500_FC_JUMP_ANY (1 << 5)
-# define R500_FC_A_OP_NONE (0 << 6)
-# define R500_FC_A_OP_POP (1 << 6)
-# define R500_FC_A_OP_PUSH (2 << 6)
-# define R500_FC_JUMP_FUNC(x) ((x) << 8)
-# define R500_FC_B_POP_CNT(x) ((x) << 16)
-# define R500_FC_B_OP0_NONE (0 << 24)
-# define R500_FC_B_OP0_DECR (1 << 24)
-# define R500_FC_B_OP0_INCR (2 << 24)
-# define R500_FC_B_OP1_NONE (0 << 26)
-# define R500_FC_B_OP1_DECR (1 << 26)
-# define R500_FC_B_OP1_INCR (2 << 26)
-# define R500_FC_IGNORE_UNCOVERED (1 << 28)
-#define R500_US_FC_INT_CONST_0 0x4c00
-# define R500_FC_INT_CONST_KR(x) ((x) << 0)
-# define R500_FC_INT_CONST_KG(x) ((x) << 8)
-# define R500_FC_INT_CONST_KB(x) ((x) << 16)
-/* _0 through _15 */
-#define R500_US_FORMAT0_0 0x4640
-# define R500_FORMAT_TXWIDTH(x) ((x) << 0)
-# define R500_FORMAT_TXHEIGHT(x) ((x) << 11)
-# define R500_FORMAT_TXDEPTH(x) ((x) << 22)
-/* _0 through _3 */
-#define R500_US_OUT_FMT_0 0x46a4
-# define R500_OUT_FMT_C4_8 (0 << 0)
-# define R500_OUT_FMT_C4_10 (1 << 0)
-# define R500_OUT_FMT_C4_10_GAMMA (2 << 0)
-# define R500_OUT_FMT_C_16 (3 << 0)
-# define R500_OUT_FMT_C2_16 (4 << 0)
-# define R500_OUT_FMT_C4_16 (5 << 0)
-# define R500_OUT_FMT_C_16_MPEG (6 << 0)
-# define R500_OUT_FMT_C2_16_MPEG (7 << 0)
-# define R500_OUT_FMT_C2_4 (8 << 0)
-# define R500_OUT_FMT_C_3_3_2 (9 << 0)
-# define R500_OUT_FMT_C_6_5_6 (10 << 0)
-# define R500_OUT_FMT_C_11_11_10 (11 << 0)
-# define R500_OUT_FMT_C_10_11_11 (12 << 0)
-# define R500_OUT_FMT_C_2_10_10_10 (13 << 0)
-/* #define R500_OUT_FMT_RESERVED (14 << 0) */
-# define R500_OUT_FMT_UNUSED (15 << 0)
-# define R500_OUT_FMT_C_16_FP (16 << 0)
-# define R500_OUT_FMT_C2_16_FP (17 << 0)
-# define R500_OUT_FMT_C4_16_FP (18 << 0)
-# define R500_OUT_FMT_C_32_FP (19 << 0)
-# define R500_OUT_FMT_C2_32_FP (20 << 0)
-# define R500_OUT_FMT_C4_32_FP (21 << 0)
-# define R500_C0_SEL_A (0 << 8)
-# define R500_C0_SEL_R (1 << 8)
-# define R500_C0_SEL_G (2 << 8)
-# define R500_C0_SEL_B (3 << 8)
-# define R500_C1_SEL_A (0 << 10)
-# define R500_C1_SEL_R (1 << 10)
-# define R500_C1_SEL_G (2 << 10)
-# define R500_C1_SEL_B (3 << 10)
-# define R500_C2_SEL_A (0 << 12)
-# define R500_C2_SEL_R (1 << 12)
-# define R500_C2_SEL_G (2 << 12)
-# define R500_C2_SEL_B (3 << 12)
-# define R500_C3_SEL_A (0 << 14)
-# define R500_C3_SEL_R (1 << 14)
-# define R500_C3_SEL_G (2 << 14)
-# define R500_C3_SEL_B (3 << 14)
-# define R500_OUT_SIGN(x) ((x) << 16)
-# define R500_ROUND_ADJ (1 << 20)
-#define R500_US_PIXSIZE 0x4604
-# define R500_PIX_SIZE(x) (x)
-#define R500_US_TEX_ADDR_0 0x9800
-# define R500_TEX_SRC_ADDR(x) ((x) << 0)
-# define R500_TEX_SRC_ADDR_REL (1 << 7)
-# define R500_TEX_SRC_S_SWIZ_R (0 << 8)
-# define R500_TEX_SRC_S_SWIZ_G (1 << 8)
-# define R500_TEX_SRC_S_SWIZ_B (2 << 8)
-# define R500_TEX_SRC_S_SWIZ_A (3 << 8)
-# define R500_TEX_SRC_T_SWIZ_R (0 << 10)
-# define R500_TEX_SRC_T_SWIZ_G (1 << 10)
-# define R500_TEX_SRC_T_SWIZ_B (2 << 10)
-# define R500_TEX_SRC_T_SWIZ_A (3 << 10)
-# define R500_TEX_SRC_R_SWIZ_R (0 << 12)
-# define R500_TEX_SRC_R_SWIZ_G (1 << 12)
-# define R500_TEX_SRC_R_SWIZ_B (2 << 12)
-# define R500_TEX_SRC_R_SWIZ_A (3 << 12)
-# define R500_TEX_SRC_Q_SWIZ_R (0 << 14)
-# define R500_TEX_SRC_Q_SWIZ_G (1 << 14)
-# define R500_TEX_SRC_Q_SWIZ_B (2 << 14)
-# define R500_TEX_SRC_Q_SWIZ_A (3 << 14)
-# define R500_TEX_DST_ADDR(x) ((x) << 16)
-# define R500_TEX_DST_ADDR_REL (1 << 23)
-# define R500_TEX_DST_R_SWIZ_R (0 << 24)
-# define R500_TEX_DST_R_SWIZ_G (1 << 24)
-# define R500_TEX_DST_R_SWIZ_B (2 << 24)
-# define R500_TEX_DST_R_SWIZ_A (3 << 24)
-# define R500_TEX_DST_G_SWIZ_R (0 << 26)
-# define R500_TEX_DST_G_SWIZ_G (1 << 26)
-# define R500_TEX_DST_G_SWIZ_B (2 << 26)
-# define R500_TEX_DST_G_SWIZ_A (3 << 26)
-# define R500_TEX_DST_B_SWIZ_R (0 << 28)
-# define R500_TEX_DST_B_SWIZ_G (1 << 28)
-# define R500_TEX_DST_B_SWIZ_B (2 << 28)
-# define R500_TEX_DST_B_SWIZ_A (3 << 28)
-# define R500_TEX_DST_A_SWIZ_R (0 << 30)
-# define R500_TEX_DST_A_SWIZ_G (1 << 30)
-# define R500_TEX_DST_A_SWIZ_B (2 << 30)
-# define R500_TEX_DST_A_SWIZ_A (3 << 30)
-#define R500_US_TEX_ADDR_DXDY_0 0xa000
-# define R500_DX_ADDR(x) ((x) << 0)
-# define R500_DX_ADDR_REL (1 << 7)
-# define R500_DX_S_SWIZ_R (0 << 8)
-# define R500_DX_S_SWIZ_G (1 << 8)
-# define R500_DX_S_SWIZ_B (2 << 8)
-# define R500_DX_S_SWIZ_A (3 << 8)
-# define R500_DX_T_SWIZ_R (0 << 10)
-# define R500_DX_T_SWIZ_G (1 << 10)
-# define R500_DX_T_SWIZ_B (2 << 10)
-# define R500_DX_T_SWIZ_A (3 << 10)
-# define R500_DX_R_SWIZ_R (0 << 12)
-# define R500_DX_R_SWIZ_G (1 << 12)
-# define R500_DX_R_SWIZ_B (2 << 12)
-# define R500_DX_R_SWIZ_A (3 << 12)
-# define R500_DX_Q_SWIZ_R (0 << 14)
-# define R500_DX_Q_SWIZ_G (1 << 14)
-# define R500_DX_Q_SWIZ_B (2 << 14)
-# define R500_DX_Q_SWIZ_A (3 << 14)
-# define R500_DY_ADDR(x) ((x) << 16)
-# define R500_DY_ADDR_REL (1 << 17)
-# define R500_DY_S_SWIZ_R (0 << 24)
-# define R500_DY_S_SWIZ_G (1 << 24)
-# define R500_DY_S_SWIZ_B (2 << 24)
-# define R500_DY_S_SWIZ_A (3 << 24)
-# define R500_DY_T_SWIZ_R (0 << 26)
-# define R500_DY_T_SWIZ_G (1 << 26)
-# define R500_DY_T_SWIZ_B (2 << 26)
-# define R500_DY_T_SWIZ_A (3 << 26)
-# define R500_DY_R_SWIZ_R (0 << 28)
-# define R500_DY_R_SWIZ_G (1 << 28)
-# define R500_DY_R_SWIZ_B (2 << 28)
-# define R500_DY_R_SWIZ_A (3 << 28)
-# define R500_DY_Q_SWIZ_R (0 << 30)
-# define R500_DY_Q_SWIZ_G (1 << 30)
-# define R500_DY_Q_SWIZ_B (2 << 30)
-# define R500_DY_Q_SWIZ_A (3 << 30)
-#define R500_US_TEX_INST_0 0x9000
-# define R500_TEX_ID(x) ((x) << 16)
-# define R500_TEX_INST_NOP (0 << 22)
-# define R500_TEX_INST_LD (1 << 22)
-# define R500_TEX_INST_TEXKILL (2 << 22)
-# define R500_TEX_INST_PROJ (3 << 22)
-# define R500_TEX_INST_LODBIAS (4 << 22)
-# define R500_TEX_INST_LOD (5 << 22)
-# define R500_TEX_INST_DXDY (6 << 22)
-# define R500_TEX_SEM_ACQUIRE (1 << 25)
-# define R500_TEX_IGNORE_UNCOVERED (1 << 26)
-# define R500_TEX_UNSCALED (1 << 27)
-#define R300_US_W_FMT 0x46b4
-# define R300_W_FMT_W0 (0 << 0)
-# define R300_W_FMT_W24 (1 << 0)
-# define R300_W_FMT_W24FP (2 << 0)
-# define R300_W_SRC_US (0 << 2)
-# define R300_W_SRC_RAS (1 << 2)
-
-
-/* Packet0 field ordering to write all values to the same reg */
-#define RADEON_ONE_REG_WR (1 << 15)
-
-/* Draw a primitive from vertex data in arrays loaded via 3D_LOAD_VBPNTR.
- * Two parameter dwords:
- * 0. VAP_VTX_FMT: The first parameter is not written to hardware
- * 1. VAP_VF_CTL: The second parameter is a standard primitive emission dword.
- */
-#define R300_PACKET3_3D_DRAW_VBUF 0x00002800
-
-/* Draw a primitive from immediate vertices in this packet
- * Up to 16382 dwords:
- * 0. VAP_VTX_FMT: The first parameter is not written to hardware
- * 1. VAP_VF_CTL: The second parameter is a standard primitive emission dword.
- * 2 to end: Up to 16380 dwords of vertex data.
- */
-#define R300_PACKET3_3D_DRAW_IMMD 0x00002900
-
-/* Draw a primitive from vertex data in arrays loaded via 3D_LOAD_VBPNTR and
- * immediate vertices in this packet
- * Up to 16382 dwords:
- * 0. VAP_VTX_FMT: The first parameter is not written to hardware
- * 1. VAP_VF_CTL: The second parameter is a standard primitive emission dword.
- * 2 to end: Up to 16380 dwords of vertex data.
- */
-#define R300_PACKET3_3D_DRAW_INDX 0x00002A00
-
-
-/* Specify the full set of vertex arrays as (address, stride).
- * The first parameter is the number of vertex arrays specified.
- * The rest of the command is a variable length list of blocks, where
- * each block is three dwords long and specifies two arrays.
- * The first dword of a block is split into two words, the lower significant
- * word refers to the first array, the more significant word to the second
- * array in the block.
- * The low byte of each word contains the size of an array entry in dwords,
- * the high byte contains the stride of the array.
- * The second dword of a block contains the pointer to the first array,
- * the third dword of a block contains the pointer to the second array.
- * Note that if the total number of arrays is odd, the third dword of
- * the last block is omitted.
- */
-#define R300_PACKET3_3D_LOAD_VBPNTR 0x00002F00
-
-#define R300_PACKET3_INDX_BUFFER 0x00003300
-# define R300_INDX_BUFFER_DST_SHIFT 0
-# define R300_INDX_BUFFER_SKIP_SHIFT 16
-# define R300_INDX_BUFFER_ONE_REG_WR (1<<31)
-
-/* Same as R300_PACKET3_3D_DRAW_VBUF but without VAP_VTX_FMT */
-#define R300_PACKET3_3D_DRAW_VBUF_2 0x00003400
-/* Same as R300_PACKET3_3D_DRAW_IMMD but without VAP_VTX_FMT */
-#define R300_PACKET3_3D_DRAW_IMMD_2 0x00003500
-/* Same as R300_PACKET3_3D_DRAW_INDX but without VAP_VTX_FMT */
-#define R300_PACKET3_3D_DRAW_INDX_2 0x00003600
-
-/* Clears a portion of hierachical Z RAM
- * 3 dword parameters
- * 0. START
- * 1. COUNT: 13:0 (max is 0x3FFF)
- * 2. CLEAR_VALUE: Value to write into HIZ RAM.
- */
-#define R300_PACKET3_3D_CLEAR_HIZ 0x00003700
-
-/* Draws a set of primitives using vertex buffers pointed by the state data.
- * At least 2 Parameters:
- * 0. VAP_VF_CNTL: The first parameter is a standard primitive emission dword.
- * 2 to end: Data or indices (see other 3D_DRAW_* packets for details)
- */
-#define R300_PACKET3_3D_DRAW_128 0x00003900
-
-/* END: Packet 3 commands */
-
-
-/* Color formats for 2d packets
- */
-#define R300_CP_COLOR_FORMAT_CI8 2
-#define R300_CP_COLOR_FORMAT_ARGB1555 3
-#define R300_CP_COLOR_FORMAT_RGB565 4
-#define R300_CP_COLOR_FORMAT_ARGB8888 6
-#define R300_CP_COLOR_FORMAT_RGB332 7
-#define R300_CP_COLOR_FORMAT_RGB8 9
-#define R300_CP_COLOR_FORMAT_ARGB4444 15
-
-/*
- * CP type-3 packets
- */
-#define R300_CP_CMD_BITBLT_MULTI 0xC0009B00
-
-#endif /* _R300_REG_H */
-
-/* *INDENT-ON* */
-
-/* vim: set foldenable foldmarker=\\{,\\} foldmethod=marker : */
+++ /dev/null
-/**************************************************************************
-
-Copyright (C) 2004 Nicolai Haehnle.
-
-All Rights Reserved.
-
-Permission is hereby granted, free of charge, to any person obtaining a
-copy of this software and associated documentation files (the "Software"),
-to deal in the Software without restriction, including without limitation
-on the rights to use, copy, modify, merge, publish, distribute, sub
-license, and/or sell copies of the Software, and to permit persons to whom
-the Software is furnished to do so, subject to the following conditions:
-
-The above copyright notice and this permission notice (including the next
-paragraph) shall be included in all copies or substantial portions of the
-Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
-ATI, VA LINUX SYSTEMS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
-DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
-USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-**************************************************************************/
-
-/**
- * \file
- *
- * \brief R300 Render (Vertex Buffer Implementation)
- *
- * The immediate implementation has been removed from CVS in favor of the vertex
- * buffer implementation.
- *
- * The render functions are called by the pipeline manager to render a batch of
- * primitives. They return TRUE to pass on to the next stage (i.e. software
- * rasterization) or FALSE to indicate that the pipeline has finished after
- * rendering something.
- *
- * When falling back to software TCL still attempt to use hardware
- * rasterization.
- *
- * I am not sure that the cache related registers are setup correctly, but
- * obviously this does work... Further investigation is needed.
- *
- * \author Nicolai Haehnle <prefect_@gmx.net>
- *
- * \todo Add immediate implementation back? Perhaps this is useful if there are
- * no bugs...
- */
-
-#include "r300_render.h"
-
-#include "main/glheader.h"
-#include "main/imports.h"
-#include "main/enums.h"
-#include "main/macros.h"
-#include "main/context.h"
-#include "main/dd.h"
-#include "main/simple_list.h"
-#include "main/api_arrayelt.h"
-#include "swrast/swrast.h"
-#include "swrast_setup/swrast_setup.h"
-#include "vbo/vbo.h"
-#include "vbo/vbo_split.h"
-#include "r300_context.h"
-#include "r300_state.h"
-#include "r300_reg.h"
-#include "r300_emit.h"
-#include "r300_swtcl.h"
-
-/**
- * \brief Convert a OpenGL primitive type into a R300 primitive type.
- */
-int r300PrimitiveType(r300ContextPtr rmesa, int prim)
-{
- switch (prim & PRIM_MODE_MASK) {
- case GL_POINTS:
- return R300_VAP_VF_CNTL__PRIM_POINTS;
- break;
- case GL_LINES:
- return R300_VAP_VF_CNTL__PRIM_LINES;
- break;
- case GL_LINE_STRIP:
- return R300_VAP_VF_CNTL__PRIM_LINE_STRIP;
- break;
- case GL_LINE_LOOP:
- return R300_VAP_VF_CNTL__PRIM_LINE_LOOP;
- break;
- case GL_TRIANGLES:
- return R300_VAP_VF_CNTL__PRIM_TRIANGLES;
- break;
- case GL_TRIANGLE_STRIP:
- return R300_VAP_VF_CNTL__PRIM_TRIANGLE_STRIP;
- break;
- case GL_TRIANGLE_FAN:
- return R300_VAP_VF_CNTL__PRIM_TRIANGLE_FAN;
- break;
- case GL_QUADS:
- return R300_VAP_VF_CNTL__PRIM_QUADS;
- break;
- case GL_QUAD_STRIP:
- return R300_VAP_VF_CNTL__PRIM_QUAD_STRIP;
- break;
- case GL_POLYGON:
- return R300_VAP_VF_CNTL__PRIM_POLYGON;
- break;
- default:
- assert(0);
- return -1;
- break;
- }
-}
-
-int r300NumVerts(r300ContextPtr rmesa, int num_verts, int prim)
-{
- int verts_off = 0;
-
- switch (prim & PRIM_MODE_MASK) {
- case GL_POINTS:
- verts_off = 0;
- break;
- case GL_LINES:
- verts_off = num_verts % 2;
- break;
- case GL_LINE_STRIP:
- if (num_verts < 2)
- verts_off = num_verts;
- break;
- case GL_LINE_LOOP:
- if (num_verts < 2)
- verts_off = num_verts;
- break;
- case GL_TRIANGLES:
- verts_off = num_verts % 3;
- break;
- case GL_TRIANGLE_STRIP:
- if (num_verts < 3)
- verts_off = num_verts;
- break;
- case GL_TRIANGLE_FAN:
- if (num_verts < 3)
- verts_off = num_verts;
- break;
- case GL_QUADS:
- verts_off = num_verts % 4;
- break;
- case GL_QUAD_STRIP:
- if (num_verts < 4)
- verts_off = num_verts;
- else
- verts_off = num_verts % 2;
- break;
- case GL_POLYGON:
- if (num_verts < 3)
- verts_off = num_verts;
- break;
- default:
- assert(0);
- return -1;
- break;
- }
-
- return num_verts - verts_off;
-}
-
-static void r300FireEB(r300ContextPtr rmesa, int vertex_count, int type, int offset)
-{
- BATCH_LOCALS(&rmesa->radeon);
- int size;
-
- /* offset is in indices */
- BEGIN_BATCH(10);
- OUT_BATCH_PACKET3(R300_PACKET3_3D_DRAW_INDX_2, 0);
- if (rmesa->ind_buf.is_32bit) {
- /* convert to bytes */
- offset *= 4;
- size = vertex_count;
- OUT_BATCH(R300_VAP_VF_CNTL__PRIM_WALK_INDICES |
- (vertex_count << 16) | type |
- R300_VAP_VF_CNTL__INDEX_SIZE_32bit);
- } else {
- /* convert to bytes */
- offset *= 2;
- size = (vertex_count + 1) >> 1;
- OUT_BATCH(R300_VAP_VF_CNTL__PRIM_WALK_INDICES |
- (vertex_count << 16) | type);
- }
-
- if (!rmesa->radeon.radeonScreen->kernel_mm) {
- OUT_BATCH_PACKET3(R300_PACKET3_INDX_BUFFER, 2);
- OUT_BATCH(R300_INDX_BUFFER_ONE_REG_WR | (0 << R300_INDX_BUFFER_SKIP_SHIFT) |
- (R300_VAP_PORT_IDX0 >> 2));
- OUT_BATCH_RELOC(0, rmesa->ind_buf.bo, rmesa->ind_buf.bo_offset + offset, RADEON_GEM_DOMAIN_GTT, 0, 0);
- OUT_BATCH(size);
- } else {
- OUT_BATCH_PACKET3(R300_PACKET3_INDX_BUFFER, 2);
- OUT_BATCH(R300_INDX_BUFFER_ONE_REG_WR | (0 << R300_INDX_BUFFER_SKIP_SHIFT) |
- (R300_VAP_PORT_IDX0 >> 2));
- OUT_BATCH(rmesa->ind_buf.bo_offset + offset);
- OUT_BATCH(size);
- radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs,
- rmesa->ind_buf.bo, RADEON_GEM_DOMAIN_GTT, 0, 0);
- }
- END_BATCH();
-}
-
-static void r300EmitAOS(r300ContextPtr rmesa, GLuint nr, GLuint offset)
-{
- BATCH_LOCALS(&rmesa->radeon);
- uint32_t voffset;
- int sz = 1 + (nr >> 1) * 3 + (nr & 1) * 2;
- int i;
-
- if (RADEON_DEBUG & RADEON_VERTS)
- fprintf(stderr, "%s: nr=%d, ofs=0x%08x\n", __FUNCTION__, nr,
- offset);
-
- if (!rmesa->radeon.radeonScreen->kernel_mm) {
- BEGIN_BATCH(sz+2+(nr * 2));
- OUT_BATCH_PACKET3(R300_PACKET3_3D_LOAD_VBPNTR, sz - 1);
- OUT_BATCH(nr);
-
- for (i = 0; i + 1 < nr; i += 2) {
- OUT_BATCH((rmesa->radeon.tcl.aos[i].components << 0) |
- (rmesa->radeon.tcl.aos[i].stride << 8) |
- (rmesa->radeon.tcl.aos[i + 1].components << 16) |
- (rmesa->radeon.tcl.aos[i + 1].stride << 24));
-
- voffset = rmesa->radeon.tcl.aos[i + 0].offset +
- offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride;
- OUT_BATCH_RELOC(voffset,
- rmesa->radeon.tcl.aos[i].bo,
- voffset,
- RADEON_GEM_DOMAIN_GTT,
- 0, 0);
- voffset = rmesa->radeon.tcl.aos[i + 1].offset +
- offset * 4 * rmesa->radeon.tcl.aos[i + 1].stride;
- OUT_BATCH_RELOC(voffset,
- rmesa->radeon.tcl.aos[i+1].bo,
- voffset,
- RADEON_GEM_DOMAIN_GTT,
- 0, 0);
- }
-
- if (nr & 1) {
- OUT_BATCH((rmesa->radeon.tcl.aos[nr - 1].components << 0) |
- (rmesa->radeon.tcl.aos[nr - 1].stride << 8));
- voffset = rmesa->radeon.tcl.aos[nr - 1].offset +
- offset * 4 * rmesa->radeon.tcl.aos[nr - 1].stride;
- OUT_BATCH_RELOC(voffset,
- rmesa->radeon.tcl.aos[nr - 1].bo,
- voffset,
- RADEON_GEM_DOMAIN_GTT,
- 0, 0);
- }
- END_BATCH();
- } else {
-
- BEGIN_BATCH(sz+2+(nr * 2));
- OUT_BATCH_PACKET3(R300_PACKET3_3D_LOAD_VBPNTR, sz - 1);
- OUT_BATCH(nr);
-
- for (i = 0; i + 1 < nr; i += 2) {
- OUT_BATCH((rmesa->radeon.tcl.aos[i].components << 0) |
- (rmesa->radeon.tcl.aos[i].stride << 8) |
- (rmesa->radeon.tcl.aos[i + 1].components << 16) |
- (rmesa->radeon.tcl.aos[i + 1].stride << 24));
-
- voffset = rmesa->radeon.tcl.aos[i + 0].offset +
- offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride;
- OUT_BATCH(voffset);
- voffset = rmesa->radeon.tcl.aos[i + 1].offset +
- offset * 4 * rmesa->radeon.tcl.aos[i + 1].stride;
- OUT_BATCH(voffset);
- }
-
- if (nr & 1) {
- OUT_BATCH((rmesa->radeon.tcl.aos[nr - 1].components << 0) |
- (rmesa->radeon.tcl.aos[nr - 1].stride << 8));
- voffset = rmesa->radeon.tcl.aos[nr - 1].offset +
- offset * 4 * rmesa->radeon.tcl.aos[nr - 1].stride;
- OUT_BATCH(voffset);
- }
- for (i = 0; i + 1 < nr; i += 2) {
- voffset = rmesa->radeon.tcl.aos[i + 0].offset +
- offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride;
- radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs,
- rmesa->radeon.tcl.aos[i+0].bo,
- RADEON_GEM_DOMAIN_GTT,
- 0, 0);
- voffset = rmesa->radeon.tcl.aos[i + 1].offset +
- offset * 4 * rmesa->radeon.tcl.aos[i + 1].stride;
- radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs,
- rmesa->radeon.tcl.aos[i+1].bo,
- RADEON_GEM_DOMAIN_GTT,
- 0, 0);
- }
- if (nr & 1) {
- voffset = rmesa->radeon.tcl.aos[nr - 1].offset +
- offset * 4 * rmesa->radeon.tcl.aos[nr - 1].stride;
- radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs,
- rmesa->radeon.tcl.aos[nr-1].bo,
- RADEON_GEM_DOMAIN_GTT,
- 0, 0);
- }
- END_BATCH();
- }
-
-}
-
-static void r300FireAOS(r300ContextPtr rmesa, int vertex_count, int type)
-{
- BATCH_LOCALS(&rmesa->radeon);
-
- r300_emit_scissor(rmesa->radeon.glCtx);
- BEGIN_BATCH(3);
- OUT_BATCH_PACKET3(R300_PACKET3_3D_DRAW_VBUF_2, 0);
- OUT_BATCH(R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_LIST | (vertex_count << 16) | type);
- END_BATCH();
-}
-
-void r300RunRenderPrimitive(struct gl_context * ctx, int start, int end, int prim)
-{
- r300ContextPtr rmesa = R300_CONTEXT(ctx);
- BATCH_LOCALS(&rmesa->radeon);
- int type, num_verts;
-
- type = r300PrimitiveType(rmesa, prim);
- num_verts = r300NumVerts(rmesa, end - start, prim);
-
- if (type < 0 || num_verts <= 0)
- return;
-
- if (rmesa->ind_buf.bo) {
- GLuint first, incr, offset = 0;
-
- if (!split_prim_inplace(prim & PRIM_MODE_MASK, &first, &incr) &&
- num_verts > 65500) {
- WARN_ONCE("Fixme: can't handle spliting prim %d\n", prim);
- return;
- }
-
-
- r300EmitAOS(rmesa, rmesa->radeon.tcl.aos_count, 0);
- if (rmesa->radeon.radeonScreen->kernel_mm) {
- BEGIN_BATCH_NO_AUTOSTATE(2);
- OUT_BATCH_REGSEQ(R300_VAP_VF_MAX_VTX_INDX, 1);
- OUT_BATCH(rmesa->radeon.tcl.aos[0].count);
- END_BATCH();
- }
-
- r300_emit_scissor(rmesa->radeon.glCtx);
- while (num_verts > 0) {
- int nr;
- int align;
-
- nr = MIN2(num_verts, 65535);
- nr -= (nr - first) % incr;
-
- /* get alignment for IB correct */
- if (nr != num_verts) {
- do {
- align = nr * (rmesa->ind_buf.is_32bit ? 4 : 2);
- if (align % 4)
- nr -= incr;
- } while(align % 4);
- if (nr <= 0) {
- WARN_ONCE("did the impossible happen? we never aligned nr to dword\n");
- return;
- }
-
- }
- r300FireEB(rmesa, nr, type, offset);
-
- num_verts -= nr;
- offset += nr;
- }
-
- } else {
- GLuint first, incr, offset = 0;
-
- if (!split_prim_inplace(prim & PRIM_MODE_MASK, &first, &incr) &&
- num_verts > 65535) {
- WARN_ONCE("Fixme: can't handle spliting prim %d\n", prim);
- return;
- }
-
- if (rmesa->radeon.radeonScreen->kernel_mm) {
- BEGIN_BATCH_NO_AUTOSTATE(2);
- OUT_BATCH_REGSEQ(R300_VAP_VF_MAX_VTX_INDX, 1);
- OUT_BATCH(rmesa->radeon.tcl.aos[0].count);
- END_BATCH();
- }
-
- r300_emit_scissor(rmesa->radeon.glCtx);
- while (num_verts > 0) {
- int nr;
- nr = MIN2(num_verts, 65535);
- nr -= (nr - first) % incr;
- r300EmitAOS(rmesa, rmesa->radeon.tcl.aos_count, start + offset);
- r300FireAOS(rmesa, nr, type);
- num_verts -= nr;
- offset += nr;
- }
- }
- COMMIT_BATCH();
-}
-
-static const char *getFallbackString(r300ContextPtr rmesa, uint32_t bit)
-{
- static char common_fallback_str[32];
- switch (bit) {
- case R300_FALLBACK_VERTEX_PROGRAM :
- return "vertex program";
- case R300_FALLBACK_LINE_SMOOTH:
- return "smooth lines";
- case R300_FALLBACK_POINT_SMOOTH:
- return "smooth points";
- case R300_FALLBACK_POLYGON_SMOOTH:
- return "smooth polygons";
- case R300_FALLBACK_LINE_STIPPLE:
- return "line stipple";
- case R300_FALLBACK_POLYGON_STIPPLE:
- return "polygon stipple";
- case R300_FALLBACK_STENCIL_TWOSIDE:
- return "two-sided stencil";
- case R300_FALLBACK_RENDER_MODE:
- return "render mode != GL_RENDER";
- case R300_FALLBACK_FRAGMENT_PROGRAM:
- return "fragment program";
- case R300_FALLBACK_RADEON_COMMON:
- snprintf(common_fallback_str, 32, "radeon common 0x%08x", rmesa->radeon.Fallback);
- return common_fallback_str;
- case R300_FALLBACK_AOS_LIMIT:
- return "aos limit";
- case R300_FALLBACK_INVALID_BUFFERS:
- return "invalid buffers";
- default:
- return "unknown";
- }
-}
-
-void r300SwitchFallback(struct gl_context *ctx, uint32_t bit, GLboolean mode)
-{
- TNLcontext *tnl = TNL_CONTEXT(ctx);
- r300ContextPtr rmesa = R300_CONTEXT(ctx);
- uint32_t old_fallback = rmesa->fallback;
- static uint32_t fallback_warn = 0;
-
- if (mode) {
- if ((fallback_warn & bit) == 0) {
- if (RADEON_DEBUG & RADEON_FALLBACKS)
- fprintf(stderr, "WARNING! Falling back to software for %s\n", getFallbackString(rmesa, bit));
- fallback_warn |= bit;
- }
- rmesa->fallback |= bit;
-
- /* update only if we change from no tcl fallbacks to some tcl fallbacks */
- if (rmesa->options.hw_tcl_enabled) {
- if (((old_fallback & R300_TCL_FALLBACK_MASK) == 0) &&
- ((bit & R300_TCL_FALLBACK_MASK) > 0)) {
- R300_STATECHANGE(rmesa, vap_cntl_status);
- rmesa->hw.vap_cntl_status.cmd[1] |= R300_VAP_TCL_BYPASS;
- }
- }
-
- /* update only if we change from no raster fallbacks to some raster fallbacks */
- if (((old_fallback & R300_RASTER_FALLBACK_MASK) == 0) &&
- ((bit & R300_RASTER_FALLBACK_MASK) > 0)) {
-
- radeon_firevertices(&rmesa->radeon);
- rmesa->radeon.swtcl.RenderIndex = ~0;
- _swsetup_Wakeup( ctx );
- }
- } else {
- rmesa->fallback &= ~bit;
-
- /* update only if we have disabled all tcl fallbacks */
- if (rmesa->options.hw_tcl_enabled) {
- if ((old_fallback & R300_TCL_FALLBACK_MASK) == bit) {
- R300_STATECHANGE(rmesa, vap_cntl_status);
- rmesa->hw.vap_cntl_status.cmd[1] &= ~R300_VAP_TCL_BYPASS;
- }
- }
-
- /* update only if we have disabled all raster fallbacks */
- if ((old_fallback & R300_RASTER_FALLBACK_MASK) == bit) {
- _swrast_flush( ctx );
-
- tnl->Driver.Render.Start = r300RenderStart;
- tnl->Driver.Render.Finish = r300RenderFinish;
- tnl->Driver.Render.PrimitiveNotify = r300RenderPrimitive;
- tnl->Driver.Render.ResetLineStipple = r300ResetLineStipple;
- tnl->Driver.Render.BuildVertices = _tnl_build_vertices;
- tnl->Driver.Render.CopyPV = _tnl_copy_pv;
- tnl->Driver.Render.Interp = _tnl_interp;
-
- _tnl_invalidate_vertex_state( ctx, ~0 );
- _tnl_invalidate_vertices( ctx, ~0 );
- }
- }
-
-}
+++ /dev/null
-/*
- * Copyright 2009 Maciej Cencora <m.cencora@gmail.com>
- *
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial
- * portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
- * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
- * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
- * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-
-#ifndef __R300_RENDER_H__
-#define __R300_RENDER_H__
-
-#include "main/mtypes.h"
-
-#define R300_FALLBACK_VERTEX_PROGRAM (1 << 0)
-#define R300_TCL_FALLBACK_MASK 0x0000ffff
-
-#define R300_FALLBACK_LINE_SMOOTH (1 << 16)
-#define R300_FALLBACK_POINT_SMOOTH (1 << 17)
-#define R300_FALLBACK_POLYGON_SMOOTH (1 << 18)
-#define R300_FALLBACK_LINE_STIPPLE (1 << 19)
-#define R300_FALLBACK_POLYGON_STIPPLE (1 << 20)
-#define R300_FALLBACK_STENCIL_TWOSIDE (1 << 21)
-#define R300_FALLBACK_RENDER_MODE (1 << 22)
-#define R300_FALLBACK_FRAGMENT_PROGRAM (1 << 23)
-#define R300_FALLBACK_RADEON_COMMON (1 << 29)
-#define R300_FALLBACK_AOS_LIMIT (1 << 30)
-#define R300_FALLBACK_INVALID_BUFFERS (1 << 31)
-#define R300_RASTER_FALLBACK_MASK 0xffff0000
-
-#define MASK_XYZW (R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W)
-#define MASK_X R300_WRITE_ENA_X
-#define MASK_Y R300_WRITE_ENA_Y
-#define MASK_Z R300_WRITE_ENA_Z
-#define MASK_W R300_WRITE_ENA_W
-
-#if SWIZZLE_X != R300_INPUT_ROUTE_SELECT_X || \
- SWIZZLE_Y != R300_INPUT_ROUTE_SELECT_Y || \
- SWIZZLE_Z != R300_INPUT_ROUTE_SELECT_Z || \
- SWIZZLE_W != R300_INPUT_ROUTE_SELECT_W || \
- SWIZZLE_ZERO != R300_INPUT_ROUTE_SELECT_ZERO || \
- SWIZZLE_ONE != R300_INPUT_ROUTE_SELECT_ONE
-#error Cannot change these!
-#endif
-
-extern const struct tnl_pipeline_stage _r300_render_stage;
-
-extern void r300SwitchFallback(struct gl_context *ctx, uint32_t bit, GLboolean mode);
-
-extern void r300RunRenderPrimitive(struct gl_context * ctx, int start, int end, int prim);
-
-#endif
+++ /dev/null
-/*
- * Copyright 2009 Maciej Cencora <m.cencora@gmail.com>
- *
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial
- * portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
- * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
- * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
- * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-
-#include "main/glheader.h"
-
-#include "program/program.h"
-#include "tnl/tnl.h"
-#include "r300_context.h"
-#include "r300_fragprog_common.h"
-
-static void freeFragProgCache(struct gl_context *ctx, struct r300_fragment_program_cont *cache)
-{
- struct r300_fragment_program *tmp, *fp = cache->progs;
-
- while (fp) {
- tmp = fp->next;
- rc_constants_destroy(&fp->code.constants);
- free(fp);
- fp = tmp;
- }
-}
-
-static void freeVertProgCache(struct gl_context *ctx, struct r300_vertex_program_cont *cache)
-{
- struct r300_vertex_program *tmp, *vp = cache->progs;
-
- while (vp) {
- tmp = vp->next;
- rc_constants_destroy(&vp->code.constants);
- _mesa_reference_vertprog(ctx, &vp->Base, NULL);
- free(vp);
- vp = tmp;
- }
-}
-
-static struct gl_program *r300NewProgram(struct gl_context * ctx, GLenum target,
- GLuint id)
-{
- struct r300_vertex_program_cont *vp;
- struct r300_fragment_program_cont *fp;
-
- switch (target) {
- case GL_VERTEX_STATE_PROGRAM_NV:
- case GL_VERTEX_PROGRAM_ARB:
- vp = CALLOC_STRUCT(r300_vertex_program_cont);
- return _mesa_init_vertex_program(ctx, &vp->mesa_program, target, id);
-
- case GL_FRAGMENT_PROGRAM_NV:
- case GL_FRAGMENT_PROGRAM_ARB:
- fp = CALLOC_STRUCT(r300_fragment_program_cont);
- return _mesa_init_fragment_program(ctx, &fp->Base, target, id);
-
- default:
- _mesa_problem(ctx, "Bad target in r300NewProgram");
- }
-
- return NULL;
-}
-
-static void r300DeleteProgram(struct gl_context * ctx, struct gl_program *prog)
-{
- struct r300_vertex_program_cont *vp = (struct r300_vertex_program_cont *)prog;
- struct r300_fragment_program_cont *fp = (struct r300_fragment_program_cont *)prog;
-
- switch (prog->Target) {
- case GL_VERTEX_PROGRAM_ARB:
- freeVertProgCache(ctx, vp);
- break;
- case GL_FRAGMENT_PROGRAM_ARB:
- freeFragProgCache(ctx, fp);
- break;
- }
-
- _mesa_delete_program(ctx, prog);
-}
-
-static GLboolean
-r300ProgramStringNotify(struct gl_context * ctx, GLenum target, struct gl_program *prog)
-{
- struct r300_vertex_program_cont *vp = (struct r300_vertex_program_cont *)prog;
- struct r300_fragment_program_cont *fp = (struct r300_fragment_program_cont *)prog;
-
- switch (target) {
- case GL_VERTEX_PROGRAM_ARB:
- freeVertProgCache(ctx, vp);
- vp->progs = NULL;
- break;
- case GL_FRAGMENT_PROGRAM_ARB:
- freeFragProgCache(ctx, fp);
- fp->progs = NULL;
- break;
- }
-
- /* need this for tcl fallbacks */
- (void) _tnl_program_string(ctx, target, prog);
-
- /* XXX check if program is legal, within limits */
- return GL_TRUE;
-}
-
-static GLboolean
-r300IsProgramNative(struct gl_context * ctx, GLenum target, struct gl_program *prog)
-{
- if (target == GL_FRAGMENT_PROGRAM_ARB) {
- struct r300_fragment_program *fp = r300SelectAndTranslateFragmentShader(ctx);
-
- return !fp->error;
- } else {
- struct r300_vertex_program *vp = r300SelectAndTranslateVertexShader(ctx);
-
- return !vp->error;
- }
-}
-
-void r300InitShaderFuncs(struct dd_function_table *functions)
-{
- functions->NewProgram = r300NewProgram;
- functions->DeleteProgram = r300DeleteProgram;
- functions->ProgramStringNotify = r300ProgramStringNotify;
- functions->IsProgramNative = r300IsProgramNative;
-}
+++ /dev/null
-/*
-Copyright (C) The Weather Channel, Inc. 2002.
-Copyright (C) 2004 Nicolai Haehnle.
-All Rights Reserved.
-
-The Weather Channel (TM) funded Tungsten Graphics to develop the
-initial release of the Radeon 8500 driver under the XFree86 license.
-This notice must be preserved.
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-**************************************************************************/
-
-/**
- * \file
- *
- * \author Nicolai Haehnle <prefect_@gmx.net>
- */
-
-#include "main/glheader.h"
-#include "main/state.h"
-#include "main/imports.h"
-#include "main/enums.h"
-#include "main/macros.h"
-#include "main/context.h"
-#include "main/dd.h"
-#include "main/framebuffer.h"
-#include "main/simple_list.h"
-#include "main/api_arrayelt.h"
-
-#include "drivers/common/meta.h"
-#include "swrast/swrast.h"
-#include "swrast_setup/swrast_setup.h"
-#include "program/prog_parameter.h"
-#include "program/prog_statevars.h"
-#include "vbo/vbo.h"
-#include "tnl/tnl.h"
-
-#include "r300_context.h"
-#include "r300_state.h"
-#include "r300_reg.h"
-#include "r300_emit.h"
-#include "r300_fragprog_common.h"
-#include "r300_render.h"
-#include "r300_vertprog.h"
-
-static void r300BlendColor(struct gl_context * ctx, const GLfloat cf[4])
-{
- r300ContextPtr rmesa = R300_CONTEXT(ctx);
-
- R300_STATECHANGE(rmesa, blend_color);
-
- if (rmesa->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) {
- GLuint r = IROUND(cf[0]*1023.0f);
- GLuint g = IROUND(cf[1]*1023.0f);
- GLuint b = IROUND(cf[2]*1023.0f);
- GLuint a = IROUND(cf[3]*1023.0f);
-
- rmesa->hw.blend_color.cmd[1] = r | (a << 16);
- rmesa->hw.blend_color.cmd[2] = b | (g << 16);
- } else {
- GLubyte color[4];
- CLAMPED_FLOAT_TO_UBYTE(color[0], cf[0]);
- CLAMPED_FLOAT_TO_UBYTE(color[1], cf[1]);
- CLAMPED_FLOAT_TO_UBYTE(color[2], cf[2]);
- CLAMPED_FLOAT_TO_UBYTE(color[3], cf[3]);
-
- rmesa->hw.blend_color.cmd[1] = PACK_COLOR_8888(color[3], color[0],
- color[1], color[2]);
- }
-}
-
-/**
- * Calculate the hardware blend factor setting. This same function is used
- * for source and destination of both alpha and RGB.
- *
- * \returns
- * The hardware register value for the specified blend factor. This value
- * will need to be shifted into the correct position for either source or
- * destination factor.
- *
- * \todo
- * Since the two cases where source and destination are handled differently
- * are essentially error cases, they should never happen. Determine if these
- * cases can be removed.
- */
-static int blend_factor(GLenum factor, GLboolean is_src)
-{
- switch (factor) {
- case GL_ZERO:
- return R300_BLEND_GL_ZERO;
- break;
- case GL_ONE:
- return R300_BLEND_GL_ONE;
- break;
- case GL_DST_COLOR:
- return R300_BLEND_GL_DST_COLOR;
- break;
- case GL_ONE_MINUS_DST_COLOR:
- return R300_BLEND_GL_ONE_MINUS_DST_COLOR;
- break;
- case GL_SRC_COLOR:
- return R300_BLEND_GL_SRC_COLOR;
- break;
- case GL_ONE_MINUS_SRC_COLOR:
- return R300_BLEND_GL_ONE_MINUS_SRC_COLOR;
- break;
- case GL_SRC_ALPHA:
- return R300_BLEND_GL_SRC_ALPHA;
- break;
- case GL_ONE_MINUS_SRC_ALPHA:
- return R300_BLEND_GL_ONE_MINUS_SRC_ALPHA;
- break;
- case GL_DST_ALPHA:
- return R300_BLEND_GL_DST_ALPHA;
- break;
- case GL_ONE_MINUS_DST_ALPHA:
- return R300_BLEND_GL_ONE_MINUS_DST_ALPHA;
- break;
- case GL_SRC_ALPHA_SATURATE:
- return (is_src) ? R300_BLEND_GL_SRC_ALPHA_SATURATE :
- R300_BLEND_GL_ZERO;
- break;
- case GL_CONSTANT_COLOR:
- return R300_BLEND_GL_CONST_COLOR;
- break;
- case GL_ONE_MINUS_CONSTANT_COLOR:
- return R300_BLEND_GL_ONE_MINUS_CONST_COLOR;
- break;
- case GL_CONSTANT_ALPHA:
- return R300_BLEND_GL_CONST_ALPHA;
- break;
- case GL_ONE_MINUS_CONSTANT_ALPHA:
- return R300_BLEND_GL_ONE_MINUS_CONST_ALPHA;
- break;
- default:
- fprintf(stderr, "unknown blend factor %x\n", factor);
- return (is_src) ? R300_BLEND_GL_ONE : R300_BLEND_GL_ZERO;
- break;
- }
-}
-
-/**
- * Sets both the blend equation and the blend function.
- * This is done in a single
- * function because some blend equations (i.e., \c GL_MIN and \c GL_MAX)
- * change the interpretation of the blend function.
- * Also, make sure that blend function and blend equation are set to their
- * default value if color blending is not enabled, since at least blend
- * equations GL_MIN and GL_FUNC_REVERSE_SUBTRACT will cause wrong results
- * otherwise for unknown reasons.
- */
-
-/* helper function */
-static void r300SetBlendCntl(r300ContextPtr r300, int func, int eqn,
- int cbits, int funcA, int eqnA)
-{
- GLuint new_ablend, new_cblend;
-
-#if 0
- fprintf(stderr,
- "eqnA=%08x funcA=%08x eqn=%08x func=%08x cbits=%08x\n",
- eqnA, funcA, eqn, func, cbits);
-#endif
- new_ablend = eqnA | funcA;
- new_cblend = eqn | func;
-
- /* Some blend factor combinations don't seem to work when the
- * BLEND_NO_SEPARATE bit is set.
- *
- * Especially problematic candidates are the ONE_MINUS_* flags,
- * but I can't see a real pattern.
- */
-#if 0
- if (new_ablend == new_cblend) {
- new_cblend |= R300_DISCARD_SRC_PIXELS_SRC_ALPHA_0;
- }
-#endif
- new_cblend |= cbits;
-
- if ((new_ablend != r300->hw.bld.cmd[R300_BLD_ABLEND]) ||
- (new_cblend != r300->hw.bld.cmd[R300_BLD_CBLEND])) {
- R300_STATECHANGE(r300, bld);
- r300->hw.bld.cmd[R300_BLD_ABLEND] = new_ablend;
- r300->hw.bld.cmd[R300_BLD_CBLEND] = new_cblend;
- }
-}
-
-static void r300SetBlendState(struct gl_context * ctx)
-{
- r300ContextPtr r300 = R300_CONTEXT(ctx);
- int func = (R300_BLEND_GL_ONE << R300_SRC_BLEND_SHIFT) |
- (R300_BLEND_GL_ZERO << R300_DST_BLEND_SHIFT);
- int eqn = R300_COMB_FCN_ADD_CLAMP;
- int funcA = (R300_BLEND_GL_ONE << R300_SRC_BLEND_SHIFT) |
- (R300_BLEND_GL_ZERO << R300_DST_BLEND_SHIFT);
- int eqnA = R300_COMB_FCN_ADD_CLAMP;
-
- if (ctx->Color.ColorLogicOpEnabled || !ctx->Color.BlendEnabled) {
- r300SetBlendCntl(r300, func, eqn, 0, func, eqn);
- return;
- }
-
- func =
- (blend_factor(ctx->Color.Blend[0].SrcRGB, GL_TRUE) <<
- R300_SRC_BLEND_SHIFT) | (blend_factor(ctx->Color.Blend[0].DstRGB,
- GL_FALSE) <<
- R300_DST_BLEND_SHIFT);
-
- switch (ctx->Color.Blend[0].EquationRGB) {
- case GL_FUNC_ADD:
- eqn = R300_COMB_FCN_ADD_CLAMP;
- break;
-
- case GL_FUNC_SUBTRACT:
- eqn = R300_COMB_FCN_SUB_CLAMP;
- break;
-
- case GL_FUNC_REVERSE_SUBTRACT:
- eqn = R300_COMB_FCN_RSUB_CLAMP;
- break;
-
- case GL_MIN:
- eqn = R300_COMB_FCN_MIN;
- func = (R300_BLEND_GL_ONE << R300_SRC_BLEND_SHIFT) |
- (R300_BLEND_GL_ONE << R300_DST_BLEND_SHIFT);
- break;
-
- case GL_MAX:
- eqn = R300_COMB_FCN_MAX;
- func = (R300_BLEND_GL_ONE << R300_SRC_BLEND_SHIFT) |
- (R300_BLEND_GL_ONE << R300_DST_BLEND_SHIFT);
- break;
-
- default:
- fprintf(stderr,
- "[%s:%u] Invalid RGB blend equation (0x%04x).\n",
- __FUNCTION__, __LINE__, ctx->Color.Blend[0].EquationRGB);
- return;
- }
-
- funcA =
- (blend_factor(ctx->Color.Blend[0].SrcA, GL_TRUE) <<
- R300_SRC_BLEND_SHIFT) | (blend_factor(ctx->Color.Blend[0].DstA,
- GL_FALSE) <<
- R300_DST_BLEND_SHIFT);
-
- switch (ctx->Color.Blend[0].EquationA) {
- case GL_FUNC_ADD:
- eqnA = R300_COMB_FCN_ADD_CLAMP;
- break;
-
- case GL_FUNC_SUBTRACT:
- eqnA = R300_COMB_FCN_SUB_CLAMP;
- break;
-
- case GL_FUNC_REVERSE_SUBTRACT:
- eqnA = R300_COMB_FCN_RSUB_CLAMP;
- break;
-
- case GL_MIN:
- eqnA = R300_COMB_FCN_MIN;
- funcA = (R300_BLEND_GL_ONE << R300_SRC_BLEND_SHIFT) |
- (R300_BLEND_GL_ONE << R300_DST_BLEND_SHIFT);
- break;
-
- case GL_MAX:
- eqnA = R300_COMB_FCN_MAX;
- funcA = (R300_BLEND_GL_ONE << R300_SRC_BLEND_SHIFT) |
- (R300_BLEND_GL_ONE << R300_DST_BLEND_SHIFT);
- break;
-
- default:
- fprintf(stderr,
- "[%s:%u] Invalid A blend equation (0x%04x).\n",
- __FUNCTION__, __LINE__, ctx->Color.Blend[0].EquationA);
- return;
- }
-
- r300SetBlendCntl(r300,
- func, eqn,
- (R300_SEPARATE_ALPHA_ENABLE |
- R300_READ_ENABLE |
- R300_ALPHA_BLEND_ENABLE), funcA, eqnA);
-}
-
-static void r300BlendEquationSeparate(struct gl_context * ctx,
- GLenum modeRGB, GLenum modeA)
-{
- r300SetBlendState(ctx);
-}
-
-static void r300BlendFuncSeparate(struct gl_context * ctx,
- GLenum sfactorRGB, GLenum dfactorRGB,
- GLenum sfactorA, GLenum dfactorA)
-{
- r300SetBlendState(ctx);
-}
-
-/**
- * Translate LogicOp enums into hardware representation.
- * Both use a very logical bit-wise layout, but unfortunately the order
- * of bits is reversed.
- */
-static GLuint translate_logicop(GLenum logicop)
-{
- GLuint bits = logicop - GL_CLEAR;
- bits = ((bits & 1) << 3) | ((bits & 2) << 1) | ((bits & 4) >> 1) | ((bits & 8) >> 3);
- return bits << R300_RB3D_ROPCNTL_ROP_SHIFT;
-}
-
-/**
- * Used internally to update the r300->hw hardware state to match the
- * current OpenGL state.
- */
-static void r300SetLogicOpState(struct gl_context *ctx)
-{
- r300ContextPtr r300 = R300_CONTEXT(ctx);
- R300_STATECHANGE(r300, rop);
- if (ctx->Color.ColorLogicOpEnabled) {
- r300->hw.rop.cmd[1] = R300_RB3D_ROPCNTL_ROP_ENABLE |
- translate_logicop(ctx->Color.LogicOp);
- } else {
- r300->hw.rop.cmd[1] = 0;
- }
-}
-
-/**
- * Called by Mesa when an application program changes the LogicOp state
- * via glLogicOp.
- */
-static void r300LogicOpcode(struct gl_context *ctx, GLenum logicop)
-{
- if (ctx->Color.ColorLogicOpEnabled)
- r300SetLogicOpState(ctx);
-}
-
-static void r300ClipPlane( struct gl_context *ctx, GLenum plane, const GLfloat *eq )
-{
- r300ContextPtr rmesa = R300_CONTEXT(ctx);
- GLint p;
- GLint *ip;
-
- /* no VAP UCP on non-TCL chipsets */
- if (!rmesa->options.hw_tcl_enabled)
- return;
-
- p = (GLint) plane - (GLint) GL_CLIP_PLANE0;
- ip = (GLint *)ctx->Transform._ClipUserPlane[p];
-
- R300_STATECHANGE( rmesa, vpucp[p] );
- rmesa->hw.vpucp[p].cmd[R300_VPUCP_X] = ip[0];
- rmesa->hw.vpucp[p].cmd[R300_VPUCP_Y] = ip[1];
- rmesa->hw.vpucp[p].cmd[R300_VPUCP_Z] = ip[2];
- rmesa->hw.vpucp[p].cmd[R300_VPUCP_W] = ip[3];
-}
-
-static void r300SetClipPlaneState(struct gl_context * ctx, GLenum cap, GLboolean state)
-{
- r300ContextPtr r300 = R300_CONTEXT(ctx);
- GLuint p;
-
- /* no VAP UCP on non-TCL chipsets */
- if (!r300->options.hw_tcl_enabled)
- return;
-
- p = cap - GL_CLIP_PLANE0;
- R300_STATECHANGE(r300, vap_clip_cntl);
- if (state) {
- r300->hw.vap_clip_cntl.cmd[1] |= (R300_VAP_UCP_ENABLE_0 << p);
- r300ClipPlane(ctx, cap, NULL);
- } else {
- r300->hw.vap_clip_cntl.cmd[1] &= ~(R300_VAP_UCP_ENABLE_0 << p);
- }
-}
-
-/**
- * Update our tracked culling state based on Mesa's state.
- */
-static void r300UpdateCulling(struct gl_context * ctx)
-{
- r300ContextPtr r300 = R300_CONTEXT(ctx);
- uint32_t val = 0;
-
- if (ctx->Polygon.CullFlag) {
- switch (ctx->Polygon.CullFaceMode) {
- case GL_FRONT:
- val = R300_CULL_FRONT;
- break;
- case GL_BACK:
- val = R300_CULL_BACK;
- break;
- case GL_FRONT_AND_BACK:
- val = R300_CULL_FRONT | R300_CULL_BACK;
- break;
- default:
- break;
- }
- }
-
- switch (ctx->Polygon.FrontFace) {
- case GL_CW:
- val |= R300_FRONT_FACE_CW;
- break;
- case GL_CCW:
- val |= R300_FRONT_FACE_CCW;
- break;
- default:
- break;
- }
-
- /* Winding is inverted when rendering to FBO */
- if (ctx->DrawBuffer && ctx->DrawBuffer->Name)
- val ^= R300_FRONT_FACE_CW;
-
- R300_STATECHANGE(r300, cul);
- r300->hw.cul.cmd[R300_CUL_CULL] = val;
-}
-
-static void r300SetPolygonOffsetState(struct gl_context * ctx, GLboolean state)
-{
- r300ContextPtr r300 = R300_CONTEXT(ctx);
-
- R300_STATECHANGE(r300, occlusion_cntl);
- if (state) {
- r300->hw.occlusion_cntl.cmd[1] |= (3 << 0);
- } else {
- r300->hw.occlusion_cntl.cmd[1] &= ~(3 << 0);
- }
-}
-
-static GLboolean current_fragment_program_writes_depth(struct gl_context* ctx)
-{
- r300ContextPtr r300 = R300_CONTEXT(ctx);
-
- return ctx->FragmentProgram._Current && r300->selected_fp->code.writes_depth;
-}
-
-static void r300SetEarlyZState(struct gl_context * ctx)
-{
- r300ContextPtr r300 = R300_CONTEXT(ctx);
- GLuint topZ = R300_ZTOP_ENABLE;
- GLuint w_fmt, fgdepthsrc;
-
- if (ctx->Color.AlphaEnabled && ctx->Color.AlphaFunc != GL_ALWAYS)
- topZ = R300_ZTOP_DISABLE;
- else if (current_fragment_program_writes_depth(ctx))
- topZ = R300_ZTOP_DISABLE;
- else if (ctx->FragmentProgram._Current && ctx->FragmentProgram._Current->UsesKill)
- topZ = R300_ZTOP_DISABLE;
- else if (r300->radeon.query.current)
- topZ = R300_ZTOP_DISABLE;
-
- if (topZ != r300->hw.zstencil_format.cmd[2]) {
- /* Note: This completely reemits the stencil format.
- * I have not tested whether this is strictly necessary,
- * or if emitting a write to ZB_ZTOP is enough.
- */
- R300_STATECHANGE(r300, zstencil_format);
- r300->hw.zstencil_format.cmd[2] = topZ;
- }
-
- /* w_fmt value is set to get best performance
- * see p.130 R5xx 3D acceleration guide v1.3 */
- if (current_fragment_program_writes_depth(ctx)) {
- fgdepthsrc = R300_FG_DEPTH_SRC_SHADER;
- w_fmt = R300_W_FMT_W24 | R300_W_SRC_US;
- } else {
- fgdepthsrc = R300_FG_DEPTH_SRC_SCAN;
- w_fmt = R300_W_FMT_W0 | R300_W_SRC_US;
- }
-
- if (w_fmt != r300->hw.us_out_fmt.cmd[5]) {
- R300_STATECHANGE(r300, us_out_fmt);
- r300->hw.us_out_fmt.cmd[5] = w_fmt;
- }
-
- if (fgdepthsrc != r300->hw.fg_depth_src.cmd[1]) {
- R300_STATECHANGE(r300, fg_depth_src);
- r300->hw.fg_depth_src.cmd[1] = fgdepthsrc;
- }
-}
-
-static void r300SetAlphaState(struct gl_context * ctx)
-{
- r300ContextPtr r300 = R300_CONTEXT(ctx);
- GLubyte refByte;
- uint32_t pp_misc = 0x0;
- GLboolean really_enabled = ctx->Color.AlphaEnabled;
-
- CLAMPED_FLOAT_TO_UBYTE(refByte, ctx->Color.AlphaRef);
-
- switch (ctx->Color.AlphaFunc) {
- case GL_NEVER:
- pp_misc |= R300_FG_ALPHA_FUNC_NEVER;
- break;
- case GL_LESS:
- pp_misc |= R300_FG_ALPHA_FUNC_LESS;
- break;
- case GL_EQUAL:
- pp_misc |= R300_FG_ALPHA_FUNC_EQUAL;
- break;
- case GL_LEQUAL:
- pp_misc |= R300_FG_ALPHA_FUNC_LE;
- break;
- case GL_GREATER:
- pp_misc |= R300_FG_ALPHA_FUNC_GREATER;
- break;
- case GL_NOTEQUAL:
- pp_misc |= R300_FG_ALPHA_FUNC_NOTEQUAL;
- break;
- case GL_GEQUAL:
- pp_misc |= R300_FG_ALPHA_FUNC_GE;
- break;
- case GL_ALWAYS:
- /*pp_misc |= FG_ALPHA_FUNC_ALWAYS; */
- really_enabled = GL_FALSE;
- break;
- }
-
- if (really_enabled) {
- pp_misc |= R300_FG_ALPHA_FUNC_ENABLE;
- pp_misc |= R500_FG_ALPHA_FUNC_8BIT;
- pp_misc |= (refByte & R300_FG_ALPHA_FUNC_VAL_MASK);
- } else {
- pp_misc = 0x0;
- }
-
- R300_STATECHANGE(r300, at);
- r300->hw.at.cmd[R300_AT_ALPHA_TEST] = pp_misc;
- r300->hw.at.cmd[R300_AT_UNKNOWN] = 0;
-}
-
-static void r300AlphaFunc(struct gl_context * ctx, GLenum func, GLfloat ref)
-{
- (void)func;
- (void)ref;
- r300SetAlphaState(ctx);
-}
-
-static int translate_func(int func)
-{
- switch (func) {
- case GL_NEVER:
- return R300_ZS_NEVER;
- case GL_LESS:
- return R300_ZS_LESS;
- case GL_EQUAL:
- return R300_ZS_EQUAL;
- case GL_LEQUAL:
- return R300_ZS_LEQUAL;
- case GL_GREATER:
- return R300_ZS_GREATER;
- case GL_NOTEQUAL:
- return R300_ZS_NOTEQUAL;
- case GL_GEQUAL:
- return R300_ZS_GEQUAL;
- case GL_ALWAYS:
- return R300_ZS_ALWAYS;
- }
- return 0;
-}
-
-static void r300SetDepthState(struct gl_context * ctx)
-{
- r300ContextPtr r300 = R300_CONTEXT(ctx);
-
- R300_STATECHANGE(r300, zs);
- r300->hw.zs.cmd[R300_ZS_CNTL_0] &= (R300_STENCIL_ENABLE |
- R300_STENCIL_FRONT_BACK |
- R500_STENCIL_REFMASK_FRONT_BACK);
- r300->hw.zs.cmd[R300_ZS_CNTL_1] &= ~(R300_ZS_MASK << R300_Z_FUNC_SHIFT);
-
- if (ctx->Depth.Test && ctx->DrawBuffer->_DepthBuffer) {
- r300->hw.zs.cmd[R300_ZS_CNTL_0] |= R300_Z_ENABLE;
- if (ctx->Depth.Mask)
- r300->hw.zs.cmd[R300_ZS_CNTL_0] |= R300_Z_WRITE_ENABLE;
- r300->hw.zs.cmd[R300_ZS_CNTL_1] |=
- translate_func(ctx->Depth.Func) << R300_Z_FUNC_SHIFT;
- }
-}
-
-static void r300CatchStencilFallback(struct gl_context *ctx)
-{
- r300ContextPtr rmesa = R300_CONTEXT(ctx);
- const unsigned back = ctx->Stencil._BackFace;
-
- if (rmesa->radeon.radeonScreen->kernel_mm &&
- (rmesa->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515)) {
- r300SwitchFallback(ctx, R300_FALLBACK_STENCIL_TWOSIDE, GL_FALSE);
- } else if (ctx->Stencil._Enabled &&
- (ctx->Stencil.Ref[0] != ctx->Stencil.Ref[back]
- || ctx->Stencil.ValueMask[0] != ctx->Stencil.ValueMask[back]
- || ctx->Stencil.WriteMask[0] != ctx->Stencil.WriteMask[back])) {
- r300SwitchFallback(ctx, R300_FALLBACK_STENCIL_TWOSIDE, GL_TRUE);
- } else {
- r300SwitchFallback(ctx, R300_FALLBACK_STENCIL_TWOSIDE, GL_FALSE);
- }
-}
-
-static void r300SetStencilState(struct gl_context * ctx, GLboolean state)
-{
- r300ContextPtr r300 = R300_CONTEXT(ctx);
- GLboolean hw_stencil = GL_FALSE;
-
- r300CatchStencilFallback(ctx);
-
- if (ctx->DrawBuffer) {
- struct radeon_renderbuffer *rrbStencil
- = radeon_get_renderbuffer(ctx->DrawBuffer, BUFFER_STENCIL);
- hw_stencil = (rrbStencil && rrbStencil->bo);
- }
-
- if (hw_stencil) {
- R300_STATECHANGE(r300, zs);
- if (state) {
- r300->hw.zs.cmd[R300_ZS_CNTL_0] |=
- R300_STENCIL_ENABLE;
- } else {
- r300->hw.zs.cmd[R300_ZS_CNTL_0] &=
- ~R300_STENCIL_ENABLE;
- }
- }
-}
-
-static void r300UpdatePolygonMode(struct gl_context * ctx)
-{
- r300ContextPtr r300 = R300_CONTEXT(ctx);
- uint32_t hw_mode = R300_GA_POLY_MODE_DISABLE;
-
- /* Only do something if a polygon mode is wanted, default is GL_FILL */
- if (ctx->Polygon.FrontMode != GL_FILL ||
- ctx->Polygon.BackMode != GL_FILL) {
- GLenum f, b;
-
- /* Handle GL_CW (clock wise and GL_CCW (counter clock wise)
- * correctly by selecting the correct front and back face
- */
- if (ctx->Polygon.FrontFace == GL_CCW) {
- f = ctx->Polygon.FrontMode;
- b = ctx->Polygon.BackMode;
- } else {
- f = ctx->Polygon.BackMode;
- b = ctx->Polygon.FrontMode;
- }
-
- /* Enable polygon mode */
- hw_mode |= R300_GA_POLY_MODE_DUAL;
-
- switch (f) {
- case GL_LINE:
- hw_mode |= R300_GA_POLY_MODE_FRONT_PTYPE_LINE;
- break;
- case GL_POINT:
- hw_mode |= R300_GA_POLY_MODE_FRONT_PTYPE_POINT;
- break;
- case GL_FILL:
- hw_mode |= R300_GA_POLY_MODE_FRONT_PTYPE_TRI;
- break;
- }
-
- switch (b) {
- case GL_LINE:
- hw_mode |= R300_GA_POLY_MODE_BACK_PTYPE_LINE;
- break;
- case GL_POINT:
- hw_mode |= R300_GA_POLY_MODE_BACK_PTYPE_POINT;
- break;
- case GL_FILL:
- hw_mode |= R300_GA_POLY_MODE_BACK_PTYPE_TRI;
- break;
- }
- }
-
- if (r300->hw.polygon_mode.cmd[1] != hw_mode) {
- R300_STATECHANGE(r300, polygon_mode);
- r300->hw.polygon_mode.cmd[1] = hw_mode;
- }
-
- r300->hw.polygon_mode.cmd[2] = 0x00000001;
- r300->hw.polygon_mode.cmd[3] = 0x00000000;
-}
-
-/**
- * Change the culling mode.
- *
- * \note Mesa already filters redundant calls to this function.
- */
-static void r300CullFace(struct gl_context * ctx, GLenum mode)
-{
- (void)mode;
-
- r300UpdateCulling(ctx);
-}
-
-/**
- * Change the polygon orientation.
- *
- * \note Mesa already filters redundant calls to this function.
- */
-static void r300FrontFace(struct gl_context * ctx, GLenum mode)
-{
- (void)mode;
-
- r300UpdateCulling(ctx);
- r300UpdatePolygonMode(ctx);
-}
-
-/**
- * Change the depth testing function.
- *
- * \note Mesa already filters redundant calls to this function.
- */
-static void r300DepthFunc(struct gl_context * ctx, GLenum func)
-{
- (void)func;
- r300SetDepthState(ctx);
-}
-
-/**
- * Enable/Disable depth writing.
- *
- * \note Mesa already filters redundant calls to this function.
- */
-static void r300DepthMask(struct gl_context * ctx, GLboolean mask)
-{
- (void)mask;
- r300SetDepthState(ctx);
-}
-
-/**
- * Handle glColorMask()
- */
-static void r300ColorMask(struct gl_context * ctx,
- GLboolean r, GLboolean g, GLboolean b, GLboolean a)
-{
- r300ContextPtr r300 = R300_CONTEXT(ctx);
- int mask = (r ? RB3D_COLOR_CHANNEL_MASK_RED_MASK0 : 0) |
- (g ? RB3D_COLOR_CHANNEL_MASK_GREEN_MASK0 : 0) |
- (b ? RB3D_COLOR_CHANNEL_MASK_BLUE_MASK0 : 0) |
- (a ? RB3D_COLOR_CHANNEL_MASK_ALPHA_MASK0 : 0);
-
- if (mask != r300->hw.cmk.cmd[R300_CMK_COLORMASK]) {
- R300_STATECHANGE(r300, cmk);
- r300->hw.cmk.cmd[R300_CMK_COLORMASK] = mask;
- }
-}
-
-/* =============================================================
- * Point state
- */
-static void r300PointSize(struct gl_context * ctx, GLfloat size)
-{
- r300ContextPtr r300 = R300_CONTEXT(ctx);
-
- /* We need to clamp to user defined range here, because
- * the HW clamping happens only for per vertex point size. */
- size = CLAMP(size, ctx->Point.MinSize, ctx->Point.MaxSize);
-
- /* same size limits for AA, non-AA points */
- size = CLAMP(size, ctx->Const.MinPointSize, ctx->Const.MaxPointSize);
-
- R300_STATECHANGE(r300, ps);
- r300->hw.ps.cmd[R300_PS_POINTSIZE] =
- ((int)(size * 6) << R300_POINTSIZE_X_SHIFT) |
- ((int)(size * 6) << R300_POINTSIZE_Y_SHIFT);
-}
-
-static void r300PointParameter(struct gl_context * ctx, GLenum pname, const GLfloat * param)
-{
- r300ContextPtr r300 = R300_CONTEXT(ctx);
-
- switch (pname) {
- case GL_POINT_SIZE_MIN:
- R300_STATECHANGE(r300, ga_point_minmax);
- r300->hw.ga_point_minmax.cmd[1] &= ~R300_GA_POINT_MINMAX_MIN_MASK;
- r300->hw.ga_point_minmax.cmd[1] |= (GLuint)(ctx->Point.MinSize * 6.0);
- r300PointSize(ctx, ctx->Point.Size);
- break;
- case GL_POINT_SIZE_MAX:
- R300_STATECHANGE(r300, ga_point_minmax);
- r300->hw.ga_point_minmax.cmd[1] &= ~R300_GA_POINT_MINMAX_MAX_MASK;
- r300->hw.ga_point_minmax.cmd[1] |= (GLuint)(ctx->Point.MaxSize * 6.0)
- << R300_GA_POINT_MINMAX_MAX_SHIFT;
- r300PointSize(ctx, ctx->Point.Size);
- break;
- case GL_POINT_DISTANCE_ATTENUATION:
- break;
- case GL_POINT_FADE_THRESHOLD_SIZE:
- break;
- default:
- break;
- }
-}
-
-/* =============================================================
- * Line state
- */
-static void r300LineWidth(struct gl_context * ctx, GLfloat widthf)
-{
- r300ContextPtr r300 = R300_CONTEXT(ctx);
-
- widthf = CLAMP(widthf,
- ctx->Const.MinPointSize,
- ctx->Const.MaxPointSize);
- R300_STATECHANGE(r300, lcntl);
- r300->hw.lcntl.cmd[1] =
- R300_LINE_CNT_HO | R300_LINE_CNT_VE | (int)(widthf * 6.0);
-}
-
-static void r300PolygonMode(struct gl_context * ctx, GLenum face, GLenum mode)
-{
- (void)face;
- (void)mode;
-
- r300UpdatePolygonMode(ctx);
-}
-
-/* =============================================================
- * Stencil
- */
-
-static int translate_stencil_op(int op)
-{
- switch (op) {
- case GL_KEEP:
- return R300_ZS_KEEP;
- case GL_ZERO:
- return R300_ZS_ZERO;
- case GL_REPLACE:
- return R300_ZS_REPLACE;
- case GL_INCR:
- return R300_ZS_INCR;
- case GL_DECR:
- return R300_ZS_DECR;
- case GL_INCR_WRAP_EXT:
- return R300_ZS_INCR_WRAP;
- case GL_DECR_WRAP_EXT:
- return R300_ZS_DECR_WRAP;
- case GL_INVERT:
- return R300_ZS_INVERT;
- default:
- WARN_ONCE("Do not know how to translate stencil op");
- return R300_ZS_KEEP;
- }
- return 0;
-}
-
-static void r300ShadeModel(struct gl_context * ctx, GLenum mode)
-{
- r300ContextPtr rmesa = R300_CONTEXT(ctx);
-
- R300_STATECHANGE(rmesa, shade);
- rmesa->hw.shade.cmd[1] = 0x00000002;
- R300_STATECHANGE(rmesa, shade2);
- switch (mode) {
- case GL_FLAT:
- rmesa->hw.shade2.cmd[1] = R300_RE_SHADE_MODEL_FLAT;
- break;
- case GL_SMOOTH:
- rmesa->hw.shade2.cmd[1] = R300_RE_SHADE_MODEL_SMOOTH;
- break;
- default:
- return;
- }
- rmesa->hw.shade2.cmd[2] = 0x00000000;
- rmesa->hw.shade2.cmd[3] = 0x00000000;
-}
-
-static void r300StencilFuncSeparate(struct gl_context * ctx, GLenum face,
- GLenum func, GLint ref, GLuint mask)
-{
- r300ContextPtr rmesa = R300_CONTEXT(ctx);
- GLuint refmask;
- GLuint flag;
- const unsigned back = ctx->Stencil._BackFace;
-
- r300CatchStencilFallback(ctx);
-
- refmask = ((ctx->Stencil.Ref[0] & 0xff) << R300_STENCILREF_SHIFT)
- | ((ctx->Stencil.ValueMask[0] & 0xff) << R300_STENCILMASK_SHIFT);
-
- R300_STATECHANGE(rmesa, zs);
- rmesa->hw.zs.cmd[R300_ZS_CNTL_0] |= R300_STENCIL_FRONT_BACK;
- rmesa->hw.zs.cmd[R300_ZS_CNTL_1] &= ~((R300_ZS_MASK <<
- R300_S_FRONT_FUNC_SHIFT)
- | (R300_ZS_MASK <<
- R300_S_BACK_FUNC_SHIFT));
-
- rmesa->hw.zs.cmd[R300_ZS_CNTL_2] &=
- ~((R300_STENCILREF_MASK << R300_STENCILREF_SHIFT) |
- (R300_STENCILREF_MASK << R300_STENCILMASK_SHIFT));
-
- flag = translate_func(ctx->Stencil.Function[0]);
- rmesa->hw.zs.cmd[R300_ZS_CNTL_1] |=
- (flag << R300_S_FRONT_FUNC_SHIFT);
-
- flag = translate_func(ctx->Stencil.Function[back]);
-
- rmesa->hw.zs.cmd[R300_ZS_CNTL_1] |=
- (flag << R300_S_BACK_FUNC_SHIFT);
- rmesa->hw.zs.cmd[R300_ZS_CNTL_2] |= refmask;
-
- if (rmesa->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) {
- rmesa->hw.zs.cmd[R300_ZS_CNTL_0] |= R500_STENCIL_REFMASK_FRONT_BACK;
- R300_STATECHANGE(rmesa, zsb);
- refmask = ((ctx->Stencil.Ref[back] & 0xff) << R300_STENCILREF_SHIFT)
- | ((ctx->Stencil.ValueMask[back] & 0xff) << R300_STENCILMASK_SHIFT);
-
- rmesa->hw.zsb.cmd[R300_ZSB_CNTL_0] &=
- ~((R300_STENCILREF_MASK << R300_STENCILREF_SHIFT) |
- (R300_STENCILREF_MASK << R300_STENCILMASK_SHIFT));
- rmesa->hw.zsb.cmd[R300_ZSB_CNTL_0] |= refmask;
- }
-}
-
-static void r300StencilMaskSeparate(struct gl_context * ctx, GLenum face, GLuint mask)
-{
- r300ContextPtr rmesa = R300_CONTEXT(ctx);
- const unsigned back = ctx->Stencil._BackFace;
-
- r300CatchStencilFallback(ctx);
-
- R300_STATECHANGE(rmesa, zs);
- rmesa->hw.zs.cmd[R300_ZS_CNTL_2] &=
- ~(R300_STENCILREF_MASK <<
- R300_STENCILWRITEMASK_SHIFT);
- rmesa->hw.zs.cmd[R300_ZS_CNTL_2] |=
- (ctx->Stencil.
- WriteMask[0] & R300_STENCILREF_MASK) <<
- R300_STENCILWRITEMASK_SHIFT;
- if (rmesa->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) {
- R300_STATECHANGE(rmesa, zsb);
- rmesa->hw.zsb.cmd[R300_ZSB_CNTL_0] |=
- (ctx->Stencil.
- WriteMask[back] & R300_STENCILREF_MASK) <<
- R300_STENCILWRITEMASK_SHIFT;
- }
-}
-
-static void r300StencilOpSeparate(struct gl_context * ctx, GLenum face,
- GLenum fail, GLenum zfail, GLenum zpass)
-{
- r300ContextPtr rmesa = R300_CONTEXT(ctx);
- const unsigned back = ctx->Stencil._BackFace;
-
- r300CatchStencilFallback(ctx);
-
- R300_STATECHANGE(rmesa, zs);
- /* It is easier to mask what's left.. */
- rmesa->hw.zs.cmd[R300_ZS_CNTL_1] &=
- (R300_ZS_MASK << R300_Z_FUNC_SHIFT) |
- (R300_ZS_MASK << R300_S_FRONT_FUNC_SHIFT) |
- (R300_ZS_MASK << R300_S_BACK_FUNC_SHIFT);
-
- rmesa->hw.zs.cmd[R300_ZS_CNTL_1] |=
- (translate_stencil_op(ctx->Stencil.FailFunc[0]) <<
- R300_S_FRONT_SFAIL_OP_SHIFT)
- | (translate_stencil_op(ctx->Stencil.ZFailFunc[0]) <<
- R300_S_FRONT_ZFAIL_OP_SHIFT)
- | (translate_stencil_op(ctx->Stencil.ZPassFunc[0]) <<
- R300_S_FRONT_ZPASS_OP_SHIFT);
-
- rmesa->hw.zs.cmd[R300_ZS_CNTL_1] |=
- (translate_stencil_op(ctx->Stencil.FailFunc[back]) <<
- R300_S_BACK_SFAIL_OP_SHIFT)
- | (translate_stencil_op(ctx->Stencil.ZFailFunc[back]) <<
- R300_S_BACK_ZFAIL_OP_SHIFT)
- | (translate_stencil_op(ctx->Stencil.ZPassFunc[back]) <<
- R300_S_BACK_ZPASS_OP_SHIFT);
-}
-
-/* =============================================================
- * Window position and viewport transformation
- */
-
-static void r300UpdateWindow(struct gl_context * ctx)
-{
- r300ContextPtr rmesa = R300_CONTEXT(ctx);
- __DRIdrawable *dPriv = radeon_get_drawable(&rmesa->radeon);
- GLfloat xoffset = dPriv ? (GLfloat) dPriv->x : 0;
- GLfloat yoffset = dPriv ? (GLfloat) dPriv->y + dPriv->h : 0;
- const GLfloat *v = ctx->Viewport._WindowMap.m;
- const GLfloat depthScale = 1.0F / ctx->DrawBuffer->_DepthMaxF;
- const GLboolean render_to_fbo = (ctx->DrawBuffer->Name != 0);
- GLfloat y_scale, y_bias;
-
- if (render_to_fbo) {
- y_scale = 1.0;
- y_bias = 0;
- } else {
- y_scale = -1.0;
- y_bias = yoffset;
- }
-
- GLfloat sx = v[MAT_SX];
- GLfloat tx = v[MAT_TX] + xoffset;
- GLfloat sy = v[MAT_SY] * y_scale;
- GLfloat ty = (v[MAT_TY] * y_scale) + y_bias;
- GLfloat sz = v[MAT_SZ] * depthScale;
- GLfloat tz = v[MAT_TZ] * depthScale;
-
- R300_STATECHANGE(rmesa, vpt);
-
- rmesa->hw.vpt.cmd[R300_VPT_XSCALE] = r300PackFloat32(sx);
- rmesa->hw.vpt.cmd[R300_VPT_XOFFSET] = r300PackFloat32(tx);
- rmesa->hw.vpt.cmd[R300_VPT_YSCALE] = r300PackFloat32(sy);
- rmesa->hw.vpt.cmd[R300_VPT_YOFFSET] = r300PackFloat32(ty);
- rmesa->hw.vpt.cmd[R300_VPT_ZSCALE] = r300PackFloat32(sz);
- rmesa->hw.vpt.cmd[R300_VPT_ZOFFSET] = r300PackFloat32(tz);
-}
-
-static void r300Viewport(struct gl_context * ctx, GLint x, GLint y,
- GLsizei width, GLsizei height)
-{
- /* Don't pipeline viewport changes, conflict with window offset
- * setting below. Could apply deltas to rescue pipelined viewport
- * values, or keep the originals hanging around.
- */
- r300UpdateWindow(ctx);
-
- radeon_viewport(ctx, x, y, width, height);
-}
-
-static void r300DepthRange(struct gl_context * ctx, GLclampd nearval, GLclampd farval)
-{
- r300UpdateWindow(ctx);
-}
-
-void r300UpdateViewportOffset(struct gl_context * ctx)
-{
- r300ContextPtr rmesa = R300_CONTEXT(ctx);
- __DRIdrawable *dPriv = radeon_get_drawable(&rmesa->radeon);
- GLfloat xoffset = (GLfloat) dPriv->x;
- GLfloat yoffset = (GLfloat) dPriv->y + dPriv->h;
- const GLfloat *v = ctx->Viewport._WindowMap.m;
-
- GLfloat tx = v[MAT_TX] + xoffset;
- GLfloat ty = (-v[MAT_TY]) + yoffset;
-
- if (rmesa->hw.vpt.cmd[R300_VPT_XOFFSET] != r300PackFloat32(tx) ||
- rmesa->hw.vpt.cmd[R300_VPT_YOFFSET] != r300PackFloat32(ty)) {
- /* Note: this should also modify whatever data the context reset
- * code uses...
- */
- R300_STATECHANGE(rmesa, vpt);
- rmesa->hw.vpt.cmd[R300_VPT_XOFFSET] = r300PackFloat32(tx);
- rmesa->hw.vpt.cmd[R300_VPT_YOFFSET] = r300PackFloat32(ty);
-
- }
-
- radeonUpdateScissor(ctx);
-}
-
-/**
- * Update R300's own internal state parameters.
- * For now just STATE_R300_WINDOW_DIMENSION
- */
-static void r300UpdateStateParameters(struct gl_context * ctx, GLuint new_state)
-{
- r300ContextPtr rmesa = R300_CONTEXT(ctx);
- struct gl_program_parameter_list *paramList;
-
- if (!(new_state & (_NEW_BUFFERS | _NEW_PROGRAM | _NEW_PROGRAM_CONSTANTS)))
- return;
-
- if (!ctx->FragmentProgram._Current || !rmesa->selected_fp)
- return;
-
- paramList = ctx->FragmentProgram._Current->Base.Parameters;
-
- if (!paramList)
- return;
-
- _mesa_load_state_parameters(ctx, paramList);
-}
-
-/* =============================================================
- * Polygon state
- */
-static void r300PolygonOffset(struct gl_context * ctx, GLfloat factor, GLfloat units)
-{
- r300ContextPtr rmesa = R300_CONTEXT(ctx);
- GLfloat constant = units;
-
- switch (ctx->Visual.depthBits) {
- case 16:
- constant *= 4.0;
- break;
- case 24:
- constant *= 2.0;
- break;
- }
-
- factor *= 12.0;
-
-/* fprintf(stderr, "%s f:%f u:%f\n", __FUNCTION__, factor, constant); */
-
- R300_STATECHANGE(rmesa, zbs);
- rmesa->hw.zbs.cmd[R300_ZBS_T_FACTOR] = r300PackFloat32(factor);
- rmesa->hw.zbs.cmd[R300_ZBS_T_CONSTANT] = r300PackFloat32(constant);
- rmesa->hw.zbs.cmd[R300_ZBS_W_FACTOR] = r300PackFloat32(factor);
- rmesa->hw.zbs.cmd[R300_ZBS_W_CONSTANT] = r300PackFloat32(constant);
-}
-
-/* Routing and texture-related */
-
-/* r300 doesnt handle GL_CLAMP and GL_MIRROR_CLAMP_EXT correctly when filter is NEAREST.
- * Since texwrap produces same results for GL_CLAMP and GL_CLAMP_TO_EDGE we use them instead.
- * We need to recalculate wrap modes whenever filter mode is changed because someone might do:
- * glTexParameteri(GL_TEXTURE_2D, GL_TEXTURE_MIN_FILTER, GL_NEAREST);
- * glTexParameteri(GL_TEXTURE_2D, GL_TEXTURE_WRAP_S, GL_CLAMP);
- * glTexParameteri(GL_TEXTURE_2D, GL_TEXTURE_MIN_FILTER, GL_LINEAR);
- * Since r300 completely ignores R300_TX_CLAMP when either min or mag is nearest it cant handle
- * combinations where only one of them is nearest.
- */
-static unsigned long gen_fixed_filter(unsigned long f)
-{
- unsigned long mag, min, needs_fixing = 0;
- //return f;
-
- /* We ignore MIRROR bit so we dont have to do everything twice */
- if ((f & ((7 - 1) << R300_TX_WRAP_S_SHIFT)) ==
- (R300_TX_CLAMP << R300_TX_WRAP_S_SHIFT)) {
- needs_fixing |= 1;
- }
- if ((f & ((7 - 1) << R300_TX_WRAP_T_SHIFT)) ==
- (R300_TX_CLAMP << R300_TX_WRAP_T_SHIFT)) {
- needs_fixing |= 2;
- }
- if ((f & ((7 - 1) << R300_TX_WRAP_R_SHIFT)) ==
- (R300_TX_CLAMP << R300_TX_WRAP_R_SHIFT)) {
- needs_fixing |= 4;
- }
-
- if (!needs_fixing)
- return f;
-
- mag = f & R300_TX_MAG_FILTER_MASK;
- min = f & (R300_TX_MIN_FILTER_MASK|R300_TX_MIN_FILTER_MIP_MASK);
-
- /* TODO: Check for anisto filters too */
- if ((mag != R300_TX_MAG_FILTER_NEAREST)
- && (min != R300_TX_MIN_FILTER_NEAREST))
- return f;
-
- /* r300 cant handle these modes hence we force nearest to linear */
- if ((mag == R300_TX_MAG_FILTER_NEAREST)
- && (min != R300_TX_MIN_FILTER_NEAREST)) {
- f &= ~R300_TX_MAG_FILTER_NEAREST;
- f |= R300_TX_MAG_FILTER_LINEAR;
- return f;
- }
-
- if ((min == R300_TX_MIN_FILTER_NEAREST)
- && (mag != R300_TX_MAG_FILTER_NEAREST)) {
- f &= ~R300_TX_MIN_FILTER_NEAREST;
- f |= R300_TX_MIN_FILTER_LINEAR;
- return f;
- }
-
- /* Both are nearest */
- if (needs_fixing & 1) {
- f &= ~((7 - 1) << R300_TX_WRAP_S_SHIFT);
- f |= R300_TX_CLAMP_TO_EDGE << R300_TX_WRAP_S_SHIFT;
- }
- if (needs_fixing & 2) {
- f &= ~((7 - 1) << R300_TX_WRAP_T_SHIFT);
- f |= R300_TX_CLAMP_TO_EDGE << R300_TX_WRAP_T_SHIFT;
- }
- if (needs_fixing & 4) {
- f &= ~((7 - 1) << R300_TX_WRAP_R_SHIFT);
- f |= R300_TX_CLAMP_TO_EDGE << R300_TX_WRAP_R_SHIFT;
- }
- return f;
-}
-
-static void r300SetupFragmentShaderTextures(struct gl_context *ctx, int *tmu_mappings)
-{
- r300ContextPtr r300 = R300_CONTEXT(ctx);
- int i;
- struct r300_fragment_program_code *code = &r300->selected_fp->code.code.r300;
-
- R300_STATECHANGE(r300, fpt);
-
- for (i = 0; i < code->tex.length; i++) {
- int unit;
- int opcode;
- unsigned long val;
-
- unit = code->tex.inst[i] >> R300_TEX_ID_SHIFT;
- unit &= 15;
-
- val = code->tex.inst[i];
- val &= ~R300_TEX_ID_MASK;
-
- opcode =
- (val & R300_TEX_INST_MASK) >> R300_TEX_INST_SHIFT;
- if (opcode == R300_TEX_OP_KIL) {
- r300->hw.fpt.cmd[R300_FPT_INSTR_0 + i] = val;
- } else {
- if (tmu_mappings[unit] >= 0) {
- val |=
- tmu_mappings[unit] <<
- R300_TEX_ID_SHIFT;
- r300->hw.fpt.cmd[R300_FPT_INSTR_0 + i] = val;
- } else {
- // We get here when the corresponding texture image is incomplete
- // (e.g. incomplete mipmaps etc.)
- r300->hw.fpt.cmd[R300_FPT_INSTR_0 + i] = val;
- }
- }
- }
-
- r300->hw.fpt.cmd[R300_FPT_CMD_0] =
- cmdpacket0(r300->radeon.radeonScreen,
- R300_US_TEX_INST_0, code->tex.length);
-}
-
-static void r500SetupFragmentShaderTextures(struct gl_context *ctx, int *tmu_mappings)
-{
- r300ContextPtr r300 = R300_CONTEXT(ctx);
- int i;
- struct r500_fragment_program_code *code = &r300->selected_fp->code.code.r500;
-
- /* find all the texture instructions and relocate the texture units */
- for (i = 0; i < code->inst_end + 1; i++) {
- if ((code->inst[i].inst0 & 0x3) == R500_INST_TYPE_TEX) {
- uint32_t val;
- int unit, opcode, new_unit;
-
- val = code->inst[i].inst1;
-
- unit = (val >> 16) & 0xf;
-
- val &= ~(0xf << 16);
-
- opcode = val & (0x7 << 22);
- if (opcode == R500_TEX_INST_TEXKILL) {
- new_unit = 0;
- } else {
- if (tmu_mappings[unit] >= 0) {
- new_unit = tmu_mappings[unit];
- } else {
- new_unit = 0;
- }
- }
- val |= R500_TEX_ID(new_unit);
- code->inst[i].inst1 = val;
- }
- }
-}
-
-static GLuint translate_lod_bias(GLfloat bias)
-{
- GLint b = (int)(bias*32);
- if (b >= (1 << 9))
- b = (1 << 9)-1;
- else if (b < -(1 << 9))
- b = -(1 << 9);
- return (((GLuint)b) << R300_LOD_BIAS_SHIFT) & R300_LOD_BIAS_MASK;
-}
-
-
-static void r300SetupTextures(struct gl_context * ctx)
-{
- int i, mtu;
- struct radeon_tex_obj *t;
- r300ContextPtr r300 = R300_CONTEXT(ctx);
- int hw_tmu = 0;
- int last_hw_tmu = -1; /* -1 translates into no setup costs for fields */
- int tmu_mappings[R300_MAX_TEXTURE_UNITS] = { -1, };
-
- R300_STATECHANGE(r300, txe);
- R300_STATECHANGE(r300, tex.filter);
- R300_STATECHANGE(r300, tex.filter_1);
- R300_STATECHANGE(r300, tex.size);
- R300_STATECHANGE(r300, tex.format);
- R300_STATECHANGE(r300, tex.pitch);
- R300_STATECHANGE(r300, tex.offset);
- R300_STATECHANGE(r300, tex.chroma_key);
- R300_STATECHANGE(r300, tex.border_color);
-
- r300->hw.txe.cmd[R300_TXE_ENABLE] = 0x0;
-
- mtu = r300->radeon.glCtx->Const.MaxTextureUnits;
- if (RADEON_DEBUG & RADEON_STATE)
- fprintf(stderr, "mtu=%d\n", mtu);
-
- if (mtu > R300_MAX_TEXTURE_UNITS) {
- fprintf(stderr,
- "Aiiee ! mtu=%d is greater than R300_MAX_TEXTURE_UNITS=%d\n",
- mtu, R300_MAX_TEXTURE_UNITS);
- exit(-1);
- }
-
- /* We cannot let disabled tmu offsets pass DRM */
- for (i = 0; i < mtu; i++) {
- if (ctx->Texture.Unit[i]._ReallyEnabled) {
- tmu_mappings[i] = hw_tmu;
-
- t = radeon_tex_obj(ctx->Texture.Unit[i]._Current);
- if (!t)
- continue;
-
- if ((t->pp_txformat & 0xffffff00) == 0xffffff00) {
- WARN_ONCE
- ("unknown texture format (entry %x) encountered. Help me !\n",
- t->pp_txformat & 0xff);
- }
-
- if (RADEON_DEBUG & RADEON_STATE)
- fprintf(stderr,
- "Activating texture unit %d\n", i);
-
- r300->hw.txe.cmd[R300_TXE_ENABLE] |= (1 << hw_tmu);
-
- r300->hw.tex.filter.cmd[R300_TEX_VALUE_0 +
- hw_tmu] =
- gen_fixed_filter(t->pp_txfilter) | (hw_tmu << 28);
- /* Note: There is a LOD bias per texture unit and a LOD bias
- * per texture object. We add them here to get the correct behaviour.
- * (The per-texture object LOD bias was introduced in OpenGL 1.4
- * and is not present in the EXT_texture_object extension).
- */
- r300->hw.tex.filter_1.cmd[R300_TEX_VALUE_0 + hw_tmu] =
- t->pp_txfilter_1 |
- translate_lod_bias(ctx->Texture.Unit[i].LodBias + t->base.Sampler.LodBias);
- r300->hw.tex.size.cmd[R300_TEX_VALUE_0 + hw_tmu] =
- t->pp_txsize;
- r300->hw.tex.format.cmd[R300_TEX_VALUE_0 +
- hw_tmu] = t->pp_txformat;
- r300->hw.tex.pitch.cmd[R300_TEX_VALUE_0 + hw_tmu] =
- t->pp_txpitch;
- r300->hw.textures[hw_tmu] = t;
-
- if (t->tile_bits & R300_TXO_MACRO_TILE) {
- WARN_ONCE("macro tiling enabled!\n");
- }
-
- if (t->tile_bits & R300_TXO_MICRO_TILE) {
- WARN_ONCE("micro tiling enabled!\n");
- }
-
- r300->hw.tex.chroma_key.cmd[R300_TEX_VALUE_0 +
- hw_tmu] = 0x0;
- r300->hw.tex.border_color.cmd[R300_TEX_VALUE_0 +
- hw_tmu] =
- t->pp_border_color;
-
- last_hw_tmu = hw_tmu;
-
- hw_tmu++;
- }
- }
-
- /* R3xx and R4xx chips require that the texture unit corresponding to
- * KIL instructions is really enabled.
- *
- * We do some fakery here and in the state atom emit logic to enable
- * the texture without tripping up the CS checker in the kernel.
- */
- if (r300->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV515) {
- if (ctx->FragmentProgram._Current->UsesKill && last_hw_tmu < 0) {
- last_hw_tmu++;
-
- r300->hw.txe.cmd[R300_TXE_ENABLE] |= 1;
-
- r300->hw.tex.border_color.cmd[R300_TEX_VALUE_0] = 0;
- r300->hw.tex.chroma_key.cmd[R300_TEX_VALUE_0] = 0;
- r300->hw.tex.filter.cmd[R300_TEX_VALUE_0] = 0;
- r300->hw.tex.filter_1.cmd[R300_TEX_VALUE_0] = 0;
- r300->hw.tex.size.cmd[R300_TEX_VALUE_0] = 0; /* 1x1 texture */
- r300->hw.tex.format.cmd[R300_TEX_VALUE_0] = 0; /* A8 format */
- r300->hw.tex.pitch.cmd[R300_TEX_VALUE_0] = 0;
- }
- }
-
- r300->hw.tex.filter.cmd[R300_TEX_CMD_0] =
- cmdpacket0(r300->radeon.radeonScreen, R300_TX_FILTER0_0, last_hw_tmu + 1);
- r300->hw.tex.filter_1.cmd[R300_TEX_CMD_0] =
- cmdpacket0(r300->radeon.radeonScreen, R300_TX_FILTER1_0, last_hw_tmu + 1);
- r300->hw.tex.size.cmd[R300_TEX_CMD_0] =
- cmdpacket0(r300->radeon.radeonScreen, R300_TX_SIZE_0, last_hw_tmu + 1);
- r300->hw.tex.format.cmd[R300_TEX_CMD_0] =
- cmdpacket0(r300->radeon.radeonScreen, R300_TX_FORMAT_0, last_hw_tmu + 1);
- r300->hw.tex.pitch.cmd[R300_TEX_CMD_0] =
- cmdpacket0(r300->radeon.radeonScreen, R300_TX_FORMAT2_0, last_hw_tmu + 1);
- r300->hw.tex.offset.cmd[R300_TEX_CMD_0] =
- cmdpacket0(r300->radeon.radeonScreen, R300_TX_OFFSET_0, last_hw_tmu + 1);
- r300->hw.tex.chroma_key.cmd[R300_TEX_CMD_0] =
- cmdpacket0(r300->radeon.radeonScreen, R300_TX_CHROMA_KEY_0, last_hw_tmu + 1);
- r300->hw.tex.border_color.cmd[R300_TEX_CMD_0] =
- cmdpacket0(r300->radeon.radeonScreen, R300_TX_BORDER_COLOR_0, last_hw_tmu + 1);
-
- r300->vtbl.SetupFragmentShaderTextures(ctx, tmu_mappings);
-
- if (RADEON_DEBUG & RADEON_STATE)
- fprintf(stderr, "TX_ENABLE: %08x last_hw_tmu=%d\n",
- r300->hw.txe.cmd[R300_TXE_ENABLE], last_hw_tmu);
-}
-
-union r300_outputs_written {
- GLuint vp_outputs; /* hw_tcl_on */
- DECLARE_RENDERINPUTS(index_bitset); /* !hw_tcl_on */
-};
-
-#define R300_OUTPUTS_WRITTEN_TEST(ow, vp_result, tnl_attrib) \
- ((hw_tcl_on) ? (ow).vp_outputs & (1 << (vp_result)) : \
- RENDERINPUTS_TEST( (ow.index_bitset), (tnl_attrib) ))
-
-static void r300SetupRSUnit(struct gl_context * ctx)
-{
- r300ContextPtr r300 = R300_CONTEXT(ctx);
- union r300_outputs_written OutputsWritten;
- GLuint InputsRead;
- int fp_reg, high_rr;
- int col_ip, tex_ip;
- int rs_tex_count = 0;
- int i, col_fmt, hw_tcl_on;
-
- hw_tcl_on = r300->options.hw_tcl_enabled;
-
- if (hw_tcl_on)
- OutputsWritten.vp_outputs = r300->selected_vp->code.OutputsWritten;
- else
- RENDERINPUTS_COPY(OutputsWritten.index_bitset, r300->render_inputs_bitset);
-
- InputsRead = r300->selected_fp->InputsRead;
-
- R300_STATECHANGE(r300, ri);
- R300_STATECHANGE(r300, rc);
- R300_STATECHANGE(r300, rr);
-
- fp_reg = col_ip = tex_ip = col_fmt = 0;
-
- r300->hw.rc.cmd[1] = 0;
- r300->hw.rc.cmd[2] = 0;
- for (i=0; i<R300_RR_CMDSIZE-1; ++i)
- r300->hw.rr.cmd[R300_RR_INST_0 + i] = 0;
-
- for (i=0; i<R300_RI_CMDSIZE-1; ++i)
- r300->hw.ri.cmd[R300_RI_INTERP_0 + i] = 0;
-
-
- if (InputsRead & FRAG_BIT_COL0) {
- if (R300_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_COL0, _TNL_ATTRIB_COLOR0)) {
- r300->hw.ri.cmd[R300_RI_INTERP_0 + col_ip] = R300_RS_COL_PTR(col_ip) | R300_RS_COL_FMT(R300_RS_COL_FMT_RGBA);
- r300->hw.rr.cmd[R300_RR_INST_0 + col_ip] = R300_RS_INST_COL_ID(col_ip) | R300_RS_INST_COL_CN_WRITE | R300_RS_INST_COL_ADDR(fp_reg);
- InputsRead &= ~FRAG_BIT_COL0;
- ++col_ip;
- ++fp_reg;
- } else {
- WARN_ONCE("fragprog wants col0, vp doesn't provide it\n");
- }
- }
-
- if (InputsRead & FRAG_BIT_COL1) {
- if (R300_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_COL1, _TNL_ATTRIB_COLOR1)) {
- r300->hw.ri.cmd[R300_RI_INTERP_0 + col_ip] = R300_RS_COL_PTR(col_ip) | R300_RS_COL_FMT(R300_RS_COL_FMT_RGBA);
- r300->hw.rr.cmd[R300_RR_INST_0 + col_ip] = R300_RS_INST_COL_ID(col_ip) | R300_RS_INST_COL_CN_WRITE | R300_RS_INST_COL_ADDR(fp_reg);
- InputsRead &= ~FRAG_BIT_COL1;
- ++col_ip;
- ++fp_reg;
- } else {
- WARN_ONCE("fragprog wants col1, vp doesn't provide it\n");
- }
- }
-
- /* We always route 4 texcoord components */
- for (i = 0; i < ctx->Const.MaxTextureUnits; i++) {
- if (! ( InputsRead & FRAG_BIT_TEX(i) ) )
- continue;
-
- if (!R300_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_TEX0 + i, _TNL_ATTRIB_TEX(i))) {
- WARN_ONCE("fragprog wants coords for tex%d, vp doesn't provide them!\n", i);
- continue;
- }
-
- r300->hw.ri.cmd[R300_RI_INTERP_0 + tex_ip] |= R300_RS_SEL_S(0) | R300_RS_SEL_T(1) | R300_RS_SEL_R(2) | R300_RS_SEL_Q(3) | R300_RS_TEX_PTR(rs_tex_count);
- r300->hw.rr.cmd[R300_RR_INST_0 + tex_ip] |= R300_RS_INST_TEX_ID(tex_ip) | R300_RS_INST_TEX_CN_WRITE | R300_RS_INST_TEX_ADDR(fp_reg);
- InputsRead &= ~(FRAG_BIT_TEX0 << i);
- rs_tex_count += 4;
- ++tex_ip;
- ++fp_reg;
- }
-
- /* Setup default color if no color or tex was set */
- if (rs_tex_count == 0 && col_ip == 0) {
- r300->hw.rr.cmd[R300_RR_INST_0] = R300_RS_INST_COL_ID(0) | R300_RS_INST_COL_ADDR(0);
- r300->hw.ri.cmd[R300_RI_INTERP_0] = R300_RS_COL_PTR(0) | R300_RS_COL_FMT(R300_RS_COL_FMT_0001);
- ++col_ip;
- }
-
- high_rr = (col_ip > tex_ip) ? col_ip : tex_ip;
- r300->hw.rc.cmd[1] |= (rs_tex_count << R300_IT_COUNT_SHIFT) | (col_ip << R300_IC_COUNT_SHIFT) | R300_HIRES_EN;
- r300->hw.rc.cmd[2] |= high_rr - 1;
-
- r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_INST_0, high_rr);
- r300->hw.ri.cmd[R300_RI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_IP_0, high_rr);
-
- if (InputsRead)
- WARN_ONCE("Don't know how to satisfy InputsRead=0x%08x\n", InputsRead);
-}
-
-static void r500SetupRSUnit(struct gl_context * ctx)
-{
- r300ContextPtr r300 = R300_CONTEXT(ctx);
- union r300_outputs_written OutputsWritten;
- GLuint InputsRead;
- int fp_reg, high_rr;
- int col_ip, tex_ip;
- int rs_tex_count = 0;
- int i, col_fmt, hw_tcl_on;
-
- hw_tcl_on = r300->options.hw_tcl_enabled;
-
- if (hw_tcl_on)
- OutputsWritten.vp_outputs = r300->selected_vp->code.OutputsWritten;
- else
- RENDERINPUTS_COPY(OutputsWritten.index_bitset, r300->render_inputs_bitset);
-
- InputsRead = r300->selected_fp->InputsRead;
-
- R300_STATECHANGE(r300, ri);
- R300_STATECHANGE(r300, rc);
- R300_STATECHANGE(r300, rr);
-
- fp_reg = col_ip = tex_ip = col_fmt = 0;
-
- r300->hw.rc.cmd[1] = 0;
- r300->hw.rc.cmd[2] = 0;
- for (i=0; i<R300_RR_CMDSIZE-1; ++i)
- r300->hw.rr.cmd[R300_RR_INST_0 + i] = 0;
-
- for (i=0; i<R500_RI_CMDSIZE-1; ++i)
- r300->hw.ri.cmd[R300_RI_INTERP_0 + i] = 0;
-
-
- if (InputsRead & FRAG_BIT_COL0) {
- if (R300_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_COL0, _TNL_ATTRIB_COLOR0)) {
- r300->hw.ri.cmd[R300_RI_INTERP_0 + col_ip] = R500_RS_COL_PTR(col_ip) | R500_RS_COL_FMT(R300_RS_COL_FMT_RGBA);
- r300->hw.rr.cmd[R300_RR_INST_0 + col_ip] = R500_RS_INST_COL_ID(col_ip) | R500_RS_INST_COL_CN_WRITE | R500_RS_INST_COL_ADDR(fp_reg);
- InputsRead &= ~FRAG_BIT_COL0;
- ++col_ip;
- ++fp_reg;
- } else {
- WARN_ONCE("fragprog wants col0, vp doesn't provide it\n");
- }
- }
-
- if (InputsRead & FRAG_BIT_COL1) {
- if (R300_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_COL1, _TNL_ATTRIB_COLOR1)) {
- r300->hw.ri.cmd[R300_RI_INTERP_0 + col_ip] = R500_RS_COL_PTR(col_ip) | R500_RS_COL_FMT(R300_RS_COL_FMT_RGBA);
- r300->hw.rr.cmd[R300_RR_INST_0 + col_ip] = R500_RS_INST_COL_ID(col_ip) | R500_RS_INST_COL_CN_WRITE | R500_RS_INST_COL_ADDR(fp_reg);
- InputsRead &= ~FRAG_BIT_COL1;
- ++col_ip;
- ++fp_reg;
- } else {
- WARN_ONCE("fragprog wants col1, vp doesn't provide it\n");
- }
- }
-
- /* We always route 4 texcoord components */
- for (i = 0; i < ctx->Const.MaxTextureUnits; i++) {
- if (! ( InputsRead & FRAG_BIT_TEX(i) ) )
- continue;
-
- if (!R300_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_TEX0 + i, _TNL_ATTRIB_TEX(i))) {
- WARN_ONCE("fragprog wants coords for tex%d, vp doesn't provide them!\n", i);
- continue;
- }
-
- r300->hw.ri.cmd[R300_RI_INTERP_0 + tex_ip] |= ((rs_tex_count + 0) << R500_RS_IP_TEX_PTR_S_SHIFT) |
- ((rs_tex_count + 1) << R500_RS_IP_TEX_PTR_T_SHIFT) |
- ((rs_tex_count + 2) << R500_RS_IP_TEX_PTR_R_SHIFT) |
- ((rs_tex_count + 3) << R500_RS_IP_TEX_PTR_Q_SHIFT);
-
- r300->hw.rr.cmd[R300_RR_INST_0 + tex_ip] |= R500_RS_INST_TEX_ID(tex_ip) | R500_RS_INST_TEX_CN_WRITE | R500_RS_INST_TEX_ADDR(fp_reg);
- InputsRead &= ~(FRAG_BIT_TEX0 << i);
- rs_tex_count += 4;
- ++tex_ip;
- ++fp_reg;
- }
-
- /* Setup default color if no color or tex was set */
- if (rs_tex_count == 0 && col_ip == 0) {
- r300->hw.rr.cmd[R300_RR_INST_0] = R500_RS_INST_COL_ID(0) | R500_RS_INST_COL_ADDR(0);
- r300->hw.ri.cmd[R300_RI_INTERP_0] = R500_RS_COL_PTR(0) | R500_RS_COL_FMT(R300_RS_COL_FMT_0001);
- ++col_ip;
- }
-
- high_rr = (col_ip > tex_ip) ? col_ip : tex_ip;
- r300->hw.rc.cmd[1] = (rs_tex_count << R300_IT_COUNT_SHIFT) | (col_ip << R300_IC_COUNT_SHIFT) | R300_HIRES_EN;
- r300->hw.rc.cmd[2] = 0xC0 | (high_rr - 1);
-
- r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_RS_INST_0, high_rr);
- r300->hw.ri.cmd[R300_RI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_RS_IP_0, high_rr);
-
- if (InputsRead)
- WARN_ONCE("Don't know how to satisfy InputsRead=0x%08x\n", InputsRead);
-}
-
-
-void r300VapCntl(r300ContextPtr rmesa, GLuint input_count,
- GLuint output_count, GLuint temp_count)
-{
- int vtx_mem_size;
- int pvs_num_slots;
- int pvs_num_cntrls;
-
- /* Flush PVS engine before changing PVS_NUM_SLOTS, PVS_NUM_CNTRLS.
- * See r500 docs 6.5.2 - done in emit */
-
- /* avoid division by zero */
- if (input_count == 0) input_count = 1;
- if (output_count == 0) output_count = 1;
- if (temp_count == 0) temp_count = 1;
-
- if (rmesa->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515)
- vtx_mem_size = 128;
- else
- vtx_mem_size = 72;
-
- pvs_num_slots = MIN3(10, vtx_mem_size/input_count, vtx_mem_size/output_count);
- pvs_num_cntrls = MIN2(6, vtx_mem_size/temp_count);
-
- R300_STATECHANGE(rmesa, vap_cntl);
- if (rmesa->options.hw_tcl_enabled) {
- rmesa->hw.vap_cntl.cmd[R300_VAP_CNTL_INSTR] =
- (pvs_num_slots << R300_PVS_NUM_SLOTS_SHIFT) |
- (pvs_num_cntrls << R300_PVS_NUM_CNTLRS_SHIFT) |
- (12 << R300_VF_MAX_VTX_NUM_SHIFT);
- if (rmesa->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515)
- rmesa->hw.vap_cntl.cmd[R300_VAP_CNTL_INSTR] |= R500_TCL_STATE_OPTIMIZATION;
- } else
- /* not sure about non-tcl */
- rmesa->hw.vap_cntl.cmd[R300_VAP_CNTL_INSTR] = ((10 << R300_PVS_NUM_SLOTS_SHIFT) |
- (5 << R300_PVS_NUM_CNTLRS_SHIFT) |
- (5 << R300_VF_MAX_VTX_NUM_SHIFT));
-
- if ((rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R300) ||
- (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R350))
- rmesa->hw.vap_cntl.cmd[R300_VAP_CNTL_INSTR] |= (4 << R300_PVS_NUM_FPUS_SHIFT);
- else if (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV530)
- rmesa->hw.vap_cntl.cmd[R300_VAP_CNTL_INSTR] |= (5 << R300_PVS_NUM_FPUS_SHIFT);
- else if ((rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV410) ||
- (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R420))
- rmesa->hw.vap_cntl.cmd[R300_VAP_CNTL_INSTR] |= (6 << R300_PVS_NUM_FPUS_SHIFT);
- else if ((rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R520) ||
- (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R580) ||
- (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV560) ||
- (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV570))
- rmesa->hw.vap_cntl.cmd[R300_VAP_CNTL_INSTR] |= (8 << R300_PVS_NUM_FPUS_SHIFT);
- else
- rmesa->hw.vap_cntl.cmd[R300_VAP_CNTL_INSTR] |= (2 << R300_PVS_NUM_FPUS_SHIFT);
-
-}
-
-/**
- * Enable/Disable states.
- *
- * \note Mesa already filters redundant calls to this function.
- */
-static void r300Enable(struct gl_context * ctx, GLenum cap, GLboolean state)
-{
- r300ContextPtr rmesa = R300_CONTEXT(ctx);
- if (RADEON_DEBUG & RADEON_STATE)
- fprintf(stderr, "%s( %s = %s )\n", __FUNCTION__,
- _mesa_lookup_enum_by_nr(cap),
- state ? "GL_TRUE" : "GL_FALSE");
-
- switch (cap) {
- case GL_ALPHA_TEST:
- r300SetAlphaState(ctx);
- break;
- case GL_COLOR_LOGIC_OP:
- r300SetLogicOpState(ctx);
- /* fall-through, because logic op overrides blending */
- case GL_BLEND:
- r300SetBlendState(ctx);
- break;
- case GL_CLIP_PLANE0:
- case GL_CLIP_PLANE1:
- case GL_CLIP_PLANE2:
- case GL_CLIP_PLANE3:
- case GL_CLIP_PLANE4:
- case GL_CLIP_PLANE5:
- r300SetClipPlaneState(ctx, cap, state);
- break;
- case GL_CULL_FACE:
- r300UpdateCulling(ctx);
- break;
- case GL_DEPTH_TEST:
- r300SetDepthState(ctx);
- break;
- case GL_LINE_SMOOTH:
- if (rmesa->options.conformance_mode)
- r300SwitchFallback(ctx, R300_FALLBACK_LINE_SMOOTH, ctx->Line.SmoothFlag);
- break;
- case GL_LINE_STIPPLE:
- if (rmesa->options.conformance_mode)
- r300SwitchFallback(ctx, R300_FALLBACK_LINE_STIPPLE, ctx->Line.StippleFlag);
- break;
- case GL_POINT_SMOOTH:
- if (rmesa->options.conformance_mode)
- r300SwitchFallback(ctx, R300_FALLBACK_POINT_SMOOTH, ctx->Point.SmoothFlag);
- break;
- case GL_POLYGON_SMOOTH:
- if (rmesa->options.conformance_mode)
- r300SwitchFallback(ctx, R300_FALLBACK_POLYGON_SMOOTH, ctx->Polygon.SmoothFlag);
- break;
- case GL_POLYGON_STIPPLE:
- if (rmesa->options.conformance_mode)
- r300SwitchFallback(ctx, R300_FALLBACK_POLYGON_STIPPLE, ctx->Polygon.StippleFlag);
- break;
- case GL_POLYGON_OFFSET_POINT:
- case GL_POLYGON_OFFSET_LINE:
- case GL_POLYGON_OFFSET_FILL:
- r300SetPolygonOffsetState(ctx, state);
- break;
- case GL_SCISSOR_TEST:
- radeon_firevertices(&rmesa->radeon);
- rmesa->radeon.state.scissor.enabled = state;
- radeonUpdateScissor( ctx );
- break;
- case GL_STENCIL_TEST:
- r300SetStencilState(ctx, state);
- break;
- default:
- break;
- }
-}
-
-/**
- * Completely recalculates hardware state based on the Mesa state.
- */
-static void r300ResetHwState(r300ContextPtr r300)
-{
- struct gl_context *ctx = r300->radeon.glCtx;
- int has_tcl;
-
- has_tcl = r300->options.hw_tcl_enabled;
-
- if (RADEON_DEBUG & RADEON_STATE)
- fprintf(stderr, "%s\n", __FUNCTION__);
-
- r300ColorMask(ctx,
- ctx->Color.ColorMask[0][RCOMP],
- ctx->Color.ColorMask[0][GCOMP],
- ctx->Color.ColorMask[0][BCOMP],
- ctx->Color.ColorMask[0][ACOMP]);
-
- r300Enable(ctx, GL_DEPTH_TEST, ctx->Depth.Test);
- r300DepthMask(ctx, ctx->Depth.Mask);
- r300DepthFunc(ctx, ctx->Depth.Func);
-
- /* stencil */
- r300Enable(ctx, GL_STENCIL_TEST, ctx->Stencil._Enabled);
- r300StencilMaskSeparate(ctx, 0, ctx->Stencil.WriteMask[0]);
- r300StencilFuncSeparate(ctx, 0, ctx->Stencil.Function[0],
- ctx->Stencil.Ref[0], ctx->Stencil.ValueMask[0]);
- r300StencilOpSeparate(ctx, 0, ctx->Stencil.FailFunc[0],
- ctx->Stencil.ZFailFunc[0],
- ctx->Stencil.ZPassFunc[0]);
-
- r300UpdateCulling(ctx);
-
- r300SetBlendState(ctx);
- r300SetLogicOpState(ctx);
-
- r300AlphaFunc(ctx, ctx->Color.AlphaFunc, ctx->Color.AlphaRef);
- r300Enable(ctx, GL_ALPHA_TEST, ctx->Color.AlphaEnabled);
-
- r300->hw.vte.cmd[1] = R300_VPORT_X_SCALE_ENA
- | R300_VPORT_X_OFFSET_ENA
- | R300_VPORT_Y_SCALE_ENA
- | R300_VPORT_Y_OFFSET_ENA
- | R300_VPORT_Z_SCALE_ENA
- | R300_VPORT_Z_OFFSET_ENA | R300_VTX_W0_FMT;
- r300->hw.vte.cmd[2] = 0x00000008;
-
- r300->hw.vap_vf_max_vtx_indx.cmd[1] = 0x00FFFFFF;
- r300->hw.vap_vf_max_vtx_indx.cmd[2] = 0x00000000;
-
-#ifdef MESA_LITTLE_ENDIAN
- r300->hw.vap_cntl_status.cmd[1] = R300_VC_NO_SWAP;
-#else
- r300->hw.vap_cntl_status.cmd[1] = R300_VC_32BIT_SWAP;
-#endif
-
- /* disable VAP/TCL on non-TCL capable chips */
- if (!has_tcl)
- r300->hw.vap_cntl_status.cmd[1] |= R300_VAP_TCL_BYPASS;
-
- r300->hw.vap_psc_sgn_norm_cntl.cmd[1] = 0xAAAAAAAA;
-
- /* XXX: Other families? */
- if (has_tcl) {
- r300->hw.vap_clip_cntl.cmd[1] = R300_PS_UCP_MODE_DIST_COP;
-
- r300->hw.vap_clip.cmd[1] = r300PackFloat32(1.0); /* X */
- r300->hw.vap_clip.cmd[2] = r300PackFloat32(1.0); /* X */
- r300->hw.vap_clip.cmd[3] = r300PackFloat32(1.0); /* Y */
- r300->hw.vap_clip.cmd[4] = r300PackFloat32(1.0); /* Y */
-
- switch (r300->radeon.radeonScreen->chip_family) {
- case CHIP_FAMILY_R300:
- r300->hw.vap_pvs_vtx_timeout_reg.cmd[1] = R300_2288_R300;
- break;
- default:
- r300->hw.vap_pvs_vtx_timeout_reg.cmd[1] = R300_2288_RV350;
- break;
- }
- }
-
- r300->hw.gb_enable.cmd[1] = R300_GB_POINT_STUFF_ENABLE
- | R300_GB_LINE_STUFF_ENABLE
- | R300_GB_TRIANGLE_STUFF_ENABLE;
-
- r300->hw.gb_misc.cmd[R300_GB_MISC_MSPOS_0] = 0x66666666;
- r300->hw.gb_misc.cmd[R300_GB_MISC_MSPOS_1] = 0x06666666;
-
- r300->hw.gb_misc.cmd[R300_GB_MISC_TILE_CONFIG] =
- R300_GB_TILE_ENABLE | R300_GB_TILE_SIZE_16 /*| R300_GB_SUBPIXEL_1_16*/;
- switch (r300->radeon.radeonScreen->num_gb_pipes) {
- case 1:
- default:
- r300->hw.gb_misc.cmd[R300_GB_MISC_TILE_CONFIG] |=
- R300_GB_TILE_PIPE_COUNT_RV300;
- break;
- case 2:
- r300->hw.gb_misc.cmd[R300_GB_MISC_TILE_CONFIG] |=
- R300_GB_TILE_PIPE_COUNT_R300;
- break;
- case 3:
- r300->hw.gb_misc.cmd[R300_GB_MISC_TILE_CONFIG] |=
- R300_GB_TILE_PIPE_COUNT_R420_3P;
- break;
- case 4:
- r300->hw.gb_misc.cmd[R300_GB_MISC_TILE_CONFIG] |=
- R300_GB_TILE_PIPE_COUNT_R420;
- break;
- }
-
- /* XXX: Enable anti-aliasing? */
- r300->hw.gb_misc2.cmd[R300_GB_MISC2_AA_CONFIG] = GB_AA_CONFIG_AA_DISABLE;
- r300->hw.gb_misc2.cmd[R300_GB_MISC2_SELECT] = 0;
-
- r300->hw.ga_point_s0.cmd[1] = r300PackFloat32(0.0);
- r300->hw.ga_point_s0.cmd[2] = r300PackFloat32(0.0);
- r300->hw.ga_point_s0.cmd[3] = r300PackFloat32(1.0);
- r300->hw.ga_point_s0.cmd[4] = r300PackFloat32(1.0);
-
- r300->hw.ga_triangle_stipple.cmd[1] = 0x00050005;
-
- r300PointSize(ctx, 1.0);
-
- r300->hw.ga_point_minmax.cmd[1] = 0x18000006;
- r300->hw.ga_point_minmax.cmd[2] = 0x00020006;
- r300->hw.ga_point_minmax.cmd[3] = r300PackFloat32(1.0 / 192.0);
-
- r300LineWidth(ctx, 1.0);
-
- r300->hw.ga_line_stipple.cmd[1] = 0;
- r300->hw.ga_line_stipple.cmd[2] = r300PackFloat32(0.0);
- r300->hw.ga_line_stipple.cmd[3] = r300PackFloat32(1.0);
-
- r300ShadeModel(ctx, ctx->Light.ShadeModel);
-
- r300PolygonMode(ctx, GL_FRONT, ctx->Polygon.FrontMode);
- r300PolygonMode(ctx, GL_BACK, ctx->Polygon.BackMode);
- r300->hw.zbias_cntl.cmd[1] = 0x00000000;
-
- r300PolygonOffset(ctx, ctx->Polygon.OffsetFactor,
- ctx->Polygon.OffsetUnits);
- r300Enable(ctx, GL_POLYGON_OFFSET_POINT, ctx->Polygon.OffsetPoint);
- r300Enable(ctx, GL_POLYGON_OFFSET_LINE, ctx->Polygon.OffsetLine);
- r300Enable(ctx, GL_POLYGON_OFFSET_FILL, ctx->Polygon.OffsetFill);
-
- r300->hw.su_depth_scale.cmd[1] = 0x4B7FFFFF;
- r300->hw.su_depth_scale.cmd[2] = 0x00000000;
-
- r300->hw.sc_hyperz.cmd[1] = 0x0000001C;
- r300->hw.sc_hyperz.cmd[2] = 0x2DA49525;
-
- r300->hw.sc_screendoor.cmd[1] = 0x00FFFFFF;
-
- r300->hw.us_out_fmt.cmd[1] = R500_OUT_FMT_C4_8 |
- R500_C0_SEL_B | R500_C1_SEL_G | R500_C2_SEL_R | R500_C3_SEL_A;
- r300->hw.us_out_fmt.cmd[2] = R500_OUT_FMT_UNUSED |
- R500_C0_SEL_B | R500_C1_SEL_G | R500_C2_SEL_R | R500_C3_SEL_A;
- r300->hw.us_out_fmt.cmd[3] = R500_OUT_FMT_UNUSED |
- R500_C0_SEL_B | R500_C1_SEL_G | R500_C2_SEL_R | R500_C3_SEL_A;
- r300->hw.us_out_fmt.cmd[4] = R500_OUT_FMT_UNUSED |
- R500_C0_SEL_B | R500_C1_SEL_G | R500_C2_SEL_R | R500_C3_SEL_A;
- r300->hw.us_out_fmt.cmd[5] = R300_W_FMT_W0 | R300_W_SRC_US;
-
- /* disable fog unit */
- r300->hw.fogs.cmd[R300_FOGS_STATE] = 0;
- r300->hw.fg_depth_src.cmd[1] = R300_FG_DEPTH_SRC_SCAN;
-
- r300->hw.rb3d_cctl.cmd[1] = 0;
-
- r300BlendColor(ctx, ctx->Color.BlendColor);
-
- r300->hw.rb3d_dither_ctl.cmd[1] = 0;
- r300->hw.rb3d_dither_ctl.cmd[2] = 0;
- r300->hw.rb3d_dither_ctl.cmd[3] = 0;
- r300->hw.rb3d_dither_ctl.cmd[4] = 0;
- r300->hw.rb3d_dither_ctl.cmd[5] = 0;
- r300->hw.rb3d_dither_ctl.cmd[6] = 0;
- r300->hw.rb3d_dither_ctl.cmd[7] = 0;
- r300->hw.rb3d_dither_ctl.cmd[8] = 0;
- r300->hw.rb3d_dither_ctl.cmd[9] = 0;
-
- r300->hw.rb3d_aaresolve_ctl.cmd[1] = 0;
-
- r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[1] = 0x00000000;
- r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[2] = 0xffffffff;
-
- r300->hw.zb_depthclearvalue.cmd[1] = 0;
-
- r300->hw.zstencil_format.cmd[2] = R300_ZTOP_DISABLE;
- r300->hw.zstencil_format.cmd[3] = 0x00000003;
- r300->hw.zstencil_format.cmd[4] = 0x00000000;
- r300SetEarlyZState(ctx);
-
- r300->hw.zb_zmask.cmd[1] = 0;
- r300->hw.zb_zmask.cmd[2] = 0;
-
- r300->hw.zb_hiz_offset.cmd[1] = 0;
-
- r300->hw.zb_hiz_pitch.cmd[1] = 0;
-
- r300VapCntl(r300, 0, 0, 0);
- if (has_tcl) {
- r300->hw.vps.cmd[R300_VPS_ZERO_0] = 0;
- r300->hw.vps.cmd[R300_VPS_ZERO_1] = 0;
- r300->hw.vps.cmd[R300_VPS_POINTSIZE] = r300PackFloat32(1.0);
- r300->hw.vps.cmd[R300_VPS_ZERO_3] = 0;
- }
-
- r300->radeon.hw.all_dirty = GL_TRUE;
-}
-
-void r300UpdateShaders(r300ContextPtr rmesa)
-{
- struct gl_context *ctx = rmesa->radeon.glCtx;
-
- /* should only happenen once, just after context is created */
- /* TODO: shouldn't we fallback to sw here? */
- if (!ctx->FragmentProgram._Current) {
- fprintf(stderr, "No ctx->FragmentProgram._Current!!\n");
- return;
- }
-
- {
- struct r300_fragment_program *fp;
-
- fp = r300SelectAndTranslateFragmentShader(ctx);
-
- r300SwitchFallback(ctx, R300_FALLBACK_FRAGMENT_PROGRAM, fp->error);
- }
-
- if (rmesa->options.hw_tcl_enabled) {
- struct r300_vertex_program *vp;
-
- vp = r300SelectAndTranslateVertexShader(ctx);
-
- r300SwitchFallback(ctx, R300_FALLBACK_VERTEX_PROGRAM, vp->error);
- }
-
- r300UpdateStateParameters(ctx, _NEW_PROGRAM | _NEW_PROGRAM_CONSTANTS);
- rmesa->radeon.NewGLState = 0;
-}
-
-static const GLfloat *get_fragmentprogram_constant(struct gl_context *ctx, GLuint index, GLfloat * buffer)
-{
- static const GLfloat dummy[4] = { 0, 0, 0, 0 };
- r300ContextPtr rmesa = R300_CONTEXT(ctx);
- struct rc_constant * rcc = &rmesa->selected_fp->code.constants.Constants[index];
-
- switch(rcc->Type) {
- case RC_CONSTANT_EXTERNAL:
- return &ctx->FragmentProgram._Current->Base.Parameters->ParameterValues[rcc->u.External][0].f;
- case RC_CONSTANT_IMMEDIATE:
- return rcc->u.Immediate;
- case RC_CONSTANT_STATE:
- switch(rcc->u.State[0]) {
- case RC_STATE_SHADOW_AMBIENT: {
- const int unit = (int) rcc->u.State[1];
- const struct gl_texture_object *texObj = ctx->Texture.Unit[unit]._Current;
- if (texObj) {
- buffer[0] =
- buffer[1] =
- buffer[2] =
- buffer[3] = texObj->Sampler.CompareFailValue;
- }
- return buffer;
- }
-
- case RC_STATE_R300_WINDOW_DIMENSION: {
- __DRIdrawable * drawable = radeon_get_drawable(&rmesa->radeon);
- buffer[0] = drawable->w * 0.5f; /* width*0.5 */
- buffer[1] = drawable->h * 0.5f; /* height*0.5 */
- buffer[2] = 0.5F; /* for moving range [-1 1] -> [0 1] */
- buffer[3] = 1.0F; /* not used */
- return buffer;
- }
-
- case RC_STATE_R300_TEXRECT_FACTOR: {
- struct gl_texture_object *t =
- ctx->Texture.Unit[rcc->u.State[1]].CurrentTex[TEXTURE_RECT_INDEX];
-
- if (t && t->Image[0][t->BaseLevel]) {
- struct gl_texture_image *image =
- t->Image[0][t->BaseLevel];
- buffer[0] = 1.0 / image->Width2;
- buffer[1] = 1.0 / image->Height2;
- } else {
- buffer[0] = 1.0;
- buffer[1] = 1.0;
- }
- buffer[2] = 1.0;
- buffer[3] = 1.0;
- return buffer;
- }
- }
- }
-
- return dummy;
-}
-
-
-static void r300SetupPixelShader(struct gl_context *ctx)
-{
- r300ContextPtr rmesa = R300_CONTEXT(ctx);
- struct r300_fragment_program *fp = rmesa->selected_fp;
- struct r300_fragment_program_code *code;
- int i;
-
- code = &fp->code.code.r300;
-
- R300_STATECHANGE(rmesa, fpi[0]);
- R300_STATECHANGE(rmesa, fpi[1]);
- R300_STATECHANGE(rmesa, fpi[2]);
- R300_STATECHANGE(rmesa, fpi[3]);
- rmesa->hw.fpi[0].cmd[R300_FPI_CMD_0] = cmdpacket0(rmesa->radeon.radeonScreen, R300_US_ALU_RGB_INST_0, code->alu.length);
- rmesa->hw.fpi[1].cmd[R300_FPI_CMD_0] = cmdpacket0(rmesa->radeon.radeonScreen, R300_US_ALU_RGB_ADDR_0, code->alu.length);
- rmesa->hw.fpi[2].cmd[R300_FPI_CMD_0] = cmdpacket0(rmesa->radeon.radeonScreen, R300_US_ALU_ALPHA_INST_0, code->alu.length);
- rmesa->hw.fpi[3].cmd[R300_FPI_CMD_0] = cmdpacket0(rmesa->radeon.radeonScreen, R300_US_ALU_ALPHA_ADDR_0, code->alu.length);
- for (i = 0; i < code->alu.length; i++) {
- rmesa->hw.fpi[0].cmd[R300_FPI_INSTR_0 + i] = code->alu.inst[i].rgb_inst;
- rmesa->hw.fpi[1].cmd[R300_FPI_INSTR_0 + i] = code->alu.inst[i].rgb_addr;
- rmesa->hw.fpi[2].cmd[R300_FPI_INSTR_0 + i] = code->alu.inst[i].alpha_inst;
- rmesa->hw.fpi[3].cmd[R300_FPI_INSTR_0 + i] = code->alu.inst[i].alpha_addr;
- }
-
- R300_STATECHANGE(rmesa, fp);
- rmesa->hw.fp.cmd[R300_FP_CNTL0] = code->config;
- rmesa->hw.fp.cmd[R300_FP_CNTL1] = code->pixsize;
- rmesa->hw.fp.cmd[R300_FP_CNTL2] = code->code_offset;
- for (i = 0; i < 4; i++)
- rmesa->hw.fp.cmd[R300_FP_NODE0 + i] = code->code_addr[i];
-
- R300_STATECHANGE(rmesa, fpp);
- rmesa->hw.fpp.cmd[R300_FPP_CMD_0] = cmdpacket0(rmesa->radeon.radeonScreen, R300_PFS_PARAM_0_X, fp->code.constants.Count * 4);
- for (i = 0; i < fp->code.constants.Count; i++) {
- GLfloat buffer[4];
- const GLfloat *constant = get_fragmentprogram_constant(ctx, i, buffer);
- rmesa->hw.fpp.cmd[R300_FPP_PARAM_0 + 4 * i + 0] = r300PackFloat24(constant[0]);
- rmesa->hw.fpp.cmd[R300_FPP_PARAM_0 + 4 * i + 1] = r300PackFloat24(constant[1]);
- rmesa->hw.fpp.cmd[R300_FPP_PARAM_0 + 4 * i + 2] = r300PackFloat24(constant[2]);
- rmesa->hw.fpp.cmd[R300_FPP_PARAM_0 + 4 * i + 3] = r300PackFloat24(constant[3]);
- }
-}
-
-#define bump_r500fp_count(ptr, new_count) do{\
- drm_r300_cmd_header_t* _p=((drm_r300_cmd_header_t*)(ptr));\
- int _nc=(new_count)/6; \
- assert(_nc < 256); \
- if(_nc>_p->r500fp.count)_p->r500fp.count=_nc;\
-} while(0)
-
-#define bump_r500fp_const_count(ptr, new_count) do{\
- drm_r300_cmd_header_t* _p=((drm_r300_cmd_header_t*)(ptr));\
- int _nc=(new_count)/4; \
- assert(_nc < 256); \
- if(_nc>_p->r500fp.count)_p->r500fp.count=_nc;\
-} while(0)
-
-static void r500SetupPixelShader(struct gl_context *ctx)
-{
- r300ContextPtr rmesa = R300_CONTEXT(ctx);
- struct r300_fragment_program *fp = rmesa->selected_fp;
- int i;
- struct r500_fragment_program_code *code;
-
- ((drm_r300_cmd_header_t *) rmesa->hw.r500fp.cmd)->r500fp.count = 0;
- ((drm_r300_cmd_header_t *) rmesa->hw.r500fp_const.cmd)->r500fp.count = 0;
-
- code = &fp->code.code.r500;
-
- R300_STATECHANGE(rmesa, fp);
- rmesa->hw.fp.cmd[R500_FP_PIXSIZE] = code->max_temp_idx;
-
- rmesa->hw.fp.cmd[R500_FP_CODE_ADDR] =
- R500_US_CODE_START_ADDR(0) |
- R500_US_CODE_END_ADDR(code->inst_end);
- rmesa->hw.fp.cmd[R500_FP_CODE_RANGE] =
- R500_US_CODE_RANGE_ADDR(0) |
- R500_US_CODE_RANGE_SIZE(code->inst_end);
- rmesa->hw.fp.cmd[R500_FP_CODE_OFFSET] =
- R500_US_CODE_OFFSET_ADDR(0);
-
- R300_STATECHANGE(rmesa, r500fp);
- /* Emit our shader... */
- for (i = 0; i < code->inst_end+1; i++) {
- rmesa->hw.r500fp.cmd[i*6+1] = code->inst[i].inst0;
- rmesa->hw.r500fp.cmd[i*6+2] = code->inst[i].inst1;
- rmesa->hw.r500fp.cmd[i*6+3] = code->inst[i].inst2;
- rmesa->hw.r500fp.cmd[i*6+4] = code->inst[i].inst3;
- rmesa->hw.r500fp.cmd[i*6+5] = code->inst[i].inst4;
- rmesa->hw.r500fp.cmd[i*6+6] = code->inst[i].inst5;
- }
-
- bump_r500fp_count(rmesa->hw.r500fp.cmd, (code->inst_end + 1) * 6);
-
- R300_STATECHANGE(rmesa, r500fp_const);
- for (i = 0; i < fp->code.constants.Count; i++) {
- GLfloat buffer[4];
- const GLfloat *constant = get_fragmentprogram_constant(ctx, i, buffer);
- rmesa->hw.r500fp_const.cmd[R300_FPP_PARAM_0 + 4 * i + 0] = r300PackFloat32(constant[0]);
- rmesa->hw.r500fp_const.cmd[R300_FPP_PARAM_0 + 4 * i + 1] = r300PackFloat32(constant[1]);
- rmesa->hw.r500fp_const.cmd[R300_FPP_PARAM_0 + 4 * i + 2] = r300PackFloat32(constant[2]);
- rmesa->hw.r500fp_const.cmd[R300_FPP_PARAM_0 + 4 * i + 3] = r300PackFloat32(constant[3]);
- }
- bump_r500fp_const_count(rmesa->hw.r500fp_const.cmd, fp->code.constants.Count * 4);
-}
-
-void r300SetupVAP(struct gl_context *ctx, GLuint InputsRead, GLuint OutputsWritten)
-{
- r300ContextPtr rmesa = R300_CONTEXT( ctx );
- struct vertex_attribute *attrs = rmesa->vbuf.attribs;
- int i, j, reg_count;
- uint32_t *vir0 = &rmesa->hw.vir[0].cmd[1];
- uint32_t *vir1 = &rmesa->hw.vir[1].cmd[1];
-
- for (i = 0; i < R300_VIR_CMDSIZE-1; ++i)
- vir0[i] = vir1[i] = 0;
-
- for (i = 0, j = 0; i < rmesa->vbuf.num_attribs; ++i) {
- int tmp;
-
- tmp = attrs[i].data_type | (attrs[i].dst_loc << R300_DST_VEC_LOC_SHIFT);
- if (attrs[i]._signed)
- tmp |= R300_SIGNED;
- if (attrs[i].normalize)
- tmp |= R300_NORMALIZE;
-
- if (i % 2 == 0) {
- vir0[j] = tmp << R300_DATA_TYPE_0_SHIFT;
- vir1[j] = attrs[i].swizzle | (attrs[i].write_mask << R300_WRITE_ENA_SHIFT);
- } else {
- vir0[j] |= tmp << R300_DATA_TYPE_1_SHIFT;
- vir1[j] |= (attrs[i].swizzle | (attrs[i].write_mask << R300_WRITE_ENA_SHIFT)) << R300_SWIZZLE1_SHIFT;
- ++j;
- }
- }
-
- reg_count = (rmesa->vbuf.num_attribs + 1) >> 1;
- if (rmesa->vbuf.num_attribs % 2 != 0) {
- vir0[reg_count-1] |= R300_LAST_VEC << R300_DATA_TYPE_0_SHIFT;
- } else {
- vir0[reg_count-1] |= R300_LAST_VEC << R300_DATA_TYPE_1_SHIFT;
- }
-
- R300_STATECHANGE(rmesa, vir[0]);
- R300_STATECHANGE(rmesa, vir[1]);
- R300_STATECHANGE(rmesa, vof);
- R300_STATECHANGE(rmesa, vic);
-
- if (rmesa->radeon.radeonScreen->kernel_mm) {
- rmesa->hw.vir[0].cmd[0] &= 0xC000FFFF;
- rmesa->hw.vir[1].cmd[0] &= 0xC000FFFF;
- rmesa->hw.vir[0].cmd[0] |= (reg_count & 0x3FFF) << 16;
- rmesa->hw.vir[1].cmd[0] |= (reg_count & 0x3FFF) << 16;
- } else {
- ((drm_r300_cmd_header_t *) rmesa->hw.vir[0].cmd)->packet0.count = reg_count;
- ((drm_r300_cmd_header_t *) rmesa->hw.vir[1].cmd)->packet0.count = reg_count;
- }
-
- rmesa->hw.vic.cmd[R300_VIC_CNTL_0] = r300VAPInputCntl0(ctx, InputsRead);
- rmesa->hw.vic.cmd[R300_VIC_CNTL_1] = r300VAPInputCntl1(ctx, InputsRead);
- rmesa->hw.vof.cmd[R300_VOF_CNTL_0] = r300VAPOutputCntl0(ctx, OutputsWritten);
- rmesa->hw.vof.cmd[R300_VOF_CNTL_1] = r300VAPOutputCntl1(ctx, OutputsWritten);
-}
-
-void r300UpdateShaderStates(r300ContextPtr rmesa)
-{
- struct gl_context *ctx;
- ctx = rmesa->radeon.glCtx;
-
- /* should only happenen once, just after context is created */
- if (!ctx->FragmentProgram._Current)
- return;
-
- r300SetEarlyZState(ctx);
-
- r300SetupTextures(ctx);
-
- rmesa->vtbl.SetupPixelShader(ctx);
-
- rmesa->vtbl.SetupRSUnit(ctx);
-
- if (rmesa->options.hw_tcl_enabled) {
- r300SetupVertexProgram(rmesa);
- }
-}
-
-#define EASY_US_OUT_FMT(comps, c0, c1, c2, c3) \
- (R500_OUT_FMT_##comps | R500_C0_SEL_##c0 | R500_C1_SEL_##c1 | \
- R500_C2_SEL_##c2 | R500_C3_SEL_##c3)
-static void r300SetupUsOutputFormat(struct gl_context *ctx)
-{
- r300ContextPtr rmesa = R300_CONTEXT(ctx);
- uint32_t hw_format;
- struct radeon_renderbuffer *rrb = radeon_get_colorbuffer(&rmesa->radeon);
-
- if (!rrb) {
- return;
- }
-
- switch (rrb->base.Format)
- {
- case MESA_FORMAT_RGBA5551:
- case MESA_FORMAT_RGBA8888:
- hw_format = EASY_US_OUT_FMT(C4_8, A, B, G, R);
- break;
- case MESA_FORMAT_RGB565_REV:
- case MESA_FORMAT_RGBA8888_REV:
- hw_format = EASY_US_OUT_FMT(C4_8, R, G, B, A);
- break;
- case MESA_FORMAT_RGB565:
- case MESA_FORMAT_ARGB4444:
- case MESA_FORMAT_ARGB1555:
- case MESA_FORMAT_XRGB8888:
- case MESA_FORMAT_ARGB8888:
- hw_format = EASY_US_OUT_FMT(C4_8, B, G, R, A);
- break;
- case MESA_FORMAT_ARGB4444_REV:
- case MESA_FORMAT_ARGB1555_REV:
- case MESA_FORMAT_XRGB8888_REV:
- case MESA_FORMAT_ARGB8888_REV:
- hw_format = EASY_US_OUT_FMT(C4_8, A, R, G, B);
- break;
- case MESA_FORMAT_SRGBA8:
- hw_format = EASY_US_OUT_FMT(C4_10_GAMMA, A, B, G, R);
- break;
- case MESA_FORMAT_SARGB8:
- hw_format = EASY_US_OUT_FMT(C4_10_GAMMA, B, G, R, A);
- break;
- case MESA_FORMAT_SL8:
- hw_format = EASY_US_OUT_FMT(C4_10_GAMMA, A, A, R, A);
- break;
- case MESA_FORMAT_A8:
- hw_format = EASY_US_OUT_FMT(C4_8, A, A, A, A);
- break;
- case MESA_FORMAT_L8:
- case MESA_FORMAT_I8:
- hw_format = EASY_US_OUT_FMT(C4_8, A, A, R, A);
- break;
- default:
- assert(!"Unsupported format");
- hw_format = 0;
- break;
- }
-
- R300_STATECHANGE(rmesa, us_out_fmt);
- rmesa->hw.us_out_fmt.cmd[1] = hw_format;
-}
-#undef EASY_US_OUT_FMT
-
-/**
- * Called by Mesa after an internal state update.
- */
-static void r300InvalidateState(struct gl_context * ctx, GLuint new_state)
-{
- r300ContextPtr r300 = R300_CONTEXT(ctx);
-
- _swrast_InvalidateState(ctx, new_state);
- _swsetup_InvalidateState(ctx, new_state);
- _vbo_InvalidateState(ctx, new_state);
- _tnl_InvalidateState(ctx, new_state);
-
- if (new_state & _NEW_BUFFERS) {
- _mesa_update_framebuffer(ctx);
- /* this updates the DrawBuffer's Width/Height if it's a FBO */
- _mesa_update_draw_buffer_bounds(ctx);
-
- R300_STATECHANGE(r300, cb);
- R300_STATECHANGE(r300, zb);
- }
-
- if (new_state & (_NEW_LIGHT)) {
- R300_STATECHANGE(r300, shade2);
- if (ctx->Light.ProvokingVertex == GL_LAST_VERTEX_CONVENTION)
- r300->hw.shade2.cmd[1] |= R300_GA_COLOR_CONTROL_PROVOKING_VERTEX_LAST;
- else
- r300->hw.shade2.cmd[1] &= ~R300_GA_COLOR_CONTROL_PROVOKING_VERTEX_LAST;
- }
-
- if (new_state & _NEW_BUFFERS) {
- r300SetupUsOutputFormat(ctx);
- }
-
- r300->radeon.NewGLState |= new_state;
-}
-
-/**
- * Calculate initial hardware state and register state functions.
- * Assumes that the command buffer and state atoms have been
- * initialized already.
- */
-void r300InitState(r300ContextPtr r300)
-{
- r300ResetHwState(r300);
-}
-
-static void r300RenderMode(struct gl_context * ctx, GLenum mode)
-{
- r300SwitchFallback(ctx, R300_FALLBACK_RENDER_MODE, ctx->RenderMode != GL_RENDER);
-}
-
-/**
- * Initialize driver's state callback functions
- */
-void r300InitStateFuncs(radeonContextPtr radeon, struct dd_function_table *functions)
-{
-
- functions->UpdateState = r300InvalidateState;
- functions->AlphaFunc = r300AlphaFunc;
- functions->BlendColor = r300BlendColor;
- functions->BlendEquationSeparate = r300BlendEquationSeparate;
- functions->BlendFuncSeparate = r300BlendFuncSeparate;
- functions->Enable = r300Enable;
- functions->ColorMask = r300ColorMask;
- functions->DepthFunc = r300DepthFunc;
- functions->DepthMask = r300DepthMask;
- functions->CullFace = r300CullFace;
- functions->FrontFace = r300FrontFace;
- functions->ShadeModel = r300ShadeModel;
- functions->LogicOpcode = r300LogicOpcode;
-
- /* ARB_point_parameters */
- functions->PointParameterfv = r300PointParameter;
-
- /* Stencil related */
- functions->StencilFuncSeparate = r300StencilFuncSeparate;
- functions->StencilMaskSeparate = r300StencilMaskSeparate;
- functions->StencilOpSeparate = r300StencilOpSeparate;
-
- /* Viewport related */
- functions->Viewport = r300Viewport;
- functions->DepthRange = r300DepthRange;
- functions->PointSize = r300PointSize;
- functions->LineWidth = r300LineWidth;
-
- functions->PolygonOffset = r300PolygonOffset;
- functions->PolygonMode = r300PolygonMode;
-
- functions->RenderMode = r300RenderMode;
-
- functions->ClipPlane = r300ClipPlane;
- functions->Scissor = radeonScissor;
-
- functions->DrawBuffer = radeonDrawBuffer;
- functions->ReadBuffer = radeonReadBuffer;
-
- functions->CopyPixels = _mesa_meta_CopyPixels;
- functions->DrawPixels = _mesa_meta_DrawPixels;
- if (radeon->radeonScreen->kernel_mm)
- functions->ReadPixels = radeonReadPixels;
-}
-
-void r300InitShaderFunctions(r300ContextPtr r300)
-{
- if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) {
- r300->vtbl.SetupRSUnit = r500SetupRSUnit;
- r300->vtbl.SetupPixelShader = r500SetupPixelShader;
- r300->vtbl.SetupFragmentShaderTextures = r500SetupFragmentShaderTextures;
- } else {
- r300->vtbl.SetupRSUnit = r300SetupRSUnit;
- r300->vtbl.SetupPixelShader = r300SetupPixelShader;
- r300->vtbl.SetupFragmentShaderTextures = r300SetupFragmentShaderTextures;
- }
-}
+++ /dev/null
-/*
-Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
-
-The Weather Channel (TM) funded Tungsten Graphics to develop the
-initial release of the Radeon 8500 driver under the XFree86 license.
-This notice must be preserved.
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-**************************************************************************/
-
-/*
- * Authors:
- * Nicolai Haehnle <prefect_@gmx.net>
- */
-
-#ifndef __R300_STATE_H__
-#define __R300_STATE_H__
-
-#include "r300_context.h"
-
-#define R300_NEWPRIM( rmesa ) \
- do { \
- if ( rmesa->radeon.dma.flush ) \
- rmesa->radeon.dma.flush( rmesa->radeon.glCtx ); \
- } while (0)
-
-#define R300_STATECHANGE(r300, atom) \
- do { \
- R300_NEWPRIM(r300); \
- r300->hw.atom.dirty = GL_TRUE; \
- r300->radeon.hw.is_dirty = GL_TRUE; \
- } while(0)
-
-void r300UpdateViewportOffset (struct gl_context * ctx);
-void r300UpdateDrawBuffer (struct gl_context * ctx);
-void r300UpdateShaders (r300ContextPtr rmesa);
-void r300UpdateShaderStates (r300ContextPtr rmesa);
-void r300InitState (r300ContextPtr r300);
-void r300InitStateFuncs (radeonContextPtr radeon, struct dd_function_table *functions);
-void r300VapCntl(r300ContextPtr rmesa, GLuint input_count, GLuint output_count, GLuint temp_count);
-void r300SetupVAP(struct gl_context *ctx, GLuint InputsRead, GLuint OutputsWritten);
-
-#endif /* __R300_STATE_H__ */
+++ /dev/null
-/**************************************************************************
-
-Copyright (C) 2007 Dave Airlie
-
-All Rights Reserved.
-
-Permission is hereby granted, free of charge, to any person obtaining a
-copy of this software and associated documentation files (the "Software"),
-to deal in the Software without restriction, including without limitation
-on the rights to use, copy, modify, merge, publish, distribute, sub
-license, and/or sell copies of the Software, and to permit persons to whom
-the Software is furnished to do so, subject to the following conditions:
-
-The above copyright notice and this permission notice (including the next
-paragraph) shall be included in all copies or substantial portions of the
-Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
-THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
-DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
-USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-**************************************************************************/
-
-/*
- * Authors:
- * Dave Airlie <airlied@linux.ie>
- * Maciej Cencora <m.cencora@gmail.com>
- */
-
-#include "tnl/tnl.h"
-#include "tnl/t_pipeline.h"
-
-#include "r300_state.h"
-#include "r300_swtcl.h"
-#include "r300_emit.h"
-#include "r300_tex.h"
-#include "r300_render.h"
-#include "main/simple_list.h"
-
-#define EMIT_ATTR( ATTR, STYLE ) \
-do { \
- rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].attrib = (ATTR); \
- rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].format = (STYLE); \
- rmesa->radeon.swtcl.vertex_attr_count++; \
-} while (0)
-
-#define EMIT_PAD( N ) \
-do { \
- rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].attrib = 0; \
- rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].format = EMIT_PAD; \
- rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].offset = (N); \
- rmesa->radeon.swtcl.vertex_attr_count++; \
-} while (0)
-
-#define ADD_ATTR(_attr, _format, _dst_loc, _swizzle, _write_mask, _normalize) \
-do { \
- attrs[num_attrs].element = (_attr); \
- attrs[num_attrs].data_type = (_format); \
- attrs[num_attrs].dst_loc = (_dst_loc); \
- attrs[num_attrs].swizzle = (_swizzle); \
- attrs[num_attrs].write_mask = (_write_mask); \
- attrs[num_attrs]._signed = 0; \
- attrs[num_attrs].normalize = (_normalize); \
- ++num_attrs; \
-} while (0)
-
-void r300ChooseSwtclVertexFormat(struct gl_context *ctx, GLuint *_InputsRead, GLuint *_OutputsWritten)
-{
- r300ContextPtr rmesa = R300_CONTEXT( ctx );
- TNLcontext *tnl = TNL_CONTEXT(ctx);
- struct vertex_buffer *VB = &tnl->vb;
- int first_free_tex = 0;
- GLuint InputsRead = 0;
- GLuint OutputsWritten = 0;
- int num_attrs = 0;
- GLuint fp_reads = rmesa->selected_fp->InputsRead;
- struct vertex_attribute *attrs = rmesa->vbuf.attribs;
-
- radeon_print(RADEON_SWRENDER, RADEON_VERBOSE, "%s\n", __func__);
- rmesa->swtcl.coloroffset = rmesa->swtcl.specoffset = 0;
- rmesa->radeon.swtcl.vertex_attr_count = 0;
-
- if (RADEON_DEBUG & RADEON_VERTS)
- fprintf(stderr, "%s\n", __func__);
-
- /* We always want non Ndc coords format */
- VB->AttribPtr[VERT_ATTRIB_POS] = VB->ClipPtr;
-
- /* Always write position vector */
- InputsRead |= 1 << VERT_ATTRIB_POS;
- OutputsWritten |= 1 << VERT_RESULT_HPOS;
- EMIT_ATTR( _TNL_ATTRIB_POS, EMIT_4F );
- ADD_ATTR(VERT_ATTRIB_POS, R300_DATA_TYPE_FLOAT_4, SWTCL_OVM_POS, SWIZZLE_XYZW, MASK_XYZW, 0);
- rmesa->swtcl.coloroffset = 4;
-
- if (fp_reads & FRAG_BIT_COL0) {
- InputsRead |= 1 << VERT_ATTRIB_COLOR0;
- OutputsWritten |= 1 << VERT_RESULT_COL0;
-#if MESA_LITTLE_ENDIAN
- EMIT_ATTR( _TNL_ATTRIB_COLOR0, EMIT_4UB_4F_RGBA );
- ADD_ATTR(VERT_ATTRIB_COLOR0, R300_DATA_TYPE_BYTE, SWTCL_OVM_COLOR0, SWIZZLE_XYZW, MASK_XYZW, 1);
-#else
- EMIT_ATTR( _TNL_ATTRIB_COLOR0, EMIT_4UB_4F_ABGR );
- ADD_ATTR(VERT_ATTRIB_COLOR0, R300_DATA_TYPE_BYTE, SWTCL_OVM_COLOR0, SWIZZLE_XYZW, MASK_XYZW, 1);
-#endif
- }
-
- if (fp_reads & FRAG_BIT_COL1) {
- GLuint swiz = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_ONE);
- InputsRead |= 1 << VERT_ATTRIB_COLOR1;
- OutputsWritten |= 1 << VERT_RESULT_COL1;
-#if MESA_LITTLE_ENDIAN
- EMIT_ATTR( _TNL_ATTRIB_COLOR1, EMIT_4UB_4F_RGBA );
- ADD_ATTR(VERT_ATTRIB_COLOR1, R300_DATA_TYPE_BYTE, SWTCL_OVM_COLOR1, swiz, MASK_XYZW, 1);
-#else
- EMIT_ATTR( _TNL_ATTRIB_COLOR1, EMIT_4UB_4F_ABGR );
- ADD_ATTR(VERT_ATTRIB_COLOR1, R300_DATA_TYPE_BYTE, SWTCL_OVM_COLOR1, swiz, MASK_XYZW, 1);
-#endif
- rmesa->swtcl.specoffset = rmesa->swtcl.coloroffset + 1;
- }
-
- if (ctx->Light.Enabled && ctx->Light.Model.TwoSide) {
- VB->AttribPtr[VERT_ATTRIB_GENERIC0] = VB->BackfaceColorPtr;
- OutputsWritten |= 1 << VERT_RESULT_BFC0;
-#if MESA_LITTLE_ENDIAN
- EMIT_ATTR( _TNL_ATTRIB_GENERIC0, EMIT_4UB_4F_RGBA );
- ADD_ATTR(VERT_ATTRIB_GENERIC0, R300_DATA_TYPE_BYTE, SWTCL_OVM_COLOR2, SWIZZLE_XYZW, MASK_XYZW, 1);
-#else
- EMIT_ATTR( _TNL_ATTRIB_GENERIC0, EMIT_4UB_4F_ABGR );
- ADD_ATTR(VERT_ATTRIB_GENERIC0, R300_DATA_TYPE_BYTE, SWTCL_OVM_COLOR2, SWIZZLE_XYZW, MASK_XYZW, 1);
-#endif
- if (fp_reads & FRAG_BIT_COL1) {
- VB->AttribPtr[VERT_ATTRIB_GENERIC1] = VB->BackfaceSecondaryColorPtr;
- GLuint swiz = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_ONE);
- OutputsWritten |= 1 << VERT_RESULT_BFC1;
-#if MESA_LITTLE_ENDIAN
- EMIT_ATTR( _TNL_ATTRIB_GENERIC1, EMIT_4UB_4F_RGBA );
- ADD_ATTR(VERT_ATTRIB_GENERIC1, R300_DATA_TYPE_BYTE, SWTCL_OVM_COLOR3, swiz, MASK_XYZW, 1);
-#else
- EMIT_ATTR( _TNL_ATTRIB_GENERIC1, EMIT_4UB_4F_ABGR );
- ADD_ATTR(VERT_ATTRIB_GENERIC1, R300_DATA_TYPE_BYTE, SWTCL_OVM_COLOR3, swiz, MASK_XYZW, 1);
-#endif
- }
- }
-
- if (RENDERINPUTS_TEST(tnl->render_inputs_bitset, _TNL_ATTRIB_POINTSIZE )) {
- GLuint swiz = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_ZERO, SWIZZLE_ZERO, SWIZZLE_ZERO);
- InputsRead |= 1 << VERT_ATTRIB_POINT_SIZE;
- OutputsWritten |= 1 << VERT_RESULT_PSIZ;
- EMIT_ATTR( _TNL_ATTRIB_POINTSIZE, EMIT_1F );
- ADD_ATTR(VERT_ATTRIB_POINT_SIZE, R300_DATA_TYPE_FLOAT_1, SWTCL_OVM_POINT_SIZE, swiz, MASK_X, 0);
- }
-
- if (rmesa->selected_fp->wpos_attr != FRAG_ATTRIB_MAX) {
- int tex_id = rmesa->selected_fp->wpos_attr - FRAG_ATTRIB_TEX0;
-
- VB->AttribPtr[VERT_ATTRIB_TEX0 + tex_id] = VB->AttribPtr[VERT_ATTRIB_POS];
- VB->AttribPtr[_TNL_ATTRIB_TEX0 + tex_id] = VB->AttribPtr[VERT_ATTRIB_POS];
- RENDERINPUTS_SET(tnl->render_inputs_bitset, _TNL_ATTRIB_TEX0 + tex_id);
- }
-
- if (rmesa->selected_fp->fog_attr != FRAG_ATTRIB_MAX) {
- int tex_id = rmesa->selected_fp->fog_attr - FRAG_ATTRIB_TEX0;
-
- VB->AttribPtr[VERT_ATTRIB_TEX0 + tex_id] = VB->AttribPtr[VERT_ATTRIB_FOG];
- VB->AttribPtr[_TNL_ATTRIB_TEX0 + tex_id] = VB->AttribPtr[VERT_ATTRIB_FOG];
- RENDERINPUTS_SET(tnl->render_inputs_bitset, _TNL_ATTRIB_TEX0 + tex_id);
- }
-
- /**
- * Sending only one texcoord component may lead to lock up,
- * so for all textures always output 4 texcoord components to RS.
- */
- {
- int i;
- GLuint swiz, format, hw_format;
- for (i = 0; i < ctx->Const.MaxTextureUnits; i++) {
- if (fp_reads & FRAG_BIT_TEX(i)) {
- switch (VB->AttribPtr[_TNL_ATTRIB_TEX0 + i]->size) {
- case 1:
- format = EMIT_1F;
- hw_format = R300_DATA_TYPE_FLOAT_1;
- swiz = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_ZERO, SWIZZLE_ZERO, SWIZZLE_ONE);
- break;
- case 2:
- format = EMIT_2F;
- hw_format = R300_DATA_TYPE_FLOAT_2;
- swiz = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_ZERO, SWIZZLE_ONE);
- break;
- case 3:
- format = EMIT_3F;
- hw_format = R300_DATA_TYPE_FLOAT_3;
- swiz = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_ONE);
- break;
- case 4:
- format = EMIT_4F;
- hw_format = R300_DATA_TYPE_FLOAT_4;
- swiz = SWIZZLE_XYZW;
- break;
- default:
- continue;
- }
- InputsRead |= 1 << (VERT_ATTRIB_TEX0 + i);
- OutputsWritten |= 1 << (VERT_RESULT_TEX0 + i);
- EMIT_ATTR(_TNL_ATTRIB_TEX(i), format);
- ADD_ATTR(VERT_ATTRIB_TEX0 + i, hw_format, SWTCL_OVM_TEX(first_free_tex), swiz, MASK_XYZW, 0);
- ++first_free_tex;
- }
- }
- }
-
- if (first_free_tex >= ctx->Const.MaxTextureUnits) {
- fprintf(stderr, "\tout of free texcoords to write fog coordinate\n");
- exit(-1);
- }
-
- R300_NEWPRIM(rmesa);
- rmesa->vbuf.num_attribs = num_attrs;
- *_InputsRead = InputsRead;
- *_OutputsWritten = OutputsWritten;
-
- RENDERINPUTS_COPY(rmesa->render_inputs_bitset, tnl->render_inputs_bitset);
-}
-
-static void r300PrepareVertices(struct gl_context *ctx)
-{
- r300ContextPtr rmesa = R300_CONTEXT(ctx);
- GLuint InputsRead, OutputsWritten;
- radeon_print(RADEON_SWRENDER, RADEON_TRACE, "%s\n", __func__);
-
- r300ChooseSwtclVertexFormat(ctx, &InputsRead, &OutputsWritten);
- r300SetupVAP(ctx, InputsRead, OutputsWritten);
-
- rmesa->radeon.swtcl.vertex_size =
- _tnl_install_attrs( ctx,
- rmesa->radeon.swtcl.vertex_attrs,
- rmesa->radeon.swtcl.vertex_attr_count,
- NULL, 0 );
-
- rmesa->radeon.swtcl.vertex_size /= 4;
-}
-
-static void r300_predict_emit_size( r300ContextPtr rmesa )
-{
- if (!rmesa->radeon.swtcl.emit_prediction) {
- const int vertex_size = 7;
- const int prim_size = 3;
- const int cache_flush_size = 4;
- const int pre_emit_state = 4;
- const int scissor_size = 3;
- const int state_size = radeonCountStateEmitSize(&rmesa->radeon);
-
- if (rcommonEnsureCmdBufSpace(&rmesa->radeon,
- state_size + pre_emit_state + scissor_size
- + vertex_size + prim_size + cache_flush_size * 2,
- __FUNCTION__))
- rmesa->radeon.swtcl.emit_prediction = radeonCountStateEmitSize(&rmesa->radeon);
- else
- rmesa->radeon.swtcl.emit_prediction = state_size;
-
- rmesa->radeon.swtcl.emit_prediction += rmesa->radeon.cmdbuf.cs->cdw
- + vertex_size + scissor_size + prim_size + cache_flush_size * 2 + pre_emit_state;
- radeon_print(RADEON_SWRENDER, RADEON_VERBOSE,
- "%s, size %d\n",
- __func__, rmesa->radeon.cmdbuf.cs->cdw
- + vertex_size + scissor_size + prim_size + cache_flush_size * 2 + pre_emit_state);
- }
-}
-
-
-static GLuint reduced_prim[] = {
- GL_POINTS,
- GL_LINES,
- GL_LINES,
- GL_LINES,
- GL_TRIANGLES,
- GL_TRIANGLES,
- GL_TRIANGLES,
- GL_TRIANGLES,
- GL_TRIANGLES,
- GL_TRIANGLES,
-};
-
-static void r300RasterPrimitive( struct gl_context *ctx, GLuint prim );
-
-/***********************************************************************
- * Emit primitives as inline vertices *
- ***********************************************************************/
-
-
-#define HAVE_POINTS 1
-#define HAVE_LINES 1
-#define HAVE_LINE_STRIPS 1
-#define HAVE_TRIANGLES 1
-#define HAVE_TRI_STRIPS 1
-#define HAVE_TRI_STRIP_1 0
-#define HAVE_TRI_FANS 1
-#define HAVE_QUADS 0
-#define HAVE_QUAD_STRIPS 0
-#define HAVE_POLYGONS 1
-#define HAVE_ELTS 1
-
-static void* r300_alloc_verts(r300ContextPtr rmesa, GLuint n, GLuint size)
-{
- void *rv;
- do {
- r300_predict_emit_size( rmesa );
- rv = rcommonAllocDmaLowVerts( &rmesa->radeon, n, size * 4 );
- } while (!rv);
- return rv;
-}
-
-#undef LOCAL_VARS
-#undef ALLOC_VERTS
-#define CTX_ARG r300ContextPtr rmesa
-#define GET_VERTEX_DWORDS() rmesa->radeon.swtcl.vertex_size
-#define ALLOC_VERTS( n, size ) r300_alloc_verts(rmesa, n, size);
-#define LOCAL_VARS \
- r300ContextPtr rmesa = R300_CONTEXT(ctx); \
- const char *r300verts = (char *)rmesa->radeon.swtcl.verts;
-#define VERT(x) (r300Vertex *)(r300verts + ((x) * vertsize * sizeof(int)))
-#define VERTEX r300Vertex
-#undef TAG
-#define TAG(x) r300_##x
-#include "tnl_dd/t_dd_triemit.h"
-
-
-
-/***********************************************************************
- * Macros for t_dd_tritmp.h to draw basic primitives *
- ***********************************************************************/
-
-#define QUAD( a, b, c, d ) r300_quad( rmesa, a, b, c, d )
-#define TRI( a, b, c ) r300_triangle( rmesa, a, b, c )
-#define LINE( a, b ) r300_line( rmesa, a, b )
-#define POINT( a ) r300_point( rmesa, a )
-
-/***********************************************************************
- * Build render functions from dd templates *
- ***********************************************************************/
-
-#define R300_UNFILLED_BIT 0x01
-#define R300_MAX_TRIFUNC 0x02
-
-static struct {
- tnl_points_func points;
- tnl_line_func line;
- tnl_triangle_func triangle;
- tnl_quad_func quad;
-} rast_tab[R300_MAX_TRIFUNC];
-
-#define DO_FALLBACK 0
-#define DO_UNFILLED (IND & R300_UNFILLED_BIT)
-#define DO_TWOSIDE 0
-#define DO_FLAT 0
-#define DO_OFFSET 0
-#define DO_TRI 1
-#define DO_QUAD 1
-#define DO_LINE 1
-#define DO_POINTS 1
-#define DO_FULL_QUAD 1
-
-#define HAVE_SPEC 1
-#define HAVE_BACK_COLORS 0
-#define HAVE_HW_FLATSHADE 1
-#define TAB rast_tab
-
-#define DEPTH_SCALE 1.0
-#define UNFILLED_TRI unfilled_tri
-#define UNFILLED_QUAD unfilled_quad
-#define VERT_X(_v) _v->v.x
-#define VERT_Y(_v) _v->v.y
-#define VERT_Z(_v) _v->v.z
-#define AREA_IS_CCW( a ) (a < 0)
-#define GET_VERTEX(e) (rmesa->radeon.swtcl.verts + (e*rmesa->radeon.swtcl.vertex_size*sizeof(int)))
-
-#define VERT_SET_RGBA( v, c ) \
-do { \
- r300_color_t *color = (r300_color_t *)&((v)->ui[coloroffset]); \
- UNCLAMPED_FLOAT_TO_UBYTE(color->red, (c)[0]); \
- UNCLAMPED_FLOAT_TO_UBYTE(color->green, (c)[1]); \
- UNCLAMPED_FLOAT_TO_UBYTE(color->blue, (c)[2]); \
- UNCLAMPED_FLOAT_TO_UBYTE(color->alpha, (c)[3]); \
-} while (0)
-
-#define VERT_COPY_RGBA( v0, v1 ) v0->ui[coloroffset] = v1->ui[coloroffset]
-
-#define VERT_SET_SPEC( v0, c ) \
-do { \
- if (specoffset) { \
- UNCLAMPED_FLOAT_TO_UBYTE(v0->v.specular.red, (c)[0]); \
- UNCLAMPED_FLOAT_TO_UBYTE(v0->v.specular.green, (c)[1]); \
- UNCLAMPED_FLOAT_TO_UBYTE(v0->v.specular.blue, (c)[2]); \
- } \
-} while (0)
-
-#define VERT_COPY_SPEC( v0, v1 ) \
-do { \
- if (specoffset) { \
- v0->v.specular.red = v1->v.specular.red; \
- v0->v.specular.green = v1->v.specular.green; \
- v0->v.specular.blue = v1->v.specular.blue; \
- } \
-} while (0)
-
-#define VERT_SAVE_RGBA( idx ) color[idx] = v[idx]->ui[coloroffset]
-#define VERT_RESTORE_RGBA( idx ) v[idx]->ui[coloroffset] = color[idx]
-#define VERT_SAVE_SPEC( idx ) if (specoffset) spec[idx] = v[idx]->ui[specoffset]
-#define VERT_RESTORE_SPEC( idx ) if (specoffset) v[idx]->ui[specoffset] = spec[idx]
-
-#undef LOCAL_VARS
-#undef TAG
-#undef INIT
-
-#define LOCAL_VARS(n) \
- r300ContextPtr rmesa = R300_CONTEXT(ctx); \
- GLuint color[n] = { 0, }, spec[n] = { 0, }; \
- GLuint coloroffset = rmesa->swtcl.coloroffset; \
- GLuint specoffset = rmesa->swtcl.specoffset; \
- (void) color; (void) spec; (void) coloroffset; (void) specoffset;
-
-/***********************************************************************
- * Helpers for rendering unfilled primitives *
- ***********************************************************************/
-
-#define RASTERIZE(x) r300RasterPrimitive( ctx, reduced_prim[x] )
-#define RENDER_PRIMITIVE rmesa->radeon.swtcl.render_primitive
-#undef TAG
-#define TAG(x) x
-#include "tnl_dd/t_dd_unfilled.h"
-#undef IND
-
-
-/***********************************************************************
- * Generate GL render functions *
- ***********************************************************************/
-
-
-#define IND (0)
-#define TAG(x) x
-#include "tnl_dd/t_dd_tritmp.h"
-
-#define IND (R300_UNFILLED_BIT)
-#define TAG(x) x##_unfilled
-#include "tnl_dd/t_dd_tritmp.h"
-
-
-static void init_rast_tab( void )
-{
- init();
- init_unfilled();
-}
-
-/**********************************************************************/
-/* Render unclipped begin/end objects */
-/**********************************************************************/
-
-#define RENDER_POINTS( start, count ) \
- for ( ; start < count ; start++) \
- r300_point( rmesa, VERT(start) )
-#define RENDER_LINE( v0, v1 ) \
- r300_line( rmesa, VERT(v0), VERT(v1) )
-#define RENDER_TRI( v0, v1, v2 ) \
- r300_triangle( rmesa, VERT(v0), VERT(v1), VERT(v2) )
-#define RENDER_QUAD( v0, v1, v2, v3 ) \
- r300_quad( rmesa, VERT(v0), VERT(v1), VERT(v2), VERT(v3) )
-#define INIT(x) do { \
- r300RenderPrimitive( ctx, x ); \
-} while (0)
-#undef LOCAL_VARS
-#define LOCAL_VARS \
- r300ContextPtr rmesa = R300_CONTEXT(ctx); \
- const GLuint vertsize = rmesa->radeon.swtcl.vertex_size; \
- const char *r300verts = (char *)rmesa->radeon.swtcl.verts; \
- const GLuint * const elt = TNL_CONTEXT(ctx)->vb.Elts; \
- const GLboolean stipple = ctx->Line.StippleFlag; \
- (void) elt; (void) stipple;
-#define RESET_STIPPLE //if ( stipple ) r200ResetLineStipple( ctx );
-#define RESET_OCCLUSION
-#define PRESERVE_VB_DEFS
-#define ELT(x) (x)
-#define TAG(x) r300_##x##_verts
-#include "tnl/t_vb_rendertmp.h"
-#undef ELT
-#undef TAG
-#define TAG(x) r300_##x##_elts
-#define ELT(x) elt[x]
-#include "tnl/t_vb_rendertmp.h"
-
-
-
-
-/**********************************************************************/
-/* Choose render functions */
-/**********************************************************************/
-static void r300ChooseRenderState( struct gl_context *ctx )
-{
- TNLcontext *tnl = TNL_CONTEXT(ctx);
- r300ContextPtr rmesa = R300_CONTEXT(ctx);
- GLuint index = 0;
- GLuint flags = ctx->_TriangleCaps;
- radeon_print(RADEON_SWRENDER, RADEON_VERBOSE, "%s\n", __func__);
-
- if (flags & DD_TRI_UNFILLED) index |= R300_UNFILLED_BIT;
-
- if (index != rmesa->radeon.swtcl.RenderIndex) {
- tnl->Driver.Render.Points = rast_tab[index].points;
- tnl->Driver.Render.Line = rast_tab[index].line;
- tnl->Driver.Render.ClippedLine = rast_tab[index].line;
- tnl->Driver.Render.Triangle = rast_tab[index].triangle;
- tnl->Driver.Render.Quad = rast_tab[index].quad;
-
- if (index == 0) {
- tnl->Driver.Render.PrimTabVerts = r300_render_tab_verts;
- tnl->Driver.Render.PrimTabElts = r300_render_tab_elts;
- tnl->Driver.Render.ClippedPolygon = r300_fast_clipped_poly;
- } else {
- tnl->Driver.Render.PrimTabVerts = _tnl_render_tab_verts;
- tnl->Driver.Render.PrimTabElts = _tnl_render_tab_elts;
- tnl->Driver.Render.ClippedPolygon = _tnl_RenderClippedPolygon;
- }
-
- rmesa->radeon.swtcl.RenderIndex = index;
- }
-}
-
-void r300RenderStart(struct gl_context *ctx)
-{
- radeon_print(RADEON_SWRENDER, RADEON_VERBOSE, "%s\n", __func__);
- r300ContextPtr rmesa = R300_CONTEXT( ctx );
-
- r300ChooseRenderState(ctx);
-
- r300UpdateShaders(rmesa);
-
- r300PrepareVertices(ctx);
-
- r300ValidateBuffers(ctx);
-
- r300UpdateShaderStates(rmesa);
-
-
- /* investigate if we can put back flush optimisation if needed */
- if (rmesa->radeon.dma.flush != NULL) {
- rmesa->radeon.dma.flush(ctx);
- }
-}
-
-void r300RenderFinish(struct gl_context *ctx)
-{
-}
-
-static void r300RasterPrimitive( struct gl_context *ctx, GLuint hwprim )
-{
- r300ContextPtr rmesa = R300_CONTEXT(ctx);
- radeon_print(RADEON_SWRENDER, RADEON_TRACE, "%s\n", __func__);
-
- if (rmesa->radeon.swtcl.hw_primitive != hwprim) {
- R300_NEWPRIM( rmesa );
- rmesa->radeon.swtcl.hw_primitive = hwprim;
- }
-}
-
-void r300RenderPrimitive(struct gl_context *ctx, GLenum prim)
-{
-
- r300ContextPtr rmesa = R300_CONTEXT(ctx);
- rmesa->radeon.swtcl.render_primitive = prim;
- radeon_print(RADEON_SWRENDER, RADEON_TRACE, "%s\n", __func__);
-
- if ((prim == GL_TRIANGLES) && (ctx->_TriangleCaps & DD_TRI_UNFILLED))
- return;
-
- r300RasterPrimitive( ctx, reduced_prim[prim] );
-}
-
-void r300ResetLineStipple(struct gl_context *ctx)
-{
- if (RADEON_DEBUG & RADEON_VERTS)
- fprintf(stderr, "%s\n", __func__);
-}
-
-void r300InitSwtcl(struct gl_context *ctx)
-{
- TNLcontext *tnl = TNL_CONTEXT(ctx);
- r300ContextPtr rmesa = R300_CONTEXT(ctx);
- static int firsttime = 1;
- radeon_print(RADEON_SWRENDER, RADEON_NORMAL, "%s\n", __func__);
-
- if (firsttime) {
- init_rast_tab();
- firsttime = 0;
- }
- rmesa->radeon.swtcl.emit_prediction = 0;
-
- tnl->Driver.Render.Start = r300RenderStart;
- tnl->Driver.Render.Finish = r300RenderFinish;
- tnl->Driver.Render.PrimitiveNotify = r300RenderPrimitive;
- tnl->Driver.Render.ResetLineStipple = r300ResetLineStipple;
- tnl->Driver.Render.BuildVertices = _tnl_build_vertices;
- tnl->Driver.Render.CopyPV = _tnl_copy_pv;
- tnl->Driver.Render.Interp = _tnl_interp;
-
- /* FIXME: what are these numbers? */
- _tnl_init_vertices( ctx, ctx->Const.MaxArrayLockSize + 12,
- 48 * sizeof(GLfloat) );
-
- rmesa->radeon.swtcl.verts = (GLubyte *)tnl->clipspace.vertex_buf;
- rmesa->radeon.swtcl.RenderIndex = ~0;
- rmesa->radeon.swtcl.render_primitive = GL_TRIANGLES;
- rmesa->radeon.swtcl.hw_primitive = 0;
-
- _tnl_invalidate_vertex_state( ctx, ~0 );
- _tnl_invalidate_vertices( ctx, ~0 );
-
- _tnl_need_projected_coords( ctx, GL_FALSE );
-}
-
-void r300DestroySwtcl(struct gl_context *ctx)
-{
-}
-
-static void r300EmitVertexAOS(r300ContextPtr rmesa, GLuint vertex_size, struct radeon_bo *bo, GLuint offset)
-{
- BATCH_LOCALS(&rmesa->radeon);
-
- radeon_print(RADEON_SWRENDER, RADEON_TRACE,
- "%s: vertex_size %d, offset 0x%x \n",
- __FUNCTION__, vertex_size, offset);
-
- BEGIN_BATCH(7);
- OUT_BATCH_PACKET3(R300_PACKET3_3D_LOAD_VBPNTR, 2);
- OUT_BATCH(1);
- OUT_BATCH(vertex_size | (vertex_size << 8));
- OUT_BATCH_RELOC(offset, bo, offset, RADEON_GEM_DOMAIN_GTT, 0, 0);
- END_BATCH();
-}
-
-static void r300EmitVbufPrim(r300ContextPtr rmesa, GLuint primitive, GLuint vertex_nr)
-{
- BATCH_LOCALS(&rmesa->radeon);
- int type, num_verts;
- if (RADEON_DEBUG & RADEON_VERTS)
- fprintf(stderr, "%s\n", __func__);
-
- type = r300PrimitiveType(rmesa, primitive);
- num_verts = r300NumVerts(rmesa, vertex_nr, primitive);
-
- BEGIN_BATCH(3);
- OUT_BATCH_PACKET3(R300_PACKET3_3D_DRAW_VBUF_2, 0);
- OUT_BATCH(R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_LIST | (num_verts << 16) | type);
- END_BATCH();
-}
-
-void r300_swtcl_flush(struct gl_context *ctx, uint32_t current_offset)
-{
- radeon_print(RADEON_SWRENDER, RADEON_TRACE, "%s\n", __func__);
- r300ContextPtr rmesa = R300_CONTEXT(ctx);
-
- r300EmitCacheFlush(rmesa);
-
- radeonEmitState(&rmesa->radeon);
- r300_emit_scissor(ctx);
- r300EmitVertexAOS(rmesa,
- rmesa->radeon.swtcl.vertex_size,
- rmesa->radeon.swtcl.bo,
- current_offset);
-
- r300EmitVbufPrim(rmesa,
- rmesa->radeon.swtcl.hw_primitive,
- rmesa->radeon.swtcl.numverts);
- r300EmitCacheFlush(rmesa);
- if ( rmesa->radeon.swtcl.emit_prediction < rmesa->radeon.cmdbuf.cs->cdw )
- WARN_ONCE("Rendering was %d commands larger than predicted size."
- " We might overflow command buffer.\n",
- rmesa->radeon.cmdbuf.cs->cdw - rmesa->radeon.swtcl.emit_prediction );
- rmesa->radeon.swtcl.emit_prediction = 0;
- COMMIT_BATCH();
-}
+++ /dev/null
-/*
-Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
-
-The Weather Channel (TM) funded Tungsten Graphics to develop the
-initial release of the Radeon 8500 driver under the XFree86 license.
-This notice must be preserved.
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-*/
-
-/*
- * Authors:
- * Keith Whitwell <keith@tungstengraphics.com> - original r200 code
- * Dave Airlie <airlied@linux.ie>
- */
-
-#ifndef __R300_SWTCL_H__
-#define __R300_SWTCL_H__
-
-#include "main/mtypes.h"
-#include "swrast/swrast.h"
-#include "r300_context.h"
-
-/*
- * Here are definitions of OVM locations of vertex attributes for non TCL hw
- */
-#define SWTCL_OVM_POS 0
-#define SWTCL_OVM_COLOR0 2
-#define SWTCL_OVM_COLOR1 3
-#define SWTCL_OVM_COLOR2 4
-#define SWTCL_OVM_COLOR3 5
-#define SWTCL_OVM_TEX(n) ((n) + 6)
-#define SWTCL_OVM_POINT_SIZE 15
-
-extern void r300ChooseSwtclVertexFormat(struct gl_context *ctx, GLuint *InputsRead, GLuint *OutputsWritten);
-
-extern void r300InitSwtcl( struct gl_context *ctx );
-extern void r300DestroySwtcl( struct gl_context *ctx );
-
-extern void r300RenderStart(struct gl_context *ctx);
-extern void r300RenderFinish(struct gl_context *ctx);
-extern void r300RenderPrimitive(struct gl_context *ctx, GLenum prim);
-extern void r300ResetLineStipple(struct gl_context *ctx);
-
-extern void r300_swtcl_flush(struct gl_context *ctx, uint32_t current_offset);
-
-#endif
+++ /dev/null
-/*
-Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
-
-The Weather Channel (TM) funded Tungsten Graphics to develop the
-initial release of the Radeon 8500 driver under the XFree86 license.
-This notice must be preserved.
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-*/
-
-/**
- * \file
- *
- * \author Keith Whitwell <keith@tungstengraphics.com>
- */
-
-#include "main/glheader.h"
-#include "main/imports.h"
-#include "main/colormac.h"
-#include "main/context.h"
-#include "main/enums.h"
-#include "main/image.h"
-#include "main/mfeatures.h"
-#include "main/mipmap.h"
-#include "main/simple_list.h"
-#include "main/texobj.h"
-
-#include "texmem.h"
-
-#include "r300_context.h"
-#include "radeon_mipmap_tree.h"
-#include "r300_tex.h"
-
-
-static unsigned int translate_wrap_mode(GLenum wrapmode)
-{
- switch(wrapmode) {
- case GL_REPEAT: return R300_TX_REPEAT;
- case GL_CLAMP: return R300_TX_CLAMP;
- case GL_CLAMP_TO_EDGE: return R300_TX_CLAMP_TO_EDGE;
- case GL_CLAMP_TO_BORDER: return R300_TX_CLAMP_TO_BORDER;
- case GL_MIRRORED_REPEAT: return R300_TX_REPEAT | R300_TX_MIRRORED;
- case GL_MIRROR_CLAMP_EXT: return R300_TX_CLAMP | R300_TX_MIRRORED;
- case GL_MIRROR_CLAMP_TO_EDGE_EXT: return R300_TX_CLAMP_TO_EDGE | R300_TX_MIRRORED;
- case GL_MIRROR_CLAMP_TO_BORDER_EXT: return R300_TX_CLAMP_TO_BORDER | R300_TX_MIRRORED;
- default:
- _mesa_problem(NULL, "bad wrap mode in %s", __FUNCTION__);
- return 0;
- }
-}
-
-
-/**
- * Update the cached hardware registers based on the current texture wrap modes.
- *
- * \param t Texture object whose wrap modes are to be set
- */
-static void r300UpdateTexWrap(radeonTexObjPtr t)
-{
- struct gl_texture_object *tObj = &t->base;
-
- t->pp_txfilter &=
- ~(R300_TX_WRAP_S_MASK | R300_TX_WRAP_T_MASK | R300_TX_WRAP_R_MASK);
-
- t->pp_txfilter |= translate_wrap_mode(tObj->Sampler.WrapS) << R300_TX_WRAP_S_SHIFT;
-
- if (tObj->Target != GL_TEXTURE_1D) {
- t->pp_txfilter |= translate_wrap_mode(tObj->Sampler.WrapT) << R300_TX_WRAP_T_SHIFT;
-
- if (tObj->Target == GL_TEXTURE_3D)
- t->pp_txfilter |= translate_wrap_mode(tObj->Sampler.WrapR) << R300_TX_WRAP_R_SHIFT;
- }
-}
-
-static GLuint aniso_filter(GLfloat anisotropy)
-{
- if (anisotropy >= 16.0) {
- return R300_TX_MAX_ANISO_16_TO_1;
- } else if (anisotropy >= 8.0) {
- return R300_TX_MAX_ANISO_8_TO_1;
- } else if (anisotropy >= 4.0) {
- return R300_TX_MAX_ANISO_4_TO_1;
- } else if (anisotropy >= 2.0) {
- return R300_TX_MAX_ANISO_2_TO_1;
- } else {
- return R300_TX_MAX_ANISO_1_TO_1;
- }
-}
-
-/**
- * Set the texture magnification and minification modes.
- *
- * \param t Texture whose filter modes are to be set
- * \param minf Texture minification mode
- * \param magf Texture magnification mode
- * \param anisotropy Maximum anisotropy level
- */
-static void r300SetTexFilter(radeonTexObjPtr t, GLenum minf, GLenum magf, GLfloat anisotropy)
-{
- /* Force revalidation to account for switches from/to mipmapping. */
- t->validated = GL_FALSE;
-
- t->pp_txfilter &= ~(R300_TX_MIN_FILTER_MASK | R300_TX_MIN_FILTER_MIP_MASK | R300_TX_MAG_FILTER_MASK | R300_TX_MAX_ANISO_MASK);
- t->pp_txfilter_1 &= ~R300_EDGE_ANISO_EDGE_ONLY;
-
- /* Note that EXT_texture_filter_anisotropic is extremely vague about
- * how anisotropic filtering interacts with the "normal" filter modes.
- * When anisotropic filtering is enabled, we override min and mag
- * filter settings completely. This includes driconf's settings.
- */
- if (anisotropy >= 2.0 && (minf != GL_NEAREST) && (magf != GL_NEAREST)) {
- t->pp_txfilter |= R300_TX_MAG_FILTER_ANISO
- | R300_TX_MIN_FILTER_ANISO
- | R300_TX_MIN_FILTER_MIP_LINEAR
- | aniso_filter(anisotropy);
- if (RADEON_DEBUG & RADEON_TEXTURE)
- fprintf(stderr, "Using maximum anisotropy of %f\n", anisotropy);
- return;
- }
-
- switch (minf) {
- case GL_NEAREST:
- t->pp_txfilter |= R300_TX_MIN_FILTER_NEAREST;
- break;
- case GL_LINEAR:
- t->pp_txfilter |= R300_TX_MIN_FILTER_LINEAR;
- break;
- case GL_NEAREST_MIPMAP_NEAREST:
- t->pp_txfilter |= R300_TX_MIN_FILTER_NEAREST|R300_TX_MIN_FILTER_MIP_NEAREST;
- break;
- case GL_NEAREST_MIPMAP_LINEAR:
- t->pp_txfilter |= R300_TX_MIN_FILTER_NEAREST|R300_TX_MIN_FILTER_MIP_LINEAR;
- break;
- case GL_LINEAR_MIPMAP_NEAREST:
- t->pp_txfilter |= R300_TX_MIN_FILTER_LINEAR|R300_TX_MIN_FILTER_MIP_NEAREST;
- break;
- case GL_LINEAR_MIPMAP_LINEAR:
- t->pp_txfilter |= R300_TX_MIN_FILTER_LINEAR|R300_TX_MIN_FILTER_MIP_LINEAR;
- break;
- }
-
- /* Note we don't have 3D mipmaps so only use the mag filter setting
- * to set the 3D texture filter mode.
- */
- switch (magf) {
- case GL_NEAREST:
- t->pp_txfilter |= R300_TX_MAG_FILTER_NEAREST;
- break;
- case GL_LINEAR:
- t->pp_txfilter |= R300_TX_MAG_FILTER_LINEAR;
- break;
- }
-}
-
-static void r300SetTexBorderColor(radeonTexObjPtr t, const GLfloat color[4])
-{
- GLubyte c[4];
- CLAMPED_FLOAT_TO_UBYTE(c[0], color[0]);
- CLAMPED_FLOAT_TO_UBYTE(c[1], color[1]);
- CLAMPED_FLOAT_TO_UBYTE(c[2], color[2]);
- CLAMPED_FLOAT_TO_UBYTE(c[3], color[3]);
- t->pp_border_color = PACK_COLOR_8888(c[3], c[0], c[1], c[2]);
-}
-
-/**
- * Changes variables and flags for a state update, which will happen at the
- * next UpdateTextureState
- */
-
-static void r300TexParameter(struct gl_context * ctx, GLenum target,
- struct gl_texture_object *texObj,
- GLenum pname, const GLfloat * params)
-{
- radeonTexObj* t = radeon_tex_obj(texObj);
- GLenum texBaseFormat;
-
- if (RADEON_DEBUG & (RADEON_STATE | RADEON_TEXTURE)) {
- fprintf(stderr, "%s( %s )\n", __FUNCTION__,
- _mesa_lookup_enum_by_nr(pname));
- }
-
- switch (pname) {
- case GL_TEXTURE_MIN_FILTER:
- case GL_TEXTURE_MAG_FILTER:
- case GL_TEXTURE_MAX_ANISOTROPY_EXT:
- r300SetTexFilter(t, texObj->Sampler.MinFilter, texObj->Sampler.MagFilter, texObj->Sampler.MaxAnisotropy);
- break;
-
- case GL_TEXTURE_WRAP_S:
- case GL_TEXTURE_WRAP_T:
- case GL_TEXTURE_WRAP_R:
- r300UpdateTexWrap(t);
- break;
-
- case GL_TEXTURE_BORDER_COLOR:
- r300SetTexBorderColor(t, texObj->Sampler.BorderColor.f);
- break;
-
- case GL_TEXTURE_BASE_LEVEL:
- case GL_TEXTURE_MAX_LEVEL:
- case GL_TEXTURE_MIN_LOD:
- case GL_TEXTURE_MAX_LOD:
- t->validated = GL_FALSE;
- break;
-
- case GL_DEPTH_TEXTURE_MODE:
- if (!texObj->Image[0][texObj->BaseLevel])
- return;
- texBaseFormat = texObj->Image[0][texObj->BaseLevel]->_BaseFormat;
-
- if (texBaseFormat == GL_DEPTH_COMPONENT ||
- texBaseFormat == GL_DEPTH_STENCIL) {
- r300SetDepthTexMode(texObj);
- break;
- } else {
- /* If the texture isn't a depth texture, changing this
- * state won't cause any changes to the hardware.
- * Don't force a flush of texture state.
- */
- return;
- }
-
- default:
- return;
- }
-}
-
-static void r300DeleteTexture(struct gl_context * ctx, struct gl_texture_object *texObj)
-{
- r300ContextPtr rmesa = R300_CONTEXT(ctx);
- radeonTexObj* t = radeon_tex_obj(texObj);
-
- if (RADEON_DEBUG & (RADEON_STATE | RADEON_TEXTURE)) {
- fprintf(stderr, "%s( %p (target = %s) )\n", __FUNCTION__,
- (void *)texObj,
- _mesa_lookup_enum_by_nr(texObj->Target));
- }
-
- if (rmesa) {
- int i;
- struct radeon_bo *bo;
- bo = !t->mt ? t->bo : t->mt->bo;
- if (bo && radeon_bo_is_referenced_by_cs(bo, rmesa->radeon.cmdbuf.cs)) {
- radeon_firevertices(&rmesa->radeon);
- }
-
- for(i = 0; i < R300_MAX_TEXTURE_UNITS; ++i)
- if (rmesa->hw.textures[i] == t)
- rmesa->hw.textures[i] = 0;
- }
-
- if (t->bo) {
- radeon_bo_unref(t->bo);
- t->bo = NULL;
- }
-
- radeon_miptree_unreference(&t->mt);
-
- _mesa_delete_texture_object(ctx, texObj);
-}
-
-/**
- * Allocate a new texture object.
- * Called via ctx->Driver.NewTextureObject.
- * Note: this function will be called during context creation to
- * allocate the default texture objects.
- * Fixup MaxAnisotropy according to user preference.
- */
-static struct gl_texture_object *r300NewTextureObject(struct gl_context * ctx,
- GLuint name,
- GLenum target)
-{
- r300ContextPtr rmesa = R300_CONTEXT(ctx);
- radeonTexObj* t = CALLOC_STRUCT(radeon_tex_obj);
-
-
- if (RADEON_DEBUG & (RADEON_STATE | RADEON_TEXTURE)) {
- fprintf(stderr, "%s( %p (target = %s) )\n", __FUNCTION__,
- t, _mesa_lookup_enum_by_nr(target));
- }
-
- _mesa_initialize_texture_object(&t->base, name, target);
- t->base.Sampler.MaxAnisotropy = rmesa->radeon.initialMaxAnisotropy;
-
- /* Initialize hardware state */
- r300UpdateTexWrap(t);
- r300SetTexFilter(t, t->base.Sampler.MinFilter,
- t->base.Sampler.MagFilter,
- t->base.Sampler.MaxAnisotropy);
- r300SetTexBorderColor(t, t->base.Sampler.BorderColor.f);
-
- return &t->base;
-}
-
-unsigned r300IsFormatRenderable(gl_format mesa_format)
-{
- switch (mesa_format)
- {
- case MESA_FORMAT_RGB565:
- case MESA_FORMAT_RGBA5551:
- case MESA_FORMAT_RGBA8888:
- case MESA_FORMAT_RGB565_REV:
- case MESA_FORMAT_RGBA8888_REV:
- case MESA_FORMAT_ARGB4444:
- case MESA_FORMAT_ARGB1555:
- case MESA_FORMAT_XRGB8888:
- case MESA_FORMAT_ARGB8888:
- case MESA_FORMAT_ARGB4444_REV:
- case MESA_FORMAT_ARGB1555_REV:
- case MESA_FORMAT_XRGB8888_REV:
- case MESA_FORMAT_ARGB8888_REV:
- case MESA_FORMAT_SRGBA8:
- case MESA_FORMAT_SARGB8:
- case MESA_FORMAT_SL8:
- case MESA_FORMAT_A8:
- case MESA_FORMAT_L8:
- case MESA_FORMAT_I8:
- case MESA_FORMAT_Z16:
- return 1;
- default:
- return 0;
- }
-}
-
-unsigned r500IsFormatRenderable(gl_format mesa_format)
-{
- if (mesa_format == MESA_FORMAT_S8_Z24) {
- return 1;
- } else {
- return r300IsFormatRenderable(mesa_format);
- }
-}
-
-void r300InitTextureFuncs(radeonContextPtr radeon, struct dd_function_table *functions)
-{
- /* Note: we only plug in the functions we implement in the driver
- * since _mesa_init_driver_functions() was already called.
- */
-
- radeon_init_common_texture_funcs(radeon, functions);
-
- functions->NewTextureObject = r300NewTextureObject;
- functions->DeleteTexture = r300DeleteTexture;
- functions->IsTextureResident = driIsTextureResident;
-
- functions->TexParameter = r300TexParameter;
-
-#if FEATURE_OES_EGL_image
- functions->EGLImageTargetTexture2D = radeon_image_target_texture_2d;
-#endif
-}
+++ /dev/null
-/*
-Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
-
-The Weather Channel (TM) funded Tungsten Graphics to develop the
-initial release of the Radeon 8500 driver under the XFree86 license.
-This notice must be preserved.
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-**************************************************************************/
-
-/*
- * Authors:
- * Keith Whitwell <keith@tungstengraphics.com>
- */
-
-#ifndef __r300_TEX_H__
-#define __r300_TEX_H__
-
-extern void r300SetDepthTexMode(struct gl_texture_object *tObj);
-
-extern void r300SetTexBuffer(__DRIcontext *pDRICtx, GLint target,
- __DRIdrawable *dPriv);
-
-extern void r300SetTexBuffer2(__DRIcontext *pDRICtx, GLint target,
- GLint format, __DRIdrawable *dPriv);
-
-extern void r300SetTexOffset(__DRIcontext *pDRICtx, GLint texname,
- unsigned long long offset, GLint depth,
- GLuint pitch);
-
-extern GLboolean r300ValidateBuffers(struct gl_context * ctx);
-
-extern void r300InitTextureFuncs(radeonContextPtr radeon, struct dd_function_table *functions);
-
-int32_t r300TranslateTexFormat(gl_format mesaFormat);
-
-unsigned r300IsFormatRenderable(gl_format mesaFormat);
-unsigned r500IsFormatRenderable(gl_format mesaFormat);
-
-#endif /* __r300_TEX_H__ */
+++ /dev/null
-/*
-Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
-
-The Weather Channel (TM) funded Tungsten Graphics to develop the
-initial release of the Radeon 8500 driver under the XFree86 license.
-This notice must be preserved.
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-**************************************************************************/
-
-/**
- * \file
- *
- * \author Keith Whitwell <keith@tungstengraphics.com>
- *
- * \todo Enable R300 texture tiling code?
- */
-
-#include "main/glheader.h"
-#include "main/imports.h"
-#include "main/context.h"
-#include "main/macros.h"
-#include "main/teximage.h"
-#include "main/texobj.h"
-#include "main/enums.h"
-#include "main/simple_list.h"
-
-#include "r300_context.h"
-#include "radeon_mipmap_tree.h"
-#include "r300_tex.h"
-#include "r300_reg.h"
-
-/*
- * Note that the _REV formats are the same as the non-REV formats. This is
- * because the REV and non-REV formats are identical as a byte string, but
- * differ when accessed as 16-bit or 32-bit words depending on the endianness of
- * the host. Since the textures are transferred to the R300 as a byte string
- * (i.e. without any byte-swapping), the R300 sees the REV and non-REV formats
- * identically. -- paulus
- */
-
-int32_t r300TranslateTexFormat(gl_format mesaFormat)
-{
- switch (mesaFormat)
- {
-#ifdef MESA_LITTLE_ENDIAN
- case MESA_FORMAT_RGBA8888:
- return R300_EASY_TX_FORMAT(Y, Z, W, X, W8Z8Y8X8);
- case MESA_FORMAT_RGBA8888_REV:
- return R300_EASY_TX_FORMAT(Z, Y, X, W, W8Z8Y8X8);
- case MESA_FORMAT_ARGB8888:
- return R300_EASY_TX_FORMAT(X, Y, Z, W, W8Z8Y8X8);
- case MESA_FORMAT_ARGB8888_REV:
- return R300_EASY_TX_FORMAT(W, Z, Y, X, W8Z8Y8X8);
-#else
- case MESA_FORMAT_RGBA8888:
- return R300_EASY_TX_FORMAT(Z, Y, X, W, W8Z8Y8X8);
- case MESA_FORMAT_RGBA8888_REV:
- return R300_EASY_TX_FORMAT(Y, Z, W, X, W8Z8Y8X8);
- case MESA_FORMAT_ARGB8888:
- return R300_EASY_TX_FORMAT(W, Z, Y, X, W8Z8Y8X8);
- case MESA_FORMAT_ARGB8888_REV:
- return R300_EASY_TX_FORMAT(X, Y, Z, W, W8Z8Y8X8);
-#endif
- case MESA_FORMAT_XRGB8888:
- return R300_EASY_TX_FORMAT(X, Y, Z, ONE, W8Z8Y8X8);
- case MESA_FORMAT_RGB888:
- return R300_EASY_TX_FORMAT(X, Y, Z, ONE, W8Z8Y8X8);
- case MESA_FORMAT_RGB565:
- return R300_EASY_TX_FORMAT(X, Y, Z, ONE, Z5Y6X5);
- case MESA_FORMAT_RGB565_REV:
- return R300_EASY_TX_FORMAT(X, Y, Z, ONE, Z5Y6X5);
- case MESA_FORMAT_ARGB4444:
- return R300_EASY_TX_FORMAT(X, Y, Z, W, W4Z4Y4X4);
- case MESA_FORMAT_ARGB4444_REV:
- return R300_EASY_TX_FORMAT(X, Y, Z, W, W4Z4Y4X4);
- case MESA_FORMAT_ARGB1555:
- return R300_EASY_TX_FORMAT(X, Y, Z, W, W1Z5Y5X5);
- case MESA_FORMAT_ARGB1555_REV:
- return R300_EASY_TX_FORMAT(X, Y, Z, W, W1Z5Y5X5);
- case MESA_FORMAT_AL88:
- return R300_EASY_TX_FORMAT(X, X, X, Y, Y8X8);
- case MESA_FORMAT_AL88_REV:
- return R300_EASY_TX_FORMAT(X, X, X, Y, Y8X8);
- case MESA_FORMAT_RGB332:
- return R300_EASY_TX_FORMAT(X, Y, Z, ONE, Z3Y3X2);
- case MESA_FORMAT_A8:
- return R300_EASY_TX_FORMAT(ZERO, ZERO, ZERO, X, X8);
- case MESA_FORMAT_L8:
- return R300_EASY_TX_FORMAT(X, X, X, ONE, X8);
- case MESA_FORMAT_I8:
- return R300_EASY_TX_FORMAT(X, X, X, X, X8);
- case MESA_FORMAT_YCBCR:
- return R300_EASY_TX_FORMAT(X, Y, Z, ONE, G8R8_G8B8) | R300_TX_FORMAT_YUV_MODE;
- case MESA_FORMAT_YCBCR_REV:
- return R300_EASY_TX_FORMAT(X, Y, Z, ONE, G8R8_G8B8) | R300_TX_FORMAT_YUV_MODE;
- case MESA_FORMAT_RGB_DXT1:
- return R300_EASY_TX_FORMAT(X, Y, Z, ONE, DXT1);
- case MESA_FORMAT_RGBA_DXT1:
- return R300_EASY_TX_FORMAT(X, Y, Z, W, DXT1);
- case MESA_FORMAT_RGBA_DXT3:
- return R300_EASY_TX_FORMAT(X, Y, Z, W, DXT3);
- case MESA_FORMAT_RGBA_DXT5:
- return R300_EASY_TX_FORMAT(Y, Z, W, X, DXT5);
- case MESA_FORMAT_RGBA_FLOAT32:
- return R300_EASY_TX_FORMAT(Z, Y, X, W, FL_R32G32B32A32);
- case MESA_FORMAT_RGBA_FLOAT16:
- return R300_EASY_TX_FORMAT(Z, Y, X, W, FL_R16G16B16A16);
- case MESA_FORMAT_ALPHA_FLOAT32:
- return R300_EASY_TX_FORMAT(ZERO, ZERO, ZERO, X, FL_I32);
- case MESA_FORMAT_ALPHA_FLOAT16:
- return R300_EASY_TX_FORMAT(ZERO, ZERO, ZERO, X, FL_I16);
- case MESA_FORMAT_LUMINANCE_FLOAT32:
- return R300_EASY_TX_FORMAT(X, X, X, ONE, FL_I32);
- case MESA_FORMAT_LUMINANCE_FLOAT16:
- return R300_EASY_TX_FORMAT(X, X, X, ONE, FL_I16);
- case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32:
- return R300_EASY_TX_FORMAT(X, X, X, Y, FL_I32A32);
- case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16:
- return R300_EASY_TX_FORMAT(X, X, X, Y, FL_I16A16);
- case MESA_FORMAT_INTENSITY_FLOAT32:
- return R300_EASY_TX_FORMAT(X, X, X, X, FL_I32);
- case MESA_FORMAT_INTENSITY_FLOAT16:
- return R300_EASY_TX_FORMAT(X, X, X, X, FL_I16);
- case MESA_FORMAT_Z16:
- return R300_EASY_TX_FORMAT(X, X, X, X, X16);
- case MESA_FORMAT_Z24_S8:
- return R300_EASY_TX_FORMAT(X, X, X, X, X24_Y8);
- case MESA_FORMAT_S8_Z24:
- return R300_EASY_TX_FORMAT(Y, Y, Y, Y, X24_Y8);
- case MESA_FORMAT_Z32:
- return R300_EASY_TX_FORMAT(X, X, X, X, X32);
- /* EXT_texture_sRGB */
- case MESA_FORMAT_SARGB8:
- return R300_EASY_TX_FORMAT(X, Y, Z, W, W8Z8Y8X8) | R300_TX_FORMAT_GAMMA;
- case MESA_FORMAT_SLA8:
- return R300_EASY_TX_FORMAT(X, X, X, Y, Y8X8) | R300_TX_FORMAT_GAMMA;
- case MESA_FORMAT_SL8:
- return R300_EASY_TX_FORMAT(X, X, X, ONE, X8) | R300_TX_FORMAT_GAMMA;
- case MESA_FORMAT_SRGB_DXT1:
- return R300_EASY_TX_FORMAT(X, Y, Z, ONE, DXT1) | R300_TX_FORMAT_GAMMA;
- case MESA_FORMAT_SRGBA_DXT1:
- return R300_EASY_TX_FORMAT(X, Y, Z, W, DXT1) | R300_TX_FORMAT_GAMMA;
- case MESA_FORMAT_SRGBA_DXT3:
- return R300_EASY_TX_FORMAT(X, Y, Z, W, DXT3) | R300_TX_FORMAT_GAMMA;
- case MESA_FORMAT_SRGBA_DXT5:
- return R300_EASY_TX_FORMAT(Y, Z, W, X, DXT5) | R300_TX_FORMAT_GAMMA;
- default:
- return -1;
- }
-};
-
-void r300SetDepthTexMode(struct gl_texture_object *tObj)
-{
- static const GLuint formats[3][3] = {
- {
- R300_EASY_TX_FORMAT(X, X, X, ONE, X16),
- R300_EASY_TX_FORMAT(X, X, X, X, X16),
- R300_EASY_TX_FORMAT(ZERO, ZERO, ZERO, X, X16),
- },
- {
- R300_EASY_TX_FORMAT(Y, Y, Y, ONE, X24_Y8),
- R300_EASY_TX_FORMAT(Y, Y, Y, Y, X24_Y8),
- R300_EASY_TX_FORMAT(ZERO, ZERO, ZERO, Y, X24_Y8),
- },
- {
- R300_EASY_TX_FORMAT(X, X, X, ONE, X32),
- R300_EASY_TX_FORMAT(X, X, X, X, X32),
- R300_EASY_TX_FORMAT(ZERO, ZERO, ZERO, X, X32),
- },
- };
- const GLuint *format;
- radeonTexObjPtr t;
-
- if (!tObj)
- return;
-
- t = radeon_tex_obj(tObj);
-
- switch (tObj->Image[0][tObj->BaseLevel]->TexFormat) {
- case MESA_FORMAT_Z16:
- format = formats[0];
- break;
- case MESA_FORMAT_S8_Z24:
- format = formats[1];
- break;
- case MESA_FORMAT_Z32:
- format = formats[2];
- break;
- default:
- /* Error...which should have already been caught by higher
- * levels of Mesa.
- */
- ASSERT(0);
- return;
- }
-
- switch (tObj->Sampler.DepthMode) {
- case GL_LUMINANCE:
- t->pp_txformat = format[0];
- break;
- case GL_INTENSITY:
- t->pp_txformat = format[1];
- break;
- case GL_ALPHA:
- t->pp_txformat = format[2];
- break;
- default:
- /* Error...which should have already been caught by higher
- * levels of Mesa.
- */
- ASSERT(0);
- return;
- }
-}
-
-
-/**
- * Compute the cached hardware register values for the given texture object.
- *
- * \param rmesa Context pointer
- * \param t the r300 texture object
- */
-static void setup_hardware_state(r300ContextPtr rmesa, radeonTexObj *t)
-{
- const struct gl_texture_image *firstImage;
- firstImage = t->base.Image[0][t->minLod];
-
- if (!t->image_override) {
- if (firstImage->_BaseFormat == GL_DEPTH_COMPONENT) {
- r300SetDepthTexMode(&t->base);
- } else {
- int32_t txformat = r300TranslateTexFormat(firstImage->TexFormat);
- if (txformat < 0) {
- _mesa_problem(rmesa->radeon.glCtx, "%s: Invalid format %s",
- __FUNCTION__, _mesa_get_format_name(firstImage->TexFormat));
- exit(1);
- }
- t->pp_txformat = (uint32_t) txformat;
- }
- }
-
- if (t->image_override && t->bo)
- return;
-
- t->pp_txsize = (((R300_TX_WIDTHMASK_MASK & ((firstImage->Width - 1) << R300_TX_WIDTHMASK_SHIFT)))
- | ((R300_TX_HEIGHTMASK_MASK & ((firstImage->Height - 1) << R300_TX_HEIGHTMASK_SHIFT)))
- | ((R300_TX_DEPTHMASK_MASK & ((firstImage->DepthLog2) << R300_TX_DEPTHMASK_SHIFT)))
- | ((R300_TX_MAX_MIP_LEVEL_MASK & ((t->maxLod - t->minLod) << R300_TX_MAX_MIP_LEVEL_SHIFT))));
-
- t->tile_bits = 0;
-
- if (t->base.Target == GL_TEXTURE_CUBE_MAP)
- t->pp_txformat |= R300_TX_FORMAT_CUBIC_MAP;
- if (t->base.Target == GL_TEXTURE_3D)
- t->pp_txformat |= R300_TX_FORMAT_3D;
-
-
- if (t->base.Target == GL_TEXTURE_RECTANGLE_NV) {
- unsigned int align = (64 / _mesa_get_format_bytes(firstImage->TexFormat)) - 1;
- t->pp_txsize |= R300_TX_SIZE_TXPITCH_EN;
- if (!t->image_override)
- t->pp_txpitch = ((firstImage->Width + align) & ~align) - 1;
- }
-
- if (rmesa->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) {
- if (firstImage->Width > 2048)
- t->pp_txpitch |= R500_TXWIDTH_BIT11;
- else
- t->pp_txpitch &= ~R500_TXWIDTH_BIT11;
- if (firstImage->Height > 2048)
- t->pp_txpitch |= R500_TXHEIGHT_BIT11;
- else
- t->pp_txpitch &= ~R500_TXHEIGHT_BIT11;
- }
-}
-
-/**
- * Ensure the given texture is ready for rendering.
- *
- * Mostly this means populating the texture object's mipmap tree.
- */
-static GLboolean r300_validate_texture(struct gl_context * ctx, struct gl_texture_object *texObj)
-{
- r300ContextPtr rmesa = R300_CONTEXT(ctx);
- radeonTexObj *t = radeon_tex_obj(texObj);
-
- if (!radeon_validate_texture_miptree(ctx, texObj))
- return GL_FALSE;
-
- /* Configure the hardware registers (more precisely, the cached version
- * of the hardware registers). */
- setup_hardware_state(rmesa, t);
-
- t->validated = GL_TRUE;
- return GL_TRUE;
-}
-
-/**
- * Ensure all enabled and complete textures are uploaded along with any buffers being used.
- */
-GLboolean r300ValidateBuffers(struct gl_context * ctx)
-{
- r300ContextPtr rmesa = R300_CONTEXT(ctx);
- struct radeon_renderbuffer *rrb;
- int i;
- int ret;
-
- radeon_cs_space_reset_bos(rmesa->radeon.cmdbuf.cs);
-
- rrb = radeon_get_colorbuffer(&rmesa->radeon);
- /* color buffer */
- if (rrb && rrb->bo) {
- radeon_cs_space_add_persistent_bo(rmesa->radeon.cmdbuf.cs,
- rrb->bo, 0,
- RADEON_GEM_DOMAIN_VRAM);
- }
-
- /* depth buffer */
- rrb = radeon_get_depthbuffer(&rmesa->radeon);
- if (rrb && rrb->bo) {
- radeon_cs_space_add_persistent_bo(rmesa->radeon.cmdbuf.cs,
- rrb->bo, 0,
- RADEON_GEM_DOMAIN_VRAM);
- }
-
- for (i = 0; i < ctx->Const.MaxTextureImageUnits; ++i) {
- radeonTexObj *t;
-
- if (!ctx->Texture.Unit[i]._ReallyEnabled)
- continue;
-
- if (!r300_validate_texture(ctx, ctx->Texture.Unit[i]._Current)) {
- _mesa_warning(ctx,
- "failed to validate texture for unit %d.\n",
- i);
- }
- t = radeon_tex_obj(ctx->Texture.Unit[i]._Current);
- if (t->image_override && t->bo)
- radeon_cs_space_add_persistent_bo(rmesa->radeon.cmdbuf.cs,
- t->bo,
- RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
- else if (t->mt->bo)
- radeon_cs_space_add_persistent_bo(rmesa->radeon.cmdbuf.cs,
- t->mt->bo,
- RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
- }
-
- ret = radeon_cs_space_check_with_bo(rmesa->radeon.cmdbuf.cs, first_elem(&rmesa->radeon.dma.reserved)->bo, RADEON_GEM_DOMAIN_GTT, 0);
- if (ret)
- return GL_FALSE;
- return GL_TRUE;
-}
-
-void r300SetTexOffset(__DRIcontext * pDRICtx, GLint texname,
- unsigned long long offset, GLint depth, GLuint pitch)
-{
- r300ContextPtr rmesa = pDRICtx->driverPrivate;
- struct gl_texture_object *tObj =
- _mesa_lookup_texture(rmesa->radeon.glCtx, texname);
- radeonTexObjPtr t = radeon_tex_obj(tObj);
- uint32_t pitch_val;
-
- if (!tObj)
- return;
-
- t->image_override = GL_TRUE;
-
- if (!offset)
- return;
-
- t->bo = NULL;
- t->override_offset = offset;
- t->pp_txpitch &= (1 << 13) -1;
- pitch_val = pitch;
-
- switch (depth) {
- case 32:
- t->pp_txformat = R300_EASY_TX_FORMAT(X, Y, Z, W, W8Z8Y8X8);
- pitch_val /= 4;
- break;
- case 24:
- default:
- t->pp_txformat = R300_EASY_TX_FORMAT(X, Y, Z, ONE, W8Z8Y8X8);
- pitch_val /= 4;
- break;
- case 16:
- t->pp_txformat = R300_EASY_TX_FORMAT(X, Y, Z, ONE, Z5Y6X5);
- pitch_val /= 2;
- break;
- }
- pitch_val--;
-
- t->pp_txpitch |= pitch_val;
-}
-
-void r300SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint texture_format, __DRIdrawable *dPriv)
-{
- struct gl_texture_unit *texUnit;
- struct gl_texture_object *texObj;
- struct gl_texture_image *texImage;
- struct radeon_renderbuffer *rb;
- radeon_texture_image *rImage;
- radeonContextPtr radeon;
- r300ContextPtr rmesa;
- struct radeon_framebuffer *rfb;
- radeonTexObjPtr t;
- uint32_t pitch_val;
- gl_format texFormat;
-
- radeon = pDRICtx->driverPrivate;
- rmesa = pDRICtx->driverPrivate;
-
- rfb = dPriv->driverPrivate;
- texUnit = &radeon->glCtx->Texture.Unit[radeon->glCtx->Texture.CurrentUnit];
- texObj = _mesa_select_tex_object(radeon->glCtx, texUnit, target);
- texImage = _mesa_get_tex_image(radeon->glCtx, texObj, target, 0);
-
- rImage = get_radeon_texture_image(texImage);
- t = radeon_tex_obj(texObj);
- if (t == NULL) {
- return;
- }
-
- radeon_update_renderbuffers(pDRICtx, dPriv, GL_TRUE);
- rb = rfb->color_rb[0];
- if (rb->bo == NULL) {
- /* Failed to BO for the buffer */
- return;
- }
-
- _mesa_lock_texture(radeon->glCtx, texObj);
- if (t->bo) {
- radeon_bo_unref(t->bo);
- t->bo = NULL;
- }
- if (rImage->bo) {
- radeon_bo_unref(rImage->bo);
- rImage->bo = NULL;
- }
-
- radeon_miptree_unreference(&t->mt);
- radeon_miptree_unreference(&rImage->mt);
-
- rImage->bo = rb->bo;
- radeon_bo_ref(rImage->bo);
- t->bo = rb->bo;
- radeon_bo_ref(t->bo);
- t->tile_bits = 0;
- t->image_override = GL_TRUE;
- t->override_offset = 0;
- t->pp_txpitch &= (1 << 13) -1;
- pitch_val = rb->pitch;
- switch (rb->cpp) {
- case 4:
- if (texture_format == __DRI_TEXTURE_FORMAT_RGB) {
- texFormat = MESA_FORMAT_RGB888;
- t->pp_txformat = R300_EASY_TX_FORMAT(X, Y, Z, ONE, W8Z8Y8X8);
- }
- else {
- texFormat = MESA_FORMAT_ARGB8888;
- t->pp_txformat = R300_EASY_TX_FORMAT(X, Y, Z, W, W8Z8Y8X8);
- }
- pitch_val /= 4;
- break;
- case 3:
- default:
- texFormat = MESA_FORMAT_RGB888;
- t->pp_txformat = R300_EASY_TX_FORMAT(X, Y, Z, ONE, W8Z8Y8X8);
- pitch_val /= 4;
- break;
- case 2:
- texFormat = MESA_FORMAT_RGB565;
- t->pp_txformat = R300_EASY_TX_FORMAT(X, Y, Z, ONE, Z5Y6X5);
- pitch_val /= 2;
- break;
- }
-
- _mesa_init_teximage_fields(radeon->glCtx, target, texImage,
- rb->base.Width, rb->base.Height, 1, 0,
- rb->cpp, texFormat);
- rImage->base.RowStride = rb->pitch / rb->cpp;
-
-
- pitch_val--;
- t->pp_txsize = (((R300_TX_WIDTHMASK_MASK & ((rb->base.Width - 1) << R300_TX_WIDTHMASK_SHIFT)))
- | ((R300_TX_HEIGHTMASK_MASK & ((rb->base.Height - 1) << R300_TX_HEIGHTMASK_SHIFT))));
- t->pp_txsize |= R300_TX_SIZE_TXPITCH_EN;
- t->pp_txpitch |= pitch_val;
-
- if (rmesa->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) {
- if (rb->base.Width > 2048)
- t->pp_txpitch |= R500_TXWIDTH_BIT11;
- else
- t->pp_txpitch &= ~R500_TXWIDTH_BIT11;
- if (rb->base.Height > 2048)
- t->pp_txpitch |= R500_TXHEIGHT_BIT11;
- else
- t->pp_txpitch &= ~R500_TXHEIGHT_BIT11;
- }
- t->validated = GL_TRUE;
- _mesa_unlock_texture(radeon->glCtx, texObj);
- return;
-}
-
-void r300SetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPriv)
-{
- r300SetTexBuffer2(pDRICtx, target, __DRI_TEXTURE_FORMAT_RGBA, dPriv);
-}
+++ /dev/null
-/**************************************************************************
-
-Copyright (C) 2005 Aapo Tahkola <aet@rasterburn.org>
-Copyright (C) 2008 Oliver McFadden <z3ro.geek@gmail.com>
-
-All Rights Reserved.
-
-Permission is hereby granted, free of charge, to any person obtaining a
-copy of this software and associated documentation files (the "Software"),
-to deal in the Software without restriction, including without limitation
-on the rights to use, copy, modify, merge, publish, distribute, sub
-license, and/or sell copies of the Software, and to permit persons to whom
-the Software is furnished to do so, subject to the following conditions:
-
-The above copyright notice and this permission notice (including the next
-paragraph) shall be included in all copies or substantial portions of the
-Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
-THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
-DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
-USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-**************************************************************************/
-
-/* Radeon R5xx Acceleration, Revision 1.2 */
-
-#include "main/glheader.h"
-#include "main/macros.h"
-#include "main/enums.h"
-#include "program/program.h"
-#include "program/programopt.h"
-#include "program/prog_instruction.h"
-#include "program/prog_parameter.h"
-#include "program/prog_print.h"
-#include "program/prog_statevars.h"
-#include "tnl/tnl.h"
-
-#include "compiler/radeon_compiler.h"
-#include "radeon_mesa_to_rc.h"
-#include "r300_context.h"
-#include "r300_fragprog_common.h"
-#include "r300_state.h"
-
-/**
- * Write parameter array for the given vertex program into dst.
- * Return the total number of components written.
- */
-static int r300VertexProgUpdateParams(struct gl_context * ctx, struct r300_vertex_program *vp, float *dst)
-{
- int i;
-
- if (vp->Base->IsNVProgram) {
- _mesa_load_tracked_matrices(ctx);
- } else {
- if (vp->Base->Base.Parameters) {
- _mesa_load_state_parameters(ctx, vp->Base->Base.Parameters);
- }
- }
-
- for(i = 0; i < vp->code.constants.Count; ++i) {
- const float * src = 0;
- const struct rc_constant * constant = &vp->code.constants.Constants[i];
-
- switch(constant->Type) {
- case RC_CONSTANT_EXTERNAL:
- if (vp->Base->IsNVProgram) {
- src = ctx->VertexProgram.Parameters[constant->u.External];
- } else {
- src = &vp->Base->Base.Parameters->ParameterValues[constant->u.External][0].f;
- }
- break;
-
- case RC_CONSTANT_IMMEDIATE:
- src = constant->u.Immediate;
- break;
- }
-
- assert(src);
- dst[4*i] = src[0];
- dst[4*i + 1] = src[1];
- dst[4*i + 2] = src[2];
- dst[4*i + 3] = src[3];
- }
-
- return 4 * vp->code.constants.Count;
-}
-
-static GLbitfield compute_required_outputs(struct gl_vertex_program * vp, GLbitfield fpreads)
-{
- GLbitfield outputs = 0;
- int i;
-
-#define ADD_OUTPUT(fp_attr, vp_result) \
- do { \
- if (fpreads & (1 << (fp_attr))) \
- outputs |= (1 << (vp_result)); \
- } while (0)
-
- ADD_OUTPUT(FRAG_ATTRIB_COL0, VERT_RESULT_COL0);
- ADD_OUTPUT(FRAG_ATTRIB_COL1, VERT_RESULT_COL1);
-
- for (i = 0; i <= 7; ++i) {
- ADD_OUTPUT(FRAG_ATTRIB_TEX0 + i, VERT_RESULT_TEX0 + i);
- }
-
-#undef ADD_OUTPUT
-
- if ((fpreads & (1 << FRAG_ATTRIB_COL0)) &&
- (vp->Base.OutputsWritten & (1 << VERT_RESULT_BFC0)))
- outputs |= 1 << VERT_RESULT_BFC0;
- if ((fpreads & (1 << FRAG_ATTRIB_COL1)) &&
- (vp->Base.OutputsWritten & (1 << VERT_RESULT_BFC1)))
- outputs |= 1 << VERT_RESULT_BFC1;
-
- outputs |= 1 << VERT_RESULT_HPOS;
- if (vp->Base.OutputsWritten & (1 << VERT_RESULT_PSIZ))
- outputs |= 1 << VERT_RESULT_PSIZ;
-
- return outputs;
-}
-
-
-static void t_inputs_outputs(struct r300_vertex_program_compiler * c)
-{
- int i;
- int cur_reg;
- GLuint OutputsWritten, InputsRead;
-
- OutputsWritten = c->Base.Program.OutputsWritten;
- InputsRead = c->Base.Program.InputsRead;
-
- cur_reg = -1;
- for (i = 0; i < VERT_ATTRIB_MAX; i++) {
- if (InputsRead & (1 << i))
- c->code->inputs[i] = ++cur_reg;
- else
- c->code->inputs[i] = -1;
- }
-
- cur_reg = 0;
- for (i = 0; i < VERT_RESULT_MAX; i++)
- c->code->outputs[i] = -1;
-
- assert(OutputsWritten & (1 << VERT_RESULT_HPOS));
-
- if (OutputsWritten & (1 << VERT_RESULT_HPOS)) {
- c->code->outputs[VERT_RESULT_HPOS] = cur_reg++;
- }
-
- if (OutputsWritten & (1 << VERT_RESULT_PSIZ)) {
- c->code->outputs[VERT_RESULT_PSIZ] = cur_reg++;
- }
-
- /* If we're writing back facing colors we need to send
- * four colors to make front/back face colors selection work.
- * If the vertex program doesn't write all 4 colors, lets
- * pretend it does by skipping output index reg so the colors
- * get written into appropriate output vectors.
- */
- if (OutputsWritten & (1 << VERT_RESULT_COL0)) {
- c->code->outputs[VERT_RESULT_COL0] = cur_reg++;
- } else if (OutputsWritten & (1 << VERT_RESULT_BFC0) ||
- OutputsWritten & (1 << VERT_RESULT_BFC1)) {
- cur_reg++;
- }
-
- if (OutputsWritten & (1 << VERT_RESULT_COL1)) {
- c->code->outputs[VERT_RESULT_COL1] = cur_reg++;
- } else if (OutputsWritten & (1 << VERT_RESULT_BFC0) ||
- OutputsWritten & (1 << VERT_RESULT_BFC1)) {
- cur_reg++;
- }
-
- if (OutputsWritten & (1 << VERT_RESULT_BFC0)) {
- c->code->outputs[VERT_RESULT_BFC0] = cur_reg++;
- } else if (OutputsWritten & (1 << VERT_RESULT_BFC1)) {
- cur_reg++;
- }
-
- if (OutputsWritten & (1 << VERT_RESULT_BFC1)) {
- c->code->outputs[VERT_RESULT_BFC1] = cur_reg++;
- } else if (OutputsWritten & (1 << VERT_RESULT_BFC0)) {
- cur_reg++;
- }
-
- for (i = VERT_RESULT_TEX0; i <= VERT_RESULT_TEX7; i++) {
- if (OutputsWritten & (1 << i)) {
- c->code->outputs[i] = cur_reg++;
- }
- }
-
- if (OutputsWritten & (1 << VERT_RESULT_FOGC)) {
- c->code->outputs[VERT_RESULT_FOGC] = cur_reg++;
- }
-}
-
-/**
- * The NV_vertex_program spec mandates that all registers be
- * initialized to zero. We do this here unconditionally.
- *
- * \note We rely on dead-code elimination in the compiler.
- */
-static void initialize_NV_registers(struct radeon_compiler * compiler)
-{
- unsigned int reg;
- struct rc_instruction * inst;
-
- for(reg = 0; reg < 12; ++reg) {
- inst = rc_insert_new_instruction(compiler, &compiler->Program.Instructions);
- inst->U.I.Opcode = RC_OPCODE_MOV;
- inst->U.I.DstReg.File = RC_FILE_TEMPORARY;
- inst->U.I.DstReg.Index = reg;
- inst->U.I.SrcReg[0].File = RC_FILE_NONE;
- inst->U.I.SrcReg[0].Swizzle = RC_SWIZZLE_0000;
- }
-
- inst = rc_insert_new_instruction(compiler, &compiler->Program.Instructions);
- inst->U.I.Opcode = RC_OPCODE_ARL;
- inst->U.I.DstReg.File = RC_FILE_ADDRESS;
- inst->U.I.DstReg.Index = 0;
- inst->U.I.DstReg.WriteMask = WRITEMASK_X;
- inst->U.I.SrcReg[0].File = RC_FILE_NONE;
- inst->U.I.SrcReg[0].Swizzle = RC_SWIZZLE_0000;
-}
-
-static struct r300_vertex_program *build_program(struct gl_context *ctx,
- struct r300_vertex_program_key *wanted_key,
- const struct gl_vertex_program *mesa_vp)
-{
- struct r300_vertex_program *vp;
- struct r300_vertex_program_compiler compiler;
-
- vp = calloc(1, sizeof(*vp));
- vp->Base = _mesa_clone_vertex_program(ctx, mesa_vp);
- memcpy(&vp->key, wanted_key, sizeof(vp->key));
-
- memset(&compiler, 0, sizeof(compiler));
- rc_init(&compiler.Base);
- compiler.Base.Debug = (RADEON_DEBUG & RADEON_VERTS) ? GL_TRUE : GL_FALSE;
-
- compiler.code = &vp->code;
- compiler.RequiredOutputs = compute_required_outputs(vp->Base, vp->key.FpReads);
- compiler.SetHwInputOutput = &t_inputs_outputs;
- compiler.Base.is_r500 = R300_CONTEXT(ctx)->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515;
- compiler.Base.disable_optimizations = 0;
- compiler.Base.has_half_swizzles = 0;
- compiler.Base.max_temp_regs = 32;
- compiler.Base.max_constants = 256;
- compiler.Base.max_alu_insts = compiler.Base.is_r500 ? 1024 : 256;
-
- if (compiler.Base.Debug) {
- fprintf(stderr, "Initial vertex program:\n");
- _mesa_print_program(&vp->Base->Base);
- fflush(stderr);
- }
-
- if (mesa_vp->IsPositionInvariant) {
- _mesa_insert_mvp_code(ctx, vp->Base);
- }
-
- radeon_mesa_to_rc_program(&compiler.Base, &vp->Base->Base);
-
- if (mesa_vp->IsNVProgram)
- initialize_NV_registers(&compiler.Base);
-
- rc_move_output(&compiler.Base, VERT_RESULT_PSIZ, VERT_RESULT_PSIZ, WRITEMASK_X);
-
- if (vp->key.WPosAttr != FRAG_ATTRIB_MAX) {
- unsigned int vp_wpos_attr = vp->key.WPosAttr - FRAG_ATTRIB_TEX0 + VERT_RESULT_TEX0;
-
- /* Set empty writemask for instructions writing to vp_wpos_attr
- * before moving the wpos attr there.
- * Such instructions will be removed by DCE.
- */
- rc_move_output(&compiler.Base, vp_wpos_attr, vp->key.WPosAttr, 0);
- rc_copy_output(&compiler.Base, VERT_RESULT_HPOS, vp_wpos_attr);
- }
-
- if (vp->key.FogAttr != FRAG_ATTRIB_MAX) {
- unsigned int vp_fog_attr = vp->key.FogAttr - FRAG_ATTRIB_TEX0 + VERT_RESULT_TEX0;
-
- /* Set empty writemask for instructions writing to vp_fog_attr
- * before moving the fog attr there.
- * Such instructions will be removed by DCE.
- */
- rc_move_output(&compiler.Base, vp_fog_attr, vp->key.FogAttr, 0);
- rc_move_output(&compiler.Base, VERT_RESULT_FOGC, vp_fog_attr, WRITEMASK_X);
- }
-
- r3xx_compile_vertex_program(&compiler);
-
- if (vp->code.constants.Count > ctx->Const.VertexProgram.MaxParameters) {
- rc_error(&compiler.Base, "Program exceeds constant buffer size limit\n");
- }
-
- vp->error = compiler.Base.Error;
-
- vp->Base->Base.InputsRead = vp->code.InputsRead;
- vp->Base->Base.OutputsWritten = vp->code.OutputsWritten;
-
- rc_destroy(&compiler.Base);
-
- return vp;
-}
-
-struct r300_vertex_program * r300SelectAndTranslateVertexShader(struct gl_context *ctx)
-{
- r300ContextPtr r300 = R300_CONTEXT(ctx);
- struct r300_vertex_program_key wanted_key = { 0 };
- struct r300_vertex_program_cont *vpc;
- struct r300_vertex_program *vp;
-
- vpc = (struct r300_vertex_program_cont *)ctx->VertexProgram._Current;
-
- if (!r300->selected_fp) {
- /* This can happen when GetProgramiv is called to check
- * whether the program runs natively.
- *
- * To be honest, this is not a very good solution,
- * but solving the problem of reporting good values
- * for those queries is tough anyway considering that
- * we recompile vertex programs based on the precise
- * fragment program that is in use.
- */
- r300SelectAndTranslateFragmentShader(ctx);
- }
-
- assert(r300->selected_fp);
- wanted_key.FpReads = r300->selected_fp->InputsRead;
- wanted_key.FogAttr = r300->selected_fp->fog_attr;
- wanted_key.WPosAttr = r300->selected_fp->wpos_attr;
-
- for (vp = vpc->progs; vp; vp = vp->next) {
- if (memcmp(&vp->key, &wanted_key, sizeof(wanted_key)) == 0) {
- return r300->selected_vp = vp;
- }
- }
-
- vp = build_program(ctx, &wanted_key, &vpc->mesa_program);
- vp->next = vpc->progs;
- vpc->progs = vp;
-
- return r300->selected_vp = vp;
-}
-
-#define bump_vpu_count(ptr, new_count) do { \
- drm_r300_cmd_header_t* _p=((drm_r300_cmd_header_t*)(ptr)); \
- int _nc=(new_count)/4; \
- if(_nc>_p->vpu.count)_p->vpu.count=_nc; \
- } while(0)
-
-static void r300EmitVertexProgram(r300ContextPtr r300, int dest, struct r300_vertex_program_code *code)
-{
- int i;
-
- assert((code->length > 0) && (code->length % 4 == 0));
-
- switch ((dest >> 8) & 0xf) {
- case 0:
- R300_STATECHANGE(r300, vpi);
- for (i = 0; i < code->length; i++)
- r300->hw.vpi.cmd[R300_VPI_INSTR_0 + i + 4 * (dest & 0xff)] = (code->body.d[i]);
- bump_vpu_count(r300->hw.vpi.cmd, code->length + 4 * (dest & 0xff));
- break;
- case 2:
- R300_STATECHANGE(r300, vpp);
- for (i = 0; i < code->length; i++)
- r300->hw.vpp.cmd[R300_VPP_PARAM_0 + i + 4 * (dest & 0xff)] = (code->body.d[i]);
- bump_vpu_count(r300->hw.vpp.cmd, code->length + 4 * (dest & 0xff));
- break;
- case 4:
- R300_STATECHANGE(r300, vps);
- for (i = 0; i < code->length; i++)
- r300->hw.vps.cmd[1 + i + 4 * (dest & 0xff)] = (code->body.d[i]);
- bump_vpu_count(r300->hw.vps.cmd, code->length + 4 * (dest & 0xff));
- break;
- default:
- fprintf(stderr, "%s:%s don't know how to handle dest %04x\n", __FILE__, __FUNCTION__, dest);
- exit(-1);
- }
-}
-
-void r300SetupVertexProgram(r300ContextPtr rmesa)
-{
- struct gl_context *ctx = rmesa->radeon.glCtx;
- struct r300_vertex_program *prog = rmesa->selected_vp;
- int inst_count = 0;
- int param_count = 0;
-
- /* Reset state, in case we don't use something */
- ((drm_r300_cmd_header_t *) rmesa->hw.vpp.cmd)->vpu.count = 0;
- ((drm_r300_cmd_header_t *) rmesa->hw.vpi.cmd)->vpu.count = 0;
- ((drm_r300_cmd_header_t *) rmesa->hw.vps.cmd)->vpu.count = 0;
-
- R300_STATECHANGE(rmesa, vap_cntl);
- R300_STATECHANGE(rmesa, vpp);
- param_count = r300VertexProgUpdateParams(ctx, prog, (float *)&rmesa->hw.vpp.cmd[R300_VPP_PARAM_0]);
- if (!rmesa->radeon.radeonScreen->kernel_mm && param_count > 255 * 4) {
- WARN_ONCE("Too many VP params, expect rendering errors\n");
- }
- /* Prevent the overflow (vpu.count is u8) */
- bump_vpu_count(rmesa->hw.vpp.cmd, MIN2(255 * 4, param_count));
- param_count /= 4;
-
- r300EmitVertexProgram(rmesa, R300_PVS_CODE_START, &(prog->code));
- inst_count = (prog->code.length / 4) - 1;
-
- r300VapCntl(rmesa, _mesa_bitcount(prog->code.InputsRead),
- _mesa_bitcount(prog->code.OutputsWritten), prog->code.num_temporaries);
-
- R300_STATECHANGE(rmesa, pvs);
- rmesa->hw.pvs.cmd[R300_PVS_CNTL_1] = (0 << R300_PVS_FIRST_INST_SHIFT) | (inst_count << R300_PVS_XYZW_VALID_INST_SHIFT) |
- (inst_count << R300_PVS_LAST_INST_SHIFT);
-
- rmesa->hw.pvs.cmd[R300_PVS_CNTL_2] = (0 << R300_PVS_CONST_BASE_OFFSET_SHIFT) | ((param_count - 1) << R300_PVS_MAX_CONST_ADDR_SHIFT);
- rmesa->hw.pvs.cmd[R300_PVS_CNTL_3] = (inst_count << R300_PVS_LAST_VTX_SRC_INST_SHIFT);
-}
+++ /dev/null
-#ifndef __R300_VERTPROG_H_
-#define __R300_VERTPROG_H_
-
-#include "r300_reg.h"
-
-
-void r300SetupVertexProgram(r300ContextPtr rmesa);
-
-struct r300_vertex_program * r300SelectAndTranslateVertexShader(struct gl_context *ctx);
-
-#endif
+++ /dev/null
-../radeon/radeon_bo.c
\ No newline at end of file
+++ /dev/null
-../radeon/radeon_bo_int_drm.h
\ No newline at end of file
+++ /dev/null
-../radeon/radeon_bo_legacy.c
\ No newline at end of file
+++ /dev/null
-../radeon/radeon_bo_legacy.h
\ No newline at end of file
+++ /dev/null
-../radeon/radeon_bocs_wrapper.h
\ No newline at end of file
+++ /dev/null
-../radeon/radeon_buffer_objects.c
\ No newline at end of file
+++ /dev/null
-../radeon/radeon_buffer_objects.h
\ No newline at end of file
+++ /dev/null
-../radeon/radeon_chipset.h
\ No newline at end of file
+++ /dev/null
-../radeon/radeon_cmdbuf.h
\ No newline at end of file
+++ /dev/null
-../radeon/radeon_common.c
\ No newline at end of file
+++ /dev/null
-../radeon/radeon_common.h
\ No newline at end of file
+++ /dev/null
-../radeon/radeon_common_context.c
\ No newline at end of file
+++ /dev/null
-../radeon/radeon_common_context.h
\ No newline at end of file
+++ /dev/null
-/**************************************************************************
-
-Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
- VA Linux Systems Inc., Fremont, California.
-Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
-
-The Weather Channel (TM) funded Tungsten Graphics to develop the
-initial release of the Radeon 8500 driver under the XFree86 license.
-This notice must be preserved.
-
-All Rights Reserved.
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-**************************************************************************/
-
-/*
- * Authors:
- * Gareth Hughes <gareth@valinux.com>
- * Keith Whitwell <keith@tungstengraphics.com>
- * Kevin E. Martin <martin@valinux.com>
- * Nicolai Haehnle <prefect_@gmx.net>
- */
-
-#ifndef __RADEON_CONTEXT_H__
-#define __RADEON_CONTEXT_H__
-
-#include "main/mtypes.h"
-#include "main/colormac.h"
-#include "radeon_screen.h"
-#include "drm.h"
-#include "dri_util.h"
-
-#define FALLBACK( radeon, bit, mode ) fprintf(stderr, "%s:%s\n", __LINE__, __FILE__);
-
-/* TCL fallbacks */
-extern void radeonTclFallback(struct gl_context * ctx, GLuint bit, GLboolean mode);
-
-#define TCL_FALLBACK( ctx, bit, mode ) ;
-
-
-#endif /* __RADEON_CONTEXT_H__ */
+++ /dev/null
-../radeon/radeon_cs.c
\ No newline at end of file
+++ /dev/null
-../radeon/radeon_cs_int_drm.h
\ No newline at end of file
+++ /dev/null
-../radeon/radeon_cs_legacy.c
\ No newline at end of file
+++ /dev/null
-../radeon/radeon_cs_legacy.h
\ No newline at end of file
+++ /dev/null
-../radeon/radeon_cs_space_drm.c
\ No newline at end of file
+++ /dev/null
-../radeon/radeon_debug.c
\ No newline at end of file
+++ /dev/null
-../radeon/radeon_debug.h
\ No newline at end of file
+++ /dev/null
-../radeon/radeon_dma.c
\ No newline at end of file
+++ /dev/null
-../radeon/radeon_dma.h
\ No newline at end of file
+++ /dev/null
-../radeon/radeon_fbo.c
\ No newline at end of file
+++ /dev/null
-../radeon/radeon_lock.c
\ No newline at end of file
+++ /dev/null
-../radeon/radeon_lock.h
\ No newline at end of file
+++ /dev/null
-/*
- * Copyright (C) 2009 Nicolai Haehnle.
- *
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial
- * portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
- * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
- * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
- * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-
-#include "radeon_mesa_to_rc.h"
-
-#include "main/mtypes.h"
-#include "program/prog_instruction.h"
-#include "program/prog_parameter.h"
-
-#include "compiler/radeon_compiler.h"
-#include "compiler/radeon_program.h"
-
-
-static rc_opcode translate_opcode(gl_inst_opcode opcode)
-{
- switch(opcode) {
- case OPCODE_NOP: return RC_OPCODE_NOP;
- case OPCODE_ABS: return RC_OPCODE_ABS;
- case OPCODE_ADD: return RC_OPCODE_ADD;
- case OPCODE_ARL: return RC_OPCODE_ARL;
- case OPCODE_CMP: return RC_OPCODE_CMP;
- case OPCODE_COS: return RC_OPCODE_COS;
- case OPCODE_DDX: return RC_OPCODE_DDX;
- case OPCODE_DDY: return RC_OPCODE_DDY;
- case OPCODE_DP3: return RC_OPCODE_DP3;
- case OPCODE_DP4: return RC_OPCODE_DP4;
- case OPCODE_DPH: return RC_OPCODE_DPH;
- case OPCODE_DST: return RC_OPCODE_DST;
- case OPCODE_EX2: return RC_OPCODE_EX2;
- case OPCODE_EXP: return RC_OPCODE_EXP;
- case OPCODE_FLR: return RC_OPCODE_FLR;
- case OPCODE_FRC: return RC_OPCODE_FRC;
- case OPCODE_KIL: return RC_OPCODE_KIL;
- case OPCODE_LG2: return RC_OPCODE_LG2;
- case OPCODE_LIT: return RC_OPCODE_LIT;
- case OPCODE_LOG: return RC_OPCODE_LOG;
- case OPCODE_LRP: return RC_OPCODE_LRP;
- case OPCODE_MAD: return RC_OPCODE_MAD;
- case OPCODE_MAX: return RC_OPCODE_MAX;
- case OPCODE_MIN: return RC_OPCODE_MIN;
- case OPCODE_MOV: return RC_OPCODE_MOV;
- case OPCODE_MUL: return RC_OPCODE_MUL;
- case OPCODE_POW: return RC_OPCODE_POW;
- case OPCODE_RCP: return RC_OPCODE_RCP;
- case OPCODE_RSQ: return RC_OPCODE_RSQ;
- case OPCODE_SCS: return RC_OPCODE_SCS;
- case OPCODE_SEQ: return RC_OPCODE_SEQ;
- case OPCODE_SFL: return RC_OPCODE_SFL;
- case OPCODE_SGE: return RC_OPCODE_SGE;
- case OPCODE_SGT: return RC_OPCODE_SGT;
- case OPCODE_SIN: return RC_OPCODE_SIN;
- case OPCODE_SLE: return RC_OPCODE_SLE;
- case OPCODE_SLT: return RC_OPCODE_SLT;
- case OPCODE_SNE: return RC_OPCODE_SNE;
- case OPCODE_SUB: return RC_OPCODE_SUB;
- case OPCODE_SWZ: return RC_OPCODE_SWZ;
- case OPCODE_TEX: return RC_OPCODE_TEX;
- case OPCODE_TXB: return RC_OPCODE_TXB;
- case OPCODE_TXD: return RC_OPCODE_TXD;
- case OPCODE_TXL: return RC_OPCODE_TXL;
- case OPCODE_TXP: return RC_OPCODE_TXP;
- case OPCODE_XPD: return RC_OPCODE_XPD;
- default: return RC_OPCODE_ILLEGAL_OPCODE;
- }
-}
-
-static rc_saturate_mode translate_saturate(unsigned int saturate)
-{
- switch(saturate) {
- default:
- case SATURATE_OFF: return RC_SATURATE_NONE;
- case SATURATE_ZERO_ONE: return RC_SATURATE_ZERO_ONE;
- }
-}
-
-static rc_register_file translate_register_file(unsigned int file)
-{
- switch(file) {
- case PROGRAM_TEMPORARY: return RC_FILE_TEMPORARY;
- case PROGRAM_INPUT: return RC_FILE_INPUT;
- case PROGRAM_OUTPUT: return RC_FILE_OUTPUT;
- case PROGRAM_LOCAL_PARAM:
- case PROGRAM_ENV_PARAM:
- case PROGRAM_STATE_VAR:
- case PROGRAM_NAMED_PARAM:
- case PROGRAM_CONSTANT:
- case PROGRAM_UNIFORM: return RC_FILE_CONSTANT;
- case PROGRAM_ADDRESS: return RC_FILE_ADDRESS;
- default: return RC_FILE_NONE;
- }
-}
-
-static void translate_srcreg(struct rc_src_register * dest, struct prog_src_register * src)
-{
- dest->File = translate_register_file(src->File);
- dest->Index = src->Index;
- dest->RelAddr = src->RelAddr;
- dest->Swizzle = src->Swizzle;
- dest->Abs = src->Abs;
- dest->Negate = src->Negate;
-}
-
-static void translate_dstreg(struct rc_dst_register * dest, struct prog_dst_register * src)
-{
- dest->File = translate_register_file(src->File);
- dest->Index = src->Index;
- dest->WriteMask = src->WriteMask;
-}
-
-static rc_texture_target translate_tex_target(gl_texture_index target)
-{
- switch(target) {
- case TEXTURE_2D_ARRAY_INDEX: return RC_TEXTURE_2D_ARRAY;
- case TEXTURE_1D_ARRAY_INDEX: return RC_TEXTURE_1D_ARRAY;
- case TEXTURE_CUBE_INDEX: return RC_TEXTURE_CUBE;
- case TEXTURE_3D_INDEX: return RC_TEXTURE_3D;
- case TEXTURE_RECT_INDEX: return RC_TEXTURE_RECT;
- default:
- case TEXTURE_2D_INDEX: return RC_TEXTURE_2D;
- case TEXTURE_1D_INDEX: return RC_TEXTURE_1D;
- }
-}
-
-static void translate_instruction(struct radeon_compiler * c,
- struct rc_instruction * dest, struct prog_instruction * src)
-{
- const struct rc_opcode_info * opcode;
- unsigned int i;
-
- dest->U.I.Opcode = translate_opcode(src->Opcode);
- if (dest->U.I.Opcode == RC_OPCODE_ILLEGAL_OPCODE) {
- rc_error(c, "Unsupported opcode %i\n", src->Opcode);
- return;
- }
- dest->U.I.SaturateMode = translate_saturate(src->SaturateMode);
-
- opcode = rc_get_opcode_info(dest->U.I.Opcode);
-
- for(i = 0; i < opcode->NumSrcRegs; ++i)
- translate_srcreg(&dest->U.I.SrcReg[i], &src->SrcReg[i]);
-
- if (opcode->HasDstReg)
- translate_dstreg(&dest->U.I.DstReg, &src->DstReg);
-
- if (opcode->HasTexture) {
- dest->U.I.TexSrcUnit = src->TexSrcUnit;
- dest->U.I.TexSrcTarget = translate_tex_target(src->TexSrcTarget);
- dest->U.I.TexShadow = src->TexShadow;
- dest->U.I.TexSwizzle = RC_SWIZZLE_XYZW;
- }
-}
-
-void radeon_mesa_to_rc_program(struct radeon_compiler * c, struct gl_program * program)
-{
- struct prog_instruction *source;
- unsigned int i;
-
- for(source = program->Instructions; source->Opcode != OPCODE_END; ++source) {
- struct rc_instruction * dest = rc_insert_new_instruction(c, c->Program.Instructions.Prev);
- translate_instruction(c, dest, source);
- }
-
- c->Program.ShadowSamplers = program->ShadowSamplers;
- c->Program.InputsRead = program->InputsRead;
- c->Program.OutputsWritten = program->OutputsWritten;
-
- int isNVProgram = 0;
-
- if (program->Target == GL_VERTEX_PROGRAM_ARB) {
- struct gl_vertex_program * vp = (struct gl_vertex_program *) program;
- isNVProgram = vp->IsNVProgram;
- }
-
- if (isNVProgram) {
- /* NV_vertex_program has a fixed-sized constant environment.
- * This could be handled more efficiently for programs that
- * do not use relative addressing.
- */
- for(i = 0; i < 96; ++i) {
- struct rc_constant constant;
-
- constant.Type = RC_CONSTANT_EXTERNAL;
- constant.Size = 4;
- constant.u.External = i;
-
- rc_constants_add(&c->Program.Constants, &constant);
- }
- } else {
- for(i = 0; i < program->Parameters->NumParameters; ++i) {
- struct rc_constant constant;
-
- constant.Type = RC_CONSTANT_EXTERNAL;
- constant.Size = 4;
- constant.u.External = i;
-
- rc_constants_add(&c->Program.Constants, &constant);
- }
- }
-}
+++ /dev/null
-/*
- * Copyright (C) 2009 Nicolai Haehnle.
- *
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial
- * portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
- * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
- * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
- * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-
-#ifndef RADEON_MESA_TO_RC_H
-#define RADEON_MESA_TO_RC_H
-
-struct gl_program;
-struct radeon_compiler;
-
-void radeon_mesa_to_rc_program(struct radeon_compiler * c, struct gl_program * program);
-
-#endif /* RADEON_MESA_TO_RC_H */
+++ /dev/null
-../radeon/radeon_mipmap_tree.c
\ No newline at end of file
+++ /dev/null
-../radeon/radeon_mipmap_tree.h
\ No newline at end of file
+++ /dev/null
-../radeon/radeon_pixel_read.c
\ No newline at end of file
+++ /dev/null
-../radeon/radeon_queryobj.c
\ No newline at end of file
+++ /dev/null
-../radeon/radeon_queryobj.h
\ No newline at end of file
+++ /dev/null
-../radeon/radeon_screen.c
\ No newline at end of file
+++ /dev/null
-../radeon/radeon_screen.h
\ No newline at end of file
+++ /dev/null
-../radeon/radeon_span.c
\ No newline at end of file
+++ /dev/null
-../radeon/radeon_span.h
\ No newline at end of file
+++ /dev/null
-../radeon/radeon_tex_copy.c
\ No newline at end of file
+++ /dev/null
-../radeon/radeon_texture.c
\ No newline at end of file
+++ /dev/null
-../radeon/radeon_texture.h
\ No newline at end of file
+++ /dev/null
-../radeon/radeon_tile.c
\ No newline at end of file
+++ /dev/null
-../radeon/radeon_tile.h
\ No newline at end of file
+++ /dev/null
-../../radeon/server/radeon.h
\ No newline at end of file
+++ /dev/null
-../../radeon/server/radeon_dri.h
\ No newline at end of file
+++ /dev/null
-../../radeon/server/radeon_macros.h
\ No newline at end of file
+++ /dev/null
-../../radeon/server/radeon_reg.h
\ No newline at end of file
+++ /dev/null
-#!/bin/sh
-indent -npro -kr -i8 -ts8 -sob -l80 -ss -ncs "$@"
+++ /dev/null
-# src/mesa/drivers/dri/r300/Makefile
-
-TOP = ../../../../..
-include $(TOP)/configs/current
-
-LIBNAME = r600_dri.so
-
-include ../Makefile.defines
-
-ifeq ($(RADEON_LDFLAGS),)
-CS_SOURCES = radeon_cs_space_drm.c radeon_bo.c radeon_cs.c
-endif
-
-RADEON_COMMON_SOURCES = \
- radeon_bo_legacy.c \
- radeon_common_context.c \
- radeon_buffer_objects.c \
- radeon_common.c \
- radeon_cs_legacy.c \
- radeon_dma.c \
- radeon_debug.c \
- radeon_fbo.c \
- radeon_lock.c \
- radeon_mipmap_tree.c \
- radeon_pixel_read.c \
- radeon_queryobj.c \
- radeon_span.c \
- radeon_texture.c \
- radeon_tex_copy.c \
- radeon_tile.c
-
-DRIVER_SOURCES = \
- radeon_screen.c \
- r600_context.c \
- r600_cmdbuf.c \
- r600_emit.c \
- r700_assembler.c \
- r700_fragprog.c \
- r700_vertprog.c \
- r700_shader.c \
- r700_shaderinst.c \
- r700_ioctl.c \
- r700_oglprog.c \
- r700_chip.c \
- r700_state.c \
- r700_clear.c \
- r700_render.c \
- r600_tex.c \
- r600_texstate.c \
- r600_blit.c \
- r700_debug.c \
- evergreen_context.c \
- evergreen_state.c \
- evergreen_tex.c \
- evergreen_ioctl.c \
- evergreen_render.c \
- evergreen_chip.c \
- evergreen_vertprog.c \
- evergreen_fragprog.c \
- evergreen_oglprog.c \
- evergreen_blit.c \
- $(RADEON_COMMON_SOURCES) \
- $(EGL_SOURCES) \
- $(CS_SOURCES)
-
-C_SOURCES = $(COMMON_SOURCES) $(DRIVER_SOURCES)
-
-DRIVER_DEFINES = -DRADEON_R600
-# -DRADEON_BO_TRACK \
-
-INCLUDES += $(RADEON_CFLAGS)
-DRI_LIB_DEPS += $(RADEON_LDFLAGS)
-
-##### TARGETS #####
-
-include ../Makefile.targets
-
+++ /dev/null
-/*
- * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Authors:
- * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
- */
-
-
-#ifndef _DEFINEENDIAN_H_
-#define _DEFINEENDIAN_H_
-
-//We have to choose a reg bits orientation if there is no compile flag for it.
-#ifdef MESA_BIG_ENDIAN
-#define BIGENDIAN_CPU
-#else
-#define LITTLEENDIAN_CPU
-#endif
-
-#endif //_DEFINEENDIAN_H_
+++ /dev/null
-/*
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial
- * portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
- * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
- * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
- * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-
-#include "radeon_common.h"
-#include "r600_context.h"
-
-#include "evergreen_off.h"
-#include "evergreen_diff.h"
-
-#include "evergreen_blit.h"
-#include "evergreen_blit_shaders.h"
-#include "r600_cmdbuf.h"
-
-/* common formats supported as both textures and render targets */
-unsigned evergreen_check_blit(gl_format mesa_format)
-{
- switch (mesa_format) {
- case MESA_FORMAT_RGBA8888:
- case MESA_FORMAT_SIGNED_RGBA8888:
- case MESA_FORMAT_RGBA8888_REV:
- case MESA_FORMAT_SIGNED_RGBA8888_REV:
- case MESA_FORMAT_ARGB8888:
- case MESA_FORMAT_XRGB8888:
- case MESA_FORMAT_ARGB8888_REV:
- case MESA_FORMAT_XRGB8888_REV:
- case MESA_FORMAT_RGB565:
- case MESA_FORMAT_RGB565_REV:
- case MESA_FORMAT_ARGB4444:
- case MESA_FORMAT_ARGB4444_REV:
- case MESA_FORMAT_ARGB1555:
- case MESA_FORMAT_ARGB1555_REV:
- case MESA_FORMAT_AL88:
- case MESA_FORMAT_AL88_REV:
- case MESA_FORMAT_RGB332:
- case MESA_FORMAT_A8:
- case MESA_FORMAT_I8:
- case MESA_FORMAT_L8:
- case MESA_FORMAT_RGBA_FLOAT32:
- case MESA_FORMAT_RGBA_FLOAT16:
- case MESA_FORMAT_ALPHA_FLOAT32:
- case MESA_FORMAT_ALPHA_FLOAT16:
- case MESA_FORMAT_LUMINANCE_FLOAT32:
- case MESA_FORMAT_LUMINANCE_FLOAT16:
- case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32:
- case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16:
- case MESA_FORMAT_INTENSITY_FLOAT32: /* X, X, X, X */
- case MESA_FORMAT_INTENSITY_FLOAT16: /* X, X, X, X */
- case MESA_FORMAT_X8_Z24:
- case MESA_FORMAT_S8_Z24:
- case MESA_FORMAT_Z24_S8:
- case MESA_FORMAT_Z16:
- case MESA_FORMAT_Z32:
- case MESA_FORMAT_SARGB8:
- case MESA_FORMAT_SLA8:
- case MESA_FORMAT_SL8:
- break;
- default:
- return 0;
- }
-
- /* ??? */
- /* not sure blit to depth works or not yet */
- if (_mesa_get_format_bits(mesa_format, GL_DEPTH_BITS) > 0)
- return 0;
-
- return 1;
-}
-
-static inline void
-eg_set_render_target(context_t *context, struct radeon_bo *bo, gl_format mesa_format,
- int nPitchInPixel, int w, int h, intptr_t dst_offset)
-{
- uint32_t cb_color0_base, cb_color0_info = 0;
- uint32_t cb_color0_pitch = 0, cb_color0_slice = 0, cb_color0_attrib = 0;
- int id = 0;
- uint32_t endian, comp_swap, format, source_format, number_type;
- BATCH_LOCALS(&context->radeon);
-
- cb_color0_base = dst_offset / 256;
- endian = ENDIAN_NONE;
-
- /* pitch */
- SETfield(cb_color0_pitch, (nPitchInPixel / 8) - 1,
- EG_CB_COLOR0_PITCH__TILE_MAX_shift,
- EG_CB_COLOR0_PITCH__TILE_MAX_mask);
-
- /* slice */
- SETfield(cb_color0_slice,
- ((nPitchInPixel * h) / 64) - 1,
- EG_CB_COLOR0_SLICE__TILE_MAX_shift,
- EG_CB_COLOR0_SLICE__TILE_MAX_mask);
-
- /* CB_COLOR0_ATTRIB */ /* TODO : for z clear, this should be set to 0 */
- SETbit(cb_color0_attrib,
- EG_CB_COLOR0_ATTRIB__NON_DISP_TILING_ORDER_bit);
-
- SETfield(cb_color0_info,
- ARRAY_LINEAR_GENERAL,
- EG_CB_COLOR0_INFO__ARRAY_MODE_shift,
- EG_CB_COLOR0_INFO__ARRAY_MODE_mask);
-
- SETbit(cb_color0_info, EG_CB_COLOR0_INFO__BLEND_BYPASS_bit);
-
- switch(mesa_format) {
- case MESA_FORMAT_RGBA8888:
-#ifdef MESA_BIG_ENDIAN
- endian = ENDIAN_8IN32;
-#endif
- format = COLOR_8_8_8_8;
- comp_swap = SWAP_STD_REV;
- number_type = NUMBER_UNORM;
- source_format = 1;
- break;
- case MESA_FORMAT_SIGNED_RGBA8888:
-#ifdef MESA_BIG_ENDIAN
- endian = ENDIAN_8IN32;
-#endif
- format = COLOR_8_8_8_8;
- comp_swap = SWAP_STD_REV;
- number_type = NUMBER_SNORM;
- source_format = 1;
- break;
- case MESA_FORMAT_RGBA8888_REV:
-#ifdef MESA_BIG_ENDIAN
- endian = ENDIAN_8IN32;
-#endif
- format = COLOR_8_8_8_8;
- comp_swap = SWAP_STD;
- number_type = NUMBER_UNORM;
- source_format = 1;
- break;
- case MESA_FORMAT_SIGNED_RGBA8888_REV:
-#ifdef MESA_BIG_ENDIAN
- endian = ENDIAN_8IN32;
-#endif
- format = COLOR_8_8_8_8;
- comp_swap = SWAP_STD;
- number_type = NUMBER_SNORM;
- source_format = 1;
- break;
- case MESA_FORMAT_ARGB8888:
- case MESA_FORMAT_XRGB8888:
-#ifdef MESA_BIG_ENDIAN
- endian = ENDIAN_8IN32;
-#endif
- format = COLOR_8_8_8_8;
- comp_swap = SWAP_ALT;
- number_type = NUMBER_UNORM;
- source_format = 1;
- break;
- case MESA_FORMAT_ARGB8888_REV:
- case MESA_FORMAT_XRGB8888_REV:
-#ifdef MESA_BIG_ENDIAN
- endian = ENDIAN_8IN32;
-#endif
- format = COLOR_8_8_8_8;
- comp_swap = SWAP_ALT_REV;
- number_type = NUMBER_UNORM;
- source_format = 1;
- break;
- case MESA_FORMAT_RGB565:
-#ifdef MESA_BIG_ENDIAN
- endian = ENDIAN_8IN16;
-#endif
- format = COLOR_5_6_5;
- comp_swap = SWAP_STD_REV;
- number_type = NUMBER_UNORM;
- source_format = 1;
- break;
- case MESA_FORMAT_RGB565_REV:
-#ifdef MESA_BIG_ENDIAN
- endian = ENDIAN_8IN16;
-#endif
- format = COLOR_5_6_5;
- comp_swap = SWAP_STD;
- number_type = NUMBER_UNORM;
- source_format = 1;
- break;
- case MESA_FORMAT_ARGB4444:
-#ifdef MESA_BIG_ENDIAN
- endian = ENDIAN_8IN16;
-#endif
- format = COLOR_4_4_4_4;
- comp_swap = SWAP_ALT;
- number_type = NUMBER_UNORM;
- source_format = 1;
- break;
- case MESA_FORMAT_ARGB4444_REV:
-#ifdef MESA_BIG_ENDIAN
- endian = ENDIAN_8IN16;
-#endif
- format = COLOR_4_4_4_4;
- comp_swap = SWAP_ALT_REV;
- number_type = NUMBER_UNORM;
- source_format = 1;
- break;
- case MESA_FORMAT_ARGB1555:
-#ifdef MESA_BIG_ENDIAN
- endian = ENDIAN_8IN16;
-#endif
- format = COLOR_1_5_5_5;
- comp_swap = SWAP_ALT;
- number_type = NUMBER_UNORM;
- source_format = 1;
- break;
- case MESA_FORMAT_ARGB1555_REV:
-#ifdef MESA_BIG_ENDIAN
- endian = ENDIAN_8IN16;
-#endif
- format = COLOR_1_5_5_5;
- comp_swap = SWAP_ALT_REV;
- number_type = NUMBER_UNORM;
- source_format = 1;
- break;
- case MESA_FORMAT_AL88:
-#ifdef MESA_BIG_ENDIAN
- endian = ENDIAN_8IN16;
-#endif
- format = COLOR_8_8;
- comp_swap = SWAP_STD;
- number_type = NUMBER_UNORM;
- source_format = 1;
- break;
- case MESA_FORMAT_AL88_REV:
-#ifdef MESA_BIG_ENDIAN
- endian = ENDIAN_8IN16;
-#endif
- format = COLOR_8_8;
- comp_swap = SWAP_STD_REV;
- number_type = NUMBER_UNORM;
- source_format = 1;
- break;
- case MESA_FORMAT_RGB332:
- format = COLOR_3_3_2;
- comp_swap = SWAP_STD_REV;
- number_type = NUMBER_UNORM;
- source_format = 1;
- break;
- case MESA_FORMAT_A8:
- format = COLOR_8;
- comp_swap = SWAP_ALT_REV;
- number_type = NUMBER_UNORM;
- source_format = 1;
- break;
- case MESA_FORMAT_I8:
- format = COLOR_8;
- comp_swap = SWAP_STD;
- number_type = NUMBER_UNORM;
- source_format = 1;
- break;
- case MESA_FORMAT_L8:
- format = COLOR_8;
- comp_swap = SWAP_ALT;
- number_type = NUMBER_UNORM;
- source_format = 1;
- break;
- case MESA_FORMAT_RGBA_FLOAT32:
-#ifdef MESA_BIG_ENDIAN
- endian = ENDIAN_8IN32;
-#endif
- format = COLOR_32_32_32_32_FLOAT;
- comp_swap = SWAP_STD;
- number_type = NUMBER_FLOAT;
- source_format = 0;
- break;
- case MESA_FORMAT_RGBA_FLOAT16:
-#ifdef MESA_BIG_ENDIAN
- endian = ENDIAN_8IN16;
-#endif
- format = COLOR_16_16_16_16_FLOAT;
- comp_swap = SWAP_STD;
- number_type = NUMBER_FLOAT;
- source_format = 0;
- break;
- case MESA_FORMAT_ALPHA_FLOAT32:
-#ifdef MESA_BIG_ENDIAN
- endian = ENDIAN_8IN32;
-#endif
- format = COLOR_32_FLOAT;
- comp_swap = SWAP_ALT_REV;
- number_type = NUMBER_FLOAT;
- source_format = 0;
- break;
- case MESA_FORMAT_ALPHA_FLOAT16:
-#ifdef MESA_BIG_ENDIAN
- endian = ENDIAN_8IN16;
-#endif
- format = COLOR_16_FLOAT;
- comp_swap = SWAP_ALT_REV;
- number_type = NUMBER_FLOAT;
- source_format = 0;
- break;
- case MESA_FORMAT_LUMINANCE_FLOAT32:
-#ifdef MESA_BIG_ENDIAN
- endian = ENDIAN_8IN32;
-#endif
- format = COLOR_32_FLOAT;
- comp_swap = SWAP_ALT;
- number_type = NUMBER_FLOAT;
- source_format = 0;
- break;
- case MESA_FORMAT_LUMINANCE_FLOAT16:
-#ifdef MESA_BIG_ENDIAN
- endian = ENDIAN_8IN16;
-#endif
- format = COLOR_16_FLOAT;
- comp_swap = SWAP_ALT;
- number_type = NUMBER_FLOAT;
- source_format = 0;
- break;
- case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32:
-#ifdef MESA_BIG_ENDIAN
- endian = ENDIAN_8IN32;
-#endif
- format = COLOR_32_32_FLOAT;
- comp_swap = SWAP_ALT_REV;
- number_type = NUMBER_FLOAT;
- source_format = 0;
- break;
- case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16:
-#ifdef MESA_BIG_ENDIAN
- endian = ENDIAN_8IN16;
-#endif
- format = COLOR_16_16_FLOAT;
- comp_swap = SWAP_ALT_REV;
- number_type = NUMBER_FLOAT;
- source_format = 0;
- break;
- case MESA_FORMAT_INTENSITY_FLOAT32: /* X, X, X, X */
-#ifdef MESA_BIG_ENDIAN
- endian = ENDIAN_8IN32;
-#endif
- format = COLOR_32_FLOAT;
- comp_swap = SWAP_STD;
- number_type = NUMBER_FLOAT;
- source_format = 0;
- break;
- case MESA_FORMAT_INTENSITY_FLOAT16: /* X, X, X, X */
-#ifdef MESA_BIG_ENDIAN
- endian = ENDIAN_8IN16;
-#endif
- format = COLOR_16_FLOAT;
- comp_swap = SWAP_STD;
- number_type = NUMBER_UNORM;
- source_format = 0;
- break;
- case MESA_FORMAT_X8_Z24:
- case MESA_FORMAT_S8_Z24:
-#ifdef MESA_BIG_ENDIAN
- endian = ENDIAN_8IN32;
-#endif
- format = COLOR_8_24;
- comp_swap = SWAP_STD;
- number_type = NUMBER_UNORM;
- SETfield(cb_color0_info,
- ARRAY_1D_TILED_THIN1,
- EG_CB_COLOR0_INFO__ARRAY_MODE_shift,
- EG_CB_COLOR0_INFO__ARRAY_MODE_mask);
- source_format = 0;
- break;
- case MESA_FORMAT_Z24_S8:
-#ifdef MESA_BIG_ENDIAN
- endian = ENDIAN_8IN32;
-#endif
- format = COLOR_24_8;
- comp_swap = SWAP_STD;
- number_type = NUMBER_UNORM;
- SETfield(cb_color0_info,
- ARRAY_1D_TILED_THIN1,
- EG_CB_COLOR0_INFO__ARRAY_MODE_shift,
- EG_CB_COLOR0_INFO__ARRAY_MODE_mask);
- source_format = 0;
- break;
- case MESA_FORMAT_Z16:
-#ifdef MESA_BIG_ENDIAN
- endian = ENDIAN_8IN16;
-#endif
- format = COLOR_16;
- comp_swap = SWAP_STD;
- number_type = NUMBER_UNORM;
- SETfield(cb_color0_info,
- ARRAY_1D_TILED_THIN1,
- EG_CB_COLOR0_INFO__ARRAY_MODE_shift,
- EG_CB_COLOR0_INFO__ARRAY_MODE_mask);
- source_format = 0;
- break;
- case MESA_FORMAT_Z32:
-#ifdef MESA_BIG_ENDIAN
- endian = ENDIAN_8IN32;
-#endif
- format = COLOR_32;
- comp_swap = SWAP_STD;
- number_type = NUMBER_UNORM;
- SETfield(cb_color0_info,
- ARRAY_1D_TILED_THIN1,
- EG_CB_COLOR0_INFO__ARRAY_MODE_shift,
- EG_CB_COLOR0_INFO__ARRAY_MODE_mask);
- source_format = 0;
- break;
- case MESA_FORMAT_SARGB8:
-#ifdef MESA_BIG_ENDIAN
- endian = ENDIAN_8IN32;
-#endif
- format = COLOR_8_8_8_8;
- comp_swap = SWAP_ALT;
- number_type = NUMBER_SRGB;
- source_format = 1;
- break;
- case MESA_FORMAT_SLA8:
-#ifdef MESA_BIG_ENDIAN
- endian = ENDIAN_8IN16;
-#endif
- format = COLOR_8_8;
- comp_swap = SWAP_ALT_REV;
- number_type = NUMBER_SRGB;
- source_format = 1;
- break;
- case MESA_FORMAT_SL8:
- format = COLOR_8;
- comp_swap = SWAP_ALT_REV;
- number_type = NUMBER_SRGB;
- source_format = 1;
- break;
- default:
- fprintf(stderr,"Invalid format for copy %s\n",_mesa_get_format_name(mesa_format));
- assert("Invalid format for US output\n");
- return;
- }
-
- SETfield(cb_color0_info,
- endian,
- EG_CB_COLOR0_INFO__ENDIAN_shift,
- EG_CB_COLOR0_INFO__ENDIAN_mask);
- SETfield(cb_color0_info,
- format,
- EG_CB_COLOR0_INFO__FORMAT_shift,
- EG_CB_COLOR0_INFO__FORMAT_mask);
- SETfield(cb_color0_info,
- comp_swap,
- EG_CB_COLOR0_INFO__COMP_SWAP_shift,
- EG_CB_COLOR0_INFO__COMP_SWAP_mask);
- SETfield(cb_color0_info,
- number_type,
- EG_CB_COLOR0_INFO__NUMBER_TYPE_shift,
- EG_CB_COLOR0_INFO__NUMBER_TYPE_mask);
- SETfield(cb_color0_info,
- source_format,
- EG_CB_COLOR0_INFO__SOURCE_FORMAT_shift,
- EG_CB_COLOR0_INFO__SOURCE_FORMAT_mask);
-
- BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
- EVERGREEN_OUT_BATCH_REGSEQ(EG_CB_COLOR0_BASE + (4 * id), 1);
- R600_OUT_BATCH(cb_color0_base);
- R600_OUT_BATCH_RELOC(cb_color0_base,
- bo,
- cb_color0_base,
- 0, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0);
- END_BATCH();
-
- BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
- EVERGREEN_OUT_BATCH_REGVAL(EG_CB_COLOR0_INFO, cb_color0_info);
- R600_OUT_BATCH_RELOC(cb_color0_info,
- bo,
- cb_color0_info,
- 0, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0);
- END_BATCH();
-
- BEGIN_BATCH_NO_AUTOSTATE(5);
- EVERGREEN_OUT_BATCH_REGSEQ(EG_CB_COLOR0_PITCH, 3);
- R600_OUT_BATCH(cb_color0_pitch);
- R600_OUT_BATCH(cb_color0_slice);
- R600_OUT_BATCH(0);
- END_BATCH();
-
- BEGIN_BATCH_NO_AUTOSTATE(4);
- EVERGREEN_OUT_BATCH_REGSEQ(EG_CB_COLOR0_ATTRIB, 2);
- R600_OUT_BATCH(cb_color0_attrib);
- R600_OUT_BATCH(0);
- /*
- R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_CMASK.u32All);
- R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_CMASK_SLICE.u32All);
- R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_FMASK.u32All);
- R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_FMASK_SLICE.u32All);
- */
- END_BATCH();
-
- COMMIT_BATCH();
-
-}
-
-static inline void eg_load_shaders(struct gl_context * ctx)
-{
-
- radeonContextPtr radeonctx = RADEON_CONTEXT(ctx);
- context_t *context = EVERGREEN_CONTEXT(ctx);
- int i, size;
- uint32_t *shader;
-
- if (context->blit_bo_loaded == 1)
- return;
-
- size = 4096;
- context->blit_bo = radeon_bo_open(radeonctx->radeonScreen->bom, 0,
- size, 256, RADEON_GEM_DOMAIN_GTT, 0);
- radeon_bo_map(context->blit_bo, 1);
- shader = context->blit_bo->ptr;
-
- for(i=0; i<sizeof(evergreen_vs)/4; i++) {
- shader[128+i] = CPU_TO_LE32(evergreen_vs[i]);
- }
- for(i=0; i<sizeof(evergreen_ps)/4; i++) {
- shader[256+i] = CPU_TO_LE32(evergreen_ps[i]);
- }
-
- radeon_bo_unmap(context->blit_bo);
- context->blit_bo_loaded = 1;
-
-}
-
-static inline void
-eg_set_shaders(context_t *context)
-{
- struct radeon_bo * pbo = context->blit_bo;
- uint32_t sq_pgm_start_fs = (512 >> 8);
- uint32_t sq_pgm_resources_fs = 0;
-
- uint32_t sq_pgm_start_vs = (512 >> 8);
- uint32_t sq_pgm_resources_vs = (2 << NUM_GPRS_shift);
-
- uint32_t sq_pgm_start_ps = (1024 >> 8);
- uint32_t sq_pgm_resources_ps = (1 << NUM_GPRS_shift);
- uint32_t sq_pgm_exports_ps = (1 << 1);
- BATCH_LOCALS(&context->radeon);
-
- r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
-
- /* FS */
- BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
- EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_START_FS, 1);
- R600_OUT_BATCH(sq_pgm_start_fs);
- R600_OUT_BATCH_RELOC(sq_pgm_start_fs,
- pbo,
- sq_pgm_start_fs,
- RADEON_GEM_DOMAIN_GTT, 0, 0);
- END_BATCH();
-
- BEGIN_BATCH_NO_AUTOSTATE(3);
- EVERGREEN_OUT_BATCH_REGVAL(EG_SQ_PGM_RESOURCES_FS, sq_pgm_resources_fs);
- END_BATCH();
-
- /* VS */
- BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
- EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_START_VS, 1);
- R600_OUT_BATCH(sq_pgm_start_vs);
- R600_OUT_BATCH_RELOC(sq_pgm_start_vs,
- pbo,
- sq_pgm_start_vs,
- RADEON_GEM_DOMAIN_GTT, 0, 0);
- END_BATCH();
-
- BEGIN_BATCH_NO_AUTOSTATE(4);
- EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_RESOURCES_VS, 2);
- R600_OUT_BATCH(sq_pgm_resources_vs);
- R600_OUT_BATCH(0);
- END_BATCH();
-
- /* PS */
- BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
- EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_START_PS, 1);
- R600_OUT_BATCH(sq_pgm_start_ps);
- R600_OUT_BATCH_RELOC(sq_pgm_start_ps,
- pbo,
- sq_pgm_start_ps,
- RADEON_GEM_DOMAIN_GTT, 0, 0);
- END_BATCH();
-
- BEGIN_BATCH_NO_AUTOSTATE(5);
- EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_RESOURCES_PS, 3);
- R600_OUT_BATCH(sq_pgm_resources_ps);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(sq_pgm_exports_ps);
- END_BATCH();
-
- COMMIT_BATCH();
-
-}
-
-static inline void
-eg_set_vtx_resource(context_t *context)
-{
- struct radeon_bo *bo = context->blit_bo;
- uint32_t sq_vtx_constant_word3 = 0;
- uint32_t sq_vtx_constant_word2 = 0;
- BATCH_LOCALS(&context->radeon);
-
- BEGIN_BATCH_NO_AUTOSTATE(6);
- R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1));
- R600_OUT_BATCH(mmSQ_VTX_BASE_VTX_LOC - ASIC_CTL_CONST_BASE_INDEX);
- R600_OUT_BATCH(0);
-
- R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1));
- R600_OUT_BATCH(mmSQ_VTX_START_INST_LOC - ASIC_CTL_CONST_BASE_INDEX);
- R600_OUT_BATCH(0);
- END_BATCH();
-
- if (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_CEDAR)
- r700SyncSurf(context, bo, RADEON_GEM_DOMAIN_GTT, 0, TC_ACTION_ENA_bit);
- else
- r700SyncSurf(context, bo, RADEON_GEM_DOMAIN_GTT, 0, VC_ACTION_ENA_bit);
-
- SETfield(sq_vtx_constant_word3, SQ_SEL_X,
- EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_X_shift,
- EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_X_mask);
- SETfield(sq_vtx_constant_word3, SQ_SEL_Y,
- EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_Y_shift,
- EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_Y_mask);
- SETfield(sq_vtx_constant_word3, SQ_SEL_Z,
- EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_Z_shift,
- EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_Z_mask);
- SETfield(sq_vtx_constant_word3, SQ_SEL_W,
- EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_W_shift,
- EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_W_mask);
-
- sq_vtx_constant_word2 = 0
-#ifdef MESA_BIG_ENDIAN
- | (SQ_ENDIAN_8IN32 << SQ_VTX_CONSTANT_WORD2_0__ENDIAN_SWAP_shift)
-#endif
- | (16 << SQ_VTX_CONSTANT_WORD2_0__STRIDE_shift);
-
- BEGIN_BATCH_NO_AUTOSTATE(10 + 2);
-
- R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 8));
- R600_OUT_BATCH(EG_SQ_FETCH_RESOURCE_VS_OFFSET * EG_FETCH_RESOURCE_STRIDE);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(48 - 1);
- R600_OUT_BATCH(sq_vtx_constant_word2);
- R600_OUT_BATCH(sq_vtx_constant_word3);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(SQ_TEX_VTX_VALID_BUFFER << SQ_TEX_RESOURCE_WORD6_0__TYPE_shift);
- R600_OUT_BATCH_RELOC(0,
- bo,
- 0,
- RADEON_GEM_DOMAIN_GTT, 0, 0);
- END_BATCH();
- COMMIT_BATCH();
-
-}
-
-static inline void
-eg_set_tex_resource(context_t * context,
- gl_format mesa_format, struct radeon_bo *bo, int w, int h,
- int TexelPitch, intptr_t src_offset)
-{
- uint32_t sq_tex_resource0, sq_tex_resource1, sq_tex_resource2, sq_tex_resource4, sq_tex_resource7;
-
- sq_tex_resource0 = sq_tex_resource1 = sq_tex_resource2 = sq_tex_resource4 = sq_tex_resource7 = 0;
- BATCH_LOCALS(&context->radeon);
-
- SETfield(sq_tex_resource0, SQ_TEX_DIM_2D, DIM_shift, DIM_mask);
- SETfield(sq_tex_resource0, ARRAY_LINEAR_GENERAL,
- SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift,
- SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask);
-
- switch (mesa_format) {
- case MESA_FORMAT_RGBA8888:
- case MESA_FORMAT_SIGNED_RGBA8888:
- SETfield(sq_tex_resource7, FMT_8_8_8_8,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
- SETfield(sq_tex_resource4, SQ_SEL_W,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(sq_tex_resource4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(sq_tex_resource4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- if (mesa_format == MESA_FORMAT_SIGNED_RGBA8888) {
- SETfield(sq_tex_resource4, SQ_FORMAT_COMP_SIGNED,
- FORMAT_COMP_X_shift, FORMAT_COMP_X_mask);
- SETfield(sq_tex_resource4, SQ_FORMAT_COMP_SIGNED,
- FORMAT_COMP_Y_shift, FORMAT_COMP_Y_mask);
- SETfield(sq_tex_resource4, SQ_FORMAT_COMP_SIGNED,
- FORMAT_COMP_Z_shift, FORMAT_COMP_Z_mask);
- SETfield(sq_tex_resource4, SQ_FORMAT_COMP_SIGNED,
- FORMAT_COMP_W_shift, FORMAT_COMP_W_mask);
- }
- break;
- case MESA_FORMAT_RGBA8888_REV:
- case MESA_FORMAT_SIGNED_RGBA8888_REV:
- SETfield(sq_tex_resource7, FMT_8_8_8_8,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(sq_tex_resource4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(sq_tex_resource4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(sq_tex_resource4, SQ_SEL_W,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- if (mesa_format == MESA_FORMAT_SIGNED_RGBA8888_REV) {
- SETfield(sq_tex_resource4, SQ_FORMAT_COMP_SIGNED,
- FORMAT_COMP_X_shift, FORMAT_COMP_X_mask);
- SETfield(sq_tex_resource4, SQ_FORMAT_COMP_SIGNED,
- FORMAT_COMP_Y_shift, FORMAT_COMP_Y_mask);
- SETfield(sq_tex_resource4, SQ_FORMAT_COMP_SIGNED,
- FORMAT_COMP_Z_shift, FORMAT_COMP_Z_mask);
- SETfield(sq_tex_resource4, SQ_FORMAT_COMP_SIGNED,
- FORMAT_COMP_W_shift, FORMAT_COMP_W_mask);
- }
- break;
- case MESA_FORMAT_ARGB8888:
- SETfield(sq_tex_resource7, FMT_8_8_8_8,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
- SETfield(sq_tex_resource4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(sq_tex_resource4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(sq_tex_resource4, SQ_SEL_W,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_XRGB8888:
- SETfield(sq_tex_resource7, FMT_8_8_8_8,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
- SETfield(sq_tex_resource4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(sq_tex_resource4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(sq_tex_resource4, SQ_SEL_1,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_ARGB8888_REV:
- SETfield(sq_tex_resource7, FMT_8_8_8_8,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
- SETfield(sq_tex_resource4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(sq_tex_resource4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(sq_tex_resource4, SQ_SEL_W,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_XRGB8888_REV:
- SETfield(sq_tex_resource7, FMT_8_8_8_8,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
- SETfield(sq_tex_resource4, SQ_SEL_1,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(sq_tex_resource4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(sq_tex_resource4, SQ_SEL_W,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_RGB565:
- SETfield(sq_tex_resource7, FMT_5_6_5,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
- SETfield(sq_tex_resource4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(sq_tex_resource4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(sq_tex_resource4, SQ_SEL_1,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_RGB565_REV:
- SETfield(sq_tex_resource7, FMT_5_6_5,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(sq_tex_resource4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(sq_tex_resource4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(sq_tex_resource4, SQ_SEL_1,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_ARGB4444:
- SETfield(sq_tex_resource7, FMT_4_4_4_4,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
- SETfield(sq_tex_resource4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(sq_tex_resource4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(sq_tex_resource4, SQ_SEL_W,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_ARGB4444_REV:
- SETfield(sq_tex_resource7, FMT_4_4_4_4,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
- SETfield(sq_tex_resource4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(sq_tex_resource4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(sq_tex_resource4, SQ_SEL_W,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_ARGB1555:
- SETfield(sq_tex_resource7, FMT_1_5_5_5,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
- SETfield(sq_tex_resource4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(sq_tex_resource4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(sq_tex_resource4, SQ_SEL_W,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_ARGB1555_REV:
- SETfield(sq_tex_resource7, FMT_1_5_5_5,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
- SETfield(sq_tex_resource4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(sq_tex_resource4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(sq_tex_resource4, SQ_SEL_W,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_AL88:
- case MESA_FORMAT_AL88_REV: /* TODO : Check this. */
- SETfield(sq_tex_resource7, FMT_8_8,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(sq_tex_resource4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_RGB332:
- SETfield(sq_tex_resource7, FMT_3_3_2,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
- SETfield(sq_tex_resource4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(sq_tex_resource4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(sq_tex_resource4, SQ_SEL_1,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_A8: /* ZERO, ZERO, ZERO, X */
- SETfield(sq_tex_resource7, FMT_8,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
- SETfield(sq_tex_resource4, SQ_SEL_0,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(sq_tex_resource4, SQ_SEL_0,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(sq_tex_resource4, SQ_SEL_0,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_L8: /* X, X, X, ONE */
- SETfield(sq_tex_resource7, FMT_8,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(sq_tex_resource4, SQ_SEL_1,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_I8: /* X, X, X, X */
- SETfield(sq_tex_resource7, FMT_8,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_RGBA_FLOAT32:
- SETfield(sq_tex_resource7, FMT_32_32_32_32_FLOAT,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(sq_tex_resource4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(sq_tex_resource4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(sq_tex_resource4, SQ_SEL_W,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_RGBA_FLOAT16:
- SETfield(sq_tex_resource7, FMT_16_16_16_16_FLOAT,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(sq_tex_resource4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(sq_tex_resource4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(sq_tex_resource4, SQ_SEL_W,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_ALPHA_FLOAT32: /* ZERO, ZERO, ZERO, X */
- SETfield(sq_tex_resource7, FMT_32_FLOAT,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
- SETfield(sq_tex_resource4, SQ_SEL_0,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(sq_tex_resource4, SQ_SEL_0,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(sq_tex_resource4, SQ_SEL_0,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_ALPHA_FLOAT16: /* ZERO, ZERO, ZERO, X */
- SETfield(sq_tex_resource7, FMT_16_FLOAT,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
- SETfield(sq_tex_resource4, SQ_SEL_0,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(sq_tex_resource4, SQ_SEL_0,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(sq_tex_resource4, SQ_SEL_0,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_LUMINANCE_FLOAT32: /* X, X, X, ONE */
- SETfield(sq_tex_resource7, FMT_32_FLOAT,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(sq_tex_resource4, SQ_SEL_1,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_LUMINANCE_FLOAT16: /* X, X, X, ONE */
- SETfield(sq_tex_resource7, FMT_16_FLOAT,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(sq_tex_resource4, SQ_SEL_1,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32:
- SETfield(sq_tex_resource7, FMT_32_32_FLOAT,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(sq_tex_resource4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16:
- SETfield(sq_tex_resource7, FMT_16_16_FLOAT,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(sq_tex_resource4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_INTENSITY_FLOAT32: /* X, X, X, X */
- SETfield(sq_tex_resource7, FMT_32_FLOAT,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_INTENSITY_FLOAT16: /* X, X, X, X */
- SETfield(sq_tex_resource7, FMT_16_FLOAT,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_Z16:
- /* ??? */
- CLEARbit(sq_tex_resource0, EG_SQ_TEX_RESOURCE_WORD0_0__NDTO_bit);
- SETfield(sq_tex_resource1, ARRAY_1D_TILED_THIN1,
- EG_SQ_TEX_RESOURCE_WORD1_0__ARRAY_MODE_shift,
- EG_SQ_TEX_RESOURCE_WORD1_0__ARRAY_MODE_mask);
- SETfield(sq_tex_resource7, FMT_16,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_X8_Z24:
- /* ??? */
- CLEARbit(sq_tex_resource0, EG_SQ_TEX_RESOURCE_WORD0_0__NDTO_bit);
- SETfield(sq_tex_resource1, ARRAY_1D_TILED_THIN1,
- EG_SQ_TEX_RESOURCE_WORD1_0__ARRAY_MODE_shift,
- EG_SQ_TEX_RESOURCE_WORD1_0__ARRAY_MODE_mask);
- SETfield(sq_tex_resource7, FMT_8_24,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(sq_tex_resource4, SQ_SEL_1,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(sq_tex_resource4, SQ_SEL_0,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(sq_tex_resource4, SQ_SEL_1,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_S8_Z24:
- /* ??? */
- CLEARbit(sq_tex_resource0, EG_SQ_TEX_RESOURCE_WORD0_0__NDTO_bit);
- SETfield(sq_tex_resource1, ARRAY_1D_TILED_THIN1,
- EG_SQ_TEX_RESOURCE_WORD1_0__ARRAY_MODE_shift,
- EG_SQ_TEX_RESOURCE_WORD1_0__ARRAY_MODE_mask);
- SETbit(sq_tex_resource0, TILE_TYPE_bit);
- SETfield(sq_tex_resource0, ARRAY_1D_TILED_THIN1,
- SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift,
- SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask);
- SETfield(sq_tex_resource7, FMT_8_24,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(sq_tex_resource4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(sq_tex_resource4, SQ_SEL_0,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(sq_tex_resource4, SQ_SEL_1,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_Z24_S8:
- /* ??? */
- CLEARbit(sq_tex_resource0, EG_SQ_TEX_RESOURCE_WORD0_0__NDTO_bit);
- SETfield(sq_tex_resource1, ARRAY_1D_TILED_THIN1,
- EG_SQ_TEX_RESOURCE_WORD1_0__ARRAY_MODE_shift,
- EG_SQ_TEX_RESOURCE_WORD1_0__ARRAY_MODE_mask);
- SETbit(sq_tex_resource0, TILE_TYPE_bit);
- SETfield(sq_tex_resource0, ARRAY_1D_TILED_THIN1,
- SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift,
- SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask);
- SETfield(sq_tex_resource7, FMT_24_8,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(sq_tex_resource4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(sq_tex_resource4, SQ_SEL_0,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(sq_tex_resource4, SQ_SEL_1,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_Z32:
- /* ??? */
- CLEARbit(sq_tex_resource0, EG_SQ_TEX_RESOURCE_WORD0_0__NDTO_bit);
- SETfield(sq_tex_resource1, ARRAY_1D_TILED_THIN1,
- EG_SQ_TEX_RESOURCE_WORD1_0__ARRAY_MODE_shift,
- EG_SQ_TEX_RESOURCE_WORD1_0__ARRAY_MODE_mask);
- SETbit(sq_tex_resource0, TILE_TYPE_bit);
- SETfield(sq_tex_resource0, ARRAY_1D_TILED_THIN1,
- SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift,
- SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask);
- SETfield(sq_tex_resource7, FMT_32,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_S8:
- /* ??? */
- CLEARbit(sq_tex_resource0, EG_SQ_TEX_RESOURCE_WORD0_0__NDTO_bit);
- SETfield(sq_tex_resource1, ARRAY_1D_TILED_THIN1,
- EG_SQ_TEX_RESOURCE_WORD1_0__ARRAY_MODE_shift,
- EG_SQ_TEX_RESOURCE_WORD1_0__ARRAY_MODE_mask);
- SETfield(sq_tex_resource7, FMT_8,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_SARGB8:
- SETfield(sq_tex_resource7, FMT_8_8_8_8,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
- SETfield(sq_tex_resource4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(sq_tex_resource4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(sq_tex_resource4, SQ_SEL_W,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- SETbit(sq_tex_resource4, SQ_TEX_RESOURCE_WORD4_0__FORCE_DEGAMMA_bit);
- break;
- case MESA_FORMAT_SLA8:
- SETfield(sq_tex_resource7, FMT_8_8,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(sq_tex_resource4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- SETbit(sq_tex_resource4, SQ_TEX_RESOURCE_WORD4_0__FORCE_DEGAMMA_bit);
- break;
- case MESA_FORMAT_SL8: /* X, X, X, ONE */
- SETfield(sq_tex_resource7, FMT_8,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(sq_tex_resource4, SQ_SEL_1,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- SETbit(sq_tex_resource4, SQ_TEX_RESOURCE_WORD4_0__FORCE_DEGAMMA_bit);
- break;
- default:
- fprintf(stderr,"Invalid format for copy %s\n",_mesa_get_format_name(mesa_format));
- assert("Invalid format for US output\n");
- return;
- };
-
- SETfield(sq_tex_resource0, (TexelPitch/8)-1,
- EG_SQ_TEX_RESOURCE_WORD0_0__PITCH_shift,
- EG_SQ_TEX_RESOURCE_WORD0_0__PITCH_mask);
- SETfield(sq_tex_resource0, w - 1,
- EG_SQ_TEX_RESOURCE_WORD0_0__TEX_WIDTH_shift,
- EG_SQ_TEX_RESOURCE_WORD0_0__TEX_WIDTH_mask);
- SETfield(sq_tex_resource1, h - 1,
- EG_SQ_TEX_RESOURCE_WORD1_0__TEX_HEIGHT_shift,
- EG_SQ_TEX_RESOURCE_WORD1_0__TEX_HEIGHT_mask);
-
- sq_tex_resource2 = src_offset / 256;
-
- SETfield(sq_tex_resource7, SQ_TEX_VTX_VALID_TEXTURE,
- SQ_TEX_RESOURCE_WORD6_0__TYPE_shift,
- SQ_TEX_RESOURCE_WORD6_0__TYPE_mask);
-
- r700SyncSurf(context, bo,
- RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM,
- 0, TC_ACTION_ENA_bit);
-
- BEGIN_BATCH_NO_AUTOSTATE(10 + 4);
- R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 8));
- R600_OUT_BATCH(0 * 7);
- R600_OUT_BATCH(sq_tex_resource0);
- R600_OUT_BATCH(sq_tex_resource1);
- R600_OUT_BATCH(sq_tex_resource2);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(sq_tex_resource4);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(sq_tex_resource7);
- R600_OUT_BATCH_RELOC(0,
- bo,
- 0,
- RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
- R600_OUT_BATCH_RELOC(0,
- bo,
- 0,
- RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
- END_BATCH();
- COMMIT_BATCH();
-}
-
-static inline void
-eg_set_tex_sampler(context_t * context)
-{
- uint32_t sq_tex_sampler_word0 = 0, sq_tex_sampler_word1 = 0, sq_tex_sampler_word2 = 0;
- int i = 0;
-
- SETbit(sq_tex_sampler_word2, EG_SQ_TEX_SAMPLER_WORD2_0__TYPE_bit);
-
- BATCH_LOCALS(&context->radeon);
-
- BEGIN_BATCH_NO_AUTOSTATE(5);
- R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_SAMPLER, 3));
- R600_OUT_BATCH(i * 3);
- R600_OUT_BATCH(sq_tex_sampler_word0);
- R600_OUT_BATCH(sq_tex_sampler_word1);
- R600_OUT_BATCH(sq_tex_sampler_word2);
- END_BATCH();
-
-}
-
-static inline void
-eg_set_scissors(context_t *context, int x1, int y1, int x2, int y2)
-{
- BATCH_LOCALS(&context->radeon);
-
- BEGIN_BATCH_NO_AUTOSTATE(17);
- EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_SCREEN_SCISSOR_TL, 2);
- R600_OUT_BATCH((x1 << 0) | (y1 << 16));
- R600_OUT_BATCH((x2 << 0) | (y2 << 16));
-
- EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_WINDOW_OFFSET, 3);
- R600_OUT_BATCH(0); //PA_SC_WINDOW_OFFSET
- R600_OUT_BATCH((x1 << 0) | (y1 << 16) | (WINDOW_OFFSET_DISABLE_bit)); //PA_SC_WINDOW_SCISSOR_TL
- R600_OUT_BATCH((x2 << 0) | (y2 << 16));
-
- EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_GENERIC_SCISSOR_TL, 2);
- R600_OUT_BATCH((x1 << 0) | (y1 << 16) | (WINDOW_OFFSET_DISABLE_bit));
- R600_OUT_BATCH((x2 << 0) | (y2 << 16));
-
- /* XXX 16 of these PA_SC_VPORT_SCISSOR_0_TL_num ... */
- EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_VPORT_SCISSOR_0_TL, 2);
- R600_OUT_BATCH((x1 << 0) | (y1 << 16) | (WINDOW_OFFSET_DISABLE_bit));
- R600_OUT_BATCH((x2 << 0) | (y2 << 16));
- END_BATCH();
-
- COMMIT_BATCH();
-
-}
-
-static inline void
-eg_set_vb_data(context_t * context, int src_x, int src_y, int dst_x, int dst_y,
- int w, int h, int src_h, unsigned flip_y)
-{
- float *vb;
- radeon_bo_map(context->blit_bo, 1);
- vb = context->blit_bo->ptr;
-
- vb[0] = (float)(dst_x);
- vb[1] = (float)(dst_y);
- vb[2] = (float)(src_x);
- vb[3] = (flip_y) ? (float)(src_h - src_y) : (float)src_y;
-
- vb[4] = (float)(dst_x);
- vb[5] = (float)(dst_y + h);
- vb[6] = (float)(src_x);
- vb[7] = (flip_y) ? (float)(src_h - (src_y + h)) : (float)(src_y + h);
-
- vb[8] = (float)(dst_x + w);
- vb[9] = (float)(dst_y + h);
- vb[10] = (float)(src_x + w);
- vb[11] = (flip_y) ? (float)(src_h - (src_y + h)) : (float)(src_y + h);
-
- radeon_bo_unmap(context->blit_bo);
-
-}
-
-static inline void
-eg_draw_auto(context_t *context)
-{
- BATCH_LOCALS(&context->radeon);
- uint32_t vgt_primitive_type = 0, vgt_index_type = 0, vgt_draw_initiator = 0, vgt_num_indices;
-
- SETfield(vgt_primitive_type, DI_PT_RECTLIST,
- VGT_PRIMITIVE_TYPE__PRIM_TYPE_shift,
- VGT_PRIMITIVE_TYPE__PRIM_TYPE_mask);
- SETfield(vgt_index_type, DI_INDEX_SIZE_16_BIT, INDEX_TYPE_shift,
- INDEX_TYPE_mask);
- SETfield(vgt_draw_initiator, DI_MAJOR_MODE_0, MAJOR_MODE_shift,
- MAJOR_MODE_mask);
- SETfield(vgt_draw_initiator, DI_SRC_SEL_AUTO_INDEX, SOURCE_SELECT_shift,
- SOURCE_SELECT_mask);
-
- vgt_num_indices = 3;
-
- BEGIN_BATCH_NO_AUTOSTATE(10);
- // prim
- EVERGREEN_OUT_BATCH_REGSEQ(EG_VGT_PRIMITIVE_TYPE, 1);
- R600_OUT_BATCH(vgt_primitive_type);
- // index type
- R600_OUT_BATCH(CP_PACKET3(R600_IT_INDEX_TYPE, 0));
- R600_OUT_BATCH(vgt_index_type);
- // num instances
- R600_OUT_BATCH(CP_PACKET3(R600_IT_NUM_INSTANCES, 0));
- R600_OUT_BATCH(1);
- //
- R600_OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX_AUTO, 1));
- R600_OUT_BATCH(vgt_num_indices);
- R600_OUT_BATCH(vgt_draw_initiator);
-
- END_BATCH();
- COMMIT_BATCH();
-}
-
-static inline void
-eg_set_default_state(context_t *context)
-{
- int num_ps_gprs;
- int num_vs_gprs;
- int num_gs_gprs;
- int num_es_gprs;
- int num_hs_gprs;
- int num_ls_gprs;
- int num_temp_gprs;
- int num_ps_threads;
- int num_vs_threads;
- int num_gs_threads;
- int num_es_threads;
- int num_hs_threads;
- int num_ls_threads;
- int num_ps_stack_entries;
- int num_vs_stack_entries;
- int num_gs_stack_entries;
- int num_es_stack_entries;
- int num_hs_stack_entries;
- int num_ls_stack_entries;
- uint32_t sq_config = 0, sq_gpr_resource_mgmt_1 = 0, sq_gpr_resource_mgmt_2 = 0;
- uint32_t sq_gpr_resource_mgmt_3 = 0;
- uint32_t sq_thread_resource_mgmt = 0, sq_thread_resource_mgmt_2 = 0;
- uint32_t sq_stack_resource_mgmt_1 = 0, sq_stack_resource_mgmt_2 = 0, sq_stack_resource_mgmt_3 = 0;
- BATCH_LOCALS(&context->radeon);
-
- switch (context->radeon.radeonScreen->chip_family) {
- case CHIP_FAMILY_CEDAR:
- default:
- num_ps_gprs = 93;
- num_vs_gprs = 46;
- num_temp_gprs = 4;
- num_gs_gprs = 31;
- num_es_gprs = 31;
- num_hs_gprs = 23;
- num_ls_gprs = 23;
- num_ps_threads = 96;
- num_vs_threads = 16;
- num_gs_threads = 16;
- num_es_threads = 16;
- num_hs_threads = 16;
- num_ls_threads = 16;
- num_ps_stack_entries = 42;
- num_vs_stack_entries = 42;
- num_gs_stack_entries = 42;
- num_es_stack_entries = 42;
- num_hs_stack_entries = 42;
- num_ls_stack_entries = 42;
- break;
- case CHIP_FAMILY_REDWOOD:
- num_ps_gprs = 93;
- num_vs_gprs = 46;
- num_temp_gprs = 4;
- num_gs_gprs = 31;
- num_es_gprs = 31;
- num_hs_gprs = 23;
- num_ls_gprs = 23;
- num_ps_threads = 128;
- num_vs_threads = 20;
- num_gs_threads = 20;
- num_es_threads = 20;
- num_hs_threads = 20;
- num_ls_threads = 20;
- num_ps_stack_entries = 42;
- num_vs_stack_entries = 42;
- num_gs_stack_entries = 42;
- num_es_stack_entries = 42;
- num_hs_stack_entries = 42;
- num_ls_stack_entries = 42;
- break;
- case CHIP_FAMILY_JUNIPER:
- num_ps_gprs = 93;
- num_vs_gprs = 46;
- num_temp_gprs = 4;
- num_gs_gprs = 31;
- num_es_gprs = 31;
- num_hs_gprs = 23;
- num_ls_gprs = 23;
- num_ps_threads = 128;
- num_vs_threads = 20;
- num_gs_threads = 20;
- num_es_threads = 20;
- num_hs_threads = 20;
- num_ls_threads = 20;
- num_ps_stack_entries = 85;
- num_vs_stack_entries = 85;
- num_gs_stack_entries = 85;
- num_es_stack_entries = 85;
- num_hs_stack_entries = 85;
- num_ls_stack_entries = 85;
- break;
- case CHIP_FAMILY_CYPRESS:
- case CHIP_FAMILY_HEMLOCK:
- num_ps_gprs = 93;
- num_vs_gprs = 46;
- num_temp_gprs = 4;
- num_gs_gprs = 31;
- num_es_gprs = 31;
- num_hs_gprs = 23;
- num_ls_gprs = 23;
- num_ps_threads = 128;
- num_vs_threads = 20;
- num_gs_threads = 20;
- num_es_threads = 20;
- num_hs_threads = 20;
- num_ls_threads = 20;
- num_ps_stack_entries = 85;
- num_vs_stack_entries = 85;
- num_gs_stack_entries = 85;
- num_es_stack_entries = 85;
- num_hs_stack_entries = 85;
- num_ls_stack_entries = 85;
- break;
- case CHIP_FAMILY_PALM:
- num_ps_gprs = 93;
- num_vs_gprs = 46;
- num_temp_gprs = 4;
- num_gs_gprs = 31;
- num_es_gprs = 31;
- num_hs_gprs = 23;
- num_ls_gprs = 23;
- num_ps_threads = 96;
- num_vs_threads = 16;
- num_gs_threads = 16;
- num_es_threads = 16;
- num_hs_threads = 16;
- num_ls_threads = 16;
- num_ps_stack_entries = 42;
- num_vs_stack_entries = 42;
- num_gs_stack_entries = 42;
- num_es_stack_entries = 42;
- num_hs_stack_entries = 42;
- num_ls_stack_entries = 42;
- break;
- case CHIP_FAMILY_SUMO:
- num_ps_gprs = 93;
- num_vs_gprs = 46;
- num_temp_gprs = 4;
- num_gs_gprs = 31;
- num_es_gprs = 31;
- num_hs_gprs = 23;
- num_ls_gprs = 23;
- num_ps_threads = 96;
- num_vs_threads = 25;
- num_gs_threads = 25;
- num_es_threads = 25;
- num_hs_threads = 25;
- num_ls_threads = 25;
- num_ps_stack_entries = 42;
- num_vs_stack_entries = 42;
- num_gs_stack_entries = 42;
- num_es_stack_entries = 42;
- num_hs_stack_entries = 42;
- num_ls_stack_entries = 42;
- break;
- case CHIP_FAMILY_SUMO2:
- num_ps_gprs = 93;
- num_vs_gprs = 46;
- num_temp_gprs = 4;
- num_gs_gprs = 31;
- num_es_gprs = 31;
- num_hs_gprs = 23;
- num_ls_gprs = 23;
- num_ps_threads = 96;
- num_vs_threads = 25;
- num_gs_threads = 25;
- num_es_threads = 25;
- num_hs_threads = 25;
- num_ls_threads = 25;
- num_ps_stack_entries = 85;
- num_vs_stack_entries = 85;
- num_gs_stack_entries = 85;
- num_es_stack_entries = 85;
- num_hs_stack_entries = 85;
- num_ls_stack_entries = 85;
- break;
- case CHIP_FAMILY_BARTS:
- num_ps_gprs = 93;
- num_vs_gprs = 46;
- num_temp_gprs = 4;
- num_gs_gprs = 31;
- num_es_gprs = 31;
- num_hs_gprs = 23;
- num_ls_gprs = 23;
- num_ps_threads = 128;
- num_vs_threads = 20;
- num_gs_threads = 20;
- num_es_threads = 20;
- num_hs_threads = 20;
- num_ls_threads = 20;
- num_ps_stack_entries = 85;
- num_vs_stack_entries = 85;
- num_gs_stack_entries = 85;
- num_es_stack_entries = 85;
- num_hs_stack_entries = 85;
- num_ls_stack_entries = 85;
- break;
- case CHIP_FAMILY_TURKS:
- num_ps_gprs = 93;
- num_vs_gprs = 46;
- num_temp_gprs = 4;
- num_gs_gprs = 31;
- num_es_gprs = 31;
- num_hs_gprs = 23;
- num_ls_gprs = 23;
- num_ps_threads = 128;
- num_vs_threads = 20;
- num_gs_threads = 20;
- num_es_threads = 20;
- num_hs_threads = 20;
- num_ls_threads = 20;
- num_ps_stack_entries = 42;
- num_vs_stack_entries = 42;
- num_gs_stack_entries = 42;
- num_es_stack_entries = 42;
- num_hs_stack_entries = 42;
- num_ls_stack_entries = 42;
- break;
- case CHIP_FAMILY_CAICOS:
- num_ps_gprs = 93;
- num_vs_gprs = 46;
- num_temp_gprs = 4;
- num_gs_gprs = 31;
- num_es_gprs = 31;
- num_hs_gprs = 23;
- num_ls_gprs = 23;
- num_ps_threads = 128;
- num_vs_threads = 10;
- num_gs_threads = 10;
- num_es_threads = 10;
- num_hs_threads = 10;
- num_ls_threads = 10;
- num_ps_stack_entries = 42;
- num_vs_stack_entries = 42;
- num_gs_stack_entries = 42;
- num_es_stack_entries = 42;
- num_hs_stack_entries = 42;
- num_ls_stack_entries = 42;
- break;
- }
-
- if ((context->radeon.radeonScreen->chip_family == CHIP_FAMILY_CEDAR) ||
- (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_PALM) ||
- (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_SUMO) ||
- (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_SUMO2) ||
- (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_CAICOS))
- CLEARbit(sq_config, EG_SQ_CONFIG__VC_ENABLE_bit);
- else
- SETbit(sq_config, EG_SQ_CONFIG__VC_ENABLE_bit);
- SETbit(sq_config, EG_SQ_CONFIG__EXPORT_SRC_C_bit);
-
- SETfield(sq_config, 0,
- EG_SQ_CONFIG__PS_PRIO_shift,
- EG_SQ_CONFIG__PS_PRIO_mask);
- SETfield(sq_config, 1,
- EG_SQ_CONFIG__VS_PRIO_shift,
- EG_SQ_CONFIG__VS_PRIO_mask);
- SETfield(sq_config, 2,
- EG_SQ_CONFIG__GS_PRIO_shift,
- EG_SQ_CONFIG__GS_PRIO_mask);
- SETfield(sq_config, 3,
- EG_SQ_CONFIG__ES_PRIO_shift,
- EG_SQ_CONFIG__ES_PRIO_mask);
-
-
- SETfield(sq_gpr_resource_mgmt_1, num_ps_gprs,
- NUM_PS_GPRS_shift, NUM_PS_GPRS_mask);
- SETfield(sq_gpr_resource_mgmt_1, num_vs_gprs,
- NUM_VS_GPRS_shift, NUM_VS_GPRS_mask);
- SETfield(sq_gpr_resource_mgmt_1, num_temp_gprs,
- NUM_CLAUSE_TEMP_GPRS_shift, NUM_CLAUSE_TEMP_GPRS_mask);
- SETfield(sq_gpr_resource_mgmt_2, num_gs_gprs,
- NUM_GS_GPRS_shift, NUM_GS_GPRS_mask);
- SETfield(sq_gpr_resource_mgmt_2, num_es_gprs,
- NUM_ES_GPRS_shift, NUM_ES_GPRS_mask);
- SETfield(sq_gpr_resource_mgmt_3, num_hs_gprs,
- NUM_PS_GPRS_shift, NUM_PS_GPRS_mask);
- SETfield(sq_gpr_resource_mgmt_3, num_ls_gprs,
- NUM_VS_GPRS_shift, NUM_VS_GPRS_mask);
-
- SETfield(sq_thread_resource_mgmt, num_ps_threads,
- NUM_PS_THREADS_shift, NUM_PS_THREADS_mask);
- SETfield(sq_thread_resource_mgmt, num_vs_threads,
- NUM_VS_THREADS_shift, NUM_VS_THREADS_mask);
- SETfield(sq_thread_resource_mgmt, num_gs_threads,
- NUM_GS_THREADS_shift, NUM_GS_THREADS_mask);
- SETfield(sq_thread_resource_mgmt, num_es_threads,
- NUM_ES_THREADS_shift, NUM_ES_THREADS_mask);
- SETfield(sq_thread_resource_mgmt_2, num_hs_threads,
- NUM_PS_THREADS_shift, NUM_PS_THREADS_mask);
- SETfield(sq_thread_resource_mgmt_2, num_ls_threads,
- NUM_VS_THREADS_shift, NUM_VS_THREADS_mask);
-
- SETfield(sq_stack_resource_mgmt_1, num_ps_stack_entries,
- NUM_PS_STACK_ENTRIES_shift, NUM_PS_STACK_ENTRIES_mask);
- SETfield(sq_stack_resource_mgmt_1, num_vs_stack_entries,
- NUM_VS_STACK_ENTRIES_shift, NUM_VS_STACK_ENTRIES_mask);
- SETfield(sq_stack_resource_mgmt_2, num_gs_stack_entries,
- NUM_GS_STACK_ENTRIES_shift, NUM_GS_STACK_ENTRIES_mask);
- SETfield(sq_stack_resource_mgmt_2, num_es_stack_entries,
- NUM_ES_STACK_ENTRIES_shift, NUM_ES_STACK_ENTRIES_mask);
- SETfield(sq_stack_resource_mgmt_3, num_hs_stack_entries,
- NUM_PS_STACK_ENTRIES_shift, NUM_PS_STACK_ENTRIES_mask);
- SETfield(sq_stack_resource_mgmt_3, num_ls_stack_entries,
- NUM_VS_STACK_ENTRIES_shift, NUM_VS_STACK_ENTRIES_mask);
-
-
- BEGIN_BATCH_NO_AUTOSTATE(196);
- //3
- EVERGREEN_OUT_BATCH_REGVAL(EG_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
- //6
- EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_CONFIG, 4);
- R600_OUT_BATCH(sq_config);
- R600_OUT_BATCH(sq_gpr_resource_mgmt_1);
- R600_OUT_BATCH(sq_gpr_resource_mgmt_2);
- R600_OUT_BATCH(sq_gpr_resource_mgmt_3);
- //7
- EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_THREAD_RESOURCE_MGMT, 5);
- R600_OUT_BATCH(sq_thread_resource_mgmt);
- R600_OUT_BATCH(sq_thread_resource_mgmt_2);
- R600_OUT_BATCH(sq_stack_resource_mgmt_1);
- R600_OUT_BATCH(sq_stack_resource_mgmt_2);
- R600_OUT_BATCH(sq_stack_resource_mgmt_3);
- //3
- R600_OUT_BATCH(CP_PACKET3(R600_IT_CONTEXT_CONTROL, 1));
- R600_OUT_BATCH(0x80000000);
- R600_OUT_BATCH(0x80000000);
- //3
- EVERGREEN_OUT_BATCH_REGVAL(EG_SQ_LDS_ALLOC_PS, 0);
- //8
- EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_ESGS_RING_ITEMSIZE, 6);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
- //6
- EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_GS_VERT_ITEMSIZE, 4);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
- //3
- EVERGREEN_OUT_BATCH_REGVAL(EG_DB_DEPTH_CONTROL, 0);
- //7
- EVERGREEN_OUT_BATCH_REGSEQ(EG_DB_RENDER_CONTROL, 5);
- R600_OUT_BATCH(0x00000060);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0x0000002a);
- R600_OUT_BATCH(0);
- //4
- EVERGREEN_OUT_BATCH_REGSEQ(EG_DB_STENCIL_CLEAR, 2);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
- //3
- EVERGREEN_OUT_BATCH_REGVAL(EG_DB_ALPHA_TO_MASK, 0x0000aa00);
- //15
- EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_CLIPRECT_RULE, 13);
- R600_OUT_BATCH(0x0000ffff);
- R600_OUT_BATCH(0x00000000);
- R600_OUT_BATCH(0x20002000);
- R600_OUT_BATCH(0x00000000);
- R600_OUT_BATCH(0x20002000);
- R600_OUT_BATCH(0x00000000);
- R600_OUT_BATCH(0x20002000);
- R600_OUT_BATCH(0x00000000);
- R600_OUT_BATCH(0x20002000);
- R600_OUT_BATCH(0xaaaaaaaa);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0x0000000f);
- R600_OUT_BATCH(0x0000000f);
- //4
- EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_VPORT_ZMIN_0, 2);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0x3f800000);
- //3
- EVERGREEN_OUT_BATCH_REGVAL(EG_SX_MISC, 0);
- //4
- EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_MODE_CNTL_0, 2);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
- //18
- EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_LINE_CNTL, 16);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0x00000005);
- R600_OUT_BATCH(0x3f800000);
- R600_OUT_BATCH(0x3f800000);
- R600_OUT_BATCH(0x3f800000);
- R600_OUT_BATCH(0x3f800000);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0xffffffff);
- //15
- EVERGREEN_OUT_BATCH_REGSEQ(EG_CB_COLOR_CONTROL, 13);
- R600_OUT_BATCH(0x00cc0010);
- R600_OUT_BATCH(0x00000210);
- R600_OUT_BATCH(0x00010000);
- R600_OUT_BATCH(0x00000004);
- R600_OUT_BATCH(0x00000100);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
- //8
- EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 6);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
- //11
- EVERGREEN_OUT_BATCH_REGSEQ(EG_VGT_MAX_VTX_INDX, 9);
- R600_OUT_BATCH(0x00ffffff);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
- //4
- EVERGREEN_OUT_BATCH_REGSEQ(EG_VGT_INSTANCE_STEP_RATE_0, 2);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
- //4
- EVERGREEN_OUT_BATCH_REGSEQ(EG_VGT_REUSE_OFF, 2);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
- //19
- EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SU_POINT_SIZE, 17);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0x00000008);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
- //3
- EVERGREEN_OUT_BATCH_REGVAL(EG_VGT_PRIMITIVEID_EN, 0);
- //3
- EVERGREEN_OUT_BATCH_REGVAL(EG_VGT_MULTI_PRIM_IB_RESET_EN, 0);
- //3
- EVERGREEN_OUT_BATCH_REGVAL(EG_VGT_SHADER_STAGES_EN, 0);
- //4
- EVERGREEN_OUT_BATCH_REGSEQ(EG_VGT_STRMOUT_CONFIG, 2);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
- //3
- EVERGREEN_OUT_BATCH_REGVAL(EG_CB_BLEND0_CONTROL, 0);
- //3
- EVERGREEN_OUT_BATCH_REGVAL(EG_SPI_VS_OUT_CONFIG, 0);
- //3
- EVERGREEN_OUT_BATCH_REGVAL(EG_SPI_VS_OUT_ID_0, 0);
- //3
- EVERGREEN_OUT_BATCH_REGVAL(EG_SPI_PS_INPUT_CNTL_0, 0);
- //13
- EVERGREEN_OUT_BATCH_REGSEQ(EG_SPI_PS_IN_CONTROL_0, 11);
- R600_OUT_BATCH(0x20000001);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0x00100000);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
-
- END_BATCH();
- COMMIT_BATCH();
-}
-
-static GLboolean eg_validate_buffers(context_t *rmesa,
- struct radeon_bo *src_bo,
- struct radeon_bo *dst_bo)
-{
- int ret;
-
- radeon_cs_space_reset_bos(rmesa->radeon.cmdbuf.cs);
-
- ret = radeon_cs_space_check_with_bo(rmesa->radeon.cmdbuf.cs,
- src_bo, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0);
- if (ret)
- return GL_FALSE;
-
- ret = radeon_cs_space_check_with_bo(rmesa->radeon.cmdbuf.cs,
- dst_bo, 0, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT);
- if (ret)
- return GL_FALSE;
-
- ret = radeon_cs_space_check_with_bo(rmesa->radeon.cmdbuf.cs,
- rmesa->blit_bo,
- RADEON_GEM_DOMAIN_GTT, 0);
- if (ret)
- return GL_FALSE;
-
- return GL_TRUE;
-}
-
-unsigned evergreen_blit(struct gl_context *ctx,
- struct radeon_bo *src_bo,
- intptr_t src_offset,
- gl_format src_mesaformat,
- unsigned src_pitch,
- unsigned src_width,
- unsigned src_height,
- unsigned src_x,
- unsigned src_y,
- struct radeon_bo *dst_bo,
- intptr_t dst_offset,
- gl_format dst_mesaformat,
- unsigned dst_pitch,
- unsigned dst_width,
- unsigned dst_height,
- unsigned dst_x,
- unsigned dst_y,
- unsigned w,
- unsigned h,
- unsigned flip_y)
-{
- context_t *context = EVERGREEN_CONTEXT(ctx);
- int id = 0;
-
- if (!evergreen_check_blit(dst_mesaformat))
- return GL_FALSE;
-
- if (src_bo == dst_bo) {
- return GL_FALSE;
- }
-
- if (src_offset % 256 || dst_offset % 256) {
- return GL_FALSE;
- }
-
- if (0) {
- fprintf(stderr, "src: width %d, height %d, pitch %d vs %d, format %s\n",
- src_width, src_height, src_pitch,
- _mesa_format_row_stride(src_mesaformat, src_width),
- _mesa_get_format_name(src_mesaformat));
- fprintf(stderr, "dst: width %d, height %d, pitch %d, format %s\n",
- dst_width, dst_height,
- _mesa_format_row_stride(dst_mesaformat, dst_width),
- _mesa_get_format_name(dst_mesaformat));
- }
-
- /* Flush is needed to make sure that source buffer has correct data */
- radeonFlush(ctx);
-
- rcommonEnsureCmdBufSpace(&context->radeon, 327, __FUNCTION__);
-
- /* load shaders */
- eg_load_shaders(context->radeon.glCtx);
-
- if (!eg_validate_buffers(context, src_bo, dst_bo))
- return GL_FALSE;
-
- /* set clear state */
- /* 196 */
- eg_set_default_state(context);
-
- /* shaders */
- /* 34 */
- eg_set_shaders(context);
-
- /* src */
- /* 21 */
- eg_set_tex_resource(context, src_mesaformat, src_bo,
- src_width, src_height, src_pitch, src_offset);
-
- /* 5 */
- eg_set_tex_sampler(context);
-
- /* dst */
- /* 19 */
- eg_set_render_target(context, dst_bo, dst_mesaformat,
- dst_pitch, dst_width, dst_height, dst_offset);
- /* scissors */
- /* 17 */
- eg_set_scissors(context, dst_x, dst_y, dst_x + dst_width, dst_y + dst_height);
-
- eg_set_vb_data(context, src_x, src_y, dst_x, dst_y, w, h, src_height, flip_y);
- /* Vertex buffer setup */
- /* 18 */
- eg_set_vtx_resource(context);
-
- /* draw */
- /* 10 */
- eg_draw_auto(context);
-
- /* 7 */
- r700SyncSurf(context, dst_bo, 0,
- RADEON_GEM_DOMAIN_VRAM|RADEON_GEM_DOMAIN_GTT,
- CB_ACTION_ENA_bit | (1 << (id + 6)));
-
- radeonFlush(ctx);
-
- return GL_TRUE;
-}
+++ /dev/null
-/*
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial
- * portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
- * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
- * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
- * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-
-#ifndef EVERGREEN_BLIT_H
-#define EVERGREEN_BLIT_H
-
-unsigned evergreen_check_blit(gl_format mesa_format);
-
-unsigned evergreen_blit(struct gl_context *ctx,
- struct radeon_bo *src_bo,
- intptr_t src_offset,
- gl_format src_mesaformat,
- unsigned src_pitch,
- unsigned src_width,
- unsigned src_height,
- unsigned src_x_offset,
- unsigned src_y_offset,
- struct radeon_bo *dst_bo,
- intptr_t dst_offset,
- gl_format dst_mesaformat,
- unsigned dst_pitch,
- unsigned dst_width,
- unsigned dst_height,
- unsigned dst_x_offset,
- unsigned dst_y_offset,
- unsigned w,
- unsigned h,
- unsigned flip_y);
-
-#endif // EVERGREEN_BLIT_H
+++ /dev/null
-/*
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial
- * portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
- * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
- * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
- * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-
-const uint32_t evergreen_vs[] =
-{
- 0x00000004,
- 0x80800400,
- 0x0000a03c,
- 0x95000688,
- 0x00004000,
- 0x15200688,
- 0x00000000,
- 0x00000000,
- 0x3c000000,
- 0x67961001,
-#ifdef MESA_BIG_ENDIAN
- 0x000a0000,
-#else
- 0x00080000,
-#endif
- 0x00000000,
- 0x1c000000,
- 0x67961000,
-#ifdef MESA_BIG_ENDIAN
- 0x00020008,
-#else
- 0x00000008,
-#endif
- 0x00000000,
-};
-
-const uint32_t evergreen_ps[] =
-{
- 0x00000003,
- 0xa00c0000,
- 0x00000008,
- 0x80400000,
- 0x00000000,
- 0x95200688,
- 0x00380400,
- 0x00146b10,
- 0x00380000,
- 0x20146b10,
- 0x00380400,
- 0x40146b00,
- 0x80380000,
- 0x60146b00,
- 0x00000000,
- 0x00000000,
- 0x00000010,
- 0x000d1000,
- 0xb0800000,
- 0x00000000,
-};
-
+++ /dev/null
-/*
- * Copyright (C) 2008-2010 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Authors:
- * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
- */
-
-#include "main/imports.h"
-#include "main/glheader.h"
-#include "main/simple_list.h"
-
-#include "r600_context.h"
-#include "r600_cmdbuf.h"
-
-#include "evergreen_chip.h"
-#include "evergreen_off.h"
-#include "evergreen_diff.h"
-#include "evergreen_fragprog.h"
-#include "evergreen_vertprog.h"
-
-#include "radeon_mipmap_tree.h"
-
-void evergreenCreateChip(context_t *context)
-{
- EVERGREEN_CHIP_CONTEXT * evergreen =
- (EVERGREEN_CHIP_CONTEXT*) CALLOC(sizeof(EVERGREEN_CHIP_CONTEXT));
-
- context->pChip = (void*)evergreen;
-}
-
-#define EVERGREEN_ALLOC_STATE( ATOM, CHK, SZ, EMIT ) \
-do { \
- context->evergreen_atoms.ATOM.cmd_size = (SZ); \
- context->evergreen_atoms.ATOM.cmd = NULL; \
- context->evergreen_atoms.ATOM.name = #ATOM; \
- context->evergreen_atoms.ATOM.idx = 0; \
- context->evergreen_atoms.ATOM.check = check_##CHK; \
- context->evergreen_atoms.ATOM.dirty = GL_FALSE; \
- context->evergreen_atoms.ATOM.emit = (EMIT); \
- context->radeon.hw.max_state_size += (SZ); \
- insert_at_tail(&context->radeon.hw.atomlist, &context->evergreen_atoms.ATOM); \
-} while (0)
-
-static int check_queryobj(struct gl_context *ctx, struct radeon_state_atom *atom)
-{
- radeonContextPtr radeon = RADEON_CONTEXT(ctx);
- struct radeon_query_object *query = radeon->query.current;
- int count;
-
- if (!query || query->emitted_begin)
- count = 0;
- else
- count = atom->cmd_size;
- radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
- return count;
-}
-
-static void evergreenSendQueryBegin(struct gl_context *ctx, struct radeon_state_atom *atom)
-{
- radeonContextPtr radeon = RADEON_CONTEXT(ctx);
- struct radeon_query_object *query = radeon->query.current;
- BATCH_LOCALS(radeon);
- radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
-
- /* clear the buffer */
- radeon_bo_map(query->bo, GL_FALSE);
- memset(query->bo->ptr, 0, 8 * 2 * sizeof(uint64_t)); /* 8 DBs, 2 qwords each */
- radeon_bo_unmap(query->bo);
-
- radeon_cs_space_check_with_bo(radeon->cmdbuf.cs,
- query->bo,
- 0, RADEON_GEM_DOMAIN_GTT);
-
- BEGIN_BATCH_NO_AUTOSTATE(4 + 2);
- R600_OUT_BATCH(CP_PACKET3(R600_IT_EVENT_WRITE, 2));
- R600_OUT_BATCH(R600_EVENT_TYPE(ZPASS_DONE) | R600_EVENT_INDEX(1));
- R600_OUT_BATCH(query->curr_offset); /* hw writes qwords */
- R600_OUT_BATCH(0x00000000);
- R600_OUT_BATCH_RELOC(VGT_EVENT_INITIATOR, query->bo, 0, 0, RADEON_GEM_DOMAIN_GTT, 0);
- END_BATCH();
- query->emitted_begin = GL_TRUE;
-}
-
-static void evergreen_init_query_stateobj(radeonContextPtr radeon, int SZ)
-{
- radeon->query.queryobj.cmd_size = (SZ);
- radeon->query.queryobj.cmd = NULL;
- radeon->query.queryobj.name = "queryobj";
- radeon->query.queryobj.idx = 0;
- radeon->query.queryobj.check = check_queryobj;
- radeon->query.queryobj.dirty = GL_FALSE;
- radeon->query.queryobj.emit = evergreenSendQueryBegin;
- radeon->hw.max_state_size += (SZ);
- insert_at_tail(&radeon->hw.atomlist, &radeon->query.queryobj);
-}
-
-
-static int check_always(struct gl_context *ctx, struct radeon_state_atom *atom)
-{
- return atom->cmd_size;
-}
-
-static void evergreenSendTexState(struct gl_context *ctx, struct radeon_state_atom *atom)
-{
- context_t *context = EVERGREEN_CONTEXT(ctx);
- EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
-
- struct evergreen_vertex_program *vp = (struct evergreen_vertex_program *) context->selected_vp;
-
- struct radeon_bo *bo = NULL;
- unsigned int i;
- unsigned int nBorderSet = 0;
- BATCH_LOCALS(&context->radeon);
-
- radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
-
- for (i = 0; i < R700_TEXTURE_NUMBERUNITS; i++) {
- if (ctx->Texture.Unit[i]._ReallyEnabled) {
- radeonTexObj *t = evergreen->textures[i];
-
- if (t) {
- /* Tex resource */
- if (!t->image_override) {
- bo = t->mt->bo;
- } else {
- bo = t->bo;
- }
- if (bo)
- {
-
- r700SyncSurf(context, bo,
- RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM,
- 0, TC_ACTION_ENA_bit);
-
- BEGIN_BATCH_NO_AUTOSTATE(10 + 4);
- R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 8));
-
- if( (1<<i) & vp->r700AsmCode.unVetTexBits )
- { /* vs texture */
- R600_OUT_BATCH((i + VERT_ATTRIB_MAX + EG_SQ_FETCH_RESOURCE_VS_OFFSET) * EG_FETCH_RESOURCE_STRIDE);
- }
- else
- {
- R600_OUT_BATCH(i * EG_FETCH_RESOURCE_STRIDE);
- }
-
- R600_OUT_BATCH(evergreen->textures[i]->SQ_TEX_RESOURCE0);
- R600_OUT_BATCH(evergreen->textures[i]->SQ_TEX_RESOURCE1);
- R600_OUT_BATCH(evergreen->textures[i]->SQ_TEX_RESOURCE2);
- R600_OUT_BATCH(evergreen->textures[i]->SQ_TEX_RESOURCE3);
- R600_OUT_BATCH(evergreen->textures[i]->SQ_TEX_RESOURCE4);
- R600_OUT_BATCH(evergreen->textures[i]->SQ_TEX_RESOURCE5);
- R600_OUT_BATCH(evergreen->textures[i]->SQ_TEX_RESOURCE6);
- R600_OUT_BATCH(evergreen->textures[i]->SQ_TEX_RESOURCE7);
-
- R600_OUT_BATCH_RELOC(evergreen->textures[i]->SQ_TEX_RESOURCE2,
- bo,
- evergreen->textures[i]->SQ_TEX_RESOURCE2,
- RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
- R600_OUT_BATCH_RELOC(evergreen->textures[i]->SQ_TEX_RESOURCE3,
- bo,
- evergreen->textures[i]->SQ_TEX_RESOURCE3,
- RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
- END_BATCH();
- COMMIT_BATCH();
- }
- /* Tex sampler */
- BEGIN_BATCH_NO_AUTOSTATE(5);
- R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_SAMPLER, 3));
-
- if( (1<<i) & vp->r700AsmCode.unVetTexBits )
- { /* vs texture */
- R600_OUT_BATCH((i+SQ_TEX_SAMPLER_VS_OFFSET) * 3);
- }
- else
- {
- R600_OUT_BATCH(i * 3);
- }
- R600_OUT_BATCH(evergreen->textures[i]->SQ_TEX_SAMPLER0);
- R600_OUT_BATCH(evergreen->textures[i]->SQ_TEX_SAMPLER1);
- R600_OUT_BATCH(evergreen->textures[i]->SQ_TEX_SAMPLER2);
-
- END_BATCH();
- COMMIT_BATCH();
-
- /* Tex border color */
- if(0 == nBorderSet)
- {
- BEGIN_BATCH_NO_AUTOSTATE(2 + 4);
- R600_OUT_BATCH_REGSEQ(EG_TD_PS_BORDER_COLOR_RED, 4);
- R600_OUT_BATCH(evergreen->textures[i]->TD_PS_SAMPLER0_BORDER_RED);
- R600_OUT_BATCH(evergreen->textures[i]->TD_PS_SAMPLER0_BORDER_GREEN);
- R600_OUT_BATCH(evergreen->textures[i]->TD_PS_SAMPLER0_BORDER_BLUE);
- R600_OUT_BATCH(evergreen->textures[i]->TD_PS_SAMPLER0_BORDER_ALPHA);
- END_BATCH();
- COMMIT_BATCH();
-
- nBorderSet = 1;
- }
- }
- }
- }
-}
-
-static int check_evergreen_tx(struct gl_context *ctx, struct radeon_state_atom *atom)
-{
- context_t *context = EVERGREEN_CONTEXT(ctx);
- unsigned int i, count = 0;
- EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
-
- for (i = 0; i < R700_TEXTURE_NUMBERUNITS; i++) {
- if (ctx->Texture.Unit[i]._ReallyEnabled) {
- radeonTexObj *t = evergreen->textures[i];
- if (t)
- count++;
- }
- }
- radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
- return count * 37 + 6;
-}
-
-static void evergreenSendSQConfig(struct gl_context *ctx, struct radeon_state_atom *atom)
-{
- context_t *context = EVERGREEN_CONTEXT(ctx);
- EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
- BATCH_LOCALS(&context->radeon);
- radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
-
- BEGIN_BATCH_NO_AUTOSTATE(19);
- //6
- EVERGREEN_OUT_BATCH_REGVAL(EG_SPI_CONFIG_CNTL, evergreen->evergreen_config.SPI_CONFIG_CNTL.u32All);
- EVERGREEN_OUT_BATCH_REGVAL(EG_SPI_CONFIG_CNTL_1, evergreen->evergreen_config.SPI_CONFIG_CNTL_1.u32All);
- //6
- EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_CONFIG, 4);
- R600_OUT_BATCH(evergreen->evergreen_config.SQ_CONFIG.u32All);
- R600_OUT_BATCH(evergreen->evergreen_config.SQ_GPR_RESOURCE_MGMT_1.u32All);
- R600_OUT_BATCH(evergreen->evergreen_config.SQ_GPR_RESOURCE_MGMT_2.u32All);
- R600_OUT_BATCH(evergreen->evergreen_config.SQ_GPR_RESOURCE_MGMT_3.u32All);
- //7
- EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_THREAD_RESOURCE_MGMT, 5);
- R600_OUT_BATCH(evergreen->evergreen_config.SQ_THREAD_RESOURCE_MGMT.u32All);
- R600_OUT_BATCH(evergreen->evergreen_config.SQ_THREAD_RESOURCE_MGMT_2.u32All);
- R600_OUT_BATCH(evergreen->evergreen_config.SQ_STACK_RESOURCE_MGMT_1.u32All);
- R600_OUT_BATCH(evergreen->evergreen_config.SQ_STACK_RESOURCE_MGMT_2.u32All);
- R600_OUT_BATCH(evergreen->evergreen_config.SQ_STACK_RESOURCE_MGMT_3.u32All);
-
- END_BATCH();
-
- COMMIT_BATCH();
-}
-
-extern int evergreen_getTypeSize(GLenum type);
-static void evergreenSetupVTXConstants(struct gl_context * ctx,
- void * pAos,
- StreamDesc * pStreamDesc)
-{
- context_t *context = EVERGREEN_CONTEXT(ctx);
- struct radeon_aos * paos = (struct radeon_aos *)pAos;
- BATCH_LOCALS(&context->radeon);
-
- unsigned int uSQ_VTX_CONSTANT_WORD0_0;
- unsigned int uSQ_VTX_CONSTANT_WORD1_0;
- unsigned int uSQ_VTX_CONSTANT_WORD2_0 = 0;
- unsigned int uSQ_VTX_CONSTANT_WORD3_0 = 0;
- unsigned int uSQ_VTX_CONSTANT_WORD7_0 = 0;
-
- if (!paos->bo)
- return;
-
- if ((context->radeon.radeonScreen->chip_family == CHIP_FAMILY_CEDAR) ||
- (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_PALM) ||
- (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_SUMO) ||
- (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_SUMO2))
- r700SyncSurf(context, paos->bo, RADEON_GEM_DOMAIN_GTT, 0, TC_ACTION_ENA_bit);
- else
- r700SyncSurf(context, paos->bo, RADEON_GEM_DOMAIN_GTT, 0, VC_ACTION_ENA_bit);
-
- //uSQ_VTX_CONSTANT_WORD0_0
- uSQ_VTX_CONSTANT_WORD0_0 = paos->offset;
-
- //uSQ_VTX_CONSTANT_WORD1_0
- uSQ_VTX_CONSTANT_WORD1_0 = paos->bo->size - paos->offset - 1;
-
- //uSQ_VTX_CONSTANT_WORD2_0
- SETfield(uSQ_VTX_CONSTANT_WORD2_0,
- pStreamDesc->stride,
- SQ_VTX_CONSTANT_WORD2_0__STRIDE_shift,
- SQ_VTX_CONSTANT_WORD2_0__STRIDE_mask);
- SETfield(uSQ_VTX_CONSTANT_WORD2_0, GetSurfaceFormat(pStreamDesc->type, pStreamDesc->size, NULL),
- SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_shift,
- SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_mask); // TODO : trace back api for initial data type, not only GL_FLOAT
- SETfield(uSQ_VTX_CONSTANT_WORD2_0, 0, BASE_ADDRESS_HI_shift, BASE_ADDRESS_HI_mask); // TODO
-
- SETfield(uSQ_VTX_CONSTANT_WORD2_0,
-#ifdef MESA_BIG_ENDIAN
- SQ_ENDIAN_8IN32,
-#else
- SQ_ENDIAN_NONE,
-#endif
- SQ_VTX_CONSTANT_WORD2_0__ENDIAN_SWAP_shift,
- SQ_VTX_CONSTANT_WORD2_0__ENDIAN_SWAP_mask);
-
- if(GL_TRUE == pStreamDesc->normalize)
- {
- SETfield(uSQ_VTX_CONSTANT_WORD2_0, SQ_NUM_FORMAT_NORM,
- SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_shift, SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_mask);
- }
- else
- {
- SETfield(uSQ_VTX_CONSTANT_WORD2_0, SQ_NUM_FORMAT_SCALED,
- SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_shift, SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_mask);
- }
- if(1 == pStreamDesc->_signed)
- {
- SETbit(uSQ_VTX_CONSTANT_WORD2_0, SQ_VTX_CONSTANT_WORD2_0__FORMAT_COMP_ALL_bit);
- }
-
- //uSQ_VTX_CONSTANT_WORD3_0
- SETfield(uSQ_VTX_CONSTANT_WORD3_0, SQ_SEL_X,
- EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_X_shift,
- EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_X_mask);
- SETfield(uSQ_VTX_CONSTANT_WORD3_0, SQ_SEL_Y,
- EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_Y_shift,
- EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_Y_mask);
- SETfield(uSQ_VTX_CONSTANT_WORD3_0, SQ_SEL_Z,
- EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_Z_shift,
- EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_Z_mask);
- SETfield(uSQ_VTX_CONSTANT_WORD3_0, SQ_SEL_W,
- EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_W_shift,
- EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_W_mask);
-
- //uSQ_VTX_CONSTANT_WORD7_0
- SETfield(uSQ_VTX_CONSTANT_WORD7_0, SQ_TEX_VTX_VALID_BUFFER,
- SQ_TEX_RESOURCE_WORD6_0__TYPE_shift, SQ_TEX_RESOURCE_WORD6_0__TYPE_mask);
-
- BEGIN_BATCH_NO_AUTOSTATE(10 + 2);
-
- R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 8));
- R600_OUT_BATCH((pStreamDesc->element + EG_SQ_FETCH_RESOURCE_VS_OFFSET) * EG_FETCH_RESOURCE_STRIDE);
- R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD0_0);
- R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD1_0);
- R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD2_0);
- R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD3_0);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD7_0);
- R600_OUT_BATCH_RELOC(uSQ_VTX_CONSTANT_WORD0_0,
- paos->bo,
- uSQ_VTX_CONSTANT_WORD0_0,
- RADEON_GEM_DOMAIN_GTT, 0, 0);
- END_BATCH();
-
- COMMIT_BATCH();
-}
-
-static int check_evergreen_vtx(struct gl_context *ctx, struct radeon_state_atom *atom)
-{
- context_t *context = EVERGREEN_CONTEXT(ctx);
- int count = context->radeon.tcl.aos_count * 12;
-
- if (count)
- count += 6;
-
- radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
- return count;
-}
-
-static void evergreenSendVTX(struct gl_context *ctx, struct radeon_state_atom *atom)
-{
- context_t *context = EVERGREEN_CONTEXT(ctx);
- struct evergreen_vertex_program *vp = (struct evergreen_vertex_program *)(context->selected_vp);
- unsigned int i, j = 0;
- BATCH_LOCALS(&context->radeon);
- (void) b_l_rmesa; /* silence unused var warning */
-
- radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
-
- if (context->radeon.tcl.aos_count == 0)
- return;
-
- for(i=0; i<VERT_ATTRIB_MAX; i++) {
- if(vp->mesa_program->Base.InputsRead & (1 << i))
- {
- evergreenSetupVTXConstants(ctx,
- (void*)(&context->radeon.tcl.aos[j]),
- &(context->stream_desc[j]));
- j++;
- }
- }
-}
-static void evergreenSendPA(struct gl_context *ctx, struct radeon_state_atom *atom)
-{
- context_t *context = EVERGREEN_CONTEXT(ctx);
- EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
- BATCH_LOCALS(&context->radeon);
- radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
- int id = 0;
-
- BEGIN_BATCH_NO_AUTOSTATE(3);
- EVERGREEN_OUT_BATCH_REGVAL(EG_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
- END_BATCH();
-
- BEGIN_BATCH_NO_AUTOSTATE(22);
- EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_SCREEN_SCISSOR_TL, 2);
- R600_OUT_BATCH(evergreen->PA_SC_SCREEN_SCISSOR_TL.u32All);
- R600_OUT_BATCH(evergreen->PA_SC_SCREEN_SCISSOR_BR.u32All);
-
- EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_WINDOW_OFFSET, 12);
- R600_OUT_BATCH(evergreen->PA_SC_WINDOW_OFFSET.u32All);
- R600_OUT_BATCH(evergreen->PA_SC_WINDOW_SCISSOR_TL.u32All);
- R600_OUT_BATCH(evergreen->PA_SC_WINDOW_SCISSOR_BR.u32All);
- R600_OUT_BATCH(evergreen->PA_SC_CLIPRECT_RULE.u32All);
- R600_OUT_BATCH(evergreen->PA_SC_CLIPRECT_0_TL.u32All);
- R600_OUT_BATCH(evergreen->PA_SC_CLIPRECT_0_BR.u32All);
- R600_OUT_BATCH(evergreen->PA_SC_CLIPRECT_1_TL.u32All);
- R600_OUT_BATCH(evergreen->PA_SC_CLIPRECT_1_BR.u32All);
- R600_OUT_BATCH(evergreen->PA_SC_CLIPRECT_2_TL.u32All);
- R600_OUT_BATCH(evergreen->PA_SC_CLIPRECT_2_BR.u32All);
- R600_OUT_BATCH(evergreen->PA_SC_CLIPRECT_3_TL.u32All);
- R600_OUT_BATCH(evergreen->PA_SC_CLIPRECT_3_BR.u32All);
-
- EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_GENERIC_SCISSOR_TL, 2);
- R600_OUT_BATCH(evergreen->PA_SC_GENERIC_SCISSOR_TL.u32All);
- R600_OUT_BATCH(evergreen->PA_SC_GENERIC_SCISSOR_BR.u32All);
- END_BATCH();
-
- BEGIN_BATCH_NO_AUTOSTATE(3);
- EVERGREEN_OUT_BATCH_REGVAL(EG_PA_SC_EDGERULE, evergreen->PA_SC_EDGERULE.u32All);
- END_BATCH();
-
-
- BEGIN_BATCH_NO_AUTOSTATE(18);
- EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_VPORT_SCISSOR_0_TL, 4);
- R600_OUT_BATCH(evergreen->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All);
- R600_OUT_BATCH(evergreen->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All);
- R600_OUT_BATCH(evergreen->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All);
- R600_OUT_BATCH(evergreen->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All);
-
- EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_VPORT_ZMIN_0, 2);
- R600_OUT_BATCH(evergreen->viewport[id].PA_SC_VPORT_ZMIN_0.u32All);
- R600_OUT_BATCH(evergreen->viewport[id].PA_SC_VPORT_ZMAX_0.u32All);
-
- EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_CL_VPORT_XSCALE, 6);
- R600_OUT_BATCH(evergreen->viewport[id].PA_CL_VPORT_XSCALE.u32All);
- R600_OUT_BATCH(evergreen->viewport[id].PA_CL_VPORT_XOFFSET.u32All);
- R600_OUT_BATCH(evergreen->viewport[id].PA_CL_VPORT_YSCALE.u32All);
- R600_OUT_BATCH(evergreen->viewport[id].PA_CL_VPORT_YOFFSET.u32All);
- R600_OUT_BATCH(evergreen->viewport[id].PA_CL_VPORT_ZSCALE.u32All);
- R600_OUT_BATCH(evergreen->viewport[id].PA_CL_VPORT_ZOFFSET.u32All);
- END_BATCH();
-
-
- for (id = 0; id < EVERGREEN_MAX_UCP; id++) {
- if (evergreen->ucp[id].enabled) {
- BEGIN_BATCH_NO_AUTOSTATE(6);
- EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_CL_UCP_0_X + (4 * id), 4);
- R600_OUT_BATCH(evergreen->ucp[id].PA_CL_UCP_0_X.u32All);
- R600_OUT_BATCH(evergreen->ucp[id].PA_CL_UCP_0_Y.u32All);
- R600_OUT_BATCH(evergreen->ucp[id].PA_CL_UCP_0_Z.u32All);
- R600_OUT_BATCH(evergreen->ucp[id].PA_CL_UCP_0_W.u32All);
- END_BATCH();
- }
- }
-
- BEGIN_BATCH_NO_AUTOSTATE(42);
- EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_CL_CLIP_CNTL, 5);
- R600_OUT_BATCH(evergreen->PA_CL_CLIP_CNTL.u32All);
- R600_OUT_BATCH(evergreen->PA_SU_SC_MODE_CNTL.u32All);
- R600_OUT_BATCH(evergreen->PA_CL_VTE_CNTL.u32All);
- R600_OUT_BATCH(evergreen->PA_CL_VS_OUT_CNTL.u32All);
- R600_OUT_BATCH(evergreen->PA_CL_NANINF_CNTL.u32All);
-
- EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SU_POINT_SIZE, 3);
- R600_OUT_BATCH(evergreen->PA_SU_POINT_SIZE.u32All);
- R600_OUT_BATCH(evergreen->PA_SU_POINT_MINMAX.u32All);
- R600_OUT_BATCH(evergreen->PA_SU_LINE_CNTL.u32All);
-
- EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_MODE_CNTL_0, 2);
- R600_OUT_BATCH(evergreen->PA_SC_MODE_CNTL_0.u32All);
- R600_OUT_BATCH(evergreen->PA_SC_MODE_CNTL_1.u32All);
-
- EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 6);
- R600_OUT_BATCH(evergreen->PA_SU_POLY_OFFSET_DB_FMT_CNTL.u32All);
- R600_OUT_BATCH(evergreen->PA_SU_POLY_OFFSET_CLAMP.u32All);
- R600_OUT_BATCH(evergreen->PA_SU_POLY_OFFSET_FRONT_SCALE.u32All);
- R600_OUT_BATCH(evergreen->PA_SU_POLY_OFFSET_FRONT_OFFSET.u32All);
- R600_OUT_BATCH(evergreen->PA_SU_POLY_OFFSET_BACK_SCALE.u32All);
- R600_OUT_BATCH(evergreen->PA_SU_POLY_OFFSET_BACK_OFFSET.u32All);
-
- EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_LINE_CNTL, 16);
- R600_OUT_BATCH(evergreen->PA_SC_LINE_CNTL.u32All);
- R600_OUT_BATCH(evergreen->PA_SC_AA_CONFIG.u32All);
- R600_OUT_BATCH(evergreen->PA_SU_VTX_CNTL.u32All);
- R600_OUT_BATCH(evergreen->PA_CL_GB_VERT_CLIP_ADJ.u32All);
- R600_OUT_BATCH(evergreen->PA_CL_GB_VERT_DISC_ADJ.u32All);
- R600_OUT_BATCH(evergreen->PA_CL_GB_HORZ_CLIP_ADJ.u32All);
- R600_OUT_BATCH(evergreen->PA_CL_GB_HORZ_DISC_ADJ.u32All);
- R600_OUT_BATCH(evergreen->PA_SC_AA_SAMPLE_LOCS_0.u32All);
- R600_OUT_BATCH(evergreen->PA_SC_AA_SAMPLE_LOCS_1.u32All);
- R600_OUT_BATCH(evergreen->PA_SC_AA_SAMPLE_LOCS_2.u32All);
- R600_OUT_BATCH(evergreen->PA_SC_AA_SAMPLE_LOCS_3.u32All);
- R600_OUT_BATCH(evergreen->PA_SC_AA_SAMPLE_LOCS_4.u32All);
- R600_OUT_BATCH(evergreen->PA_SC_AA_SAMPLE_LOCS_5.u32All);
- R600_OUT_BATCH(evergreen->PA_SC_AA_SAMPLE_LOCS_6.u32All);
- R600_OUT_BATCH(evergreen->PA_SC_AA_SAMPLE_LOCS_7.u32All);
- R600_OUT_BATCH(evergreen->PA_SC_AA_MASK.u32All);
-
- END_BATCH();
-
- COMMIT_BATCH();
-}
-static void evergreenSendTP(struct gl_context *ctx, struct radeon_state_atom *atom)
-{
- /*
- context_t *context = EVERGREEN_CONTEXT(ctx);
- EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
- BATCH_LOCALS(&context->radeon);
- radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
-
- COMMIT_BATCH();
- */
-}
-
-static void evergreenSendPSresource(struct gl_context *ctx)
-{
- context_t *context = EVERGREEN_CONTEXT(ctx);
- EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
- struct radeon_bo * pbo;
- struct radeon_bo * pbo_const;
- /* const size reg is in units of 16 consts */
- int const_size = ((evergreen->ps.num_consts * 4) + 15) & ~15;
-
- BATCH_LOCALS(&context->radeon);
- radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
-
- pbo = (struct radeon_bo *)evergreenGetActiveFpShaderBo(GL_CONTEXT(context));
-
- if (!pbo)
- return;
-
- r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
-
- BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
- EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_START_PS, 1);
- R600_OUT_BATCH(evergreen->ps.SQ_PGM_START_PS.u32All);
- R600_OUT_BATCH_RELOC(evergreen->ps.SQ_PGM_START_PS.u32All,
- pbo,
- evergreen->ps.SQ_PGM_START_PS.u32All,
- RADEON_GEM_DOMAIN_GTT, 0, 0);
- END_BATCH();
-
- BEGIN_BATCH_NO_AUTOSTATE(3);
- EVERGREEN_OUT_BATCH_REGVAL(EG_SQ_LOOP_CONST_0, 0x01000FFF);
- END_BATCH();
-
- pbo_const = (struct radeon_bo *)(context->fp_Constbo);
-
- if(NULL != pbo_const)
- {
- r700SyncSurf(context, pbo_const, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
-
- BEGIN_BATCH_NO_AUTOSTATE(3);
- EVERGREEN_OUT_BATCH_REGVAL(EG_SQ_ALU_CONST_BUFFER_SIZE_PS_0, const_size / 16);
- END_BATCH();
-
- BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
- EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_ALU_CONST_CACHE_PS_0, 1);
- R600_OUT_BATCH(context->fp_bo_offset >> 8);
- R600_OUT_BATCH_RELOC(0,
- pbo_const,
- 0,
- RADEON_GEM_DOMAIN_GTT, 0, 0);
- END_BATCH();
- }
-
- COMMIT_BATCH();
-}
-
-static void evergreenSendVSresource(struct gl_context *ctx, struct radeon_state_atom *atom)
-{
- context_t *context = EVERGREEN_CONTEXT(ctx);
- EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
- struct radeon_bo * pbo;
- struct radeon_bo * pbo_const;
- /* const size reg is in units of 16 consts */
- int const_size = ((evergreen->vs.num_consts * 4) + 15) & ~15;
-
- BATCH_LOCALS(&context->radeon);
- radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
-
- pbo = (struct radeon_bo *)evergreenGetActiveVpShaderBo(GL_CONTEXT(context));
-
- if (!pbo)
- return;
-
- r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
-
- BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
- EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_START_VS, 1);
- R600_OUT_BATCH(evergreen->vs.SQ_PGM_START_VS.u32All);
- R600_OUT_BATCH_RELOC(evergreen->vs.SQ_PGM_START_VS.u32All,
- pbo,
- evergreen->vs.SQ_PGM_START_VS.u32All,
- RADEON_GEM_DOMAIN_GTT, 0, 0);
- END_BATCH();
-
- BEGIN_BATCH_NO_AUTOSTATE(3);
- EVERGREEN_OUT_BATCH_REGVAL((EG_SQ_LOOP_CONST_0 + 32*1), 0x0100000F); //consts == 1
- //EVERGREEN_OUT_BATCH_REGVAL((EG_SQ_LOOP_CONST_0 + (SQ_LOOP_CONST_vs<2)), 0x0100000F);
- END_BATCH();
-
- pbo_const = (struct radeon_bo *)(context->vp_Constbo);
-
- if(NULL != pbo_const)
- {
- r700SyncSurf(context, pbo_const, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
-
- BEGIN_BATCH_NO_AUTOSTATE(3);
- EVERGREEN_OUT_BATCH_REGVAL(EG_SQ_ALU_CONST_BUFFER_SIZE_VS_0, const_size / 16);
- END_BATCH();
-
- BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
- EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_ALU_CONST_CACHE_VS_0, 1);
- R600_OUT_BATCH(context->vp_bo_offset >> 8);
- R600_OUT_BATCH_RELOC(0,
- pbo_const,
- 0,
- RADEON_GEM_DOMAIN_GTT, 0, 0);
- END_BATCH();
- }
-
- COMMIT_BATCH();
-}
-
-static void evergreenSendSQ(struct gl_context *ctx, struct radeon_state_atom *atom)
-{
- context_t *context = EVERGREEN_CONTEXT(ctx);
- EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
- BATCH_LOCALS(&context->radeon);
- radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
-
- evergreenSendPSresource(ctx); //16 entries now
-
- BEGIN_BATCH_NO_AUTOSTATE(77);
-
- //34
- EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_VTX_SEMANTIC_0, 32);
- R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_0.u32All); //// // = 0x28380, // SAME
- R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_1.u32All); //// // = 0x28384, // SAME
- R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_2.u32All); //// // = 0x28388, // SAME
- R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_3.u32All); //// // = 0x2838C, // SAME
- R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_4.u32All); //// // = 0x28390, // SAME
- R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_5.u32All); //// // = 0x28394, // SAME
- R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_6.u32All); //// // = 0x28398, // SAME
- R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_7.u32All); //// // = 0x2839C, // SAME
- R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_8.u32All); //// // = 0x283A0, // SAME
- R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_9.u32All); //// // = 0x283A4, // SAME
- R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_10.u32All); //// // = 0x283A8, // SAME
- R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_11.u32All); //// // = 0x283AC, // SAME
- R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_12.u32All); //// // = 0x283B0, // SAME
- R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_13.u32All); //// // = 0x283B4, // SAME
- R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_14.u32All); //// // = 0x283B8, // SAME
- R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_15.u32All); //// // = 0x283BC, // SAME
- R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_16.u32All); //// // = 0x283C0, // SAME
- R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_17.u32All); //// // = 0x283C4, // SAME
- R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_18.u32All); //// // = 0x283C8, // SAME
- R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_19.u32All); //// // = 0x283CC, // SAME
- R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_20.u32All); //// // = 0x283D0, // SAME
- R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_21.u32All); //// // = 0x283D4, // SAME
- R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_22.u32All); //// // = 0x283D8, // SAME
- R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_23.u32All); //// // = 0x283DC, // SAME
- R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_24.u32All); //// // = 0x283E0, // SAME
- R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_25.u32All); //// // = 0x283E4, // SAME
- R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_26.u32All); //// // = 0x283E8, // SAME
- R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_27.u32All); //// // = 0x283EC, // SAME
- R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_28.u32All); //// // = 0x283F0, // SAME
- R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_29.u32All); //// // = 0x283F4, // SAME
- R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_30.u32All); //// // = 0x283F8, // SAME
- R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_31.u32All); //// // = 0x283FC, // SAME
-
-
- //3
- EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_DYN_GPR_RESOURCE_LIMIT_1, 1);
- R600_OUT_BATCH(evergreen->SQ_DYN_GPR_RESOURCE_LIMIT_1.u32All);//// // = 0x28838, //
-
- //5
- EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_RESOURCES_PS, 3);
- R600_OUT_BATCH(evergreen->SQ_PGM_RESOURCES_PS.u32All); //// // = 0x28844, // DIFF 0x28850
- R600_OUT_BATCH(evergreen->SQ_PGM_RESOURCES_2_PS.u32All); //// // = 0x28848, //
- R600_OUT_BATCH(evergreen->SQ_PGM_EXPORTS_PS.u32All); //// // = 0x2884C, // SAME 0x28854
-
- //4
- EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_RESOURCES_VS, 2);
- R600_OUT_BATCH(evergreen->SQ_PGM_RESOURCES_VS.u32All);//// // = 0x28860, // DIFF 0x28868
- R600_OUT_BATCH(evergreen->SQ_PGM_RESOURCES_2_VS.u32All); //// // = 0x28864, //
-
- //5
- EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_RESOURCES_GS, 2);
- /*
- R600_OUT_BATCH(evergreen->SQ_PGM_START_GS.u32All); //// // = 0x28874, // SAME 0x2886C
- */
- R600_OUT_BATCH(evergreen->SQ_PGM_RESOURCES_GS.u32All); //// // = 0x28878, // DIFF 0x2887C
- R600_OUT_BATCH(evergreen->SQ_PGM_RESOURCES_2_GS.u32All); //// // = 0x2887C, //
-
- //5
- EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_RESOURCES_ES, 2);
- /*
- R600_OUT_BATCH(evergreen->SQ_PGM_START_ES.u32All); //// // = 0x2888C, // SAME 0x28880
- */
- R600_OUT_BATCH(evergreen->SQ_PGM_RESOURCES_ES.u32All); //// // = 0x28890, // DIFF
- R600_OUT_BATCH(evergreen->SQ_PGM_RESOURCES_2_ES.u32All); //// // = 0x28894, //
-
- //4
- EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_RESOURCES_FS, 1);
- /*
- R600_OUT_BATCH(evergreen->SQ_PGM_START_FS.u32All); //// // = 0x288A4, // SAME 0x28894
- */
- R600_OUT_BATCH(evergreen->SQ_PGM_RESOURCES_FS.u32All); //// // = 0x288A8, // DIFF 0x288A4
-
- //3
- EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_RESOURCES_2_HS, 1);
- R600_OUT_BATCH(evergreen->SQ_PGM_RESOURCES_2_HS.u32All);//// // = 0x288C0, //
-
- //3
- EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_RESOURCES_2_LS, 1);
- R600_OUT_BATCH(evergreen->SQ_PGM_RESOURCES_2_LS.u32All); //// // = 0x288D8, //
-
- //3
- EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_LDS_ALLOC_PS, 1);
- R600_OUT_BATCH(evergreen->SQ_LDS_ALLOC_PS.u32All); //// // = 0x288EC, //
-
- //8
- EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_ESGS_RING_ITEMSIZE, 6);
- R600_OUT_BATCH(evergreen->SQ_ESGS_RING_ITEMSIZE.u32All); //// // = 0x28900, // SAME 0x288A8
- R600_OUT_BATCH(evergreen->SQ_GSVS_RING_ITEMSIZE.u32All); //// // = 0x28904, // SAME 0x288AC
- R600_OUT_BATCH(evergreen->SQ_ESTMP_RING_ITEMSIZE.u32All); //// // = 0x28908, // SAME 0x288B0
- R600_OUT_BATCH(evergreen->SQ_GSTMP_RING_ITEMSIZE.u32All); //// // = 0x2890C, // SAME 0x288B4
- R600_OUT_BATCH(evergreen->SQ_VSTMP_RING_ITEMSIZE.u32All); //// // = 0x28910, // SAME 0x288B8
- R600_OUT_BATCH(evergreen->SQ_PSTMP_RING_ITEMSIZE.u32All); //// // = 0x28914, // SAME 0x288BC
-
- //3
- EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_GS_VERT_ITEMSIZE, 1);
- R600_OUT_BATCH(evergreen->SQ_GS_VERT_ITEMSIZE.u32All); //// // = 0x2891C, // SAME 0x288C8
-
- END_BATCH();
-
- COMMIT_BATCH();
-
-}
-static void evergreenSendSPI(struct gl_context *ctx, struct radeon_state_atom *atom)
-{
- context_t *context = EVERGREEN_CONTEXT(ctx);
- EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
- BATCH_LOCALS(&context->radeon);
- radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
-
- BEGIN_BATCH_NO_AUTOSTATE(59);
-
- EVERGREEN_OUT_BATCH_REGSEQ(EG_SPI_VS_OUT_ID_0, 10);
- R600_OUT_BATCH(evergreen->SPI_VS_OUT_ID_0.u32All);
- R600_OUT_BATCH(evergreen->SPI_VS_OUT_ID_1.u32All);
- R600_OUT_BATCH(evergreen->SPI_VS_OUT_ID_2.u32All);
- R600_OUT_BATCH(evergreen->SPI_VS_OUT_ID_3.u32All);
- R600_OUT_BATCH(evergreen->SPI_VS_OUT_ID_4.u32All);
- R600_OUT_BATCH(evergreen->SPI_VS_OUT_ID_5.u32All);
- R600_OUT_BATCH(evergreen->SPI_VS_OUT_ID_6.u32All);
- R600_OUT_BATCH(evergreen->SPI_VS_OUT_ID_7.u32All);
- R600_OUT_BATCH(evergreen->SPI_VS_OUT_ID_8.u32All);
- R600_OUT_BATCH(evergreen->SPI_VS_OUT_ID_9.u32All);
-
- EVERGREEN_OUT_BATCH_REGSEQ(EG_SPI_PS_INPUT_CNTL_0, 45);
- R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[0].u32All);
- R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[1].u32All);
- R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[2].u32All);
- R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[3].u32All);
- R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[4].u32All);
- R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[5].u32All);
- R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[6].u32All);
- R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[7].u32All);
- R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[8].u32All);
- R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[9].u32All);
- R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[10].u32All);
- R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[11].u32All);
- R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[12].u32All);
- R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[13].u32All);
- R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[14].u32All);
- R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[15].u32All);
- R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[16].u32All);
- R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[17].u32All);
- R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[18].u32All);
- R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[19].u32All);
- R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[20].u32All);
- R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[21].u32All);
- R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[22].u32All);
- R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[23].u32All);
- R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[24].u32All);
- R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[25].u32All);
- R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[26].u32All);
- R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[27].u32All);
- R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[28].u32All);
- R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[29].u32All);
- R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[30].u32All);
- R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[31].u32All);
- R600_OUT_BATCH(evergreen->SPI_VS_OUT_CONFIG.u32All);
- R600_OUT_BATCH(evergreen->SPI_THREAD_GROUPING.u32All);
- R600_OUT_BATCH(evergreen->SPI_PS_IN_CONTROL_0.u32All);
- R600_OUT_BATCH(evergreen->SPI_PS_IN_CONTROL_1.u32All);
- R600_OUT_BATCH(evergreen->SPI_INTERP_CONTROL_0.u32All);
- R600_OUT_BATCH(evergreen->SPI_INPUT_Z.u32All);
- R600_OUT_BATCH(evergreen->SPI_FOG_CNTL.u32All);
- R600_OUT_BATCH(evergreen->SPI_BARYC_CNTL.u32All);
- R600_OUT_BATCH(evergreen->SPI_PS_IN_CONTROL_2.u32All);
- R600_OUT_BATCH(evergreen->SPI_COMPUTE_INPUT_CNTL.u32All);
- R600_OUT_BATCH(evergreen->SPI_COMPUTE_NUM_THREAD_X.u32All);
- R600_OUT_BATCH(evergreen->SPI_COMPUTE_NUM_THREAD_Y.u32All);
- R600_OUT_BATCH(evergreen->SPI_COMPUTE_NUM_THREAD_Z.u32All);
-
- END_BATCH();
-
- COMMIT_BATCH();
-}
-static void evergreenSendSX(struct gl_context *ctx, struct radeon_state_atom *atom)
-{
- context_t *context = EVERGREEN_CONTEXT(ctx);
- EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
- BATCH_LOCALS(&context->radeon);
- radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
-
- BEGIN_BATCH_NO_AUTOSTATE(9);
-
- EVERGREEN_OUT_BATCH_REGVAL(EG_SX_MISC, evergreen->SX_MISC.u32All);
- EVERGREEN_OUT_BATCH_REGVAL(EG_SX_ALPHA_TEST_CONTROL, evergreen->SX_ALPHA_TEST_CONTROL.u32All);
- EVERGREEN_OUT_BATCH_REGVAL(EG_SX_ALPHA_REF, evergreen->SX_ALPHA_REF.u32All);
-
- END_BATCH();
-
- COMMIT_BATCH();
-}
-
-static void evergreenSetDepthTarget(context_t *context)
-{
- EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
- struct radeon_renderbuffer *rrb;
- unsigned int nPitchInPixel, height, offtostencil;
-
- rrb = radeon_get_depthbuffer(&context->radeon);
- if (!rrb)
- {
- return;
- }
-
- EVERGREEN_STATECHANGE(context, db);
-
- evergreen->DB_DEPTH_SIZE.u32All = 0;
-
- nPitchInPixel = rrb->pitch/rrb->cpp;
-
- if (context->radeon.radeonScreen->driScreen->dri2.enabled)
- {
- height = rrb->base.Height;
- }
- else
- {
- height = context->radeon.radeonScreen->driScreen->fbHeight;
- }
-
- SETfield(evergreen->DB_DEPTH_SIZE.u32All, (nPitchInPixel/8)-1,
- EG_DB_DEPTH_SIZE__PITCH_TILE_MAX_shift,
- EG_DB_DEPTH_SIZE__PITCH_TILE_MAX_mask);
- SETfield(evergreen->DB_DEPTH_SIZE.u32All, (height/8)-1,
- EG_DB_DEPTH_SIZE__HEIGHT_TILE_MAX_shift,
- EG_DB_DEPTH_SIZE__HEIGHT_TILE_MAX_mask);
- evergreen->DB_DEPTH_SLICE.u32All = ( (nPitchInPixel * height)/64 )-1;
-
- if(4 == rrb->cpp)
- {
- SETfield(evergreen->DB_Z_INFO.u32All, EG_Z_24,
- EG_DB_Z_INFO__FORMAT_shift,
- EG_DB_Z_INFO__FORMAT_mask);
- }
- else
- {
- SETfield(evergreen->DB_Z_INFO.u32All, EG_Z_16,
- EG_DB_Z_INFO__FORMAT_shift,
- EG_DB_Z_INFO__FORMAT_mask);
- }
- SETfield(evergreen->DB_Z_INFO.u32All, ARRAY_1D_TILED_THIN1,
- EG_DB_Z_INFO__ARRAY_MODE_shift,
- EG_DB_Z_INFO__ARRAY_MODE_mask);
-
-
- offtostencil = ((height * rrb->pitch) + 255) & ~255;
- evergreen->DB_STENCIL_WRITE_BASE.u32All = offtostencil >> 8;
- evergreen->DB_STENCIL_READ_BASE.u32All = offtostencil >> 8;
-
-}
-
-static void evergreenSendDB(struct gl_context *ctx, struct radeon_state_atom *atom)
-{
- context_t *context = EVERGREEN_CONTEXT(ctx);
- EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
- struct radeon_renderbuffer *rrb;
- BATCH_LOCALS(&context->radeon);
- radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
-
- evergreenSetDepthTarget(context);
-
- //8
- BEGIN_BATCH_NO_AUTOSTATE(7);
- EVERGREEN_OUT_BATCH_REGSEQ(EG_DB_RENDER_CONTROL, 5);
- R600_OUT_BATCH(evergreen->DB_RENDER_CONTROL.u32All);
- R600_OUT_BATCH(evergreen->DB_COUNT_CONTROL.u32All);
- R600_OUT_BATCH(evergreen->DB_DEPTH_VIEW.u32All);
- R600_OUT_BATCH(evergreen->DB_RENDER_OVERRIDE.u32All);
- R600_OUT_BATCH(evergreen->DB_RENDER_OVERRIDE2.u32All);
- END_BATCH();
-
- //4
- BEGIN_BATCH_NO_AUTOSTATE(4);
- EVERGREEN_OUT_BATCH_REGSEQ(EG_DB_STENCIL_CLEAR, 2);
- R600_OUT_BATCH(evergreen->DB_STENCIL_CLEAR.u32All);
- R600_OUT_BATCH(evergreen->DB_DEPTH_CLEAR.u32All);
- END_BATCH();
-
- //4
- BEGIN_BATCH_NO_AUTOSTATE(4);
- EVERGREEN_OUT_BATCH_REGSEQ(EG_DB_DEPTH_SIZE, 2);
- R600_OUT_BATCH(evergreen->DB_DEPTH_SIZE.u32All);
- R600_OUT_BATCH(evergreen->DB_DEPTH_SLICE.u32All);
- END_BATCH();
-
- //3
- BEGIN_BATCH_NO_AUTOSTATE(3);
- EVERGREEN_OUT_BATCH_REGVAL(EG_DB_DEPTH_CONTROL, evergreen->DB_DEPTH_CONTROL.u32All);
- END_BATCH();
-
- //3
- BEGIN_BATCH_NO_AUTOSTATE(3);
- EVERGREEN_OUT_BATCH_REGVAL(EG_DB_SHADER_CONTROL, evergreen->DB_SHADER_CONTROL.u32All);
- END_BATCH();
-
- //5
- BEGIN_BATCH_NO_AUTOSTATE(5);
- EVERGREEN_OUT_BATCH_REGSEQ(EG_DB_SRESULTS_COMPARE_STATE0, 3);
- R600_OUT_BATCH(evergreen->DB_SRESULTS_COMPARE_STATE0.u32All);
- R600_OUT_BATCH(evergreen->DB_SRESULTS_COMPARE_STATE1.u32All);
- R600_OUT_BATCH(evergreen->DB_PRELOAD_CONTROL.u32All);
- END_BATCH();
-
- //3
- BEGIN_BATCH_NO_AUTOSTATE(3);
- EVERGREEN_OUT_BATCH_REGVAL(EG_DB_ALPHA_TO_MASK, evergreen->DB_ALPHA_TO_MASK.u32All);
- END_BATCH();
-
- rrb = radeon_get_depthbuffer(&context->radeon);
-
- if( (rrb != NULL) && (rrb->bo != NULL) )
- {
-
- /* make the hw happy */
- BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
- EVERGREEN_OUT_BATCH_REGVAL(EG_DB_HTILE_DATA_BASE, evergreen->DB_HTILE_DATA_BASE.u32All);
- R600_OUT_BATCH_RELOC(evergreen->DB_HTILE_DATA_BASE.u32All,
- rrb->bo,
- evergreen->DB_HTILE_DATA_BASE.u32All,
- 0, RADEON_GEM_DOMAIN_VRAM, 0);
- END_BATCH();
-
- //5
- BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
- EVERGREEN_OUT_BATCH_REGVAL(EG_DB_Z_INFO, evergreen->DB_Z_INFO.u32All);
- R600_OUT_BATCH_RELOC(evergreen->DB_Z_INFO.u32All,
- rrb->bo,
- evergreen->DB_Z_INFO.u32All,
- 0, RADEON_GEM_DOMAIN_VRAM, 0);
- END_BATCH();
-
- //5
- if((evergreen->DB_DEPTH_CONTROL.u32All & Z_ENABLE_bit) > 0)
- {
- BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
- EVERGREEN_OUT_BATCH_REGVAL(EG_DB_Z_READ_BASE, evergreen->DB_Z_READ_BASE.u32All);
- R600_OUT_BATCH_RELOC(evergreen->DB_Z_READ_BASE.u32All,
- rrb->bo,
- evergreen->DB_Z_READ_BASE.u32All,
- 0, RADEON_GEM_DOMAIN_VRAM, 0);
- END_BATCH();
- }
- //5
- if((evergreen->DB_DEPTH_CONTROL.u32All & Z_WRITE_ENABLE_bit) > 0)
- {
- BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
- EVERGREEN_OUT_BATCH_REGVAL(EG_DB_Z_WRITE_BASE, evergreen->DB_Z_READ_BASE.u32All);
- R600_OUT_BATCH_RELOC(evergreen->DB_Z_WRITE_BASE.u32All,
- rrb->bo,
- evergreen->DB_Z_WRITE_BASE.u32All,
- 0, RADEON_GEM_DOMAIN_VRAM, 0);
- END_BATCH();
- }
- }
-
- if (ctx->DrawBuffer)
- {
- rrb = radeon_get_renderbuffer(ctx->DrawBuffer, BUFFER_STENCIL);
-
- if((rrb != NULL) && (rrb->bo != NULL))
- {
- //5
- BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
- EVERGREEN_OUT_BATCH_REGVAL(EG_DB_STENCIL_INFO, evergreen->DB_STENCIL_INFO.u32All);
- R600_OUT_BATCH_RELOC(evergreen->DB_STENCIL_INFO.u32All,
- rrb->bo,
- evergreen->DB_STENCIL_INFO.u32All,
- 0, RADEON_GEM_DOMAIN_VRAM, 0);
- END_BATCH();
-
- //4
- BEGIN_BATCH_NO_AUTOSTATE(4);
- R600_OUT_BATCH_REGSEQ(DB_STENCILREFMASK, 2);
- R600_OUT_BATCH(evergreen->DB_STENCILREFMASK.u32All);
- R600_OUT_BATCH(evergreen->DB_STENCILREFMASK_BF.u32All);
- END_BATCH();
- //------------------------
-
- //10
- if((evergreen->DB_DEPTH_CONTROL.u32All & STENCIL_ENABLE_bit) > 0)
- {
-
- BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
- EVERGREEN_OUT_BATCH_REGVAL(EG_DB_STENCIL_READ_BASE, evergreen->DB_STENCIL_READ_BASE.u32All);
- R600_OUT_BATCH_RELOC(evergreen->DB_STENCIL_READ_BASE.u32All,
- rrb->bo,
- evergreen->DB_STENCIL_READ_BASE.u32All,
- 0, RADEON_GEM_DOMAIN_VRAM, 0);
- END_BATCH();
-
- BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
- EVERGREEN_OUT_BATCH_REGVAL(EG_DB_STENCIL_WRITE_BASE, evergreen->DB_STENCIL_WRITE_BASE.u32All);
- R600_OUT_BATCH_RELOC(evergreen->DB_STENCIL_WRITE_BASE.u32All,
- rrb->bo,
- evergreen->DB_STENCIL_WRITE_BASE.u32All,
- 0, RADEON_GEM_DOMAIN_VRAM, 0);
- END_BATCH();
- }
- }
- }
-
- COMMIT_BATCH();
-}
-
-static void evergreenSetRenderTarget(context_t *context, int id)
-{
- EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
- uint32_t format = COLOR_8_8_8_8, comp_swap = SWAP_ALT, number_type = NUMBER_UNORM, source_format = 1;
- struct radeon_renderbuffer *rrb;
- unsigned int nPitchInPixel, height;
-
- rrb = radeon_get_colorbuffer(&context->radeon);
- if (!rrb || !rrb->bo) {
- return;
- }
-
- EVERGREEN_STATECHANGE(context, cb);
-
- /* addr */
- evergreen->render_target[id].CB_COLOR0_BASE.u32All = context->radeon.state.color.draw_offset / 256;
-
- /* pitch */
- nPitchInPixel = rrb->pitch/rrb->cpp;
-
- if (context->radeon.radeonScreen->driScreen->dri2.enabled)
- {
- height = rrb->base.Height;
- }
- else
- {
- height = context->radeon.radeonScreen->driScreen->fbHeight;
- }
-
- SETfield(evergreen->render_target[id].CB_COLOR0_PITCH.u32All, (nPitchInPixel/8)-1,
- EG_CB_COLOR0_PITCH__TILE_MAX_shift,
- EG_CB_COLOR0_PITCH__TILE_MAX_mask);
-
- /* slice */
- SETfield(evergreen->render_target[id].CB_COLOR0_SLICE.u32All,
- ( (nPitchInPixel * height)/64 )-1,
- EG_CB_COLOR0_SLICE__TILE_MAX_shift,
- EG_CB_COLOR0_SLICE__TILE_MAX_mask);
-
- /* CB_COLOR0_ATTRIB */ /* TODO : for z clear, this should be set to 0 */
- SETbit(evergreen->render_target[id].CB_COLOR0_ATTRIB.u32All,
- EG_CB_COLOR0_ATTRIB__NON_DISP_TILING_ORDER_bit);
-
- /* CB_COLOR0_INFO */
- SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
- ENDIAN_NONE,
- EG_CB_COLOR0_INFO__ENDIAN_shift,
- EG_CB_COLOR0_INFO__ENDIAN_mask);
- SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
- ARRAY_LINEAR_GENERAL,
- EG_CB_COLOR0_INFO__ARRAY_MODE_shift,
- EG_CB_COLOR0_INFO__ARRAY_MODE_mask);
-
- switch (rrb->base.Format) {
- case MESA_FORMAT_RGBA8888:
- format = COLOR_8_8_8_8;
- comp_swap = SWAP_STD_REV;
- number_type = NUMBER_UNORM;
- source_format = 1;
- break;
- case MESA_FORMAT_SIGNED_RGBA8888:
- format = COLOR_8_8_8_8;
- comp_swap = SWAP_STD_REV;
- number_type = NUMBER_SNORM;
- source_format = 1;
- break;
- case MESA_FORMAT_RGBA8888_REV:
- format = COLOR_8_8_8_8;
- comp_swap = SWAP_STD;
- number_type = NUMBER_UNORM;
- source_format = 1;
- break;
- case MESA_FORMAT_SIGNED_RGBA8888_REV:
- format = COLOR_8_8_8_8;
- comp_swap = SWAP_STD;
- number_type = NUMBER_SNORM;
- source_format = 1;
- break;
- case MESA_FORMAT_ARGB8888:
- case MESA_FORMAT_XRGB8888:
- format = COLOR_8_8_8_8;
- comp_swap = SWAP_ALT;
- number_type = NUMBER_UNORM;
- source_format = 1;
- break;
- case MESA_FORMAT_ARGB8888_REV:
- case MESA_FORMAT_XRGB8888_REV:
- format = COLOR_8_8_8_8;
- comp_swap = SWAP_ALT_REV;
- number_type = NUMBER_UNORM;
- source_format = 1;
- break;
- case MESA_FORMAT_RGB565:
- format = COLOR_5_6_5;
- comp_swap = SWAP_STD_REV;
- number_type = NUMBER_UNORM;
- source_format = 1;
- break;
- case MESA_FORMAT_RGB565_REV:
- format = COLOR_5_6_5;
- comp_swap = SWAP_STD;
- number_type = NUMBER_UNORM;
- source_format = 1;
- break;
- case MESA_FORMAT_ARGB4444:
- format = COLOR_4_4_4_4;
- comp_swap = SWAP_ALT;
- number_type = NUMBER_UNORM;
- source_format = 1;
- break;
- case MESA_FORMAT_ARGB4444_REV:
- format = COLOR_4_4_4_4;
- comp_swap = SWAP_ALT_REV;
- number_type = NUMBER_UNORM;
- source_format = 1;
- break;
- case MESA_FORMAT_ARGB1555:
- format = COLOR_1_5_5_5;
- comp_swap = SWAP_ALT;
- number_type = NUMBER_UNORM;
- source_format = 1;
- break;
- case MESA_FORMAT_ARGB1555_REV:
- format = COLOR_1_5_5_5;
- comp_swap = SWAP_ALT_REV;
- number_type = NUMBER_UNORM;
- source_format = 1;
- break;
- case MESA_FORMAT_AL88:
- format = COLOR_8_8;
- comp_swap = SWAP_STD;
- number_type = NUMBER_UNORM;
- source_format = 1;
- break;
- case MESA_FORMAT_AL88_REV:
- format = COLOR_8_8;
- comp_swap = SWAP_STD_REV;
- number_type = NUMBER_UNORM;
- source_format = 1;
- break;
- case MESA_FORMAT_RGB332:
- format = COLOR_3_3_2;
- comp_swap = SWAP_STD_REV;
- number_type = NUMBER_UNORM;
- source_format = 1;
- break;
- case MESA_FORMAT_A8:
- format = COLOR_8;
- comp_swap = SWAP_ALT_REV;
- number_type = NUMBER_UNORM;
- source_format = 1;
- break;
- case MESA_FORMAT_I8:
- format = COLOR_8;
- comp_swap = SWAP_STD;
- number_type = NUMBER_UNORM;
- source_format = 1;
- break;
- case MESA_FORMAT_L8:
- format = COLOR_8;
- comp_swap = SWAP_ALT;
- number_type = NUMBER_UNORM;
- source_format = 1;
- break;
- case MESA_FORMAT_RGBA_FLOAT32:
- format = COLOR_32_32_32_32_FLOAT;
- comp_swap = SWAP_STD_REV;
- number_type = NUMBER_FLOAT;
- source_format = 0;
- break;
- case MESA_FORMAT_RGBA_FLOAT16:
- format = COLOR_16_16_16_16_FLOAT;
- comp_swap = SWAP_STD_REV;
- number_type = NUMBER_FLOAT;
- source_format = 0;
- break;
- case MESA_FORMAT_ALPHA_FLOAT32:
- format = COLOR_32_FLOAT;
- comp_swap = SWAP_ALT_REV;
- number_type = NUMBER_FLOAT;
- source_format = 0;
- break;
- case MESA_FORMAT_ALPHA_FLOAT16:
- format = COLOR_16_FLOAT;
- comp_swap = SWAP_ALT_REV;
- number_type = NUMBER_FLOAT;
- source_format = 0;
- break;
- case MESA_FORMAT_LUMINANCE_FLOAT32:
- format = COLOR_32_FLOAT;
- comp_swap = SWAP_ALT;
- number_type = NUMBER_FLOAT;
- source_format = 0;
- break;
- case MESA_FORMAT_LUMINANCE_FLOAT16:
- format = COLOR_16_FLOAT;
- comp_swap = SWAP_ALT;
- number_type = NUMBER_FLOAT;
- source_format = 0;
- break;
- case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32:
- format = COLOR_32_32_FLOAT;
- comp_swap = SWAP_ALT_REV;
- number_type = NUMBER_FLOAT;
- source_format = 0;
- break;
- case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16:
- format = COLOR_16_16_FLOAT;
- comp_swap = SWAP_ALT_REV;
- number_type = NUMBER_FLOAT;
- source_format = 0;
- break;
- case MESA_FORMAT_INTENSITY_FLOAT32: /* X, X, X, X */
- format = COLOR_32_FLOAT;
- comp_swap = SWAP_STD;
- number_type = NUMBER_FLOAT;
- source_format = 0;
- break;
- case MESA_FORMAT_INTENSITY_FLOAT16: /* X, X, X, X */
- format = COLOR_16_FLOAT;
- comp_swap = SWAP_STD;
- number_type = NUMBER_UNORM;
- source_format = 0;
- break;
- case MESA_FORMAT_X8_Z24:
- case MESA_FORMAT_S8_Z24:
- format = COLOR_8_24;
- comp_swap = SWAP_STD;
- number_type = NUMBER_UNORM;
- SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
- ARRAY_1D_TILED_THIN1,
- EG_CB_COLOR0_INFO__ARRAY_MODE_shift,
- EG_CB_COLOR0_INFO__ARRAY_MODE_mask);
- source_format = 0;
- break;
- case MESA_FORMAT_Z24_S8:
- format = COLOR_24_8;
- comp_swap = SWAP_STD;
- number_type = NUMBER_UNORM;
- SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
- ARRAY_1D_TILED_THIN1,
- EG_CB_COLOR0_INFO__ARRAY_MODE_shift,
- EG_CB_COLOR0_INFO__ARRAY_MODE_mask);
- source_format = 0;
- break;
- case MESA_FORMAT_Z16:
- format = COLOR_16;
- comp_swap = SWAP_STD;
- number_type = NUMBER_UNORM;
- SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
- ARRAY_1D_TILED_THIN1,
- EG_CB_COLOR0_INFO__ARRAY_MODE_shift,
- EG_CB_COLOR0_INFO__ARRAY_MODE_mask);
- source_format = 0;
- break;
- case MESA_FORMAT_Z32:
- format = COLOR_32;
- comp_swap = SWAP_STD;
- number_type = NUMBER_UNORM;
- SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
- ARRAY_1D_TILED_THIN1,
- EG_CB_COLOR0_INFO__ARRAY_MODE_shift,
- EG_CB_COLOR0_INFO__ARRAY_MODE_mask);
- source_format = 0;
- break;
- case MESA_FORMAT_SARGB8:
- format = COLOR_8_8_8_8;
- comp_swap = SWAP_ALT;
- number_type = NUMBER_SRGB;
- source_format = 1;
- break;
- case MESA_FORMAT_SLA8:
- format = COLOR_8_8;
- comp_swap = SWAP_ALT_REV;
- number_type = NUMBER_SRGB;
- source_format = 1;
- break;
- case MESA_FORMAT_SL8:
- format = COLOR_8;
- comp_swap = SWAP_ALT_REV;
- number_type = NUMBER_SRGB;
- source_format = 1;
- break;
- default:
- _mesa_problem(context->radeon.glCtx, "unexpected format in evergreenSetRenderTarget()");
- break;
- }
-
- SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
- format,
- EG_CB_COLOR0_INFO__FORMAT_shift,
- EG_CB_COLOR0_INFO__FORMAT_mask);
- SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
- comp_swap,
- EG_CB_COLOR0_INFO__COMP_SWAP_shift,
- EG_CB_COLOR0_INFO__COMP_SWAP_mask);
- SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
- number_type,
- EG_CB_COLOR0_INFO__NUMBER_TYPE_shift,
- EG_CB_COLOR0_INFO__NUMBER_TYPE_mask);
- SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
- source_format,
- EG_CB_COLOR0_INFO__SOURCE_FORMAT_shift,
- EG_CB_COLOR0_INFO__SOURCE_FORMAT_mask);
- SETbit(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
- EG_CB_COLOR0_INFO__BLEND_CLAMP_bit);
-
- evergreen->render_target[id].CB_COLOR0_VIEW.u32All = 0;
- evergreen->render_target[id].CB_COLOR0_CMASK.u32All = 0;
- evergreen->render_target[id].CB_COLOR0_FMASK.u32All = 0;
- evergreen->render_target[id].CB_COLOR0_FMASK_SLICE.u32All = 0;
-
- evergreen->render_target[id].enabled = GL_TRUE;
-}
-
-static void evergreenSendCB(struct gl_context *ctx, struct radeon_state_atom *atom)
-{
- context_t *context = EVERGREEN_CONTEXT(ctx);
- EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
- struct radeon_renderbuffer *rrb;
- BATCH_LOCALS(&context->radeon);
- int id = 0;
- radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
-
- rrb = radeon_get_colorbuffer(&context->radeon);
- if (!rrb || !rrb->bo) {
- return;
- }
-
- evergreenSetRenderTarget(context, 0);
-
- if (!evergreen->render_target[id].enabled)
- return;
-
- BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
- EVERGREEN_OUT_BATCH_REGSEQ(EG_CB_COLOR0_BASE + (4 * id), 1);
- R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_BASE.u32All);
- R600_OUT_BATCH_RELOC(evergreen->render_target[id].CB_COLOR0_BASE.u32All,
- rrb->bo,
- evergreen->render_target[id].CB_COLOR0_BASE.u32All,
- 0, RADEON_GEM_DOMAIN_VRAM, 0);
- END_BATCH();
-
- BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
- EVERGREEN_OUT_BATCH_REGVAL(EG_CB_COLOR0_INFO, evergreen->render_target[id].CB_COLOR0_INFO.u32All);
- R600_OUT_BATCH_RELOC(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
- rrb->bo,
- evergreen->render_target[id].CB_COLOR0_INFO.u32All,
- 0, RADEON_GEM_DOMAIN_VRAM, 0);
- END_BATCH();
-
- BEGIN_BATCH_NO_AUTOSTATE(5);
- EVERGREEN_OUT_BATCH_REGSEQ(EG_CB_COLOR0_PITCH, 3);
- R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_PITCH.u32All);
- R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_SLICE.u32All);
- R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_VIEW.u32All);
- END_BATCH();
-
- BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
- EVERGREEN_OUT_BATCH_REGSEQ(EG_CB_COLOR0_ATTRIB, 1);
- R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_ATTRIB.u32All);
- R600_OUT_BATCH_RELOC(0,
- rrb->bo,
- 0,
- 0, RADEON_GEM_DOMAIN_VRAM, 0);
- END_BATCH();
-
- BEGIN_BATCH_NO_AUTOSTATE(3);
- EVERGREEN_OUT_BATCH_REGSEQ(EG_CB_COLOR0_DIM, 1);
- R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_DIM.u32All);
- /*
- R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_CMASK.u32All);
- R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_CMASK_SLICE.u32All);
- R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_FMASK.u32All);
- R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_FMASK_SLICE.u32All);
- */
- END_BATCH();
-
- BEGIN_BATCH_NO_AUTOSTATE(4);
- EVERGREEN_OUT_BATCH_REGSEQ(EG_CB_TARGET_MASK, 2);
- R600_OUT_BATCH(evergreen->CB_TARGET_MASK.u32All);
- R600_OUT_BATCH(evergreen->CB_SHADER_MASK.u32All);
- END_BATCH();
-
- BEGIN_BATCH_NO_AUTOSTATE(6);
- EVERGREEN_OUT_BATCH_REGSEQ(EG_CB_BLEND_RED, 4);
- R600_OUT_BATCH(evergreen->CB_BLEND_RED.u32All);
- R600_OUT_BATCH(evergreen->CB_BLEND_GREEN.u32All);
- R600_OUT_BATCH(evergreen->CB_BLEND_BLUE.u32All);
- R600_OUT_BATCH(evergreen->CB_BLEND_ALPHA.u32All);
- END_BATCH();
-
- BEGIN_BATCH_NO_AUTOSTATE(6);
- EVERGREEN_OUT_BATCH_REGVAL(EG_CB_BLEND0_CONTROL, evergreen->CB_BLEND0_CONTROL.u32All);
- EVERGREEN_OUT_BATCH_REGVAL(EG_CB_COLOR_CONTROL, evergreen->CB_COLOR_CONTROL.u32All);
- END_BATCH();
-
- COMMIT_BATCH();
-}
-
-static void evergreenSendVGT(struct gl_context *ctx, struct radeon_state_atom *atom)
-{
- context_t *context = EVERGREEN_CONTEXT(ctx);
- EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
- BATCH_LOCALS(&context->radeon);
- radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
-
-/* moved to draw:
- VGT_DRAW_INITIATOR
- VGT_INDEX_TYPE
- VGT_PRIMITIVE_TYPE
-*/
- BEGIN_BATCH_NO_AUTOSTATE(5);
- EVERGREEN_OUT_BATCH_REGSEQ(EG_VGT_MAX_VTX_INDX, 3);
- R600_OUT_BATCH(evergreen->VGT_MAX_VTX_INDX.u32All);
- R600_OUT_BATCH(evergreen->VGT_MIN_VTX_INDX.u32All);
- R600_OUT_BATCH(evergreen->VGT_INDX_OFFSET.u32All);
- END_BATCH();
-
- BEGIN_BATCH_NO_AUTOSTATE(6);
- EVERGREEN_OUT_BATCH_REGVAL(EG_VGT_OUTPUT_PATH_CNTL, evergreen->VGT_OUTPUT_PATH_CNTL.u32All);
-
- EVERGREEN_OUT_BATCH_REGVAL(EG_VGT_GS_MODE, evergreen->VGT_GS_MODE.u32All);
- END_BATCH();
-
- BEGIN_BATCH_NO_AUTOSTATE(3);
- EVERGREEN_OUT_BATCH_REGSEQ(EG_VGT_PRIMITIVEID_EN, 1);
- R600_OUT_BATCH(evergreen->VGT_PRIMITIVEID_EN.u32All);
- END_BATCH();
-
- BEGIN_BATCH_NO_AUTOSTATE(4);
- EVERGREEN_OUT_BATCH_REGSEQ(EG_VGT_INSTANCE_STEP_RATE_0, 2);
- R600_OUT_BATCH(evergreen->VGT_INSTANCE_STEP_RATE_0.u32All);
- R600_OUT_BATCH(evergreen->VGT_INSTANCE_STEP_RATE_1.u32All);
- END_BATCH();
-
- BEGIN_BATCH_NO_AUTOSTATE(4);
- EVERGREEN_OUT_BATCH_REGSEQ(EG_VGT_REUSE_OFF, 2);
- R600_OUT_BATCH(evergreen->VGT_REUSE_OFF.u32All);
- R600_OUT_BATCH(evergreen->VGT_VTX_CNT_EN.u32All);
- END_BATCH();
-
- BEGIN_BATCH_NO_AUTOSTATE(3);
- EVERGREEN_OUT_BATCH_REGVAL(EG_VGT_SHADER_STAGES_EN, evergreen->VGT_SHADER_STAGES_EN.u32All);
- END_BATCH();
-
- BEGIN_BATCH_NO_AUTOSTATE(4);
- EVERGREEN_OUT_BATCH_REGSEQ(EG_VGT_STRMOUT_CONFIG, 2);
- R600_OUT_BATCH(evergreen->VGT_STRMOUT_CONFIG.u32All);
- R600_OUT_BATCH(evergreen->VGT_STRMOUT_BUFFER_CONFIG.u32All);
- END_BATCH();
-
- COMMIT_BATCH();
-}
-
-void evergreenInitAtoms(context_t *context)
-{
- radeon_print(RADEON_STATE, RADEON_NORMAL, "%s %p\n", __func__, context);
- context->radeon.hw.max_state_size = 10 + 5 + 14 + 3; /* start 3d, idle, cb/db flush, 3 for time stamp */
-
- /* Setup the atom linked list */
- make_empty_list(&context->radeon.hw.atomlist);
- context->radeon.hw.atomlist.name = "atom-list";
-
- EVERGREEN_ALLOC_STATE(init, always, 19, evergreenSendSQConfig);
- EVERGREEN_ALLOC_STATE(vtx, evergreen_vtx, (VERT_ATTRIB_MAX * 12), evergreenSendVTX);
- EVERGREEN_ALLOC_STATE(pa, always, 124, evergreenSendPA);
- EVERGREEN_ALLOC_STATE(tp, always, 0, evergreenSendTP);
- EVERGREEN_ALLOC_STATE(sq, always, 86, evergreenSendSQ); /* 85 */
- EVERGREEN_ALLOC_STATE(vs, always, 16, evergreenSendVSresource);
- EVERGREEN_ALLOC_STATE(spi, always, 59, evergreenSendSPI);
- EVERGREEN_ALLOC_STATE(sx, always, 9, evergreenSendSX);
- EVERGREEN_ALLOC_STATE(tx, evergreen_tx, (R700_TEXTURE_NUMBERUNITS * (21+5) + 6), evergreenSendTexState); /* 21 for resource, 5 for sampler */
- EVERGREEN_ALLOC_STATE(db, always, 69, evergreenSendDB);
- EVERGREEN_ALLOC_STATE(cb, always, 37, evergreenSendCB);
- EVERGREEN_ALLOC_STATE(vgt, always, 29, evergreenSendVGT);
-
- evergreen_init_query_stateobj(&context->radeon, 6 * 2);
-
- context->radeon.hw.is_dirty = GL_TRUE;
- context->radeon.hw.all_dirty = GL_TRUE;
-}
+++ /dev/null
-/*
- * Copyright (C) 2008-2010 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Authors:
- * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
- */
-
-#ifndef _EVERGREEN_CHIP_H_
-#define _EVERGREEN_CHIP_H_
-
-#include "r700_chip.h"
-
-#define EVERGREEN_MAX_DX9_CONSTS 256
-#define EVERGREEN_MAX_SHADER_EXPORTS 32
-#define EVERGREEN_MAX_VIEWPORTS 16
-
-typedef struct _EVERGREEN_VIEWPORT_STATE
-{
- union UINT_FLOAT PA_SC_VPORT_SCISSOR_0_TL; ////0,1 // = 0x28250, // DIFF
- union UINT_FLOAT PA_SC_VPORT_SCISSOR_0_BR; ////0,1 // = 0x28254, // DIFF
- union UINT_FLOAT PA_SC_VPORT_ZMIN_0; ////0 // = 0x282D0, // SAME
- union UINT_FLOAT PA_SC_VPORT_ZMAX_0; ////0 // = 0x282D4, // SAME
- union UINT_FLOAT PA_CL_VPORT_XSCALE; //// // = 0x2843C, // SAME
- union UINT_FLOAT PA_CL_VPORT_XOFFSET; //// // = 0x28440, // SAME
- union UINT_FLOAT PA_CL_VPORT_YSCALE; //// // = 0x28444, // SAME
- union UINT_FLOAT PA_CL_VPORT_YOFFSET; //// // = 0x28448, // SAME
- union UINT_FLOAT PA_CL_VPORT_ZSCALE; //// // = 0x2844C, // SAME
- union UINT_FLOAT PA_CL_VPORT_ZOFFSET; //// // = 0x28450, // SAME
- GLboolean enabled;
- GLboolean dirty;
-} EVERGREEN_VIEWPORT_STATE;
-
-#define EVERGREEN_MAX_UCP 6
-
-typedef struct _EVERGREEN_UCP_STATE
-{
- union UINT_FLOAT PA_CL_UCP_0_X; // = 0x285BC, // SAME 0x28E20
- union UINT_FLOAT PA_CL_UCP_0_Y; // = 0x285C0, // SAME 0x28E24
- union UINT_FLOAT PA_CL_UCP_0_Z; // = 0x285C4, // SAME 0x28E28
- union UINT_FLOAT PA_CL_UCP_0_W; // = 0x285C8, // SAME 0x28E2C
- GLboolean enabled;
- GLboolean dirty;
-} EVERGREEN_UCP_STATE;
-
-#define EVERGREEN_MAX_RENDER_TARGETS 12
-
-typedef struct _EVERGREEN_RENDER_TARGET_STATE
-{
- union UINT_FLOAT CB_COLOR0_BASE; ////0 // = 0x28C60, // SAME 0x28040
- union UINT_FLOAT CB_COLOR0_PITCH; ////0 // = 0x28C64, //
- union UINT_FLOAT CB_COLOR0_SLICE; ////0 // = 0x28C68, //
- union UINT_FLOAT CB_COLOR0_VIEW; ////0 // = 0x28C6C, // SAME 0x28080
- union UINT_FLOAT CB_COLOR0_INFO; ////0,1,2,3,4,5,6,78,9,10,11 // = 0x28C70, // DIFF 0x280A0
- union UINT_FLOAT CB_COLOR0_ATTRIB; ////0 // = 0x28C74, //
- union UINT_FLOAT CB_COLOR0_DIM; // = 0x28C78, //
- union UINT_FLOAT CB_COLOR0_CMASK; ////0 // = 0x28C7C, //
- union UINT_FLOAT CB_COLOR0_CMASK_SLICE; ////0 // = 0x28C80, //
- union UINT_FLOAT CB_COLOR0_FMASK; ////0 // = 0x28C84, //
- union UINT_FLOAT CB_COLOR0_FMASK_SLICE; ////0 // = 0x28C88, //
- union UINT_FLOAT CB_COLOR0_CLEAR_WORD0; // = 0x28C8C, //
- union UINT_FLOAT CB_COLOR0_CLEAR_WORD1; // = 0x28C90, //
- union UINT_FLOAT CB_COLOR0_CLEAR_WORD2; // = 0x28C94, //
- union UINT_FLOAT CB_COLOR0_CLEAR_WORD3; // = 0x28C98, //
- GLboolean enabled;
- GLboolean dirty;
-} EVERGREEN_RENDER_TARGET_STATE;
-
-typedef struct _EVERGREEN_CONFIG
-{
- union UINT_FLOAT SPI_CONFIG_CNTL; // = 0x9100, // DIFF
- union UINT_FLOAT SPI_CONFIG_CNTL_1; // = 0x913C, // DIFF
- union UINT_FLOAT CP_PERFMON_CNTL; // = 0x87FC, // SAME
- union UINT_FLOAT SQ_MS_FIFO_SIZES; // = 0x8CF0, // SAME
-
- union UINT_FLOAT SQ_CONFIG; // = 0x8C00, // DIFF
- union UINT_FLOAT SQ_GPR_RESOURCE_MGMT_1; // = 0x8C04, // SAME
- union UINT_FLOAT SQ_GPR_RESOURCE_MGMT_2; // = 0x8C08, // SAME
- union UINT_FLOAT SQ_GPR_RESOURCE_MGMT_3; // = 0x8C0C, //
-
- union UINT_FLOAT SQ_THREAD_RESOURCE_MGMT; // = 0x8C18, // SAME 0x8C0C
- union UINT_FLOAT SQ_THREAD_RESOURCE_MGMT_2; // = 0x8C1C, //
- union UINT_FLOAT SQ_STACK_RESOURCE_MGMT_1; // = 0x8C20, // SAME 0x8C10
- union UINT_FLOAT SQ_STACK_RESOURCE_MGMT_2; // = 0x8C24, // SAME 0x8C14
- union UINT_FLOAT SQ_STACK_RESOURCE_MGMT_3; // = 0x8C28, //
-
- union UINT_FLOAT SQ_DYN_GPR_CNTL_PS_FLUSH_REQ; // = 0x8D8C, // DIFF
- union UINT_FLOAT SQ_LDS_RESOURCE_MGMT; // = 0x8E2C, //
- union UINT_FLOAT VGT_CACHE_INVALIDATION; // = 0x88C4, // DIFF
- union UINT_FLOAT VGT_GS_VERTEX_REUSE; // = 0x88D4, // SAME
- union UINT_FLOAT PA_SC_FORCE_EOV_MAX_CNTS; // = 0x8B24, // SAME
- union UINT_FLOAT PA_SC_LINE_STIPPLE_STATE; // = 0x8B10, // SAME
- union UINT_FLOAT PA_CL_ENHANCE; // = 0x8A14, // SAME
-} EVERGREEN_CONFIG;
-
-typedef struct _EVERGREEN_PS_RES
-{
- union UINT_FLOAT SQ_PGM_START_PS; //// // = 0x28840, // SAME
- GLboolean dirty;
-
- union UINT_FLOAT SQ_ALU_CONST_CACHE_PS_0; // = 0x28940, // SAME
- union UINT_FLOAT SQ_ALU_CONST_CACHE_PS_1; // = 0x28944, // SAME
- union UINT_FLOAT SQ_ALU_CONST_CACHE_PS_2; // = 0x28948, // SAME
- union UINT_FLOAT SQ_ALU_CONST_CACHE_PS_3; // = 0x2894C, // SAME
- union UINT_FLOAT SQ_ALU_CONST_CACHE_PS_4; // = 0x28950, // SAME
- union UINT_FLOAT SQ_ALU_CONST_CACHE_PS_5; // = 0x28954, // SAME
- union UINT_FLOAT SQ_ALU_CONST_CACHE_PS_6; // = 0x28958, // SAME
- union UINT_FLOAT SQ_ALU_CONST_CACHE_PS_7; // = 0x2895C, // SAME
- union UINT_FLOAT SQ_ALU_CONST_CACHE_PS_8; // = 0x28960, // SAME
- union UINT_FLOAT SQ_ALU_CONST_CACHE_PS_9; // = 0x28964, // SAME
- union UINT_FLOAT SQ_ALU_CONST_CACHE_PS_10; // = 0x28968, // SAME
- union UINT_FLOAT SQ_ALU_CONST_CACHE_PS_11; // = 0x2896C, // SAME
- union UINT_FLOAT SQ_ALU_CONST_CACHE_PS_12; // = 0x28970, // SAME
- union UINT_FLOAT SQ_ALU_CONST_CACHE_PS_13; // = 0x28974, // SAME
- union UINT_FLOAT SQ_ALU_CONST_CACHE_PS_14; // = 0x28978, // SAME
- union UINT_FLOAT SQ_ALU_CONST_CACHE_PS_15; // = 0x2897C, // SAME
-
- int num_consts;
- union UINT_FLOAT consts[EVERGREEN_MAX_DX9_CONSTS][4];
-} EVERGREEN_PS_RES;
-
-typedef struct _EVERGREEN_VS_RES
-{
- union UINT_FLOAT SQ_PGM_START_VS; //// // = 0x2885C, // SAME 0x28858
- union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_VS_0; //// // = 0x28180, //?
- union UINT_FLOAT SQ_ALU_CONST_CACHE_VS_0; //// // = 0x28980, // SAME
-
- union UINT_FLOAT SQ_ALU_CONST_CACHE_VS_1; // = 0x28984, // SAME
- union UINT_FLOAT SQ_ALU_CONST_CACHE_VS_2; // = 0x28988, // SAME
- union UINT_FLOAT SQ_ALU_CONST_CACHE_VS_3; // = 0x2898C, // SAME
- union UINT_FLOAT SQ_ALU_CONST_CACHE_VS_4; // = 0x28990, // SAME
- union UINT_FLOAT SQ_ALU_CONST_CACHE_VS_5; // = 0x28994, // SAME
- union UINT_FLOAT SQ_ALU_CONST_CACHE_VS_6; // = 0x28998, // SAME
- union UINT_FLOAT SQ_ALU_CONST_CACHE_VS_7; // = 0x2899C, // SAME
- union UINT_FLOAT SQ_ALU_CONST_CACHE_VS_8; // = 0x289A0, // SAME
- union UINT_FLOAT SQ_ALU_CONST_CACHE_VS_9; // = 0x289A4, // SAME
- union UINT_FLOAT SQ_ALU_CONST_CACHE_VS_10; // = 0x289A8, // SAME
- union UINT_FLOAT SQ_ALU_CONST_CACHE_VS_11; // = 0x289AC, // SAME
- union UINT_FLOAT SQ_ALU_CONST_CACHE_VS_12; // = 0x289B0, // SAME
- union UINT_FLOAT SQ_ALU_CONST_CACHE_VS_13; // = 0x289B4, // SAME
- union UINT_FLOAT SQ_ALU_CONST_CACHE_VS_14; // = 0x289B8, // SAME
- union UINT_FLOAT SQ_ALU_CONST_CACHE_VS_15; // = 0x289BC, // SAME
-
- GLboolean dirty;
- int num_consts;
- union UINT_FLOAT consts[EVERGREEN_MAX_DX9_CONSTS][4];
-} EVERGREEN_VS_RES;
-
-typedef struct _EVERGREEN_CHIP_CONTEXT
-{
-/* Registers from PA block: */
- union UINT_FLOAT PA_SC_SCREEN_SCISSOR_TL; //// // = 0x28030, // DIFF
- union UINT_FLOAT PA_SC_SCREEN_SCISSOR_BR; //// // = 0x28034, // DIFF
- union UINT_FLOAT PA_SC_WINDOW_OFFSET; //// // = 0x28200, // DIFF
- union UINT_FLOAT PA_SC_WINDOW_SCISSOR_TL; //// // = 0x28204, // DIFF
- union UINT_FLOAT PA_SC_WINDOW_SCISSOR_BR; //// // = 0x28208, // DIFF
- union UINT_FLOAT PA_SC_CLIPRECT_RULE; //// // = 0x2820C, // SAME
- union UINT_FLOAT PA_SC_CLIPRECT_0_TL; //// // = 0x28210, // DIFF
- union UINT_FLOAT PA_SC_CLIPRECT_0_BR; //// // = 0x28214, // DIFF
- union UINT_FLOAT PA_SC_CLIPRECT_1_TL; //// // = 0x28218, // DIFF
- union UINT_FLOAT PA_SC_CLIPRECT_1_BR; //// // = 0x2821C, // DIFF
- union UINT_FLOAT PA_SC_CLIPRECT_2_TL; //// // = 0x28220, // DIFF
- union UINT_FLOAT PA_SC_CLIPRECT_2_BR; //// // = 0x28224, // DIFF
- union UINT_FLOAT PA_SC_CLIPRECT_3_TL; //// // = 0x28228, // DIFF
- union UINT_FLOAT PA_SC_CLIPRECT_3_BR; //// // = 0x2822C, // DIFF
- union UINT_FLOAT PA_SC_EDGERULE; // = 0x28230, // SAME
- union UINT_FLOAT PA_SU_HARDWARE_SCREEN_OFFSET; // = 0x28234, //
- union UINT_FLOAT PA_SC_GENERIC_SCISSOR_TL; //// // = 0x28240, // DIFF
- union UINT_FLOAT PA_SC_GENERIC_SCISSOR_BR; //// // = 0x28244, // DIFF
-
- EVERGREEN_VIEWPORT_STATE viewport[EVERGREEN_MAX_VIEWPORTS];
- EVERGREEN_UCP_STATE ucp[EVERGREEN_MAX_UCP];
-
- union UINT_FLOAT PA_CL_POINT_X_RAD; // = 0x287D4, // SAME 0x28E10
- union UINT_FLOAT PA_CL_POINT_Y_RAD; // = 0x287D8, // SAME 0x28E14
- union UINT_FLOAT PA_CL_POINT_SIZE; // = 0x287DC, // SAME 0x28E18
- union UINT_FLOAT PA_CL_POINT_CULL_RAD; // = 0x287E0, // SAME 0x28E1C
- union UINT_FLOAT PA_CL_CLIP_CNTL; //// // = 0x28810, // SAME
- union UINT_FLOAT PA_SU_SC_MODE_CNTL; //// // = 0x28814, // SAME
- union UINT_FLOAT PA_CL_VTE_CNTL; //// // = 0x28818, // SAME
- union UINT_FLOAT PA_CL_VS_OUT_CNTL; //// // = 0x2881C, // SAME
- union UINT_FLOAT PA_CL_NANINF_CNTL; //// // = 0x28820, // SAME
- union UINT_FLOAT PA_SU_LINE_STIPPLE_CNTL; // = 0x28824, //
- union UINT_FLOAT PA_SU_LINE_STIPPLE_SCALE; // = 0x28828, //
- union UINT_FLOAT PA_SU_PRIM_FILTER_CNTL; // = 0x2882C, //
- union UINT_FLOAT PA_SU_POINT_SIZE; //// // = 0x28A00, // SAME
- union UINT_FLOAT PA_SU_POINT_MINMAX; //// // = 0x28A04, // SAME
- union UINT_FLOAT PA_SU_LINE_CNTL; //// // = 0x28A08, // SAME
- union UINT_FLOAT PA_SC_LINE_STIPPLE; // = 0x28A0C, // SAME
- union UINT_FLOAT PA_SC_MODE_CNTL_0; //// // = 0x28A48, //
- union UINT_FLOAT PA_SC_MODE_CNTL_1; //// // = 0x28A4C, //
- union UINT_FLOAT PA_SU_POLY_OFFSET_DB_FMT_CNTL; //// // = 0x28B78, // SAME 0x28DF8
- union UINT_FLOAT PA_SU_POLY_OFFSET_CLAMP; //// // = 0x28B7C, // SAME 0x28DFC
- union UINT_FLOAT PA_SU_POLY_OFFSET_FRONT_SCALE;//// // = 0x28B80, // SAME 0x28E00
- union UINT_FLOAT PA_SU_POLY_OFFSET_FRONT_OFFSET; //// // = 0x28B84, // SAME 0x28E04
- union UINT_FLOAT PA_SU_POLY_OFFSET_BACK_SCALE; //// // = 0x28B88, // SAME 0x28E08
- union UINT_FLOAT PA_SU_POLY_OFFSET_BACK_OFFSET; //// // = 0x28B8C, // SAME 0x28E0C
- union UINT_FLOAT PA_SC_LINE_CNTL; //// // = 0x28C00, // DIFF
- union UINT_FLOAT PA_SC_AA_CONFIG; //// // = 0x28C04, // SAME
- union UINT_FLOAT PA_SU_VTX_CNTL; //// // = 0x28C08, // SAME
- union UINT_FLOAT PA_CL_GB_VERT_CLIP_ADJ; //// // = 0x28C0C, // SAME
- union UINT_FLOAT PA_CL_GB_VERT_DISC_ADJ; //// // = 0x28C10, // SAME
- union UINT_FLOAT PA_CL_GB_HORZ_CLIP_ADJ; //// // = 0x28C14, // SAME
- union UINT_FLOAT PA_CL_GB_HORZ_DISC_ADJ; //// // = 0x28C18, // SAME
- union UINT_FLOAT PA_SC_AA_SAMPLE_LOCS_0; //// // = 0x28C1C, //
- union UINT_FLOAT PA_SC_AA_SAMPLE_LOCS_1; //// // = 0x28C20, //
- union UINT_FLOAT PA_SC_AA_SAMPLE_LOCS_2; //// // = 0x28C24, //
- union UINT_FLOAT PA_SC_AA_SAMPLE_LOCS_3; //// // = 0x28C28, //
- union UINT_FLOAT PA_SC_AA_SAMPLE_LOCS_4; //// // = 0x28C2C, //
- union UINT_FLOAT PA_SC_AA_SAMPLE_LOCS_5; //// // = 0x28C30, //
- union UINT_FLOAT PA_SC_AA_SAMPLE_LOCS_6; //// // = 0x28C34, //
- union UINT_FLOAT PA_SC_AA_SAMPLE_LOCS_7; //// // = 0x28C38, //
- union UINT_FLOAT PA_SC_AA_MASK; //// // = 0x28C3C, // SAME 0x28C48
-
-/* Registers from VGT block: */
- union UINT_FLOAT VGT_INDEX_TYPE; // = 0x895C, // SAME
- union UINT_FLOAT VGT_PRIMITIVE_TYPE; // = 0x8958, // SAME
- union UINT_FLOAT VGT_MAX_VTX_INDX; //// // = 0x28400, // SAME
- union UINT_FLOAT VGT_MIN_VTX_INDX; //// // = 0x28404, // SAME
- union UINT_FLOAT VGT_INDX_OFFSET; //// // = 0x28408, // SAME
- union UINT_FLOAT VGT_MULTI_PRIM_IB_RESET_INDX; // = 0x2840C, // SAME
-
- union UINT_FLOAT VGT_DRAW_INITIATOR; // = 0x287F0, // SAME
- union UINT_FLOAT VGT_IMMED_DATA; // = 0x287F4, // SAME
-
- union UINT_FLOAT VGT_OUTPUT_PATH_CNTL; //// // = 0x28A10, // DIFF
- union UINT_FLOAT VGT_HOS_CNTL; // = 0x28A14, // SAME
- union UINT_FLOAT VGT_HOS_MAX_TESS_LEVEL; // = 0x28A18, // SAME
- union UINT_FLOAT VGT_HOS_MIN_TESS_LEVEL; // = 0x28A1C, // SAME
- union UINT_FLOAT VGT_HOS_REUSE_DEPTH; // = 0x28A20, // SAME
- union UINT_FLOAT VGT_GROUP_PRIM_TYPE; // = 0x28A24, // SAME
- union UINT_FLOAT VGT_GROUP_FIRST_DECR; // = 0x28A28, // SAME
- union UINT_FLOAT VGT_GROUP_DECR; // = 0x28A2C, // SAME
- union UINT_FLOAT VGT_GROUP_VECT_0_CNTL; // = 0x28A30, // SAME
- union UINT_FLOAT VGT_GROUP_VECT_1_CNTL; // = 0x28A34, // SAME
- union UINT_FLOAT VGT_GROUP_VECT_0_FMT_CNTL; // = 0x28A38, // SAME
- union UINT_FLOAT VGT_GROUP_VECT_1_FMT_CNTL; // = 0x28A3C, // SAME
- union UINT_FLOAT VGT_GS_MODE; //// // = 0x28A40, // DIFF
-
- union UINT_FLOAT VGT_PRIMITIVEID_EN; //// // = 0x28A84, // SAME
- union UINT_FLOAT VGT_DMA_NUM_INSTANCES; //// // = 0x28A88, // SAME
- union UINT_FLOAT VGT_EVENT_INITIATOR; // = 0x28A90, // SAME
- union UINT_FLOAT VGT_MULTI_PRIM_IB_RESET_EN; // = 0x28A94, // SAME
- union UINT_FLOAT VGT_INSTANCE_STEP_RATE_0; //// // = 0x28AA0, // SAME
- union UINT_FLOAT VGT_INSTANCE_STEP_RATE_1; //// // = 0x28AA4, // SAME
- union UINT_FLOAT VGT_REUSE_OFF; //// // = 0x28AB4, // SAME
- union UINT_FLOAT VGT_VTX_CNT_EN; //// // = 0x28AB8, // SAME
-
- union UINT_FLOAT VGT_SHADER_STAGES_EN; //// // = 0x28B54, //
-
- union UINT_FLOAT VGT_STRMOUT_CONFIG; //// // = 0x28B94, //
- union UINT_FLOAT VGT_STRMOUT_BUFFER_CONFIG; //// // = 0x28B98, //
- union UINT_FLOAT VGT_VERTEX_REUSE_BLOCK_CNTL;//// // = 0x28C58, // SAME
- union UINT_FLOAT VGT_OUT_DEALLOC_CNTL; //// // = 0x28C5C, // SAME
-
-/* Registers from SQ block: */
- union UINT_FLOAT SQ_VTX_SEMANTIC_0; //// // = 0x28380, // SAME
- union UINT_FLOAT SQ_VTX_SEMANTIC_1; //// // = 0x28384, // SAME
- union UINT_FLOAT SQ_VTX_SEMANTIC_2; //// // = 0x28388, // SAME
- union UINT_FLOAT SQ_VTX_SEMANTIC_3; //// // = 0x2838C, // SAME
- union UINT_FLOAT SQ_VTX_SEMANTIC_4; //// // = 0x28390, // SAME
- union UINT_FLOAT SQ_VTX_SEMANTIC_5; //// // = 0x28394, // SAME
- union UINT_FLOAT SQ_VTX_SEMANTIC_6; //// // = 0x28398, // SAME
- union UINT_FLOAT SQ_VTX_SEMANTIC_7; //// // = 0x2839C, // SAME
- union UINT_FLOAT SQ_VTX_SEMANTIC_8; //// // = 0x283A0, // SAME
- union UINT_FLOAT SQ_VTX_SEMANTIC_9; //// // = 0x283A4, // SAME
- union UINT_FLOAT SQ_VTX_SEMANTIC_10; //// // = 0x283A8, // SAME
- union UINT_FLOAT SQ_VTX_SEMANTIC_11; //// // = 0x283AC, // SAME
- union UINT_FLOAT SQ_VTX_SEMANTIC_12; //// // = 0x283B0, // SAME
- union UINT_FLOAT SQ_VTX_SEMANTIC_13; //// // = 0x283B4, // SAME
- union UINT_FLOAT SQ_VTX_SEMANTIC_14; //// // = 0x283B8, // SAME
- union UINT_FLOAT SQ_VTX_SEMANTIC_15; //// // = 0x283BC, // SAME
- union UINT_FLOAT SQ_VTX_SEMANTIC_16; //// // = 0x283C0, // SAME
- union UINT_FLOAT SQ_VTX_SEMANTIC_17; //// // = 0x283C4, // SAME
- union UINT_FLOAT SQ_VTX_SEMANTIC_18; //// // = 0x283C8, // SAME
- union UINT_FLOAT SQ_VTX_SEMANTIC_19; //// // = 0x283CC, // SAME
- union UINT_FLOAT SQ_VTX_SEMANTIC_20; //// // = 0x283D0, // SAME
- union UINT_FLOAT SQ_VTX_SEMANTIC_21; //// // = 0x283D4, // SAME
- union UINT_FLOAT SQ_VTX_SEMANTIC_22; //// // = 0x283D8, // SAME
- union UINT_FLOAT SQ_VTX_SEMANTIC_23; //// // = 0x283DC, // SAME
- union UINT_FLOAT SQ_VTX_SEMANTIC_24; //// // = 0x283E0, // SAME
- union UINT_FLOAT SQ_VTX_SEMANTIC_25; //// // = 0x283E4, // SAME
- union UINT_FLOAT SQ_VTX_SEMANTIC_26; //// // = 0x283E8, // SAME
- union UINT_FLOAT SQ_VTX_SEMANTIC_27; //// // = 0x283EC, // SAME
- union UINT_FLOAT SQ_VTX_SEMANTIC_28; //// // = 0x283F0, // SAME
- union UINT_FLOAT SQ_VTX_SEMANTIC_29; //// // = 0x283F4, // SAME
- union UINT_FLOAT SQ_VTX_SEMANTIC_30; //// // = 0x283F8, // SAME
- union UINT_FLOAT SQ_VTX_SEMANTIC_31; //// // = 0x283FC, // SAME
- union UINT_FLOAT SQ_DYN_GPR_RESOURCE_LIMIT_1;//// // = 0x28838, //
-
- union UINT_FLOAT SQ_PGM_RESOURCES_PS; //// // = 0x28844, // DIFF 0x28850
- union UINT_FLOAT SQ_PGM_RESOURCES_2_PS; //// // = 0x28848, //
- union UINT_FLOAT SQ_PGM_EXPORTS_PS; //// // = 0x2884C, // SAME 0x28854
-
- union UINT_FLOAT SQ_PGM_RESOURCES_VS;//// // = 0x28860, // DIFF 0x28868
- union UINT_FLOAT SQ_PGM_RESOURCES_2_VS; //// // = 0x28864, //
- union UINT_FLOAT SQ_PGM_START_GS; //// // = 0x28874, // SAME 0x2886C
- union UINT_FLOAT SQ_PGM_RESOURCES_GS; //// // = 0x28878, // DIFF 0x2887C
- union UINT_FLOAT SQ_PGM_RESOURCES_2_GS; //// // = 0x2887C, //
- union UINT_FLOAT SQ_PGM_START_ES; //// // = 0x2888C, // SAME 0x28880
- union UINT_FLOAT SQ_PGM_RESOURCES_ES; //// // = 0x28890, // DIFF
- union UINT_FLOAT SQ_PGM_RESOURCES_2_ES; //// // = 0x28894, //
- union UINT_FLOAT SQ_PGM_START_FS; //// // = 0x288A4, // SAME 0x28894
- union UINT_FLOAT SQ_PGM_RESOURCES_FS; //// // = 0x288A8, // DIFF 0x288A4
- union UINT_FLOAT SQ_PGM_START_HS; // = 0x288B8, //
- union UINT_FLOAT SQ_PGM_RESOURCES_HS; // = 0x288BC, //
- union UINT_FLOAT SQ_PGM_RESOURCES_2_HS;//// // = 0x288C0, //
- union UINT_FLOAT SQ_PGM_START_LS; // = 0x288D0, //
- union UINT_FLOAT SQ_PGM_RESOURCES_LS; // = 0x288D4, //
- union UINT_FLOAT SQ_PGM_RESOURCES_2_LS; //// // = 0x288D8, //
- union UINT_FLOAT SQ_LDS_ALLOC_PS; //// // = 0x288EC, //
- union UINT_FLOAT SQ_ESGS_RING_ITEMSIZE; //// // = 0x28900, // SAME 0x288A8
- union UINT_FLOAT SQ_GSVS_RING_ITEMSIZE; //// // = 0x28904, // SAME 0x288AC
- union UINT_FLOAT SQ_ESTMP_RING_ITEMSIZE; //// // = 0x28908, // SAME 0x288B0
- union UINT_FLOAT SQ_GSTMP_RING_ITEMSIZE; //// // = 0x2890C, // SAME 0x288B4
- union UINT_FLOAT SQ_VSTMP_RING_ITEMSIZE; //// // = 0x28910, // SAME 0x288B8
- union UINT_FLOAT SQ_PSTMP_RING_ITEMSIZE; //// // = 0x28914, // SAME 0x288BC
- union UINT_FLOAT SQ_GS_VERT_ITEMSIZE; //// // = 0x2891C, // SAME 0x288C8
- union UINT_FLOAT SQ_GS_VERT_ITEMSIZE_1; // = 0x28920, //
- union UINT_FLOAT SQ_GS_VERT_ITEMSIZE_2; // = 0x28924, //
- union UINT_FLOAT SQ_GS_VERT_ITEMSIZE_3; // = 0x28928, //
-
- union UINT_FLOAT SQ_ALU_CONST_CACHE_GS_0; // = 0x289C0, // SAME
- union UINT_FLOAT SQ_ALU_CONST_CACHE_GS_1; // = 0x289C4, // SAME
- union UINT_FLOAT SQ_ALU_CONST_CACHE_GS_2; // = 0x289C8, // SAME
- union UINT_FLOAT SQ_ALU_CONST_CACHE_GS_3; // = 0x289CC, // SAME
- union UINT_FLOAT SQ_ALU_CONST_CACHE_GS_4; // = 0x289D0, // SAME
- union UINT_FLOAT SQ_ALU_CONST_CACHE_GS_5; // = 0x289D4, // SAME
- union UINT_FLOAT SQ_ALU_CONST_CACHE_GS_6; // = 0x289D8, // SAME
- union UINT_FLOAT SQ_ALU_CONST_CACHE_GS_7; // = 0x289DC, // SAME
- union UINT_FLOAT SQ_ALU_CONST_CACHE_GS_8; // = 0x289E0, // SAME
- union UINT_FLOAT SQ_ALU_CONST_CACHE_GS_9; // = 0x289E4, // SAME
- union UINT_FLOAT SQ_ALU_CONST_CACHE_GS_10; // = 0x289E8, // SAME
- union UINT_FLOAT SQ_ALU_CONST_CACHE_GS_11; // = 0x289EC, // SAME
- union UINT_FLOAT SQ_ALU_CONST_CACHE_GS_12; // = 0x289F0, // SAME
- union UINT_FLOAT SQ_ALU_CONST_CACHE_GS_13; // = 0x289F4, // SAME
- union UINT_FLOAT SQ_ALU_CONST_CACHE_GS_14; // = 0x289F8, // SAME
- union UINT_FLOAT SQ_ALU_CONST_CACHE_GS_15; // = 0x289FC, // SAME
- union UINT_FLOAT SQ_ALU_CONST_CACHE_HS_0; // = 0x28F00, //
- union UINT_FLOAT SQ_ALU_CONST_CACHE_HS_1; // = 0x28F04, //
- union UINT_FLOAT SQ_ALU_CONST_CACHE_HS_2; // = 0x28F08, //
- union UINT_FLOAT SQ_ALU_CONST_CACHE_HS_3; // = 0x28F0C, //
- union UINT_FLOAT SQ_ALU_CONST_CACHE_HS_4; // = 0x28F10, //
- union UINT_FLOAT SQ_ALU_CONST_CACHE_HS_5; // = 0x28F14, //
- union UINT_FLOAT SQ_ALU_CONST_CACHE_HS_6; // = 0x28F18, //
- union UINT_FLOAT SQ_ALU_CONST_CACHE_HS_7; // = 0x28F1C, //
- union UINT_FLOAT SQ_ALU_CONST_CACHE_HS_8; // = 0x28F20, //
- union UINT_FLOAT SQ_ALU_CONST_CACHE_HS_9; // = 0x28F24, //
- union UINT_FLOAT SQ_ALU_CONST_CACHE_HS_10; // = 0x28F28, //
- union UINT_FLOAT SQ_ALU_CONST_CACHE_HS_11; // = 0x28F2C, //
- union UINT_FLOAT SQ_ALU_CONST_CACHE_HS_12; // = 0x28F30, //
- union UINT_FLOAT SQ_ALU_CONST_CACHE_HS_13; // = 0x28F34, //
- union UINT_FLOAT SQ_ALU_CONST_CACHE_HS_14; // = 0x28F38, //
- union UINT_FLOAT SQ_ALU_CONST_CACHE_HS_15; // = 0x28F3C, //
- union UINT_FLOAT SQ_ALU_CONST_CACHE_LS_0; // = 0x28F40, //
- union UINT_FLOAT SQ_ALU_CONST_CACHE_LS_1; // = 0x28F44, //
- union UINT_FLOAT SQ_ALU_CONST_CACHE_LS_2; // = 0x28F48, //
- union UINT_FLOAT SQ_ALU_CONST_CACHE_LS_3; // = 0x28F4C, //
- union UINT_FLOAT SQ_ALU_CONST_CACHE_LS_4; // = 0x28F50, //
- union UINT_FLOAT SQ_ALU_CONST_CACHE_LS_5; // = 0x28F54, //
- union UINT_FLOAT SQ_ALU_CONST_CACHE_LS_6; // = 0x28F58, //
- union UINT_FLOAT SQ_ALU_CONST_CACHE_LS_7; // = 0x28F5C, //
- union UINT_FLOAT SQ_ALU_CONST_CACHE_LS_8; // = 0x28F60, //
- union UINT_FLOAT SQ_ALU_CONST_CACHE_LS_9; // = 0x28F64, //
- union UINT_FLOAT SQ_ALU_CONST_CACHE_LS_10; // = 0x28F68, //
- union UINT_FLOAT SQ_ALU_CONST_CACHE_LS_11; // = 0x28F6C, //
- union UINT_FLOAT SQ_ALU_CONST_CACHE_LS_12; // = 0x28F70, //
- union UINT_FLOAT SQ_ALU_CONST_CACHE_LS_13; // = 0x28F74, //
- union UINT_FLOAT SQ_ALU_CONST_CACHE_LS_14; // = 0x28F78, //
- union UINT_FLOAT SQ_ALU_CONST_CACHE_LS_15; // = 0x28F7C, //
- union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_HS_0; // = 0x28F80, //
- union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_HS_1; // = 0x28F84, //
- union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_HS_2; // = 0x28F88, //
- union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_HS_3; // = 0x28F8C, //
- union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_HS_4; // = 0x28F90, //
- union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_HS_5; // = 0x28F94, //
- union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_HS_6; // = 0x28F98, //
- union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_HS_7; // = 0x28F9C, //
- union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_HS_8; // = 0x28FA0, //
- union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_HS_9; // = 0x28FA4, //
- union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_HS_10; // = 0x28FA8, //
- union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_HS_11; // = 0x28FAC, //
- union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_HS_12; // = 0x28FB0, //
- union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_HS_13; // = 0x28FB4, //
- union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_HS_14; // = 0x28FB8, //
- union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_HS_15; // = 0x28FBC, //
- union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_LS_0; // = 0x28FC0, //
- union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_LS_1; // = 0x28FC4, //
- union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_LS_2; // = 0x28FC8, //
- union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_LS_3; // = 0x28FCC, //
- union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_LS_4; // = 0x28FD0, //
- union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_LS_5; // = 0x28FD4, //
- union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_LS_6; // = 0x28FD8, //
- union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_LS_7; // = 0x28FDC, //
- union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_LS_8; // = 0x28FE0, //
- union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_LS_9; // = 0x28FE4, //
- union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_LS_10; // = 0x28FE8, //
- union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_LS_11; // = 0x28FEC, //
- union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_LS_12; // = 0x28FF0, //
- union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_LS_13; // = 0x28FF4, //
- union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_LS_14; // = 0x28FF8, //
- union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_LS_15; // = 0x28FFC, //
-
- EVERGREEN_PS_RES ps;
- EVERGREEN_VS_RES vs;
-
-/* Registers from SPI block: */
- union UINT_FLOAT SPI_VS_OUT_ID_0; //// // = 0x2861C, // SAME 0x28614
- union UINT_FLOAT SPI_VS_OUT_ID_1; //// // = 0x28620, // SAME 0x28618
- union UINT_FLOAT SPI_VS_OUT_ID_2; //// // = 0x28624, // SAME 0x2861C
- union UINT_FLOAT SPI_VS_OUT_ID_3; //// // = 0x28628, // SAME 0x28620
- union UINT_FLOAT SPI_VS_OUT_ID_4; //// // = 0x2862C, // SAME 0x28624
- union UINT_FLOAT SPI_VS_OUT_ID_5; //// // = 0x28630, // SAME 0x28628
- union UINT_FLOAT SPI_VS_OUT_ID_6; //// // = 0x28634, // SAME 0x2862C
- union UINT_FLOAT SPI_VS_OUT_ID_7; //// // = 0x28638, // SAME 0x28630
- union UINT_FLOAT SPI_VS_OUT_ID_8; //// // = 0x2863C, // SAME 0x28634
- union UINT_FLOAT SPI_VS_OUT_ID_9; //// // = 0x28640, // SAME 0x28638
- union UINT_FLOAT SPI_PS_INPUT_CNTL[32]; //// // = 0x28644, // SAME
-
- union UINT_FLOAT SPI_VS_OUT_CONFIG; //// // = 0x286C4, // SAME
- union UINT_FLOAT SPI_THREAD_GROUPING; //// // = 0x286C8, // DIFF
- union UINT_FLOAT SPI_PS_IN_CONTROL_0; //// // = 0x286CC, // SAME
- union UINT_FLOAT SPI_PS_IN_CONTROL_1; //// // = 0x286D0, // SAME
- union UINT_FLOAT SPI_INTERP_CONTROL_0; //// // = 0x286D4, // SAME
- union UINT_FLOAT SPI_INPUT_Z; //// // = 0x286D8, // SAME
- union UINT_FLOAT SPI_FOG_CNTL; //// // = 0x286DC, // SAME
- union UINT_FLOAT SPI_BARYC_CNTL; //// // = 0x286E0, //
- union UINT_FLOAT SPI_PS_IN_CONTROL_2; //// // = 0x286E4, //
- union UINT_FLOAT SPI_COMPUTE_INPUT_CNTL; // = 0x286E8, //
- union UINT_FLOAT SPI_COMPUTE_NUM_THREAD_X; // = 0x286EC, //
- union UINT_FLOAT SPI_COMPUTE_NUM_THREAD_Y; // = 0x286F0, //
- union UINT_FLOAT SPI_COMPUTE_NUM_THREAD_Z; // = 0x286F4, //
-
-/* Registers from SX block: */
- union UINT_FLOAT SX_MISC; // = 0x28350, // SAME
- union UINT_FLOAT SX_SURFACE_SYNC; // = 0x28354, // DIFF
- union UINT_FLOAT SX_ALPHA_TEST_CONTROL; //// // = 0x28410, // SAME
- union UINT_FLOAT SX_ALPHA_REF; // = 0x28438, // SAME
-
-/* Registers from DB block: */
- union UINT_FLOAT DB_RENDER_CONTROL; //// // = 0x28000, // DIFF 0x28D0C
- union UINT_FLOAT DB_COUNT_CONTROL; //// // = 0x28004, //
- union UINT_FLOAT DB_DEPTH_VIEW; //// // = 0x28008, // DIFF 0x28004
- union UINT_FLOAT DB_RENDER_OVERRIDE; //// // = 0x2800C, // DIFF 0x28D10
- union UINT_FLOAT DB_RENDER_OVERRIDE2; //// // = 0x28010, //
- union UINT_FLOAT DB_HTILE_DATA_BASE; //// // = 0x28014, // SAME
- union UINT_FLOAT DB_STENCIL_CLEAR; //// // = 0x28028, // SAME
- union UINT_FLOAT DB_DEPTH_CLEAR; //// // = 0x2802C, // SAME
- union UINT_FLOAT DB_Z_INFO; //// // = 0x28040, //
- union UINT_FLOAT DB_STENCIL_INFO; //// // = 0x28044, //
- union UINT_FLOAT DB_Z_READ_BASE; //// // = 0x28048, //
- union UINT_FLOAT DB_STENCIL_READ_BASE;//// // = 0x2804C, //
- union UINT_FLOAT DB_Z_WRITE_BASE; //// // = 0x28050, //
- union UINT_FLOAT DB_STENCIL_WRITE_BASE; //// // = 0x28054, //
- union UINT_FLOAT DB_DEPTH_SIZE; //// // = 0x28058, // DIFF 0x28000
- union UINT_FLOAT DB_DEPTH_SLICE; //// // = 0x2805C, //
- union UINT_FLOAT DB_STENCILREFMASK; // = 0x28430, // SAME
- union UINT_FLOAT DB_STENCILREFMASK_BF; // = 0x28434, // SAME
- union UINT_FLOAT DB_DEPTH_CONTROL; //// // = 0x28800, // SAME
- union UINT_FLOAT DB_SHADER_CONTROL;//// // = 0x2880C, // DIFF
- union UINT_FLOAT DB_HTILE_SURFACE; //// // = 0x28ABC, // SAME 0x28D24
- union UINT_FLOAT DB_SRESULTS_COMPARE_STATE0; //// // = 0x28AC0, // SAME 0x28D28
- union UINT_FLOAT DB_SRESULTS_COMPARE_STATE1; //// // = 0x28AC4, // SAME 0x28D2C
- union UINT_FLOAT DB_PRELOAD_CONTROL; //// // = 0x28AC8, // SAME 0x28D30
- union UINT_FLOAT DB_ALPHA_TO_MASK; //// // = 0x28B70, // SAME 0x28D44
-
-/* Registers from CB block: */
- union UINT_FLOAT CB_TARGET_MASK; //// // = 0x28238, // SAME
- union UINT_FLOAT CB_SHADER_MASK; //// // = 0x2823C, // SAME
- union UINT_FLOAT CB_BLEND_RED; //// // = 0x28414, // SAME
- union UINT_FLOAT CB_BLEND_GREEN; //// // = 0x28418, // SAME
- union UINT_FLOAT CB_BLEND_BLUE; //// // = 0x2841C, // SAME
- union UINT_FLOAT CB_BLEND_ALPHA; //// // = 0x28420, // SAME
- union UINT_FLOAT CB_BLEND0_CONTROL; //// // = 0x28780, // DIFF
- union UINT_FLOAT CB_BLEND1_CONTROL; // = 0x28784, // DIFF
- union UINT_FLOAT CB_BLEND2_CONTROL; // = 0x28788, // DIFF
- union UINT_FLOAT CB_BLEND3_CONTROL; // = 0x2878C, // DIFF
- union UINT_FLOAT CB_BLEND4_CONTROL; // = 0x28790, // DIFF
- union UINT_FLOAT CB_BLEND5_CONTROL; // = 0x28794, // DIFF
- union UINT_FLOAT CB_BLEND6_CONTROL; // = 0x28798, // DIFF
- union UINT_FLOAT CB_BLEND7_CONTROL; // = 0x2879C, // DIFF
- union UINT_FLOAT CB_COLOR_CONTROL; //// // = 0x28808, // DIFF
- union UINT_FLOAT CB_CLRCMP_CONTROL; //// // = 0x28C40, // SAME 0x28C30
- union UINT_FLOAT CB_CLRCMP_SRC; //// // = 0x28C44, // SAME 0x28C34
- union UINT_FLOAT CB_CLRCMP_DST; //// // = 0x28C48, // SAME 0x28C38
- union UINT_FLOAT CB_CLRCMP_MSK; //// // = 0x28C4C, // SAME 0x28C3C
-
- EVERGREEN_RENDER_TARGET_STATE render_target[EVERGREEN_MAX_RENDER_TARGETS];
-
- radeonTexObj* textures[R700_TEXTURE_NUMBERUNITS];
-
- EVERGREEN_CONFIG evergreen_config;
-
- GLboolean bEnablePerspective;
-
-} EVERGREEN_CHIP_CONTEXT;
-
-#endif /* _EVERGREEN_CHIP_H_ */
\ No newline at end of file
+++ /dev/null
-/*
- * Copyright (C) 2008-2010 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Authors:
- * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
- */
-
-#include "main/glheader.h"
-#include "main/api_arrayelt.h"
-#include "main/context.h"
-#include "main/simple_list.h"
-#include "main/imports.h"
-#include "main/bufferobj.h"
-#include "main/texobj.h"
-
-#include "radeon_common_context.h"
-#include "evergreen_context.h"
-#include "evergreen_state.h"
-#include "evergreen_blit.h"
-#include "r600_cmdbuf.h"
-#include "radeon_queryobj.h"
-
-static void evergreen_get_lock(radeonContextPtr rmesa)
-{
- drm_radeon_sarea_t *sarea = rmesa->sarea;
-
- if (sarea->ctx_owner != rmesa->dri.hwContext) {
- sarea->ctx_owner = rmesa->dri.hwContext;
- if (!rmesa->radeonScreen->kernel_mm)
- radeon_bo_legacy_texture_age(rmesa->radeonScreen->bom);
- }
-}
-
-static void evergreen_vtbl_emit_cs_header(struct radeon_cs *cs, radeonContextPtr rmesa)
-{
- /* please flush pipe do all pending work */
- /* to be enabled */
-}
-
-static void evergreen_vtbl_pre_emit_atoms(radeonContextPtr radeon)
-{
- r700Start3D((context_t *)radeon);
-}
-
-static void evergreen_fallback(struct gl_context *ctx, GLuint bit, GLboolean mode)
-{
- context_t *context = EVERGREEN_CONTEXT(ctx);
- if (mode)
- context->radeon.Fallback |= bit;
- else
- context->radeon.Fallback &= ~bit;
-}
-
-static void evergreen_emit_query_finish(radeonContextPtr radeon)
-{
- context_t *context = (context_t*) radeon;
- BATCH_LOCALS(&context->radeon);
-
- struct radeon_query_object *query = radeon->query.current;
-
- BEGIN_BATCH_NO_AUTOSTATE(4 + 2);
- R600_OUT_BATCH(CP_PACKET3(R600_IT_EVENT_WRITE, 2));
- R600_OUT_BATCH(R600_EVENT_TYPE(ZPASS_DONE) | R600_EVENT_INDEX(1));
- R600_OUT_BATCH(query->curr_offset + 8); /* hw writes qwords */
- R600_OUT_BATCH(0x00000000);
- R600_OUT_BATCH_RELOC(VGT_EVENT_INITIATOR, query->bo, 0, 0, RADEON_GEM_DOMAIN_GTT, 0);
- END_BATCH();
- assert(query->curr_offset < RADEON_QUERY_PAGE_SIZE);
- query->emitted_begin = GL_FALSE;
-}
-
-void evergreen_init_vtbl(radeonContextPtr radeon)
-{
- radeon->vtbl.get_lock = evergreen_get_lock;
- radeon->vtbl.update_viewport_offset = evergreenUpdateViewportOffset;
- radeon->vtbl.emit_cs_header = evergreen_vtbl_emit_cs_header;
- radeon->vtbl.swtcl_flush = NULL;
- radeon->vtbl.pre_emit_atoms = evergreen_vtbl_pre_emit_atoms;
- radeon->vtbl.fallback = evergreen_fallback;
- radeon->vtbl.emit_query_finish = evergreen_emit_query_finish;
- radeon->vtbl.check_blit = evergreen_check_blit;
- radeon->vtbl.blit = evergreen_blit;
- radeon->vtbl.is_format_renderable = r600IsFormatRenderable;
-}
-
-
-
+++ /dev/null
-/*
- * Copyright (C) 2008-2010 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Authors:
- * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
- */
-
-#ifndef _EVERGREEN_CONTEXT_H_
-#define _EVERGREEN_CONTEXT_H_
-
-extern void evergreen_init_vtbl(radeonContextPtr radeon);
-
-#endif //_EVERGREEN_CONTEXT_H_
-
-
-
-
-
-
+++ /dev/null
-/*
- * Copyright (C) 2008-2010 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Authors:
- * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
- */
-
-#ifndef _EVERGREEN_DIFF_H_
-#define _EVERGREEN_DIFF_H_
-
-enum {
- /* CB_BLEND_CONTROL */
- EG_CB_BLENDX_CONTROL_ENABLE_bit = 1 << 30,
- /* PA_SC_SCREEN_SCISSOR_TL */
- EG_PA_SC_SCREEN_SCISSOR_TL__TL_X_mask = 0xffff << 0,
- EG_PA_SC_SCREEN_SCISSOR_TL__TL_Y_mask = 0xffff << 16,
- /* PA_SC_SCREEN_SCISSOR_BR */
- EG_PA_SC_SCREEN_SCISSOR_BR__BR_X_mask = 0xffff << 0,
- EG_PA_SC_SCREEN_SCISSOR_BR__BR_Y_mask = 0xffff << 16,
- /* PA_SC_WINDOW_SCISSOR_TL */
- EG_PA_SC_WINDOW_SCISSOR_TL__TL_X_mask = 0x7fff << 0,
- EG_PA_SC_WINDOW_SCISSOR_TL__TL_Y_mask = 0x7fff << 16,
- /* PA_SC_WINDOW_SCISSOR_BR */
- EG_PA_SC_WINDOW_SCISSOR_BR__BR_X_mask = 0x7fff << 0,
- EG_PA_SC_WINDOW_SCISSOR_BR__BR_Y_mask = 0x7fff << 16,
- /* PA_SC_CLIPRECT_0_TL */
- EG_PA_SC_CLIPRECT_0_TL__TL_X_mask = 0x7fff << 0,
- EG_PA_SC_CLIPRECT_0_TL__TL_Y_mask = 0x7fff << 16,
- /* PA_SC_CLIPRECT_0_BR */
- EG_PA_SC_CLIPRECT_0_BR__BR_X_mask = 0x7fff << 0,
- EG_PA_SC_CLIPRECT_0_BR__BR_Y_mask = 0x7fff << 16,
- /* PA_SC_GENERIC_SCISSOR_TL */
- EG_PA_SC_GENERIC_SCISSOR_TL__TL_X_mask = 0x7fff << 0,
- EG_PA_SC_GENERIC_SCISSOR_TL__TL_Y_mask = 0x7fff << 16,
- /* PA_SC_GENERIC_SCISSOR_BR */
- EG_PA_SC_GENERIC_SCISSOR_BR__BR_X_mask = 0x7fff << 0,
- EG_PA_SC_GENERIC_SCISSOR_BR__BR_Y_mask = 0x7fff << 16,
- /* PA_SC_VPORT_SCISSOR_0_TL */
- EG_PA_SC_VPORT_SCISSOR_0_TL__TL_X_mask = 0x7fff << 0,
- EG_PA_SC_VPORT_SCISSOR_0_TL__TL_Y_mask = 0x7fff << 16,
- /* PA_SC_VPORT_SCISSOR_0_BR */
- EG_PA_SC_VPORT_SCISSOR_0_BR__BR_X_mask = 0x7fff << 0,
- EG_PA_SC_VPORT_SCISSOR_0_BR__BR_Y_mask = 0x7fff << 16,
- /* PA_SC_WINDOW_OFFSET */
- EG_PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET_shift = 0,
- EG_PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET_mask = 0xffff << 0,
- EG_PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET_shift = 16,
- EG_PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET_mask = 0xffff << 16,
- /* SPI_BARYC_CNTL */
- EG_SPI_BARYC_CNTL__PERSP_CENTROID_ENA_shift = 4,
- EG_SPI_BARYC_CNTL__PERSP_CENTROID_ENA_mask = 0x3 << 4,
- EG_SPI_BARYC_CNTL__LINEAR_CENTROID_ENA_shift = 20,
- EG_SPI_BARYC_CNTL__LINEAR_CENTROID_ENA_mask = 0x3 << 20,
- /* DB_SHADER_CONTROL */
- EG_DB_SHADER_CONTROL__DUAL_EXPORT_ENABLE_bit = 1 << 9,
-
- /* DB_Z_INFO */
- EG_DB_Z_INFO__FORMAT_shift = 0, //2;
- EG_DB_Z_INFO__FORMAT_mask = 0x3,
- //2;
- EG_DB_Z_INFO__ARRAY_MODE_shift = 4, //4;
- EG_DB_Z_INFO__ARRAY_MODE_mask = 0xf << 4,
- EG_DB_Z_INFO__TILE_SPLIT_shift = 8, //3;
- EG_DB_Z_INFO__TILE_SPLIT_mask = 0x7 << 8,
- //1;
- EG_DB_Z_INFO__NUM_BANKS_shift = 12, //2;
- EG_DB_Z_INFO__NUM_BANKS_mask = 0x3 << 12,
- //2;
- EG_DB_Z_INFO__BANK_WIDTH_shift = 16, //2;
- EG_DB_Z_INFO__BANK_WIDTH_mask = 0x3 << 16,
- //2;
- EG_DB_Z_INFO__BANK_HEIGHT_shift = 20, //2;
- EG_DB_Z_INFO__BANK_HEIGHT_mask = 0x3 << 20,
-
- EG_Z_INVALID = 0x00000000,
- EG_Z_16 = 0x00000001,
- EG_Z_24 = 0x00000002,
- EG_Z_32_FLOAT = 0x00000003,
- EG_ADDR_SURF_TILE_SPLIT_256B = 0x00000002,
- EG_ADDR_SURF_8_BANK = 0x00000002,
- EG_ADDR_SURF_BANK_WIDTH_1 = 0x00000000,
- EG_ADDR_SURF_BANK_HEIGHT_1 = 0x00000000,
- /* DB_STENCIL_INFO */
- EG_DB_STENCIL_INFO__FORMAT_bit = 1, //1;
- //7;
- EG_DB_STENCIL_INFO__TILE_SPLIT_shift = 8, //3;
- EG_DB_STENCIL_INFO__TILE_SPLIT_mask = 0x7 << 8,
-
- /* DB_DEPTH_SIZE */
- EG_DB_DEPTH_SIZE__PITCH_TILE_MAX_shift = 0, // 11;
- EG_DB_DEPTH_SIZE__PITCH_TILE_MAX_mask = 0x7ff,
- EG_DB_DEPTH_SIZE__HEIGHT_TILE_MAX_shift = 11, // 11;
- EG_DB_DEPTH_SIZE__HEIGHT_TILE_MAX_mask = 0x7ff << 11,
-
- /* DB_COUNT_CONTROL */
- EG_DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE_shift = 0, //1
- EG_DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE_bit = 1,
- EG_DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS_shift = 1, //1
- EG_DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS_bit = 1 << 1,
-
- /* CB_COLOR_CONTROL */
- //3;
- EG_CB_COLOR_CONTROL__DEGAMMA_ENABLE_bit = 1 << 3,//1;
- EG_CB_COLOR_CONTROL__MODE_shift = 4, //3;
- EG_CB_COLOR_CONTROL__MODE_mask = 0x7 << 4,
- //9;
- EG_CB_COLOR_CONTROL__ROP3_shift = 16, //8;
- EG_CB_COLOR_CONTROL__ROP3_mask = 0xff << 16,
- EG_CB_NORMAL = 0x00000001,
-
- /* CB_COLOR0_INFO */
- EG_CB_COLOR0_INFO__ENDIAN_shift = 0, //2;
- EG_CB_COLOR0_INFO__ENDIAN_mask = 0x3,
- EG_CB_COLOR0_INFO__FORMAT_shift = 2, //6;
- EG_CB_COLOR0_INFO__FORMAT_mask = 0x3f << 2,
- EG_CB_COLOR0_INFO__ARRAY_MODE_shift = 8, //4;
- EG_CB_COLOR0_INFO__ARRAY_MODE_mask = 0xf << 8,
- EG_CB_COLOR0_INFO__NUMBER_TYPE_shift = 12, //3;
- EG_CB_COLOR0_INFO__NUMBER_TYPE_mask = 0x7 << 12,
- EG_CB_COLOR0_INFO__COMP_SWAP_shift = 15, //2;
- EG_CB_COLOR0_INFO__COMP_SWAP_mask = 0x3 << 15,
- EG_CB_COLOR0_INFO__FAST_CLEAR_bit = 1 << 17,//1;
- EG_CB_COLOR0_INFO__COMPRESSION_bit = 1 << 18,//1;
- EG_CB_COLOR0_INFO__BLEND_CLAMP_bit = 1 << 19,//1;
- EG_CB_COLOR0_INFO__BLEND_BYPASS_bit = 1 << 20,//1;
- EG_CB_COLOR0_INFO__SIMPLE_FLOAT_bit = 1 << 21,//1;
- EG_CB_COLOR0_INFO__ROUND_MODE_bit = 1 << 22,//1;
- EG_CB_COLOR0_INFO__TILE_COMPACT_bit = 1 << 23,//1;
- EG_CB_COLOR0_INFO__SOURCE_FORMAT_shift = 24, //2;
- EG_CB_COLOR0_INFO__SOURCE_FORMAT_mask = 0x3 << 24,
- EG_CB_COLOR0_INFO__RAT_bit = 1 << 26,//1;
- EG_CB_COLOR0_INFO__RESOURCE_TYPE_shift = 27, //3;
- EG_CB_COLOR0_INFO__RESOURCE_TYPE_mask = 0x7 << 27,
-
- /* CB_COLOR0_ATTRIB */
- EG_CB_COLOR0_ATTRIB__NON_DISP_TILING_ORDER_shift = 4,
- EG_CB_COLOR0_ATTRIB__NON_DISP_TILING_ORDER_bit = 1 << 4,
-
- /* SPI_CONFIG_CNTL_1 */
- EG_SPI_CONFIG_CNTL_1__VTX_DONE_DELAY_shift = 0,
- EG_SPI_CONFIG_CNTL_1__VTX_DONE_DELAY_mask = 0xf,
- /* SQ_MS_FIFO_SIZES */
- EG_SQ_MS_FIFO_SIZES__CACHE_FIFO_SIZE_shift = 0,
- EG_SQ_MS_FIFO_SIZES__CACHE_FIFO_SIZE_mask = 0xff,
- EG_SQ_MS_FIFO_SIZES__FETCH_FIFO_HIWATER_shift = 8,
- EG_SQ_MS_FIFO_SIZES__FETCH_FIFO_HIWATER_mask = 0x1f << 8,
- EG_SQ_MS_FIFO_SIZES__DONE_FIFO_HIWATER_shift = 16,
- EG_SQ_MS_FIFO_SIZES__DONE_FIFO_HIWATER_mask = 0xff << 16,
- EG_SQ_MS_FIFO_SIZES__ALU_UPDATE_FIFO_HIWATER_shift = 24,
- EG_SQ_MS_FIFO_SIZES__ALU_UPDATE_FIFO_HIWATER_mask = 0x1f << 24,
- /* SQ_CONFIG */
- EG_SQ_CONFIG__VC_ENABLE_bit = 1,
- EG_SQ_CONFIG__EXPORT_SRC_C_bit = 1 << 1,
- EG_SQ_CONFIG__PS_PRIO_shift = 24,
- EG_SQ_CONFIG__PS_PRIO_mask = 0x3 << 24,
- EG_SQ_CONFIG__VS_PRIO_shift = 26,
- EG_SQ_CONFIG__VS_PRIO_mask = 0x3 << 26,
- EG_SQ_CONFIG__GS_PRIO_shift = 28,
- EG_SQ_CONFIG__GS_PRIO_mask = 0x3 << 28,
- EG_SQ_CONFIG__ES_PRIO_shift = 30,
- EG_SQ_CONFIG__ES_PRIO_mask = 0x3 << 30,
- /* PA_SC_FORCE_EOV_MAX_CNTS */
- EG_PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT_shift = 0,
- EG_PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT_mask = 0x3fff,
- EG_PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT_shift = 16,
- EG_PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT_mask = 0x3fff << 16,
- /* VGT_CACHE_INVALIDATION */
- EG_VGT_CACHE_INVALIDATION__CACHE_INVALIDATION_shift = 0,
- EG_VGT_CACHE_INVALIDATION__CACHE_INVALIDATION_mask = 0x3,
- /* CB_COLOR0_PITCH */
- EG_CB_COLOR0_PITCH__TILE_MAX_shift = 0,
- EG_CB_COLOR0_PITCH__TILE_MAX_mask = 0x7ff,
- /* CB_COLOR0_SLICE */
- EG_CB_COLOR0_SLICE__TILE_MAX_shift = 0,
- EG_CB_COLOR0_SLICE__TILE_MAX_mask = 0x3fffff,
- /* SQ_VTX_CONSTANT_WORD3_0 */
- EG_SQ_VTX_CONSTANT_WORD3_0__UNCACHED_shift = 2,
- EG_SQ_VTX_CONSTANT_WORD3_0__UNCACHED_bit = 1 << 2,
-
- EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_X_shift = 3,
- EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_X_mask = 0x7 << 3,
-
- EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_Y_shift = 6,
- EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_Y_mask = 0x7 << 6,
-
- EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_Z_shift = 9,
- EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_Z_mask = 0x7 << 9,
-
- EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_W_shift = 12,
- EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_W_mask = 0x7 << 12,
- /* SQ_VTX_CONSTANT_WORD4_0 */
- EG_SQ_VTX_CONSTANT_WORD4_0__NUM_ELEMENTS_shift = 0,
- EG_SQ_VTX_CONSTANT_WORD4_0__NUM_ELEMENTS_mask = 0xFFFFFFFF,
- /* SQ_VTX_CONSTANT_WORD7_0 */
- EG_SQ_VTX_CONSTANT_WORD7_0__TYPE_shift = 30,
- EG_SQ_VTX_CONSTANT_WORD7_0__TYPE_mask = 0x3 << 30,
- /* SQ_TEX_SAMPLER_WORD0_0 */
- EG_SQ_TEX_SAMPLER_WORD0_0__CLAMP_X_shift = 0, // 3;
- EG_SQ_TEX_SAMPLER_WORD0_0__CLAMP_X_mask = 0x7,
- EG_SQ_TEX_SAMPLER_WORD0_0__CLAMP_Y_shift = 3, // 3;
- EG_SQ_TEX_SAMPLER_WORD0_0__CLAMP_Y_mask = 0x7 << 3,
- EG_SQ_TEX_SAMPLER_WORD0_0__CLAMP_Z_shift = 6, // 3;
- EG_SQ_TEX_SAMPLER_WORD0_0__CLAMP_Z_mask = 0x7 << 6,
- EG_SQ_TEX_SAMPLER_WORD0_0__XY_MAG_FILTER_shift = 9, // 2;
- EG_SQ_TEX_SAMPLER_WORD0_0__XY_MAG_FILTER_mask = 0x3 << 9,
- EG_SQ_TEX_SAMPLER_WORD0_0__XY_MIN_FILTER_shift = 11, // 2;
- EG_SQ_TEX_SAMPLER_WORD0_0__XY_MIN_FILTER_mask = 0x3 << 11,
- EG_SQ_TEX_SAMPLER_WORD0_0__Z_FILTER_shift = 13, // 2;
- EG_SQ_TEX_SAMPLER_WORD0_0__Z_FILTER_mask = 0x3 << 13,
- EG_SQ_TEX_SAMPLER_WORD0_0__MIP_FILTER_shift = 15, // 2;
- EG_SQ_TEX_SAMPLER_WORD0_0__MIP_FILTER_mask = 0x3 << 15,
- EG_SQ_TEX_SAMPLER_WORD0_0__MAX_ANISO_RATIO_shift = 17, // 3;
- EG_SQ_TEX_SAMPLER_WORD0_0__MAX_ANISO_RATIO_mask = 0x7 << 17,
- EG_SQ_TEX_SAMPLER_WORD0_0__BORDER_COLOR_TYPE_shift = 20,//2;
- EG_SQ_TEX_SAMPLER_WORD0_0__BORDER_COLOR_TYPE_mask = 0x3 << 20,
- EG_SQ_TEX_SAMPLER_WORD0_0__DCF_shift = 22, // 3;
- EG_SQ_TEX_SAMPLER_WORD0_0__DCF_mask = 0x7 << 22,
- EG_SQ_TEX_SAMPLER_WORD0_0__CHROMA_KEY_shift = 25, // 2;
- EG_SQ_TEX_SAMPLER_WORD0_0__CHROMA_KEY_mask = 0x3 << 25,
- EG_SQ_TEX_SAMPLER_WORD0_0__ANISO_THRESHOLD_shift = 27, // 3;
- EG_SQ_TEX_SAMPLER_WORD0_0__ANISO_THRESHOLD_mask = 0x7 << 27,
- EG_SQ_TEX_SAMPLER_WORD0_0__Reserved_shift = 30, // 2
- EG_SQ_TEX_SAMPLER_WORD0_0__Reserved_mask = 0x3 << 30,
- /* SQ_TEX_SAMPLER_WORD1_0 */
- EG_SQ_TEX_SAMPLER_WORD1_0__MIN_LOD_shift = 0, // 12;
- EG_SQ_TEX_SAMPLER_WORD1_0__MIN_LOD_mask = 0xfff,
- EG_SQ_TEX_SAMPLER_WORD1_0__MAX_LOD_shift = 12,// 12;
- EG_SQ_TEX_SAMPLER_WORD1_0__MAX_LOD_mask = 0xfff << 12,
- /* SQ_TEX_SAMPLER_WORD2_0 */
- EG_SQ_TEX_SAMPLER_WORD2_0__LOD_BIAS_shift = 0, //14;
- EG_SQ_TEX_SAMPLER_WORD2_0__LOD_BIAS_mask = 0x3fff,
- EG_SQ_TEX_SAMPLER_WORD2_0__LOD_BIAS_SEC_shift = 14,//6;
- EG_SQ_TEX_SAMPLER_WORD2_0__LOD_BIAS_SEC_mask = 0x3f << 14,
- EG_SQ_TEX_SAMPLER_WORD2_0__MC_COORD_TRUNCATE_shift = 20,//1;
- EG_SQ_TEX_SAMPLER_WORD2_0__MC_COORD_TRUNCATE_bit = 1 << 20,
- EG_SQ_TEX_SAMPLER_WORD2_0__FORCE_DEGAMMA_shift = 21,//1;
- EG_SQ_TEX_SAMPLER_WORD2_0__FORCE_DEGAMMA_bit = 1 << 21,
- EG_SQ_TEX_SAMPLER_WORD2_0__ANISO_BIAS_shift = 22,//6;
- EG_SQ_TEX_SAMPLER_WORD2_0__ANISO_BIAS_mask = 0x3f << 22,
- EG_SQ_TEX_SAMPLER_WORD2_0__TRUNCATE_COORD_shift = 28,//1;
- EG_SQ_TEX_SAMPLER_WORD2_0__TRUNCATE_COORD_bit = 1 << 28,
- EG_SQ_TEX_SAMPLER_WORD2_0__DISABLE_CUBE_WRAP_shift = 29,//1;
- EG_SQ_TEX_SAMPLER_WORD2_0__DISABLE_CUBE_WRAP_bit = 1 << 29,
- EG_SQ_TEX_SAMPLER_WORD2_0__Reserved_shift = 30,//1;
- EG_SQ_TEX_SAMPLER_WORD2_0__Reserved_bit = 1 << 30,
- EG_SQ_TEX_SAMPLER_WORD2_0__TYPE_shift = 31,//1;
- EG_SQ_TEX_SAMPLER_WORD2_0__TYPE_bit = 1 << 31,
- /* SQ_TEX_RESOURCE_WORD0_0 */
- EG_SQ_TEX_RESOURCE_WORD0_0__DIM_shift = 0, // 3;
- EG_SQ_TEX_RESOURCE_WORD0_0__DIM_mask = 0x7,
- EG_SQ_TEX_RESOURCE_WORD0_0__ISET_shift = 3, // 1;
- EG_SQ_TEX_RESOURCE_WORD0_0__ISET_bit = 1 << 3,
- EG_SQ_TEX_RESOURCE_WORD0_0__Reserve_shift = 4, // 1;
- EG_SQ_TEX_RESOURCE_WORD0_0__Reserve_bit = 1 << 4,
- EG_SQ_TEX_RESOURCE_WORD0_0__NDTO_shift = 5, // 1;
- EG_SQ_TEX_RESOURCE_WORD0_0__NDTO_bit = 1 << 5,
- EG_SQ_TEX_RESOURCE_WORD0_0__PITCH_shift = 6, // 12;
- EG_SQ_TEX_RESOURCE_WORD0_0__PITCH_mask = 0xfff << 6,
- EG_SQ_TEX_RESOURCE_WORD0_0__TEX_WIDTH_shift = 18,// 14;
- EG_SQ_TEX_RESOURCE_WORD0_0__TEX_WIDTH_mask = 0x3fff << 18,
- /* SQ_TEX_RESOURCE_WORD1_0 */
- EG_SQ_TEX_RESOURCE_WORD1_0__TEX_HEIGHT_shift = 0, // 14;
- EG_SQ_TEX_RESOURCE_WORD1_0__TEX_HEIGHT_mask = 0x3fff,
- EG_SQ_TEX_RESOURCE_WORD1_0__TEX_DEPTH_shift = 14,// 13;
- EG_SQ_TEX_RESOURCE_WORD1_0__TEX_DEPTH_mask = 0x1fff << 14,
- EG_SQ_TEX_RESOURCE_WORD1_0__Reserved_shift = 27,// 1;
- EG_SQ_TEX_RESOURCE_WORD1_0__Reserved_bit = 1 << 27,
- EG_SQ_TEX_RESOURCE_WORD1_0__ARRAY_MODE_shift = 28,// 4;
- EG_SQ_TEX_RESOURCE_WORD1_0__ARRAY_MODE_mask = 0xf << 28,
- /* SQ_TEX_RESOURCE_WORD6_0 */
- EG_SQ_TEX_RESOURCE_WORD6_0__MAX_ANISO_RATIO_shift = 0, //: 3;
- EG_SQ_TEX_RESOURCE_WORD6_0__MAX_ANISO_RATIO_mask = 0x7,
- EG_SQ_TEX_RESOURCE_WORD6_0__INTERLACED_shift = 6, //1;
- EG_SQ_TEX_RESOURCE_WORD6_0__INTERLACED_bit = 1 << 6,
- EG_SQ_TEX_RESOURCE_WORD6_0__MIN_LOD_shift = 8, //12;
- EG_SQ_TEX_RESOURCE_WORD6_0__MIN_LOD_mask = 0xfff << 8,
- EG_SQ_TEX_RESOURCE_WORD6_0__TILE_SPLIT_shift = 29,// 3;
- EG_SQ_TEX_RESOURCE_WORD6_0__TILE_SPLIT_mask = 0x7 << 29,
- /* SQ_TEX_RESOURCE_WORD7_0 */
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift = 0, // 6;
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask = 0x3f,
- EG_SQ_TEX_RESOURCE_WORD7_0__MACRO_TILE_ASPECT_shift = 6, // 2;
- EG_SQ_TEX_RESOURCE_WORD7_0__MACRO_TILE_ASPECT_mask = 0x3 << 6,
- EG_SQ_TEX_RESOURCE_WORD7_0__BANK_WIDTH_shift = 8, // 2;
- EG_SQ_TEX_RESOURCE_WORD7_0__BANK_WIDTH_mask = 0x3 << 8,
- EG_SQ_TEX_RESOURCE_WORD7_0__BANK_HEIGHT_shift = 10,// 2;
- EG_SQ_TEX_RESOURCE_WORD7_0__BANK_HEIGHT_mask = 0x3 << 10,
- EG_SQ_TEX_RESOURCE_WORD7_0__DEPTH_SAMPLE_ORDER_shift = 15,// 1;
- EG_SQ_TEX_RESOURCE_WORD7_0__DEPTH_SAMPLE_ORDER_bit = 1 << 15,
- EG_SQ_TEX_RESOURCE_WORD7_0__NUM_BANKS_shift = 16,// 2;
- EG_SQ_TEX_RESOURCE_WORD7_0__NUM_BANKS_mask = 0x3 << 16,
- EG_SQ_TEX_RESOURCE_WORD7_0__TYPE_shift = 30,// 2;
- EG_SQ_TEX_RESOURCE_WORD7_0__TYPE_mask = 0x3 << 30,
-};
-
-/* */
-
-#define EG_SQ_FETCH_RESOURCE_COUNT 0x00000400
-#define EG_SQ_TEX_SAMPLER_COUNT 0x0000006c
-#define EG_SQ_LOOP_CONST_COUNT 0x000000c0
-
-#define EG_SET_RESOURCE_OFFSET 0x30000
-#define EG_SET_RESOURCE_END 0x30400 //r600 := offset + 0x4000
-
-#define EG_SET_LOOP_CONST_OFFSET 0x3A200
-#define EG_SET_LOOP_CONST_END 0x3A26C //r600 := offset + 0x180
-
-
-#define EG_SQ_FETCH_RESOURCE_VS_OFFSET 0x000000b0
-#define EG_FETCH_RESOURCE_STRIDE 8
-
-#define EG_SET_BOOL_CONST_OFFSET 0x3A500
-#define EG_SET_BOOL_CONST_END 0x3A506
-
-
-#endif //_EVERGREEN_DIFF_H_
+++ /dev/null
-/*
- * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Authors:
- * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
- * CooperYuan <cooper.yuan@amd.com>, <cooperyuan@gmail.com>
- */
-
-#include <stdio.h>
-#include <stdarg.h>
-#include <stdlib.h>
-#include <string.h>
-#include <math.h>
-
-#include "main/imports.h"
-
-#include "program/prog_parameter.h"
-#include "program/prog_statevars.h"
-#include "program/program.h"
-
-#include "r600_context.h"
-#include "r600_cmdbuf.h"
-#include "r600_emit.h"
-
-#include "evergreen_vertprog.h"
-#include "evergreen_fragprog.h"
-
-void evergreen_insert_wpos_code(struct gl_context *ctx, struct gl_fragment_program *fprog)
-{
- static const gl_state_index winstate[STATE_LENGTH]
- = { STATE_INTERNAL, STATE_FB_SIZE, 0, 0, 0};
- struct prog_instruction *newInst, *inst;
- GLint win_size; /* state reference */
- GLuint wpos_temp; /* temp register */
- int i, j;
-
- /* PARAM win_size = STATE_FB_SIZE */
- win_size = _mesa_add_state_reference(fprog->Base.Parameters, winstate);
-
- wpos_temp = fprog->Base.NumTemporaries++;
-
- /* scan program where WPOS is used and replace with wpos_temp */
- inst = fprog->Base.Instructions;
- for (i = 0; i < fprog->Base.NumInstructions; i++) {
- for (j=0; j < 3; j++) {
- if(inst->SrcReg[j].File == PROGRAM_INPUT &&
- inst->SrcReg[j].Index == FRAG_ATTRIB_WPOS) {
- inst->SrcReg[j].File = PROGRAM_TEMPORARY;
- inst->SrcReg[j].Index = wpos_temp;
- }
- }
- inst++;
- }
-
- _mesa_insert_instructions(&(fprog->Base), 0, 1);
-
- newInst = fprog->Base.Instructions;
- /* invert wpos.y
- * wpos_temp.xyzw = wpos.x-yzw + winsize.0y00 */
- newInst[0].Opcode = OPCODE_ADD;
- newInst[0].DstReg.File = PROGRAM_TEMPORARY;
- newInst[0].DstReg.Index = wpos_temp;
- newInst[0].DstReg.WriteMask = WRITEMASK_XYZW;
-
- newInst[0].SrcReg[0].File = PROGRAM_INPUT;
- newInst[0].SrcReg[0].Index = FRAG_ATTRIB_WPOS;
- newInst[0].SrcReg[0].Swizzle = SWIZZLE_XYZW;
- newInst[0].SrcReg[0].Negate = NEGATE_Y;
-
- newInst[0].SrcReg[1].File = PROGRAM_STATE_VAR;
- newInst[0].SrcReg[1].Index = win_size;
- newInst[0].SrcReg[1].Swizzle = MAKE_SWIZZLE4(SWIZZLE_ZERO, SWIZZLE_Y, SWIZZLE_ZERO, SWIZZLE_ZERO);
-
-}
-
-//TODO : Validate FP input with VP output.
-void evergreen_Map_Fragment_Program(r700_AssemblerBase *pAsm,
- struct gl_fragment_program *mesa_fp,
- struct gl_context *ctx)
-{
- unsigned int unBit;
- unsigned int i;
-
- /* match fp inputs with vp exports. */
- struct evergreen_vertex_program_cont *vpc =
- (struct evergreen_vertex_program_cont *)ctx->VertexProgram._Current;
- GLbitfield OutputsWritten = vpc->mesa_program.Base.OutputsWritten;
-
- pAsm->number_used_registers = 0;
-
-//Input mapping : mesa_fp->Base.InputsRead set the flag, set in
- //The flags parsed in parse_attrib_binding. FRAG_ATTRIB_COLx, FRAG_ATTRIB_TEXx, ...
- //MUST match order in Map_Vertex_Output
- unBit = 1 << FRAG_ATTRIB_WPOS;
- if(mesa_fp->Base.InputsRead & unBit)
- {
- pAsm->uiFP_AttributeMap[FRAG_ATTRIB_WPOS] = pAsm->number_used_registers++;
- }
-
- unBit = 1 << VERT_RESULT_COL0;
- if(OutputsWritten & unBit)
- {
- pAsm->uiFP_AttributeMap[FRAG_ATTRIB_COL0] = pAsm->number_used_registers++;
- }
-
- unBit = 1 << VERT_RESULT_COL1;
- if(OutputsWritten & unBit)
- {
- pAsm->uiFP_AttributeMap[FRAG_ATTRIB_COL1] = pAsm->number_used_registers++;
- }
-
- unBit = 1 << VERT_RESULT_FOGC;
- if(OutputsWritten & unBit)
- {
- pAsm->uiFP_AttributeMap[FRAG_ATTRIB_FOGC] = pAsm->number_used_registers++;
- }
-
- for(i=0; i<8; i++)
- {
- unBit = 1 << (VERT_RESULT_TEX0 + i);
- if(OutputsWritten & unBit)
- {
- pAsm->uiFP_AttributeMap[FRAG_ATTRIB_TEX0 + i] = pAsm->number_used_registers++;
- }
- }
-
-/* order has been taken care of */
-#if 1
- for(i=VERT_RESULT_VAR0; i<VERT_RESULT_MAX; i++)
- {
- unBit = 1 << i;
- if(OutputsWritten & unBit)
- {
- pAsm->uiFP_AttributeMap[i-VERT_RESULT_VAR0+FRAG_ATTRIB_VAR0] = pAsm->number_used_registers++;
- }
- }
-#else
- if( (mesa_fp->Base.InputsRead >> FRAG_ATTRIB_VAR0) > 0 )
- {
- struct evergreen_vertex_program_cont *vpc =
- (struct evergreen_vertex_program_cont *)ctx->VertexProgram._Current;
- struct gl_program_parameter_list * VsVarying = vpc->mesa_program.Base.Varying;
- struct gl_program_parameter_list * PsVarying = mesa_fp->Base.Varying;
- struct gl_program_parameter * pVsParam;
- struct gl_program_parameter * pPsParam;
- GLuint j, k;
- GLuint unMaxVarying = 0;
-
- for(i=0; i<VsVarying->NumParameters; i++)
- {
- pAsm->uiFP_AttributeMap[i + FRAG_ATTRIB_VAR0] = 0;
- }
-
- for(i=FRAG_ATTRIB_VAR0; i<FRAG_ATTRIB_MAX; i++)
- {
- unBit = 1 << i;
- if(mesa_fp->Base.InputsRead & unBit)
- {
- j = i - FRAG_ATTRIB_VAR0;
- pPsParam = PsVarying->Parameters + j;
-
- for(k=0; k<VsVarying->NumParameters; k++)
- {
- pVsParam = VsVarying->Parameters + k;
-
- if( strcmp(pPsParam->Name, pVsParam->Name) == 0)
- {
- pAsm->uiFP_AttributeMap[i] = pAsm->number_used_registers + k;
- if(k > unMaxVarying)
- {
- unMaxVarying = k;
- }
- break;
- }
- }
- }
- }
-
- pAsm->number_used_registers += unMaxVarying + 1;
- }
-#endif
- unBit = 1 << FRAG_ATTRIB_FACE;
- if(mesa_fp->Base.InputsRead & unBit)
- {
- pAsm->uiFP_AttributeMap[FRAG_ATTRIB_FACE] = pAsm->number_used_registers++;
- }
-
- unBit = 1 << FRAG_ATTRIB_PNTC;
- if(mesa_fp->Base.InputsRead & unBit)
- {
- pAsm->uiFP_AttributeMap[FRAG_ATTRIB_PNTC] = pAsm->number_used_registers++;
- }
-
- pAsm->uIIns = pAsm->number_used_registers;
-
-/* Map temporary registers (GPRs) */
- pAsm->starting_temp_register_number = pAsm->number_used_registers;
-
- if(mesa_fp->Base.NumNativeTemporaries >= mesa_fp->Base.NumTemporaries)
- {
- pAsm->number_used_registers += mesa_fp->Base.NumNativeTemporaries;
- }
- else
- {
- pAsm->number_used_registers += mesa_fp->Base.NumTemporaries;
- }
-
-/* Output mapping */
- pAsm->number_of_exports = 0;
- pAsm->number_of_colorandz_exports = 0; /* don't include stencil and mask out. */
- pAsm->starting_export_register_number = pAsm->number_used_registers;
- unBit = 1 << FRAG_RESULT_COLOR;
- if(mesa_fp->Base.OutputsWritten & unBit)
- {
- pAsm->uiFP_OutputMap[FRAG_RESULT_COLOR] = pAsm->number_used_registers++;
- pAsm->number_of_exports++;
- pAsm->number_of_colorandz_exports++;
- }
- unBit = 1 << FRAG_RESULT_DEPTH;
- if(mesa_fp->Base.OutputsWritten & unBit)
- {
- pAsm->depth_export_register_number = pAsm->number_used_registers;
- pAsm->uiFP_OutputMap[FRAG_RESULT_DEPTH] = pAsm->number_used_registers++;
- pAsm->number_of_exports++;
- pAsm->number_of_colorandz_exports++;
- pAsm->pR700Shader->depthIsExported = 1;
- }
-
- pAsm->flag_reg_index = pAsm->number_used_registers++;
-
- pAsm->uFirstHelpReg = pAsm->number_used_registers;
-}
-
-GLboolean evergreen_Find_Instruction_Dependencies_fp(struct evergreen_fragment_program *fp,
- struct gl_fragment_program *mesa_fp)
-{
- GLuint i, j;
- GLint * puiTEMPwrites;
- GLint * puiTEMPreads;
- struct prog_instruction * pILInst;
- InstDeps *pInstDeps;
- struct prog_instruction * texcoord_DepInst;
- GLint nDepInstID;
-
- puiTEMPwrites = (GLint*) MALLOC(sizeof(GLuint)*mesa_fp->Base.NumTemporaries);
- puiTEMPreads = (GLint*) MALLOC(sizeof(GLuint)*mesa_fp->Base.NumTemporaries);
-
- for(i=0; i<mesa_fp->Base.NumTemporaries; i++)
- {
- puiTEMPwrites[i] = -1;
- puiTEMPreads[i] = -1;
- }
-
- pInstDeps = (InstDeps*)MALLOC(sizeof(InstDeps)*mesa_fp->Base.NumInstructions);
-
- for(i=0; i<mesa_fp->Base.NumInstructions; i++)
- {
- pInstDeps[i].nDstDep = -1;
- pILInst = &(mesa_fp->Base.Instructions[i]);
-
- //Dst
- if(pILInst->DstReg.File == PROGRAM_TEMPORARY)
- {
- //Set lastwrite for the temp
- puiTEMPwrites[pILInst->DstReg.Index] = i;
- }
-
- //Src
- for(j=0; j<3; j++)
- {
- if(pILInst->SrcReg[j].File == PROGRAM_TEMPORARY)
- {
- //Set dep.
- pInstDeps[i].nSrcDeps[j] = puiTEMPwrites[pILInst->SrcReg[j].Index];
- //Set first read
- if(puiTEMPreads[pILInst->SrcReg[j].Index] < 0 )
- {
- puiTEMPreads[pILInst->SrcReg[j].Index] = i;
- }
- }
- else
- {
- pInstDeps[i].nSrcDeps[j] = -1;
- }
- }
- }
-
- fp->r700AsmCode.pInstDeps = pInstDeps;
-
- //Find dep for tex inst
- for(i=0; i<mesa_fp->Base.NumInstructions; i++)
- {
- pILInst = &(mesa_fp->Base.Instructions[i]);
-
- if(GL_TRUE == IsTex(pILInst->Opcode))
- { //src0 is the tex coord register, src1 is texunit, src2 is textype
- nDepInstID = pInstDeps[i].nSrcDeps[0];
- if(nDepInstID >= 0)
- {
- texcoord_DepInst = &(mesa_fp->Base.Instructions[nDepInstID]);
- if(GL_TRUE == IsAlu(texcoord_DepInst->Opcode) )
- {
- pInstDeps[nDepInstID].nDstDep = i;
- pInstDeps[i].nDstDep = i;
- }
- else if(GL_TRUE == IsTex(texcoord_DepInst->Opcode) )
- {
- pInstDeps[i].nDstDep = i;
- }
- else
- { //... other deps?
- }
- }
- // make sure that we dont overwrite src used earlier
- nDepInstID = puiTEMPreads[pILInst->DstReg.Index];
- if(nDepInstID < i)
- {
- pInstDeps[i].nDstDep = puiTEMPreads[pILInst->DstReg.Index];
- texcoord_DepInst = &(mesa_fp->Base.Instructions[nDepInstID]);
- if(GL_TRUE == IsAlu(texcoord_DepInst->Opcode) )
- {
- pInstDeps[nDepInstID].nDstDep = i;
- }
-
- }
-
- }
- }
-
- FREE(puiTEMPwrites);
- FREE(puiTEMPreads);
-
- return GL_TRUE;
-}
-
-GLboolean evergreenTranslateFragmentShader(struct evergreen_fragment_program *fp,
- struct gl_fragment_program *mesa_fp,
- struct gl_context *ctx)
-{
- GLuint number_of_colors_exported;
- GLboolean z_enabled = GL_FALSE;
- GLuint unBit, shadow_unit;
- int i;
- struct prog_instruction *inst;
- gl_state_index shadow_ambient[STATE_LENGTH]
- = { STATE_INTERNAL, STATE_SHADOW_AMBIENT, 0, 0, 0};
-
- //Init_Program
- Init_r700_AssemblerBase( SPT_FP, &(fp->r700AsmCode), &(fp->r700Shader) );
-
- fp->constbo0 = NULL;
- fp->r700AsmCode.bUseMemConstant = GL_TRUE;
- fp->r700AsmCode.unAsic = 8;
-
- if(mesa_fp->Base.InputsRead & FRAG_BIT_WPOS)
- {
- evergreen_insert_wpos_code(ctx, mesa_fp);
- }
-
- /* add/map consts for ARB_shadow_ambient */
- if(mesa_fp->Base.ShadowSamplers)
- {
- inst = mesa_fp->Base.Instructions;
- for (i = 0; i < mesa_fp->Base.NumInstructions; i++)
- {
- if(inst->TexShadow == 1)
- {
- shadow_unit = inst->TexSrcUnit;
- shadow_ambient[2] = shadow_unit;
- fp->r700AsmCode.shadow_regs[shadow_unit] =
- _mesa_add_state_reference(mesa_fp->Base.Parameters, shadow_ambient);
- }
- inst++;
- }
- }
-
- evergreen_Map_Fragment_Program(&(fp->r700AsmCode), mesa_fp, ctx);
-
- if( GL_FALSE == evergreen_Find_Instruction_Dependencies_fp(fp, mesa_fp) )
- {
- return GL_FALSE;
- }
-
- InitShaderProgram(&(fp->r700AsmCode));
-
- for(i=0; i < MAX_SAMPLERS; i++)
- {
- fp->r700AsmCode.SamplerUnits[i] = fp->mesa_program.Base.SamplerUnits[i];
- }
-
- fp->r700AsmCode.unCurNumILInsts = mesa_fp->Base.NumInstructions;
-
- if( GL_FALSE == AssembleInstr(0,
- 0,
- mesa_fp->Base.NumInstructions,
- &(mesa_fp->Base.Instructions[0]),
- &(fp->r700AsmCode)) )
- {
- return GL_FALSE;
- }
-
- if(GL_FALSE == Process_Fragment_Exports(&(fp->r700AsmCode), mesa_fp->Base.OutputsWritten) )
- {
- return GL_FALSE;
- }
-
- if( GL_FALSE == RelocProgram(&(fp->r700AsmCode), &(mesa_fp->Base)) )
- {
- return GL_FALSE;
- }
-
- fp->r700Shader.nRegs = (fp->r700AsmCode.number_used_registers == 0) ? 0
- : (fp->r700AsmCode.number_used_registers - 1);
-
- fp->r700Shader.nParamExports = fp->r700AsmCode.number_of_exports;
-
- number_of_colors_exported = fp->r700AsmCode.number_of_colorandz_exports;
-
- unBit = 1 << FRAG_RESULT_DEPTH;
- if(mesa_fp->Base.OutputsWritten & unBit)
- {
- z_enabled = GL_TRUE;
- number_of_colors_exported--;
- }
-
- /* illegal to set this to 0 */
- if(number_of_colors_exported || z_enabled)
- {
- fp->r700Shader.exportMode = number_of_colors_exported << 1 | z_enabled;
- }
- else
- {
- fp->r700Shader.exportMode = (1 << 1);
- }
-
- fp->translated = GL_TRUE;
-
- return GL_TRUE;
-}
-
-void evergreenSelectFragmentShader(struct gl_context *ctx)
-{
- context_t *context = EVERGREEN_CONTEXT(ctx);
- struct evergreen_fragment_program *fp = (struct evergreen_fragment_program *)
- (ctx->FragmentProgram._Current);
- if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
- {
- fp->r700AsmCode.bR6xx = 1;
- }
-
- if (GL_FALSE == fp->translated)
- evergreenTranslateFragmentShader(fp, &(fp->mesa_program), ctx);
-}
-
-void * evergreenGetActiveFpShaderBo(struct gl_context * ctx)
-{
- struct evergreen_fragment_program *fp = (struct evergreen_fragment_program *)
- (ctx->FragmentProgram._Current);
-
- return fp->shaderbo;
-}
-
-void * evergreenGetActiveFpShaderConstBo(struct gl_context * ctx)
-{
- struct evergreen_fragment_program *fp = (struct evergreen_fragment_program *)
- (ctx->FragmentProgram._Current);
-
- return fp->constbo0;
-}
-
-GLboolean evergreenSetupFragmentProgram(struct gl_context * ctx)
-{
- context_t *context = EVERGREEN_CONTEXT(ctx);
- EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
- struct evergreen_fragment_program *fp = (struct evergreen_fragment_program *)
- (ctx->FragmentProgram._Current);
- r700_AssemblerBase *pAsm = &(fp->r700AsmCode);
- struct gl_fragment_program *mesa_fp = &(fp->mesa_program);
- unsigned int ui, i;
- unsigned int unNumOfReg;
- unsigned int unBit;
- GLuint exportCount;
- GLboolean point_sprite = GL_FALSE;
-
- if(GL_FALSE == fp->loaded)
- {
- if(fp->r700Shader.bNeedsAssembly == GL_TRUE)
- {
- Assemble( &(fp->r700Shader) );
- }
-
- r600EmitShader(ctx,
- &(fp->shaderbo),
- (GLvoid *)(fp->r700Shader.pProgram),
- fp->r700Shader.uShaderBinaryDWORDSize,
- "FS");
-
- fp->loaded = GL_TRUE;
- }
-
- /* TODO : enable this after MemUse fixed *=
- (context->chipobj.MemUse)(context, fp->shadercode.buf->id);
- */
-
- EVERGREEN_STATECHANGE(context, sq);
-
- evergreen->SQ_PGM_RESOURCES_PS.u32All = 0;
- SETbit(evergreen->SQ_PGM_RESOURCES_PS.u32All, PGM_RESOURCES__PRIME_CACHE_ON_DRAW_bit);
-
- evergreen->ps.SQ_ALU_CONST_CACHE_PS_0.u32All = 0;
- evergreen->ps.SQ_PGM_START_PS.u32All = 0;
-
- EVERGREEN_STATECHANGE(context, spi);
-
- unNumOfReg = fp->r700Shader.nRegs + 1;
-
- ui = (evergreen->SPI_PS_IN_CONTROL_0.u32All & NUM_INTERP_mask) / (1 << NUM_INTERP_shift);
-
- /* PS uses fragment.position */
- if (mesa_fp->Base.InputsRead & (1 << FRAG_ATTRIB_WPOS))
- {
- ui += 1;
- SETfield(evergreen->SPI_PS_IN_CONTROL_0.u32All, ui, NUM_INTERP_shift, NUM_INTERP_mask);
- SETfield(evergreen->SPI_PS_IN_CONTROL_0.u32All, CENTERS_ONLY, BARYC_SAMPLE_CNTL_shift, BARYC_SAMPLE_CNTL_mask);
- SETbit(evergreen->SPI_PS_IN_CONTROL_0.u32All, POSITION_ENA_bit);
- SETbit(evergreen->SPI_INPUT_Z.u32All, PROVIDE_Z_TO_SPI_bit);
- }
- else
- {
- CLEARbit(evergreen->SPI_PS_IN_CONTROL_0.u32All, POSITION_ENA_bit);
- CLEARbit(evergreen->SPI_INPUT_Z.u32All, PROVIDE_Z_TO_SPI_bit);
- }
-
- if (mesa_fp->Base.InputsRead & (1 << FRAG_ATTRIB_FACE))
- {
- ui += 1;
- SETfield(evergreen->SPI_PS_IN_CONTROL_0.u32All, ui, NUM_INTERP_shift, NUM_INTERP_mask);
- SETbit(evergreen->SPI_PS_IN_CONTROL_1.u32All, FRONT_FACE_ENA_bit);
- SETbit(evergreen->SPI_PS_IN_CONTROL_1.u32All, FRONT_FACE_ALL_BITS_bit);
- SETfield(evergreen->SPI_PS_IN_CONTROL_1.u32All, pAsm->uiFP_AttributeMap[FRAG_ATTRIB_FACE], FRONT_FACE_ADDR_shift, FRONT_FACE_ADDR_mask);
- }
- else
- {
- CLEARbit(evergreen->SPI_PS_IN_CONTROL_1.u32All, FRONT_FACE_ENA_bit);
- }
-
- /* see if we need any point_sprite replacements */
- for (i = VERT_RESULT_TEX0; i<= VERT_RESULT_TEX7; i++)
- {
- if(ctx->Point.CoordReplace[i - VERT_RESULT_TEX0] == GL_TRUE)
- point_sprite = GL_TRUE;
- }
-
- if ((mesa_fp->Base.InputsRead & (1 << FRAG_ATTRIB_PNTC)) || point_sprite)
- {
- /* for FRAG_ATTRIB_PNTC we need to increase num_interp */
- if(mesa_fp->Base.InputsRead & (1 << FRAG_ATTRIB_PNTC))
- {
- ui++;
- SETfield(evergreen->SPI_PS_IN_CONTROL_0.u32All, ui, NUM_INTERP_shift, NUM_INTERP_mask);
- }
- SETbit(evergreen->SPI_INTERP_CONTROL_0.u32All, PNT_SPRITE_ENA_bit);
- SETfield(evergreen->SPI_INTERP_CONTROL_0.u32All, SPI_PNT_SPRITE_SEL_S, PNT_SPRITE_OVRD_X_shift, PNT_SPRITE_OVRD_X_mask);
- SETfield(evergreen->SPI_INTERP_CONTROL_0.u32All, SPI_PNT_SPRITE_SEL_T, PNT_SPRITE_OVRD_Y_shift, PNT_SPRITE_OVRD_Y_mask);
- SETfield(evergreen->SPI_INTERP_CONTROL_0.u32All, SPI_PNT_SPRITE_SEL_0, PNT_SPRITE_OVRD_Z_shift, PNT_SPRITE_OVRD_Z_mask);
- SETfield(evergreen->SPI_INTERP_CONTROL_0.u32All, SPI_PNT_SPRITE_SEL_1, PNT_SPRITE_OVRD_W_shift, PNT_SPRITE_OVRD_W_mask);
- if(ctx->Point.SpriteOrigin == GL_LOWER_LEFT)
- SETbit(evergreen->SPI_INTERP_CONTROL_0.u32All, PNT_SPRITE_TOP_1_bit);
- else
- CLEARbit(evergreen->SPI_INTERP_CONTROL_0.u32All, PNT_SPRITE_TOP_1_bit);
- }
- else
- {
- CLEARbit(evergreen->SPI_INTERP_CONTROL_0.u32All, PNT_SPRITE_ENA_bit);
- }
-
-
- ui = (unNumOfReg < ui) ? ui : unNumOfReg;
-
- SETfield(evergreen->SQ_PGM_RESOURCES_PS.u32All, ui, NUM_GPRS_shift, NUM_GPRS_mask);
-
- CLEARbit(evergreen->SQ_PGM_RESOURCES_PS.u32All, UNCACHED_FIRST_INST_bit);
-
- if(fp->r700Shader.uStackSize) /* we don't use branch for now, it should be zero. */
- {
- SETfield(evergreen->SQ_PGM_RESOURCES_PS.u32All, fp->r700Shader.uStackSize,
- STACK_SIZE_shift, STACK_SIZE_mask);
- }
-
- SETfield(evergreen->SQ_PGM_EXPORTS_PS.u32All, fp->r700Shader.exportMode,
- EXPORT_MODE_shift, EXPORT_MODE_mask);
-
- // emit ps input map
- struct evergreen_vertex_program_cont *vpc =
- (struct evergreen_vertex_program_cont *)ctx->VertexProgram._Current;
- GLbitfield OutputsWritten = vpc->mesa_program.Base.OutputsWritten;
-
- for(ui = 0; ui < EVERGREEN_MAX_SHADER_EXPORTS; ui++)
- evergreen->SPI_PS_INPUT_CNTL[ui].u32All = 0;
-
- unBit = 1 << FRAG_ATTRIB_WPOS;
- if(mesa_fp->Base.InputsRead & unBit)
- {
- ui = pAsm->uiFP_AttributeMap[FRAG_ATTRIB_WPOS];
- SETbit(evergreen->SPI_PS_INPUT_CNTL[ui].u32All, SEL_CENTROID_bit);
- SETfield(evergreen->SPI_PS_INPUT_CNTL[ui].u32All, ui,
- SEMANTIC_shift, SEMANTIC_mask);
- CLEARbit(evergreen->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit);
- }
-
- unBit = 1 << VERT_RESULT_COL0;
- if(OutputsWritten & unBit)
- {
- ui = pAsm->uiFP_AttributeMap[FRAG_ATTRIB_COL0];
- SETbit(evergreen->SPI_PS_INPUT_CNTL[ui].u32All, SEL_CENTROID_bit);
- SETfield(evergreen->SPI_PS_INPUT_CNTL[ui].u32All, ui,
- SEMANTIC_shift, SEMANTIC_mask);
- if (evergreen->SPI_INTERP_CONTROL_0.u32All & FLAT_SHADE_ENA_bit)
- SETbit(evergreen->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit);
- else
- CLEARbit(evergreen->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit);
- }
-
- unBit = 1 << VERT_RESULT_COL1;
- if(OutputsWritten & unBit)
- {
- ui = pAsm->uiFP_AttributeMap[FRAG_ATTRIB_COL1];
- SETbit(evergreen->SPI_PS_INPUT_CNTL[ui].u32All, SEL_CENTROID_bit);
- SETfield(evergreen->SPI_PS_INPUT_CNTL[ui].u32All, ui,
- SEMANTIC_shift, SEMANTIC_mask);
- if (evergreen->SPI_INTERP_CONTROL_0.u32All & FLAT_SHADE_ENA_bit)
- SETbit(evergreen->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit);
- else
- CLEARbit(evergreen->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit);
- }
-
- unBit = 1 << VERT_RESULT_FOGC;
- if(OutputsWritten & unBit)
- {
- ui = pAsm->uiFP_AttributeMap[FRAG_ATTRIB_FOGC];
- SETbit(evergreen->SPI_PS_INPUT_CNTL[ui].u32All, SEL_CENTROID_bit);
- SETfield(evergreen->SPI_PS_INPUT_CNTL[ui].u32All, ui,
- SEMANTIC_shift, SEMANTIC_mask);
- CLEARbit(evergreen->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit);
- }
-
- for(i=0; i<8; i++)
- {
- unBit = 1 << (VERT_RESULT_TEX0 + i);
- if(OutputsWritten & unBit)
- {
- ui = pAsm->uiFP_AttributeMap[FRAG_ATTRIB_TEX0 + i];
- SETbit(evergreen->SPI_PS_INPUT_CNTL[ui].u32All, SEL_CENTROID_bit);
- SETfield(evergreen->SPI_PS_INPUT_CNTL[ui].u32All, ui,
- SEMANTIC_shift, SEMANTIC_mask);
- CLEARbit(evergreen->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit);
- /* ARB_point_sprite */
- if(ctx->Point.CoordReplace[i] == GL_TRUE)
- {
- SETbit(evergreen->SPI_PS_INPUT_CNTL[ui].u32All, PT_SPRITE_TEX_bit);
- }
- }
- }
-
- unBit = 1 << FRAG_ATTRIB_FACE;
- if(mesa_fp->Base.InputsRead & unBit)
- {
- ui = pAsm->uiFP_AttributeMap[FRAG_ATTRIB_FACE];
- SETbit(evergreen->SPI_PS_INPUT_CNTL[ui].u32All, SEL_CENTROID_bit);
- SETfield(evergreen->SPI_PS_INPUT_CNTL[ui].u32All, ui,
- SEMANTIC_shift, SEMANTIC_mask);
- CLEARbit(evergreen->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit);
- }
- unBit = 1 << FRAG_ATTRIB_PNTC;
- if(mesa_fp->Base.InputsRead & unBit)
- {
- ui = pAsm->uiFP_AttributeMap[FRAG_ATTRIB_PNTC];
- SETbit(evergreen->SPI_PS_INPUT_CNTL[ui].u32All, SEL_CENTROID_bit);
- SETfield(evergreen->SPI_PS_INPUT_CNTL[ui].u32All, ui,
- SEMANTIC_shift, SEMANTIC_mask);
- CLEARbit(evergreen->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit);
- SETbit(evergreen->SPI_PS_INPUT_CNTL[ui].u32All, PT_SPRITE_TEX_bit);
- }
-
-
-
-
- for(i=VERT_RESULT_VAR0; i<VERT_RESULT_MAX; i++)
- {
- unBit = 1 << i;
- if(OutputsWritten & unBit)
- {
- ui = pAsm->uiFP_AttributeMap[i-VERT_RESULT_VAR0+FRAG_ATTRIB_VAR0];
- SETbit(evergreen->SPI_PS_INPUT_CNTL[ui].u32All, SEL_CENTROID_bit);
- SETfield(evergreen->SPI_PS_INPUT_CNTL[ui].u32All, ui,
- SEMANTIC_shift, SEMANTIC_mask);
- CLEARbit(evergreen->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit);
- }
- }
-
- exportCount = (evergreen->SQ_PGM_EXPORTS_PS.u32All & EXPORT_MODE_mask) / (1 << EXPORT_MODE_shift);
-
- return GL_TRUE;
-}
-
-GLboolean evergreenSetupFPconstants(struct gl_context * ctx)
-{
- context_t *context = EVERGREEN_CONTEXT(ctx);
- EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
- struct evergreen_fragment_program *fp = (struct evergreen_fragment_program *)
- (ctx->FragmentProgram._Current);
- r700_AssemblerBase *pAsm = &(fp->r700AsmCode);
-
- struct gl_program_parameter_list *paramList;
- unsigned int unNumParamData;
- unsigned int ui;
- int alloc_size;
-
- /* sent out shader constants. */
- paramList = fp->mesa_program.Base.Parameters;
-
- if(NULL != paramList)
- {
- _mesa_load_state_parameters(ctx, paramList);
-
- if (paramList->NumParameters > EVERGREEN_MAX_DX9_CONSTS)
- return GL_FALSE;
-
- EVERGREEN_STATECHANGE(context, sq);
-
- evergreen->ps.num_consts = paramList->NumParameters;
-
- unNumParamData = paramList->NumParameters;
-
- for(ui=0; ui<unNumParamData; ui++) {
- evergreen->ps.consts[ui][0].f32All = paramList->ParameterValues[ui][0].f;
- evergreen->ps.consts[ui][1].f32All = paramList->ParameterValues[ui][1].f;
- evergreen->ps.consts[ui][2].f32All = paramList->ParameterValues[ui][2].f;
- evergreen->ps.consts[ui][3].f32All = paramList->ParameterValues[ui][3].f;
- }
-
- /* alloc multiple of 16 constants */
- alloc_size = ((unNumParamData * 4 * 4) + 255) & ~255;
-
- /* Load fp constants to gpu */
- if(unNumParamData > 0)
- {
- radeonAllocDmaRegion(&context->radeon,
- &context->fp_Constbo,
- &context->fp_bo_offset,
- alloc_size,
- 256);
- r600EmitShaderConsts(ctx,
- context->fp_Constbo,
- context->fp_bo_offset,
- (GLvoid *)&(evergreen->ps.consts[0][0]),
- unNumParamData * 4 * 4);
- }
- } else
- evergreen->ps.num_consts = 0;
-
- COMPILED_SUB * pCompiledSub;
- GLuint uj;
- GLuint unConstOffset = evergreen->ps.num_consts;
- for(ui=0; ui<pAsm->unNumPresub; ui++)
- {
- pCompiledSub = pAsm->presubs[ui].pCompiledSub;
-
- evergreen->ps.num_consts += pCompiledSub->NumParameters;
-
- for(uj=0; uj<pCompiledSub->NumParameters; uj++)
- {
- evergreen->ps.consts[uj + unConstOffset][0].f32All = pCompiledSub->ParameterValues[uj][0];
- evergreen->ps.consts[uj + unConstOffset][1].f32All = pCompiledSub->ParameterValues[uj][1];
- evergreen->ps.consts[uj + unConstOffset][2].f32All = pCompiledSub->ParameterValues[uj][2];
- evergreen->ps.consts[uj + unConstOffset][3].f32All = pCompiledSub->ParameterValues[uj][3];
- }
- unConstOffset += pCompiledSub->NumParameters;
- }
-
- return GL_TRUE;
-}
-
+++ /dev/null
-/*
- * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Authors:
- * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
- */
-
-#ifndef _EVERGREEN_FRAGPROG_H_
-#define _EVERGREEN_FRAGPROG_H_
-
-#include "r600_context.h"
-#include "r700_assembler.h"
-
-struct evergreen_fragment_program
-{
- struct gl_fragment_program mesa_program;
-
- r700_AssemblerBase r700AsmCode;
- R700_Shader r700Shader;
-
- GLboolean translated;
- GLboolean loaded;
- GLboolean error;
-
- void * shaderbo;
-
- GLuint k0used;
- void * constbo0;
-
- GLboolean WritesDepth;
- GLuint optimization;
-};
-
-/* Internal */
-void evergreen_insert_wpos_code(struct gl_context *ctx, struct gl_fragment_program *fprog);
-
-void evergreen_Map_Fragment_Program(r700_AssemblerBase *pAsm,
- struct gl_fragment_program *mesa_fp,
- struct gl_context *ctx);
-GLboolean evergreen_Find_Instruction_Dependencies_fp(struct evergreen_fragment_program *fp,
- struct gl_fragment_program *mesa_fp);
-
-GLboolean evergreenTranslateFragmentShader(struct evergreen_fragment_program *fp,
- struct gl_fragment_program *mesa_vp,
- struct gl_context *ctx);
-
-/* Interface */
-extern void evergreenSelectFragmentShader(struct gl_context *ctx);
-
-extern GLboolean evergreenSetupFragmentProgram(struct gl_context * ctx);
-
-extern GLboolean evergreenSetupFPconstants(struct gl_context * ctx);
-
-extern void * evergreenGetActiveFpShaderBo(struct gl_context * ctx);
-
-extern void * evergreenGetActiveFpShaderConstBo(struct gl_context * ctx);
-
-#endif /*_EVERGREEN_FRAGPROG_H_*/
+++ /dev/null
-/*
- * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Authors:
- * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
- */
-
-#include <sched.h>
-#include <errno.h>
-
-#include "main/glheader.h"
-#include "main/imports.h"
-#include "main/macros.h"
-#include "main/context.h"
-#include "main/simple_list.h"
-
-#include "radeon_common.h"
-#include "r600_context.h"
-
-#include "evergreen_ioctl.h"
-
-#include "r700_clear.h"
-
-void evergreenClear(struct gl_context * ctx, GLbitfield mask)
-{
- r700Clear(ctx, mask);
-}
-
-void evergreenInitIoctlFuncs(struct dd_function_table *functions)
-{
- functions->Clear = evergreenClear;
- functions->Finish = radeonFinish;
- functions->Flush = radeonFlush;
-}
+++ /dev/null
-/*
- * Copyright (C) 2008-2010 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Authors:
- * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
- */
-
-#ifndef _EVERGREEN_IOCTL_H_
-#define _EVERGREEN_IOCTL_H_
-
-#include "r600_context.h"
-#include "radeon_drm.h"
-
-extern void evergreenClear(struct gl_context * ctx, GLbitfield mask);
-extern void evergreenInitIoctlFuncs(struct dd_function_table *functions);
-
-#endif /* _EVERGREEN_IOCTL_H_ */
+++ /dev/null
-/*
- * Copyright (C) 2008-2010 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Authors:
- * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
- */
-
-#ifndef _EVERGREEN_OFF_H_
-#define _EVERGREEN_OFF_H_
-
-enum
-{
-/* Registers from PA block: */
- EG_PA_SC_SCREEN_SCISSOR_TL = 0x28030, // DIFF
- EG_PA_SC_SCREEN_SCISSOR_BR = 0x28034, // DIFF
- EG_PA_SC_WINDOW_OFFSET = 0x28200, // DIFF
- EG_PA_SC_WINDOW_SCISSOR_TL = 0x28204, // DIFF
- EG_PA_SC_WINDOW_SCISSOR_BR = 0x28208, // DIFF
- EG_PA_SC_CLIPRECT_RULE = 0x2820C, // SAME
- EG_PA_SC_CLIPRECT_0_TL = 0x28210, // DIFF
- EG_PA_SC_CLIPRECT_0_BR = 0x28214, // DIFF
- EG_PA_SC_CLIPRECT_1_TL = 0x28218, // DIFF
- EG_PA_SC_CLIPRECT_1_BR = 0x2821C, // DIFF
- EG_PA_SC_CLIPRECT_2_TL = 0x28220, // DIFF
- EG_PA_SC_CLIPRECT_2_BR = 0x28224, // DIFF
- EG_PA_SC_CLIPRECT_3_TL = 0x28228, // DIFF
- EG_PA_SC_CLIPRECT_3_BR = 0x2822C, // DIFF
- EG_PA_SC_EDGERULE = 0x28230, // SAME
- EG_PA_SU_HARDWARE_SCREEN_OFFSET = 0x28234, //
- EG_PA_SC_GENERIC_SCISSOR_TL = 0x28240, // DIFF
- EG_PA_SC_GENERIC_SCISSOR_BR = 0x28244, // DIFF
- EG_PA_SC_VPORT_SCISSOR_0_TL = 0x28250, // DIFF
- EG_PA_SC_VPORT_SCISSOR_0_BR = 0x28254, // DIFF
- EG_PA_SC_VPORT_SCISSOR_1_TL = 0x28258, // DIFF
- EG_PA_SC_VPORT_SCISSOR_1_BR = 0x2825C, // DIFF
- EG_PA_SC_VPORT_SCISSOR_2_TL = 0x28260, // DIFF
- EG_PA_SC_VPORT_SCISSOR_2_BR = 0x28264, // DIFF
- EG_PA_SC_VPORT_SCISSOR_3_TL = 0x28268, // DIFF
- EG_PA_SC_VPORT_SCISSOR_3_BR = 0x2826C, // DIFF
- EG_PA_SC_VPORT_SCISSOR_4_TL = 0x28270, // DIFF
- EG_PA_SC_VPORT_SCISSOR_4_BR = 0x28274, // DIFF
- EG_PA_SC_VPORT_SCISSOR_5_TL = 0x28278, // DIFF
- EG_PA_SC_VPORT_SCISSOR_5_BR = 0x2827C, // DIFF
- EG_PA_SC_VPORT_SCISSOR_6_TL = 0x28280, // DIFF
- EG_PA_SC_VPORT_SCISSOR_6_BR = 0x28284, // DIFF
- EG_PA_SC_VPORT_SCISSOR_7_TL = 0x28288, // DIFF
- EG_PA_SC_VPORT_SCISSOR_7_BR = 0x2828C, // DIFF
- EG_PA_SC_VPORT_SCISSOR_8_TL = 0x28290, // DIFF
- EG_PA_SC_VPORT_SCISSOR_8_BR = 0x28294, // DIFF
- EG_PA_SC_VPORT_SCISSOR_9_TL = 0x28298, // DIFF
- EG_PA_SC_VPORT_SCISSOR_9_BR = 0x2829C, // DIFF
- EG_PA_SC_VPORT_SCISSOR_10_TL = 0x282A0, // DIFF
- EG_PA_SC_VPORT_SCISSOR_10_BR = 0x282A4, // DIFF
- EG_PA_SC_VPORT_SCISSOR_11_TL = 0x282A8, // DIFF
- EG_PA_SC_VPORT_SCISSOR_11_BR = 0x282AC, // DIFF
- EG_PA_SC_VPORT_SCISSOR_12_TL = 0x282B0, // DIFF
- EG_PA_SC_VPORT_SCISSOR_12_BR = 0x282B4, // DIFF
- EG_PA_SC_VPORT_SCISSOR_13_TL = 0x282B8, // DIFF
- EG_PA_SC_VPORT_SCISSOR_13_BR = 0x282BC, // DIFF
- EG_PA_SC_VPORT_SCISSOR_14_TL = 0x282C0, // DIFF
- EG_PA_SC_VPORT_SCISSOR_14_BR = 0x282C4, // DIFF
- EG_PA_SC_VPORT_SCISSOR_15_TL = 0x282C8, // DIFF
- EG_PA_SC_VPORT_SCISSOR_15_BR = 0x282CC, // DIFF
- EG_PA_SC_VPORT_ZMIN_0 = 0x282D0, // SAME
- EG_PA_SC_VPORT_ZMAX_0 = 0x282D4, // SAME
- EG_PA_SC_VPORT_ZMIN_1 = 0x282D8, // SAME
- EG_PA_SC_VPORT_ZMAX_1 = 0x282DC, // SAME
- EG_PA_SC_VPORT_ZMIN_2 = 0x282E0, // SAME
- EG_PA_SC_VPORT_ZMAX_2 = 0x282E4, // SAME
- EG_PA_SC_VPORT_ZMIN_3 = 0x282E8, // SAME
- EG_PA_SC_VPORT_ZMAX_3 = 0x282EC, // SAME
- EG_PA_SC_VPORT_ZMIN_4 = 0x282F0, // SAME
- EG_PA_SC_VPORT_ZMAX_4 = 0x282F4, // SAME
- EG_PA_SC_VPORT_ZMIN_5 = 0x282F8, // SAME
- EG_PA_SC_VPORT_ZMAX_5 = 0x282FC, // SAME
- EG_PA_SC_VPORT_ZMIN_6 = 0x28300, // SAME
- EG_PA_SC_VPORT_ZMAX_6 = 0x28304, // SAME
- EG_PA_SC_VPORT_ZMIN_7 = 0x28308, // SAME
- EG_PA_SC_VPORT_ZMAX_7 = 0x2830C, // SAME
- EG_PA_SC_VPORT_ZMIN_8 = 0x28310, // SAME
- EG_PA_SC_VPORT_ZMAX_8 = 0x28314, // SAME
- EG_PA_SC_VPORT_ZMIN_9 = 0x28318, // SAME
- EG_PA_SC_VPORT_ZMAX_9 = 0x2831C, // SAME
- EG_PA_SC_VPORT_ZMIN_10 = 0x28320, // SAME
- EG_PA_SC_VPORT_ZMAX_10 = 0x28324, // SAME
- EG_PA_SC_VPORT_ZMIN_11 = 0x28328, // SAME
- EG_PA_SC_VPORT_ZMAX_11 = 0x2832C, // SAME
- EG_PA_SC_VPORT_ZMIN_12 = 0x28330, // SAME
- EG_PA_SC_VPORT_ZMAX_12 = 0x28334, // SAME
- EG_PA_SC_VPORT_ZMIN_13 = 0x28338, // SAME
- EG_PA_SC_VPORT_ZMAX_13 = 0x2833C, // SAME
- EG_PA_SC_VPORT_ZMIN_14 = 0x28340, // SAME
- EG_PA_SC_VPORT_ZMAX_14 = 0x28344, // SAME
- EG_PA_SC_VPORT_ZMIN_15 = 0x28348, // SAME
- EG_PA_SC_VPORT_ZMAX_15 = 0x2834C, // SAME
- EG_PA_CL_VPORT_XSCALE = 0x2843C, // SAME
- EG_PA_CL_VPORT_XOFFSET = 0x28440, // SAME
- EG_PA_CL_VPORT_YSCALE = 0x28444, // SAME
- EG_PA_CL_VPORT_YOFFSET = 0x28448, // SAME
- EG_PA_CL_VPORT_ZSCALE = 0x2844C, // SAME
- EG_PA_CL_VPORT_ZOFFSET = 0x28450, // SAME
- EG_PA_CL_VPORT_XSCALE_1 = 0x28454, // SAME
- EG_PA_CL_VPORT_XOFFSET_1 = 0x28458, // SAME
- EG_PA_CL_VPORT_YSCALE_1 = 0x2845C, // SAME
- EG_PA_CL_VPORT_YOFFSET_1 = 0x28460, // SAME
- EG_PA_CL_VPORT_ZSCALE_1 = 0x28464, // SAME
- EG_PA_CL_VPORT_ZOFFSET_1 = 0x28468, // SAME
- EG_PA_CL_VPORT_XSCALE_2 = 0x2846C, // SAME
- EG_PA_CL_VPORT_XOFFSET_2 = 0x28470, // SAME
- EG_PA_CL_VPORT_YSCALE_2 = 0x28474, // SAME
- EG_PA_CL_VPORT_YOFFSET_2 = 0x28478, // SAME
- EG_PA_CL_VPORT_ZSCALE_2 = 0x2847C, // SAME
- EG_PA_CL_VPORT_ZOFFSET_2 = 0x28480, // SAME
- EG_PA_CL_VPORT_XSCALE_3 = 0x28484, // SAME
- EG_PA_CL_VPORT_XOFFSET_3 = 0x28488, // SAME
- EG_PA_CL_VPORT_YSCALE_3 = 0x2848C, // SAME
- EG_PA_CL_VPORT_YOFFSET_3 = 0x28490, // SAME
- EG_PA_CL_VPORT_ZSCALE_3 = 0x28494, // SAME
- EG_PA_CL_VPORT_ZOFFSET_3 = 0x28498, // SAME
- EG_PA_CL_VPORT_XSCALE_4 = 0x2849C, // SAME
- EG_PA_CL_VPORT_XOFFSET_4 = 0x284A0, // SAME
- EG_PA_CL_VPORT_YSCALE_4 = 0x284A4, // SAME
- EG_PA_CL_VPORT_YOFFSET_4 = 0x284A8, // SAME
- EG_PA_CL_VPORT_ZSCALE_4 = 0x284AC, // SAME
- EG_PA_CL_VPORT_ZOFFSET_4 = 0x284B0, // SAME
- EG_PA_CL_VPORT_XSCALE_5 = 0x284B4, // SAME
- EG_PA_CL_VPORT_XOFFSET_5 = 0x284B8, // SAME
- EG_PA_CL_VPORT_YSCALE_5 = 0x284BC, // SAME
- EG_PA_CL_VPORT_YOFFSET_5 = 0x284C0, // SAME
- EG_PA_CL_VPORT_ZSCALE_5 = 0x284C4, // SAME
- EG_PA_CL_VPORT_ZOFFSET_5 = 0x284C8, // SAME
- EG_PA_CL_VPORT_XSCALE_6 = 0x284CC, // SAME
- EG_PA_CL_VPORT_XOFFSET_6 = 0x284D0, // SAME
- EG_PA_CL_VPORT_YSCALE_6 = 0x284D4, // SAME
- EG_PA_CL_VPORT_YOFFSET_6 = 0x284D8, // SAME
- EG_PA_CL_VPORT_ZSCALE_6 = 0x284DC, // SAME
- EG_PA_CL_VPORT_ZOFFSET_6 = 0x284E0, // SAME
- EG_PA_CL_VPORT_XSCALE_7 = 0x284E4, // SAME
- EG_PA_CL_VPORT_XOFFSET_7 = 0x284E8, // SAME
- EG_PA_CL_VPORT_YSCALE_7 = 0x284EC, // SAME
- EG_PA_CL_VPORT_YOFFSET_7 = 0x284F0, // SAME
- EG_PA_CL_VPORT_ZSCALE_7 = 0x284F4, // SAME
- EG_PA_CL_VPORT_ZOFFSET_7 = 0x284F8, // SAME
- EG_PA_CL_VPORT_XSCALE_8 = 0x284FC, // SAME
- EG_PA_CL_VPORT_XOFFSET_8 = 0x28500, // SAME
- EG_PA_CL_VPORT_YSCALE_8 = 0x28504, // SAME
- EG_PA_CL_VPORT_YOFFSET_8 = 0x28508, // SAME
- EG_PA_CL_VPORT_ZSCALE_8 = 0x2850C, // SAME
- EG_PA_CL_VPORT_ZOFFSET_8 = 0x28510, // SAME
- EG_PA_CL_VPORT_XSCALE_9 = 0x28514, // SAME
- EG_PA_CL_VPORT_XOFFSET_9 = 0x28518, // SAME
- EG_PA_CL_VPORT_YSCALE_9 = 0x2851C, // SAME
- EG_PA_CL_VPORT_YOFFSET_9 = 0x28520, // SAME
- EG_PA_CL_VPORT_ZSCALE_9 = 0x28524, // SAME
- EG_PA_CL_VPORT_ZOFFSET_9 = 0x28528, // SAME
- EG_PA_CL_VPORT_XSCALE_10 = 0x2852C, // SAME
- EG_PA_CL_VPORT_XOFFSET_10 = 0x28530, // SAME
- EG_PA_CL_VPORT_YSCALE_10 = 0x28534, // SAME
- EG_PA_CL_VPORT_YOFFSET_10 = 0x28538, // SAME
- EG_PA_CL_VPORT_ZSCALE_10 = 0x2853C, // SAME
- EG_PA_CL_VPORT_ZOFFSET_10 = 0x28540, // SAME
- EG_PA_CL_VPORT_XSCALE_11 = 0x28544, // SAME
- EG_PA_CL_VPORT_XOFFSET_11 = 0x28548, // SAME
- EG_PA_CL_VPORT_YSCALE_11 = 0x2854C, // SAME
- EG_PA_CL_VPORT_YOFFSET_11 = 0x28550, // SAME
- EG_PA_CL_VPORT_ZSCALE_11 = 0x28554, // SAME
- EG_PA_CL_VPORT_ZOFFSET_11 = 0x28558, // SAME
- EG_PA_CL_VPORT_XSCALE_12 = 0x2855C, // SAME
- EG_PA_CL_VPORT_XOFFSET_12 = 0x28560, // SAME
- EG_PA_CL_VPORT_YSCALE_12 = 0x28564, // SAME
- EG_PA_CL_VPORT_YOFFSET_12 = 0x28568, // SAME
- EG_PA_CL_VPORT_ZSCALE_12 = 0x2856C, // SAME
- EG_PA_CL_VPORT_ZOFFSET_12 = 0x28570, // SAME
- EG_PA_CL_VPORT_XSCALE_13 = 0x28574, // SAME
- EG_PA_CL_VPORT_XOFFSET_13 = 0x28578, // SAME
- EG_PA_CL_VPORT_YSCALE_13 = 0x2857C, // SAME
- EG_PA_CL_VPORT_YOFFSET_13 = 0x28580, // SAME
- EG_PA_CL_VPORT_ZSCALE_13 = 0x28584, // SAME
- EG_PA_CL_VPORT_ZOFFSET_13 = 0x28588, // SAME
- EG_PA_CL_VPORT_XSCALE_14 = 0x2858C, // SAME
- EG_PA_CL_VPORT_XOFFSET_14 = 0x28590, // SAME
- EG_PA_CL_VPORT_YSCALE_14 = 0x28594, // SAME
- EG_PA_CL_VPORT_YOFFSET_14 = 0x28598, // SAME
- EG_PA_CL_VPORT_ZSCALE_14 = 0x2859C, // SAME
- EG_PA_CL_VPORT_ZOFFSET_14 = 0x285A0, // SAME
- EG_PA_CL_VPORT_XSCALE_15 = 0x285A4, // SAME
- EG_PA_CL_VPORT_XOFFSET_15 = 0x285A8, // SAME
- EG_PA_CL_VPORT_YSCALE_15 = 0x285AC, // SAME
- EG_PA_CL_VPORT_YOFFSET_15 = 0x285B0, // SAME
- EG_PA_CL_VPORT_ZSCALE_15 = 0x285B4, // SAME
- EG_PA_CL_VPORT_ZOFFSET_15 = 0x285B8, // SAME
- EG_PA_CL_UCP_0_X = 0x285BC, // SAME 0x28E20
- EG_PA_CL_UCP_0_Y = 0x285C0, // SAME 0x28E24
- EG_PA_CL_UCP_0_Z = 0x285C4, // SAME 0x28E28
- EG_PA_CL_UCP_0_W = 0x285C8, // SAME 0x28E2C
- EG_PA_CL_UCP_1_X = 0x285CC, // SAME 0x28E30
- EG_PA_CL_UCP_1_Y = 0x285D0, // SAME 0x28E34
- EG_PA_CL_UCP_1_Z = 0x285D4, // SAME 0x28E38
- EG_PA_CL_UCP_1_W = 0x285D8, // SAME 0x28E3C
- EG_PA_CL_UCP_2_X = 0x285DC, // SAME 0x28E40
- EG_PA_CL_UCP_2_Y = 0x285E0, // SAME 0x28E44
- EG_PA_CL_UCP_2_Z = 0x285E4, // SAME 0x28E48
- EG_PA_CL_UCP_2_W = 0x285E8, // SAME 0x28E4C
- EG_PA_CL_UCP_3_X = 0x285EC, // SAME 0x28E50
- EG_PA_CL_UCP_3_Y = 0x285F0, // SAME 0x28E54
- EG_PA_CL_UCP_3_Z = 0x285F4, // SAME 0x28E58
- EG_PA_CL_UCP_3_W = 0x285F8, // SAME 0x28E5C
- EG_PA_CL_UCP_4_X = 0x285FC, // SAME 0x28E60
- EG_PA_CL_UCP_4_Y = 0x28600, // SAME 0x28E64
- EG_PA_CL_UCP_4_Z = 0x28604, // SAME 0x28E68
- EG_PA_CL_UCP_4_W = 0x28608, // SAME 0x28E6C
- EG_PA_CL_UCP_5_X = 0x2860C, // SAME 0x28E70
- EG_PA_CL_UCP_5_Y = 0x28610, // SAME 0x28E74
- EG_PA_CL_UCP_5_Z = 0x28614, // SAME 0x28E78
- EG_PA_CL_UCP_5_W = 0x28618, // SAME 0x28E7C
- EG_PA_CL_POINT_X_RAD = 0x287D4, // SAME 0x28E10
- EG_PA_CL_POINT_Y_RAD = 0x287D8, // SAME 0x28E14
- EG_PA_CL_POINT_SIZE = 0x287DC, // SAME 0x28E18
- EG_PA_CL_POINT_CULL_RAD = 0x287E0, // SAME 0x28E1C
- EG_PA_CL_CLIP_CNTL = 0x28810, // SAME
- EG_PA_SU_SC_MODE_CNTL = 0x28814, // SAME
- EG_PA_CL_VTE_CNTL = 0x28818, // SAME
- EG_PA_CL_VS_OUT_CNTL = 0x2881C, // SAME
- EG_PA_CL_NANINF_CNTL = 0x28820, // SAME
- EG_PA_SU_LINE_STIPPLE_CNTL = 0x28824, //
- EG_PA_SU_LINE_STIPPLE_SCALE = 0x28828, //
- EG_PA_SU_PRIM_FILTER_CNTL = 0x2882C, //
- EG_PA_SU_POINT_SIZE = 0x28A00, // SAME
- EG_PA_SU_POINT_MINMAX = 0x28A04, // SAME
- EG_PA_SU_LINE_CNTL = 0x28A08, // SAME
- EG_PA_SC_LINE_STIPPLE = 0x28A0C, // SAME
- EG_PA_SC_MODE_CNTL_0 = 0x28A48, //
- EG_PA_SC_MODE_CNTL_1 = 0x28A4C, //
- EG_PA_SU_POLY_OFFSET_DB_FMT_CNTL = 0x28B78, // SAME 0x28DF8
- EG_PA_SU_POLY_OFFSET_CLAMP = 0x28B7C, // SAME 0x28DFC
- EG_PA_SU_POLY_OFFSET_FRONT_SCALE = 0x28B80, // SAME 0x28E00
- EG_PA_SU_POLY_OFFSET_FRONT_OFFSET = 0x28B84, // SAME 0x28E04
- EG_PA_SU_POLY_OFFSET_BACK_SCALE = 0x28B88, // SAME 0x28E08
- EG_PA_SU_POLY_OFFSET_BACK_OFFSET = 0x28B8C, // SAME 0x28E0C
- EG_PA_SC_LINE_CNTL = 0x28C00, // DIFF
- EG_PA_SC_AA_CONFIG = 0x28C04, // SAME
- EG_PA_SU_VTX_CNTL = 0x28C08, // SAME
- EG_PA_CL_GB_VERT_CLIP_ADJ = 0x28C0C, // SAME
- EG_PA_CL_GB_VERT_DISC_ADJ = 0x28C10, // SAME
- EG_PA_CL_GB_HORZ_CLIP_ADJ = 0x28C14, // SAME
- EG_PA_CL_GB_HORZ_DISC_ADJ = 0x28C18, // SAME
- EG_PA_SC_AA_SAMPLE_LOCS_0 = 0x28C1C, //
- EG_PA_SC_AA_SAMPLE_LOCS_1 = 0x28C20, //
- EG_PA_SC_AA_SAMPLE_LOCS_2 = 0x28C24, //
- EG_PA_SC_AA_SAMPLE_LOCS_3 = 0x28C28, //
- EG_PA_SC_AA_SAMPLE_LOCS_4 = 0x28C2C, //
- EG_PA_SC_AA_SAMPLE_LOCS_5 = 0x28C30, //
- EG_PA_SC_AA_SAMPLE_LOCS_6 = 0x28C34, //
- EG_PA_SC_AA_SAMPLE_LOCS_7 = 0x28C38, //
- EG_PA_SC_AA_MASK = 0x28C3C, // SAME 0x28C48
-
-/* Registers from VGT block: */
- EG_VGT_INDEX_TYPE = 0x895C, //? config space
- EG_VGT_PRIMITIVE_TYPE = 0x8958, //? config space
-
- EG_VGT_MAX_VTX_INDX = 0x28400, // SAME
- EG_VGT_MIN_VTX_INDX = 0x28404, // SAME
- EG_VGT_INDX_OFFSET = 0x28408, // SAME
- EG_VGT_MULTI_PRIM_IB_RESET_INDX = 0x2840C, // SAME
- EG_CS_COPY_STATE = 0x287CC, //
- EG_GFX_COPY_STATE = 0x287D0, // SAME
- EG_VGT_DMA_BASE_HI = 0x287E4, // SAME
- EG_VGT_DMA_BASE = 0x287E8, // SAME
- EG_VGT_DRAW_INITIATOR = 0x287F0, // SAME
- EG_VGT_IMMED_DATA = 0x287F4, // SAME
- EG_VGT_EVENT_ADDRESS_REG = 0x287F8, // SAME
- EG_VGT_OUTPUT_PATH_CNTL = 0x28A10, // DIFF
- EG_VGT_HOS_CNTL = 0x28A14, // SAME
- EG_VGT_HOS_MAX_TESS_LEVEL = 0x28A18, // SAME
- EG_VGT_HOS_MIN_TESS_LEVEL = 0x28A1C, // SAME
- EG_VGT_HOS_REUSE_DEPTH = 0x28A20, // SAME
- EG_VGT_GROUP_PRIM_TYPE = 0x28A24, // SAME
- EG_VGT_GROUP_FIRST_DECR = 0x28A28, // SAME
- EG_VGT_GROUP_DECR = 0x28A2C, // SAME
- EG_VGT_GROUP_VECT_0_CNTL = 0x28A30, // SAME
- EG_VGT_GROUP_VECT_1_CNTL = 0x28A34, // SAME
- EG_VGT_GROUP_VECT_0_FMT_CNTL = 0x28A38, // SAME
- EG_VGT_GROUP_VECT_1_FMT_CNTL = 0x28A3C, // SAME
- EG_VGT_GS_MODE = 0x28A40, // DIFF
- EG_VGT_ENHANCE = 0x28A50, // DIFF
- EG_VGT_GS_PER_ES = 0x28A54, // DIFF 0x88C8
- EG_VGT_ES_PER_GS = 0x28A58, // DIFF 0x88CC
- EG_VGT_GS_PER_VS = 0x28A5C, // SAME 0x88E8
- EG_VGT_GS_OUT_PRIM_TYPE = 0x28A6C, // SAME
- EG_VGT_DMA_SIZE = 0x28A74, // SAME
- EG_VGT_DMA_MAX_SIZE = 0x28A78, // SAME
- EG_VGT_DMA_INDEX_TYPE = 0x28A7C, // SAME
- EG_VGT_PRIMITIVEID_EN = 0x28A84, // SAME
- EG_VGT_DMA_NUM_INSTANCES = 0x28A88, // SAME
- EG_VGT_EVENT_INITIATOR = 0x28A90, // SAME
- EG_VGT_MULTI_PRIM_IB_RESET_EN = 0x28A94, // SAME
- EG_VGT_INSTANCE_STEP_RATE_0 = 0x28AA0, // SAME
- EG_VGT_INSTANCE_STEP_RATE_1 = 0x28AA4, // SAME
- EG_VGT_REUSE_OFF = 0x28AB4, // SAME
- EG_VGT_VTX_CNT_EN = 0x28AB8, // SAME
- EG_VGT_STRMOUT_BUFFER_SIZE_0 = 0x28AD0, // SAME
- EG_VGT_STRMOUT_VTX_STRIDE_0 = 0x28AD4, // SAME
- EG_VGT_STRMOUT_BUFFER_BASE_0 = 0x28AD8, // SAME
- EG_VGT_STRMOUT_BUFFER_OFFSET_0 = 0x28ADC, // SAME
- EG_VGT_STRMOUT_BUFFER_SIZE_1 = 0x28AE0, // SAME
- EG_VGT_STRMOUT_VTX_STRIDE_1 = 0x28AE4, // SAME
- EG_VGT_STRMOUT_BUFFER_BASE_1 = 0x28AE8, // SAME
- EG_VGT_STRMOUT_BUFFER_OFFSET_1 = 0x28AEC, // SAME
- EG_VGT_STRMOUT_BUFFER_SIZE_2 = 0x28AF0, // SAME
- EG_VGT_STRMOUT_VTX_STRIDE_2 = 0x28AF4, // SAME
- EG_VGT_STRMOUT_BUFFER_BASE_2 = 0x28AF8, // SAME
- EG_VGT_STRMOUT_BUFFER_OFFSET_2 = 0x28AFC, // SAME
- EG_VGT_STRMOUT_BUFFER_SIZE_3 = 0x28B00, // SAME
- EG_VGT_STRMOUT_VTX_STRIDE_3 = 0x28B04, // SAME
- EG_VGT_STRMOUT_BUFFER_BASE_3 = 0x28B08, // SAME
- EG_VGT_STRMOUT_BUFFER_OFFSET_3 = 0x28B0C, // SAME
- EG_VGT_STRMOUT_BASE_OFFSET_0 = 0x28B10, // SAME
- EG_VGT_STRMOUT_BASE_OFFSET_1 = 0x28B14, // SAME
- EG_VGT_STRMOUT_BASE_OFFSET_2 = 0x28B18, // SAME
- EG_VGT_STRMOUT_BASE_OFFSET_3 = 0x28B1C, // SAME
- EG_VGT_STRMOUT_DRAW_OPAQUE_OFFSET = 0x28B28, // SAME
- EG_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE = 0x28B2C, // SAME
- EG_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE = 0x28B30, // DIFF
- EG_VGT_GS_MAX_VERT_OUT = 0x28B38, // SAME
- EG_VGT_STRMOUT_BASE_OFFSET_HI_0 = 0x28B44, // SAME
- EG_VGT_STRMOUT_BASE_OFFSET_HI_1 = 0x28B48, // SAME
- EG_VGT_STRMOUT_BASE_OFFSET_HI_2 = 0x28B4C, // SAME
- EG_VGT_STRMOUT_BASE_OFFSET_HI_3 = 0x28B50, // SAME
- EG_VGT_SHADER_STAGES_EN = 0x28B54, //
- EG_VGT_LS_HS_CONFIG = 0x28B58, //
- EG_VGT_LS_SIZE = 0x28B5C, //
- EG_VGT_HS_SIZE = 0x28B60, //
- EG_VGT_LS_HS_ALLOC = 0x28B64, //
- EG_VGT_HS_PATCH_CONST = 0x28B68, //
- EG_VGT_TF_PARAM = 0x28B6C, //
- EG_VGT_DISPATCH_INITIATOR = 0x28B74, //
- EG_VGT_GS_INSTANCE_CNT = 0x28B90, //
- EG_VGT_STRMOUT_CONFIG = 0x28B94, //
- EG_VGT_STRMOUT_BUFFER_CONFIG = 0x28B98, //
- EG_VGT_VERTEX_REUSE_BLOCK_CNTL = 0x28C58, // SAME
- EG_VGT_OUT_DEALLOC_CNTL = 0x28C5C, // SAME
-
-/* Registers from TP block: */
- EG_GDS_ADDR_BASE = 0x28720, //
- EG_GDS_ADDR_SIZE = 0x28724, //
- EG_GDS_ORDERED_WAVE_PER_SE = 0x28728, //
- EG_GDS_APPEND_CONSUME_UAV0 = 0x2872C, //
- EG_GDS_APPEND_CONSUME_UAV1 = 0x28730, //
- EG_GDS_APPEND_CONSUME_UAV2 = 0x28734, //
- EG_GDS_APPEND_CONSUME_UAV3 = 0x28738, //
- EG_GDS_APPEND_CONSUME_UAV4 = 0x2873C, //
- EG_GDS_APPEND_CONSUME_UAV5 = 0x28740, //
- EG_GDS_APPEND_CONSUME_UAV6 = 0x28744, //
- EG_GDS_APPEND_CONSUME_UAV7 = 0x28748, //
- EG_GDS_APPEND_CONSUME_UAV8 = 0x2874C, //
- EG_GDS_APPEND_CONSUME_UAV9 = 0x28750, //
- EG_GDS_APPEND_CONSUME_UAV10 = 0x28754, //
- EG_GDS_APPEND_CONSUME_UAV11 = 0x28758, //
-
-/* Registers from SQ block: */
- EG_SQ_LOOP_CONST_0 = 0x3A200, // 0x3E200
- EG_SQ_ALU_CONST_BUFFER_SIZE_VS_0 = 0x28180, // ?
- EG_SQ_VTX_SEMANTIC_0 = 0x28380, // SAME
- EG_SQ_VTX_SEMANTIC_1 = 0x28384, // SAME
- EG_SQ_VTX_SEMANTIC_2 = 0x28388, // SAME
- EG_SQ_VTX_SEMANTIC_3 = 0x2838C, // SAME
- EG_SQ_VTX_SEMANTIC_4 = 0x28390, // SAME
- EG_SQ_VTX_SEMANTIC_5 = 0x28394, // SAME
- EG_SQ_VTX_SEMANTIC_6 = 0x28398, // SAME
- EG_SQ_VTX_SEMANTIC_7 = 0x2839C, // SAME
- EG_SQ_VTX_SEMANTIC_8 = 0x283A0, // SAME
- EG_SQ_VTX_SEMANTIC_9 = 0x283A4, // SAME
- EG_SQ_VTX_SEMANTIC_10 = 0x283A8, // SAME
- EG_SQ_VTX_SEMANTIC_11 = 0x283AC, // SAME
- EG_SQ_VTX_SEMANTIC_12 = 0x283B0, // SAME
- EG_SQ_VTX_SEMANTIC_13 = 0x283B4, // SAME
- EG_SQ_VTX_SEMANTIC_14 = 0x283B8, // SAME
- EG_SQ_VTX_SEMANTIC_15 = 0x283BC, // SAME
- EG_SQ_VTX_SEMANTIC_16 = 0x283C0, // SAME
- EG_SQ_VTX_SEMANTIC_17 = 0x283C4, // SAME
- EG_SQ_VTX_SEMANTIC_18 = 0x283C8, // SAME
- EG_SQ_VTX_SEMANTIC_19 = 0x283CC, // SAME
- EG_SQ_VTX_SEMANTIC_20 = 0x283D0, // SAME
- EG_SQ_VTX_SEMANTIC_21 = 0x283D4, // SAME
- EG_SQ_VTX_SEMANTIC_22 = 0x283D8, // SAME
- EG_SQ_VTX_SEMANTIC_23 = 0x283DC, // SAME
- EG_SQ_VTX_SEMANTIC_24 = 0x283E0, // SAME
- EG_SQ_VTX_SEMANTIC_25 = 0x283E4, // SAME
- EG_SQ_VTX_SEMANTIC_26 = 0x283E8, // SAME
- EG_SQ_VTX_SEMANTIC_27 = 0x283EC, // SAME
- EG_SQ_VTX_SEMANTIC_28 = 0x283F0, // SAME
- EG_SQ_VTX_SEMANTIC_29 = 0x283F4, // SAME
- EG_SQ_VTX_SEMANTIC_30 = 0x283F8, // SAME
- EG_SQ_VTX_SEMANTIC_31 = 0x283FC, // SAME
- EG_SQ_LSTMP_RING_ITEMSIZE = 0x28830, //
- EG_SQ_HSTMP_RING_ITEMSIZE = 0x28834, //
- EG_SQ_DYN_GPR_RESOURCE_LIMIT_1 = 0x28838, //
- EG_SQ_PGM_START_PS = 0x28840, // SAME
- EG_SQ_PGM_RESOURCES_PS = 0x28844, // DIFF 0x28850
- EG_SQ_PGM_RESOURCES_2_PS = 0x28848, //
- EG_SQ_PGM_EXPORTS_PS = 0x2884C, // SAME 0x28854
- EG_SQ_PGM_START_VS = 0x2885C, // SAME 0x28858
- EG_SQ_PGM_RESOURCES_VS = 0x28860, // DIFF 0x28868
- EG_SQ_PGM_RESOURCES_2_VS = 0x28864, //
- EG_SQ_PGM_START_GS = 0x28874, // SAME 0x2886C
- EG_SQ_PGM_RESOURCES_GS = 0x28878, // DIFF 0x2887C
- EG_SQ_PGM_RESOURCES_2_GS = 0x2887C, //
- EG_SQ_PGM_START_ES = 0x2888C, // SAME 0x28880
- EG_SQ_PGM_RESOURCES_ES = 0x28890, // DIFF
- EG_SQ_PGM_RESOURCES_2_ES = 0x28894, //
- EG_SQ_PGM_START_FS = 0x288A4, // SAME 0x28894
- EG_SQ_PGM_RESOURCES_FS = 0x288A8, // DIFF 0x288A4
- EG_SQ_PGM_START_HS = 0x288B8, //
- EG_SQ_PGM_RESOURCES_HS = 0x288BC, //
- EG_SQ_PGM_RESOURCES_2_HS = 0x288C0, //
- EG_SQ_PGM_START_LS = 0x288D0, //
- EG_SQ_PGM_RESOURCES_LS = 0x288D4, //
- EG_SQ_PGM_RESOURCES_2_LS = 0x288D8, //
- EG_SQ_THREAD_TRACE_USERDATA = 0x288DC, //
- EG_SQ_LDS_ALLOC = 0x288E8, //
- EG_SQ_LDS_ALLOC_PS = 0x288EC, //
- EG_SQ_VTX_SEMANTIC_CLEAR = 0x288F0, // SAME 0x288E0
- EG_SQ_THREAD_TRACE_CTRL = 0x288F8, //
- EG_SQ_ESGS_RING_ITEMSIZE = 0x28900, // SAME 0x288A8
- EG_SQ_GSVS_RING_ITEMSIZE = 0x28904, // SAME 0x288AC
- EG_SQ_ESTMP_RING_ITEMSIZE = 0x28908, // SAME 0x288B0
- EG_SQ_GSTMP_RING_ITEMSIZE = 0x2890C, // SAME 0x288B4
- EG_SQ_VSTMP_RING_ITEMSIZE = 0x28910, // SAME 0x288B8
- EG_SQ_PSTMP_RING_ITEMSIZE = 0x28914, // SAME 0x288BC
- EG_SQ_GS_VERT_ITEMSIZE = 0x2891C, // SAME 0x288C8
- EG_SQ_GS_VERT_ITEMSIZE_1 = 0x28920, //
- EG_SQ_GS_VERT_ITEMSIZE_2 = 0x28924, //
- EG_SQ_GS_VERT_ITEMSIZE_3 = 0x28928, //
- EG_SQ_GSVS_RING_OFFSET_1 = 0x2892C, //
- EG_SQ_GSVS_RING_OFFSET_2 = 0x28930, //
- EG_SQ_GSVS_RING_OFFSET_3 = 0x28934, //
- EG_SQ_ALU_CONST_CACHE_PS_0 = 0x28940, // SAME
- EG_SQ_ALU_CONST_CACHE_PS_1 = 0x28944, // SAME
- EG_SQ_ALU_CONST_CACHE_PS_2 = 0x28948, // SAME
- EG_SQ_ALU_CONST_CACHE_PS_3 = 0x2894C, // SAME
- EG_SQ_ALU_CONST_CACHE_PS_4 = 0x28950, // SAME
- EG_SQ_ALU_CONST_CACHE_PS_5 = 0x28954, // SAME
- EG_SQ_ALU_CONST_CACHE_PS_6 = 0x28958, // SAME
- EG_SQ_ALU_CONST_CACHE_PS_7 = 0x2895C, // SAME
- EG_SQ_ALU_CONST_CACHE_PS_8 = 0x28960, // SAME
- EG_SQ_ALU_CONST_CACHE_PS_9 = 0x28964, // SAME
- EG_SQ_ALU_CONST_CACHE_PS_10 = 0x28968, // SAME
- EG_SQ_ALU_CONST_CACHE_PS_11 = 0x2896C, // SAME
- EG_SQ_ALU_CONST_CACHE_PS_12 = 0x28970, // SAME
- EG_SQ_ALU_CONST_CACHE_PS_13 = 0x28974, // SAME
- EG_SQ_ALU_CONST_CACHE_PS_14 = 0x28978, // SAME
- EG_SQ_ALU_CONST_CACHE_PS_15 = 0x2897C, // SAME
- EG_SQ_ALU_CONST_CACHE_VS_0 = 0x28980, // SAME
- EG_SQ_ALU_CONST_CACHE_VS_1 = 0x28984, // SAME
- EG_SQ_ALU_CONST_CACHE_VS_2 = 0x28988, // SAME
- EG_SQ_ALU_CONST_CACHE_VS_3 = 0x2898C, // SAME
- EG_SQ_ALU_CONST_CACHE_VS_4 = 0x28990, // SAME
- EG_SQ_ALU_CONST_CACHE_VS_5 = 0x28994, // SAME
- EG_SQ_ALU_CONST_CACHE_VS_6 = 0x28998, // SAME
- EG_SQ_ALU_CONST_CACHE_VS_7 = 0x2899C, // SAME
- EG_SQ_ALU_CONST_CACHE_VS_8 = 0x289A0, // SAME
- EG_SQ_ALU_CONST_CACHE_VS_9 = 0x289A4, // SAME
- EG_SQ_ALU_CONST_CACHE_VS_10 = 0x289A8, // SAME
- EG_SQ_ALU_CONST_CACHE_VS_11 = 0x289AC, // SAME
- EG_SQ_ALU_CONST_CACHE_VS_12 = 0x289B0, // SAME
- EG_SQ_ALU_CONST_CACHE_VS_13 = 0x289B4, // SAME
- EG_SQ_ALU_CONST_CACHE_VS_14 = 0x289B8, // SAME
- EG_SQ_ALU_CONST_CACHE_VS_15 = 0x289BC, // SAME
- EG_SQ_ALU_CONST_CACHE_GS_0 = 0x289C0, // SAME
- EG_SQ_ALU_CONST_CACHE_GS_1 = 0x289C4, // SAME
- EG_SQ_ALU_CONST_CACHE_GS_2 = 0x289C8, // SAME
- EG_SQ_ALU_CONST_CACHE_GS_3 = 0x289CC, // SAME
- EG_SQ_ALU_CONST_CACHE_GS_4 = 0x289D0, // SAME
- EG_SQ_ALU_CONST_CACHE_GS_5 = 0x289D4, // SAME
- EG_SQ_ALU_CONST_CACHE_GS_6 = 0x289D8, // SAME
- EG_SQ_ALU_CONST_CACHE_GS_7 = 0x289DC, // SAME
- EG_SQ_ALU_CONST_CACHE_GS_8 = 0x289E0, // SAME
- EG_SQ_ALU_CONST_CACHE_GS_9 = 0x289E4, // SAME
- EG_SQ_ALU_CONST_CACHE_GS_10 = 0x289E8, // SAME
- EG_SQ_ALU_CONST_CACHE_GS_11 = 0x289EC, // SAME
- EG_SQ_ALU_CONST_CACHE_GS_12 = 0x289F0, // SAME
- EG_SQ_ALU_CONST_CACHE_GS_13 = 0x289F4, // SAME
- EG_SQ_ALU_CONST_CACHE_GS_14 = 0x289F8, // SAME
- EG_SQ_ALU_CONST_CACHE_GS_15 = 0x289FC, // SAME
- EG_SQ_ALU_CONST_CACHE_HS_0 = 0x28F00, //
- EG_SQ_ALU_CONST_CACHE_HS_1 = 0x28F04, //
- EG_SQ_ALU_CONST_CACHE_HS_2 = 0x28F08, //
- EG_SQ_ALU_CONST_CACHE_HS_3 = 0x28F0C, //
- EG_SQ_ALU_CONST_CACHE_HS_4 = 0x28F10, //
- EG_SQ_ALU_CONST_CACHE_HS_5 = 0x28F14, //
- EG_SQ_ALU_CONST_CACHE_HS_6 = 0x28F18, //
- EG_SQ_ALU_CONST_CACHE_HS_7 = 0x28F1C, //
- EG_SQ_ALU_CONST_CACHE_HS_8 = 0x28F20, //
- EG_SQ_ALU_CONST_CACHE_HS_9 = 0x28F24, //
- EG_SQ_ALU_CONST_CACHE_HS_10 = 0x28F28, //
- EG_SQ_ALU_CONST_CACHE_HS_11 = 0x28F2C, //
- EG_SQ_ALU_CONST_CACHE_HS_12 = 0x28F30, //
- EG_SQ_ALU_CONST_CACHE_HS_13 = 0x28F34, //
- EG_SQ_ALU_CONST_CACHE_HS_14 = 0x28F38, //
- EG_SQ_ALU_CONST_CACHE_HS_15 = 0x28F3C, //
- EG_SQ_ALU_CONST_CACHE_LS_0 = 0x28F40, //
- EG_SQ_ALU_CONST_CACHE_LS_1 = 0x28F44, //
- EG_SQ_ALU_CONST_CACHE_LS_2 = 0x28F48, //
- EG_SQ_ALU_CONST_CACHE_LS_3 = 0x28F4C, //
- EG_SQ_ALU_CONST_CACHE_LS_4 = 0x28F50, //
- EG_SQ_ALU_CONST_CACHE_LS_5 = 0x28F54, //
- EG_SQ_ALU_CONST_CACHE_LS_6 = 0x28F58, //
- EG_SQ_ALU_CONST_CACHE_LS_7 = 0x28F5C, //
- EG_SQ_ALU_CONST_CACHE_LS_8 = 0x28F60, //
- EG_SQ_ALU_CONST_CACHE_LS_9 = 0x28F64, //
- EG_SQ_ALU_CONST_CACHE_LS_10 = 0x28F68, //
- EG_SQ_ALU_CONST_CACHE_LS_11 = 0x28F6C, //
- EG_SQ_ALU_CONST_CACHE_LS_12 = 0x28F70, //
- EG_SQ_ALU_CONST_CACHE_LS_13 = 0x28F74, //
- EG_SQ_ALU_CONST_CACHE_LS_14 = 0x28F78, //
- EG_SQ_ALU_CONST_CACHE_LS_15 = 0x28F7C, //
- EG_SQ_ALU_CONST_BUFFER_SIZE_PS_0 = 0x28140,
- EG_SQ_ALU_CONST_BUFFER_SIZE_HS_0 = 0x28F80, //
- EG_SQ_ALU_CONST_BUFFER_SIZE_HS_1 = 0x28F84, //
- EG_SQ_ALU_CONST_BUFFER_SIZE_HS_2 = 0x28F88, //
- EG_SQ_ALU_CONST_BUFFER_SIZE_HS_3 = 0x28F8C, //
- EG_SQ_ALU_CONST_BUFFER_SIZE_HS_4 = 0x28F90, //
- EG_SQ_ALU_CONST_BUFFER_SIZE_HS_5 = 0x28F94, //
- EG_SQ_ALU_CONST_BUFFER_SIZE_HS_6 = 0x28F98, //
- EG_SQ_ALU_CONST_BUFFER_SIZE_HS_7 = 0x28F9C, //
- EG_SQ_ALU_CONST_BUFFER_SIZE_HS_8 = 0x28FA0, //
- EG_SQ_ALU_CONST_BUFFER_SIZE_HS_9 = 0x28FA4, //
- EG_SQ_ALU_CONST_BUFFER_SIZE_HS_10 = 0x28FA8, //
- EG_SQ_ALU_CONST_BUFFER_SIZE_HS_11 = 0x28FAC, //
- EG_SQ_ALU_CONST_BUFFER_SIZE_HS_12 = 0x28FB0, //
- EG_SQ_ALU_CONST_BUFFER_SIZE_HS_13 = 0x28FB4, //
- EG_SQ_ALU_CONST_BUFFER_SIZE_HS_14 = 0x28FB8, //
- EG_SQ_ALU_CONST_BUFFER_SIZE_HS_15 = 0x28FBC, //
- EG_SQ_ALU_CONST_BUFFER_SIZE_LS_0 = 0x28FC0, //
- EG_SQ_ALU_CONST_BUFFER_SIZE_LS_1 = 0x28FC4, //
- EG_SQ_ALU_CONST_BUFFER_SIZE_LS_2 = 0x28FC8, //
- EG_SQ_ALU_CONST_BUFFER_SIZE_LS_3 = 0x28FCC, //
- EG_SQ_ALU_CONST_BUFFER_SIZE_LS_4 = 0x28FD0, //
- EG_SQ_ALU_CONST_BUFFER_SIZE_LS_5 = 0x28FD4, //
- EG_SQ_ALU_CONST_BUFFER_SIZE_LS_6 = 0x28FD8, //
- EG_SQ_ALU_CONST_BUFFER_SIZE_LS_7 = 0x28FDC, //
- EG_SQ_ALU_CONST_BUFFER_SIZE_LS_8 = 0x28FE0, //
- EG_SQ_ALU_CONST_BUFFER_SIZE_LS_9 = 0x28FE4, //
- EG_SQ_ALU_CONST_BUFFER_SIZE_LS_10 = 0x28FE8, //
- EG_SQ_ALU_CONST_BUFFER_SIZE_LS_11 = 0x28FEC, //
- EG_SQ_ALU_CONST_BUFFER_SIZE_LS_12 = 0x28FF0, //
- EG_SQ_ALU_CONST_BUFFER_SIZE_LS_13 = 0x28FF4, //
- EG_SQ_ALU_CONST_BUFFER_SIZE_LS_14 = 0x28FF8, //
- EG_SQ_ALU_CONST_BUFFER_SIZE_LS_15 = 0x28FFC, //
-
-/* Registers from SPI block: */
- EG_SPI_VS_OUT_ID_0 = 0x2861C, // SAME 0x28614
- EG_SPI_VS_OUT_ID_1 = 0x28620, // SAME 0x28618
- EG_SPI_VS_OUT_ID_2 = 0x28624, // SAME 0x2861C
- EG_SPI_VS_OUT_ID_3 = 0x28628, // SAME 0x28620
- EG_SPI_VS_OUT_ID_4 = 0x2862C, // SAME 0x28624
- EG_SPI_VS_OUT_ID_5 = 0x28630, // SAME 0x28628
- EG_SPI_VS_OUT_ID_6 = 0x28634, // SAME 0x2862C
- EG_SPI_VS_OUT_ID_7 = 0x28638, // SAME 0x28630
- EG_SPI_VS_OUT_ID_8 = 0x2863C, // SAME 0x28634
- EG_SPI_VS_OUT_ID_9 = 0x28640, // SAME 0x28638
- EG_SPI_PS_INPUT_CNTL_0 = 0x28644, // SAME
- EG_SPI_PS_INPUT_CNTL_1 = 0x28648, // SAME
- EG_SPI_PS_INPUT_CNTL_2 = 0x2864C, // SAME
- EG_SPI_PS_INPUT_CNTL_3 = 0x28650, // SAME
- EG_SPI_PS_INPUT_CNTL_4 = 0x28654, // SAME
- EG_SPI_PS_INPUT_CNTL_5 = 0x28658, // SAME
- EG_SPI_PS_INPUT_CNTL_6 = 0x2865C, // SAME
- EG_SPI_PS_INPUT_CNTL_7 = 0x28660, // SAME
- EG_SPI_PS_INPUT_CNTL_8 = 0x28664, // SAME
- EG_SPI_PS_INPUT_CNTL_9 = 0x28668, // SAME
- EG_SPI_PS_INPUT_CNTL_10 = 0x2866C, // SAME
- EG_SPI_PS_INPUT_CNTL_11 = 0x28670, // SAME
- EG_SPI_PS_INPUT_CNTL_12 = 0x28674, // SAME
- EG_SPI_PS_INPUT_CNTL_13 = 0x28678, // SAME
- EG_SPI_PS_INPUT_CNTL_14 = 0x2867C, // SAME
- EG_SPI_PS_INPUT_CNTL_15 = 0x28680, // SAME
- EG_SPI_PS_INPUT_CNTL_16 = 0x28684, // SAME
- EG_SPI_PS_INPUT_CNTL_17 = 0x28688, // SAME
- EG_SPI_PS_INPUT_CNTL_18 = 0x2868C, // SAME
- EG_SPI_PS_INPUT_CNTL_19 = 0x28690, // SAME
- EG_SPI_PS_INPUT_CNTL_20 = 0x28694, // SAME
- EG_SPI_PS_INPUT_CNTL_21 = 0x28698, // SAME
- EG_SPI_PS_INPUT_CNTL_22 = 0x2869C, // SAME
- EG_SPI_PS_INPUT_CNTL_23 = 0x286A0, // SAME
- EG_SPI_PS_INPUT_CNTL_24 = 0x286A4, // SAME
- EG_SPI_PS_INPUT_CNTL_25 = 0x286A8, // SAME
- EG_SPI_PS_INPUT_CNTL_26 = 0x286AC, // SAME
- EG_SPI_PS_INPUT_CNTL_27 = 0x286B0, // SAME
- EG_SPI_PS_INPUT_CNTL_28 = 0x286B4, // SAME
- EG_SPI_PS_INPUT_CNTL_29 = 0x286B8, // SAME
- EG_SPI_PS_INPUT_CNTL_30 = 0x286BC, // SAME
- EG_SPI_PS_INPUT_CNTL_31 = 0x286C0, // SAME
- EG_SPI_VS_OUT_CONFIG = 0x286C4, // SAME
- EG_SPI_THREAD_GROUPING = 0x286C8, // DIFF
- EG_SPI_PS_IN_CONTROL_0 = 0x286CC, // SAME
- EG_SPI_PS_IN_CONTROL_1 = 0x286D0, // SAME
- EG_SPI_INTERP_CONTROL_0 = 0x286D4, // SAME
- EG_SPI_INPUT_Z = 0x286D8, // SAME
- EG_SPI_FOG_CNTL = 0x286DC, // SAME
- EG_SPI_BARYC_CNTL = 0x286E0, //
- EG_SPI_PS_IN_CONTROL_2 = 0x286E4, //
- EG_SPI_COMPUTE_INPUT_CNTL = 0x286E8, //
- EG_SPI_COMPUTE_NUM_THREAD_X = 0x286EC, //
- EG_SPI_COMPUTE_NUM_THREAD_Y = 0x286F0, //
- EG_SPI_COMPUTE_NUM_THREAD_Z = 0x286F4, //
-
-/* Registers from SX block: */
- EG_SX_MISC = 0x28350, // SAME
- EG_SX_SURFACE_SYNC = 0x28354, // DIFF
- EG_SX_ALPHA_TEST_CONTROL = 0x28410, // SAME
- EG_SX_ALPHA_REF = 0x28438, // SAME
-
-/* Registers from DB block: */
- EG_DB_RENDER_CONTROL = 0x28000, // DIFF 0x28D0C
- EG_DB_COUNT_CONTROL = 0x28004, //
- EG_DB_DEPTH_VIEW = 0x28008, // DIFF 0x28004
- EG_DB_RENDER_OVERRIDE = 0x2800C, // DIFF 0x28D10
- EG_DB_RENDER_OVERRIDE2 = 0x28010, //
- EG_DB_HTILE_DATA_BASE = 0x28014, // SAME
-
- EG_DB_STENCIL_CLEAR = 0x28028, // SAME
- EG_DB_DEPTH_CLEAR = 0x2802C, // SAME
-
- EG_DB_Z_INFO = 0x28040, //
- EG_DB_STENCIL_INFO = 0x28044, //
- EG_DB_Z_READ_BASE = 0x28048, //
- EG_DB_STENCIL_READ_BASE = 0x2804C, //
- EG_DB_Z_WRITE_BASE = 0x28050, //
- EG_DB_STENCIL_WRITE_BASE = 0x28054, //
- EG_DB_DEPTH_SIZE = 0x28058, // DIFF 0x28000
- EG_DB_DEPTH_SLICE = 0x2805C, //
-
- EG_DB_STENCILREFMASK = 0x28430, // SAME
- EG_DB_STENCILREFMASK_BF = 0x28434, // SAME
- EG_DB_DEPTH_CONTROL = 0x28800, // SAME
- EG_DB_SHADER_CONTROL = 0x2880C, // DIFF
- EG_DB_HTILE_SURFACE = 0x28ABC, // SAME 0x28D24
- EG_DB_SRESULTS_COMPARE_STATE0 = 0x28AC0, // SAME 0x28D28
- EG_DB_SRESULTS_COMPARE_STATE1 = 0x28AC4, // SAME 0x28D2C
- EG_DB_PRELOAD_CONTROL = 0x28AC8, // SAME 0x28D30
- EG_DB_ALPHA_TO_MASK = 0x28B70, // SAME 0x28D44
-
-/* Registers from CB block: */
- EG_CB_TARGET_MASK = 0x28238, // SAME
- EG_CB_SHADER_MASK = 0x2823C, // SAME
- EG_CB_BLEND_RED = 0x28414, // SAME
- EG_CB_BLEND_GREEN = 0x28418, // SAME
- EG_CB_BLEND_BLUE = 0x2841C, // SAME
- EG_CB_BLEND_ALPHA = 0x28420, // SAME
- EG_CB_BLEND0_CONTROL = 0x28780, // DIFF
- EG_CB_BLEND1_CONTROL = 0x28784, // DIFF
- EG_CB_BLEND2_CONTROL = 0x28788, // DIFF
- EG_CB_BLEND3_CONTROL = 0x2878C, // DIFF
- EG_CB_BLEND4_CONTROL = 0x28790, // DIFF
- EG_CB_BLEND5_CONTROL = 0x28794, // DIFF
- EG_CB_BLEND6_CONTROL = 0x28798, // DIFF
- EG_CB_BLEND7_CONTROL = 0x2879C, // DIFF
- EG_CB_COLOR_CONTROL = 0x28808, // DIFF
- EG_CB_IMMED0_BASE = 0x28B9C, //
- EG_CB_IMMED1_BASE = 0x28BA0, //
- EG_CB_IMMED2_BASE = 0x28BA4, //
- EG_CB_IMMED3_BASE = 0x28BA8, //
- EG_CB_IMMED4_BASE = 0x28BAC, //
- EG_CB_IMMED5_BASE = 0x28BB0, //
- EG_CB_IMMED6_BASE = 0x28BB4, //
- EG_CB_IMMED7_BASE = 0x28BB8, //
- EG_CB_IMMED8_BASE = 0x28BBC, //
- EG_CB_IMMED9_BASE = 0x28BC0, //
- EG_CB_IMMED10_BASE = 0x28BC4, //
- EG_CB_IMMED11_BASE = 0x28BC8, //
- EG_CB_CLRCMP_CONTROL = 0x28C40, // SAME 0x28C30
- EG_CB_CLRCMP_SRC = 0x28C44, // SAME 0x28C34
- EG_CB_CLRCMP_DST = 0x28C48, // SAME 0x28C38
- EG_CB_CLRCMP_MSK = 0x28C4C, // SAME 0x28C3C
- EG_CB_COLOR0_BASE = 0x28C60, // SAME 0x28040
- EG_CB_COLOR0_PITCH = 0x28C64, //
- EG_CB_COLOR0_SLICE = 0x28C68, //
- EG_CB_COLOR0_VIEW = 0x28C6C, // SAME 0x28080
- EG_CB_COLOR0_INFO = 0x28C70, // DIFF 0x280A0
- EG_CB_COLOR0_ATTRIB = 0x28C74, //
- EG_CB_COLOR0_DIM = 0x28C78, //
- EG_CB_COLOR0_CMASK = 0x28C7C, //
- EG_CB_COLOR0_CMASK_SLICE = 0x28C80, //
- EG_CB_COLOR0_FMASK = 0x28C84, //
- EG_CB_COLOR0_FMASK_SLICE = 0x28C88, //
- EG_CB_COLOR0_CLEAR_WORD0 = 0x28C8C, //
- EG_CB_COLOR0_CLEAR_WORD1 = 0x28C90, //
- EG_CB_COLOR0_CLEAR_WORD2 = 0x28C94, //
- EG_CB_COLOR0_CLEAR_WORD3 = 0x28C98, //
- EG_CB_COLOR1_BASE = 0x28C9C, // SAME 0x28044
- EG_CB_COLOR1_PITCH = 0x28CA0, //
- EG_CB_COLOR1_SLICE = 0x28CA4, //
- EG_CB_COLOR1_VIEW = 0x28CA8, // SAME 0x28084
- EG_CB_COLOR1_INFO = 0x28CAC, // DIFF 0x280A4
- EG_CB_COLOR1_ATTRIB = 0x28CB0, //
- EG_CB_COLOR1_DIM = 0x28CB4, //
- EG_CB_COLOR1_CMASK = 0x28CB8, //
- EG_CB_COLOR1_CMASK_SLICE = 0x28CBC, //
- EG_CB_COLOR1_FMASK = 0x28CC0, //
- EG_CB_COLOR1_FMASK_SLICE = 0x28CC4, //
- EG_CB_COLOR1_CLEAR_WORD0 = 0x28CC8, //
- EG_CB_COLOR1_CLEAR_WORD1 = 0x28CCC, //
- EG_CB_COLOR1_CLEAR_WORD2 = 0x28CD0, //
- EG_CB_COLOR1_CLEAR_WORD3 = 0x28CD4, //
- EG_CB_COLOR2_BASE = 0x28CD8, // SAME 0x28048
- EG_CB_COLOR2_PITCH = 0x28CDC, //
- EG_CB_COLOR2_SLICE = 0x28CE0, //
- EG_CB_COLOR2_VIEW = 0x28CE4, // SAME 0x28088
- EG_CB_COLOR2_INFO = 0x28CE8, // DIFF 0x280A8
- EG_CB_COLOR2_ATTRIB = 0x28CEC, //
- EG_CB_COLOR2_DIM = 0x28CF0, //
- EG_CB_COLOR2_CMASK = 0x28CF4, //
- EG_CB_COLOR2_CMASK_SLICE = 0x28CF8, //
- EG_CB_COLOR2_FMASK = 0x28CFC, //
- EG_CB_COLOR2_FMASK_SLICE = 0x28D00, //
- EG_CB_COLOR2_CLEAR_WORD0 = 0x28D04, //
- EG_CB_COLOR2_CLEAR_WORD1 = 0x28D08, //
- EG_CB_COLOR2_CLEAR_WORD2 = 0x28D0C, //
- EG_CB_COLOR2_CLEAR_WORD3 = 0x28D10, //
- EG_CB_COLOR3_BASE = 0x28D14, // SAME 0x2804C
- EG_CB_COLOR3_PITCH = 0x28D18, //
- EG_CB_COLOR3_SLICE = 0x28D1C, //
- EG_CB_COLOR3_VIEW = 0x28D20, // SAME 0x2808C
- EG_CB_COLOR3_INFO = 0x28D24, // DIFF 0x280AC
- EG_CB_COLOR3_ATTRIB = 0x28D28, //
- EG_CB_COLOR3_DIM = 0x28D2C, //
- EG_CB_COLOR3_CMASK = 0x28D30, //
- EG_CB_COLOR3_CMASK_SLICE = 0x28D34, //
- EG_CB_COLOR3_FMASK = 0x28D38, //
- EG_CB_COLOR3_FMASK_SLICE = 0x28D3C, //
- EG_CB_COLOR3_CLEAR_WORD0 = 0x28D40, //
- EG_CB_COLOR3_CLEAR_WORD1 = 0x28D44, //
- EG_CB_COLOR3_CLEAR_WORD2 = 0x28D48, //
- EG_CB_COLOR3_CLEAR_WORD3 = 0x28D4C, //
- EG_CB_COLOR4_BASE = 0x28D50, // SAME 0x28050
- EG_CB_COLOR4_PITCH = 0x28D54, //
- EG_CB_COLOR4_SLICE = 0x28D58, //
- EG_CB_COLOR4_VIEW = 0x28D5C, // SAME 0x28090
- EG_CB_COLOR4_INFO = 0x28D60, // DIFF 0x280B0
- EG_CB_COLOR4_ATTRIB = 0x28D64, //
- EG_CB_COLOR4_DIM = 0x28D68, //
- EG_CB_COLOR4_CMASK = 0x28D6C, //
- EG_CB_COLOR4_CMASK_SLICE = 0x28D70, //
- EG_CB_COLOR4_FMASK = 0x28D74, //
- EG_CB_COLOR4_FMASK_SLICE = 0x28D78, //
- EG_CB_COLOR4_CLEAR_WORD0 = 0x28D7C, //
- EG_CB_COLOR4_CLEAR_WORD1 = 0x28D80, //
- EG_CB_COLOR4_CLEAR_WORD2 = 0x28D84, //
- EG_CB_COLOR4_CLEAR_WORD3 = 0x28D88, //
- EG_CB_COLOR5_BASE = 0x28D8C, // SAME 0x28054
- EG_CB_COLOR5_PITCH = 0x28D90, //
- EG_CB_COLOR5_SLICE = 0x28D94, //
- EG_CB_COLOR5_VIEW = 0x28D98, // SAME 0x28094
- EG_CB_COLOR5_INFO = 0x28D9C, // DIFF 0x280B4
- EG_CB_COLOR5_ATTRIB = 0x28DA0, //
- EG_CB_COLOR5_DIM = 0x28DA4, //
- EG_CB_COLOR5_CMASK = 0x28DA8, //
- EG_CB_COLOR5_CMASK_SLICE = 0x28DAC, //
- EG_CB_COLOR5_FMASK = 0x28DB0, //
- EG_CB_COLOR5_FMASK_SLICE = 0x28DB4, //
- EG_CB_COLOR5_CLEAR_WORD0 = 0x28DB8, //
- EG_CB_COLOR5_CLEAR_WORD1 = 0x28DBC, //
- EG_CB_COLOR5_CLEAR_WORD2 = 0x28DC0, //
- EG_CB_COLOR5_CLEAR_WORD3 = 0x28DC4, //
- EG_CB_COLOR6_BASE = 0x28DC8, // SAME 0x28058
- EG_CB_COLOR6_PITCH = 0x28DCC, //
- EG_CB_COLOR6_SLICE = 0x28DD0, //
- EG_CB_COLOR6_VIEW = 0x28DD4, // SAME 0x28098
- EG_CB_COLOR6_INFO = 0x28DD8, // DIFF 0x280B8
- EG_CB_COLOR6_ATTRIB = 0x28DDC, //
- EG_CB_COLOR6_DIM = 0x28DE0, //
- EG_CB_COLOR6_CMASK = 0x28DE4, //
- EG_CB_COLOR6_CMASK_SLICE = 0x28DE8, //
- EG_CB_COLOR6_FMASK = 0x28DEC, //
- EG_CB_COLOR6_FMASK_SLICE = 0x28DF0, //
- EG_CB_COLOR6_CLEAR_WORD0 = 0x28DF4, //
- EG_CB_COLOR6_CLEAR_WORD1 = 0x28DF8, //
- EG_CB_COLOR6_CLEAR_WORD2 = 0x28DFC, //
- EG_CB_COLOR6_CLEAR_WORD3 = 0x28E00, //
- EG_CB_COLOR7_BASE = 0x28E04, // SAME 0x2805C
- EG_CB_COLOR7_PITCH = 0x28E08, //
- EG_CB_COLOR7_SLICE = 0x28E0C, //
- EG_CB_COLOR7_VIEW = 0x28E10, // SAME 0x2809C
- EG_CB_COLOR7_INFO = 0x28E14, // DIFF 0x280BC
- EG_CB_COLOR7_ATTRIB = 0x28E18, //
- EG_CB_COLOR7_DIM = 0x28E1C, //
- EG_CB_COLOR7_CMASK = 0x28E20, //
- EG_CB_COLOR7_CMASK_SLICE = 0x28E24, //
- EG_CB_COLOR7_FMASK = 0x28E28, //
- EG_CB_COLOR7_FMASK_SLICE = 0x28E2C, //
- EG_CB_COLOR7_CLEAR_WORD0 = 0x28E30, //
- EG_CB_COLOR7_CLEAR_WORD1 = 0x28E34, //
- EG_CB_COLOR7_CLEAR_WORD2 = 0x28E38, //
- EG_CB_COLOR7_CLEAR_WORD3 = 0x28E3C, //
- EG_CB_COLOR8_BASE = 0x28E40, //
- EG_CB_COLOR8_PITCH = 0x28E44, //
- EG_CB_COLOR8_SLICE = 0x28E48, //
- EG_CB_COLOR8_VIEW = 0x28E4C, //
- EG_CB_COLOR8_INFO = 0x28E50, //
- EG_CB_COLOR8_ATTRIB = 0x28E54, //
- EG_CB_COLOR8_DIM = 0x28E58, //
- EG_CB_COLOR9_BASE = 0x28E5C, //
- EG_CB_COLOR9_PITCH = 0x28E60, //
- EG_CB_COLOR9_SLICE = 0x28E64, //
- EG_CB_COLOR9_VIEW = 0x28E68, //
- EG_CB_COLOR9_INFO = 0x28E6C, //
- EG_CB_COLOR9_ATTRIB = 0x28E70, //
- EG_CB_COLOR9_DIM = 0x28E74, //
- EG_CB_COLOR10_BASE = 0x28E78, //
- EG_CB_COLOR10_PITCH = 0x28E7C, //
- EG_CB_COLOR10_SLICE = 0x28E80, //
- EG_CB_COLOR10_VIEW = 0x28E84, //
- EG_CB_COLOR10_INFO = 0x28E88, //
- EG_CB_COLOR10_ATTRIB = 0x28E8C, //
- EG_CB_COLOR10_DIM = 0x28E90, //
- EG_CB_COLOR11_BASE = 0x28E94, //
- EG_CB_COLOR11_PITCH = 0x28E98, //
- EG_CB_COLOR11_SLICE = 0x28E9C, //
- EG_CB_COLOR11_VIEW = 0x28EA0, //
- EG_CB_COLOR11_INFO = 0x28EA4, //
- EG_CB_COLOR11_ATTRIB = 0x28EA8, //
- EG_CB_COLOR11_DIM = 0x28EAC, //
-
-/* Registers from CP block: */
- EG_COHER_DEST_BASE_0 = 0x28248, // SAME
- EG_COHER_DEST_BASE_1 = 0x2824C, // SAME
- EG_CP_PERFMON_CNTX_CNTL = 0x28358, //
-
-/* Config: */
- EG_SPI_CONFIG_CNTL = 0x9100, // DIFF
- EG_SPI_CONFIG_CNTL_1 = 0x913C, // DIFF
- EG_CP_PERFMON_CNTL = 0x87FC, // SAME
- EG_SQ_MS_FIFO_SIZES = 0x8CF0, // SAME
- EG_SQ_CONFIG = 0x8C00, // DIFF
- EG_SQ_GPR_RESOURCE_MGMT_1 = 0x8C04, // SAME
- EG_SQ_GPR_RESOURCE_MGMT_2 = 0x8C08, // SAME
- EG_SQ_THREAD_RESOURCE_MGMT = 0x8C18, // SAME 0x8C0C,
- EG_SQ_STACK_RESOURCE_MGMT_1 = 0x8C20, // SAME 0x8C10,
- EG_SQ_STACK_RESOURCE_MGMT_2 = 0x8C24, // SAME 0x8C14,
- EG_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ = 0x8D8C, // DIFF
- EG_SQ_LDS_RESOURCE_MGMT = 0x8E2C, //
- EG_SQ_GPR_RESOURCE_MGMT_3 = 0x8C0C, //
- EG_SQ_STACK_RESOURCE_MGMT_3 = 0x8C28, //
- EG_SQ_THREAD_RESOURCE_MGMT_2 = 0x8C1C, //
- EG_VGT_CACHE_INVALIDATION = 0x88C4, // DIFF
- EG_VGT_GS_VERTEX_REUSE = 0x88D4, // SAME
- EG_PA_SC_FORCE_EOV_MAX_CNTS = 0x8B24, // SAME
- EG_PA_SC_LINE_STIPPLE_STATE = 0x8B10, // SAME
- EG_PA_CL_ENHANCE = 0x8A14, // SAME
-
-/* Tex border color */
- EG_TD_PS_BORDER_COLOR_RED = 0xA404,
- EG_TD_PS_BORDER_COLOR_GREEN = 0xA408,
- EG_TD_PS_BORDER_COLOR_BLUE = 0xA40C,
- EG_TD_PS_BORDER_COLOR_ALPHA = 0xA410,
-
-/* const */
- EG_SQ_VTX_CONSTANT_WORD0_0 = 0x30000, // 0x38000
-};
-
-#endif /* _EVERGREEN_OFF_H_ */
\ No newline at end of file
+++ /dev/null
-/*
- * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Authors:
- * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
- */
-
-#include <string.h>
-
-#include "main/glheader.h"
-#include "main/imports.h"
-#include "program/program.h"
-
-#include "tnl/tnl.h"
-
-#include "r600_context.h"
-#include "r600_emit.h"
-
-#include "evergreen_oglprog.h"
-#include "evergreen_fragprog.h"
-#include "evergreen_vertprog.h"
-
-
-static void evergreen_freeVertProgCache(struct gl_context *ctx, struct r700_vertex_program_cont *cache)
-{
- struct evergreen_vertex_program *tmp, *vp = (struct evergreen_vertex_program *) cache->progs;
-
- while (vp) {
- tmp = vp->next;
- /* Release DMA region */
- r600DeleteShader(ctx, vp->shaderbo);
-
- if(NULL != vp->constbo0)
- {
- r600DeleteShader(ctx, vp->constbo0);
- }
-
- /* Clean up */
- Clean_Up_Assembler(&(vp->r700AsmCode));
- Clean_Up_Shader(&(vp->r700Shader));
-
- _mesa_reference_vertprog(ctx, &vp->mesa_program, NULL);
- free(vp);
- vp = tmp;
- }
-}
-
-static struct gl_program *evergreenNewProgram(struct gl_context * ctx,
- GLenum target,
- GLuint id)
-{
- struct gl_program *pProgram = NULL;
-
- struct evergreen_vertex_program_cont *vpc;
- struct evergreen_fragment_program *fp;
-
- radeon_print(RADEON_SHADER, RADEON_VERBOSE,
- "%s %u, %u\n", __func__, target, id);
-
- switch (target)
- {
- case GL_VERTEX_STATE_PROGRAM_NV:
- case GL_VERTEX_PROGRAM_ARB:
- vpc = CALLOC_STRUCT(evergreen_vertex_program_cont);
- pProgram = _mesa_init_vertex_program(ctx,
- &vpc->mesa_program,
- target,
- id);
-
- break;
- case GL_FRAGMENT_PROGRAM_NV:
- case GL_FRAGMENT_PROGRAM_ARB:
- fp = CALLOC_STRUCT(evergreen_fragment_program);
- pProgram = _mesa_init_fragment_program(ctx,
- &fp->mesa_program,
- target,
- id);
- fp->translated = GL_FALSE;
- fp->loaded = GL_FALSE;
-
- fp->shaderbo = NULL;
-
- fp->constbo0 = NULL;
-
- break;
- default:
- _mesa_problem(ctx, "Bad target in evergreenNewProgram");
- }
-
- return pProgram;
-}
-
-static void evergreenDeleteProgram(struct gl_context * ctx, struct gl_program *prog)
-{
- struct evergreen_vertex_program_cont *vpc = (struct evergreen_vertex_program_cont *)prog;
- struct evergreen_fragment_program * fp;
-
- radeon_print(RADEON_SHADER, RADEON_VERBOSE,
- "%s %p\n", __func__, prog);
-
- switch (prog->Target)
- {
- case GL_VERTEX_STATE_PROGRAM_NV:
- case GL_VERTEX_PROGRAM_ARB:
- evergreen_freeVertProgCache(ctx, (struct r700_vertex_program_cont *) vpc);
- break;
- case GL_FRAGMENT_PROGRAM_NV:
- case GL_FRAGMENT_PROGRAM_ARB:
- fp = (struct evergreen_fragment_program*)prog;
- /* Release DMA region */
-
- r600DeleteShader(ctx, fp->shaderbo);
-
- if(NULL != fp->constbo0)
- {
- r600DeleteShader(ctx, fp->constbo0);
- }
-
- /* Clean up */
- Clean_Up_Assembler(&(fp->r700AsmCode));
- Clean_Up_Shader(&(fp->r700Shader));
- break;
- default:
- _mesa_problem(ctx, "Bad target in evergreenNewProgram");
- }
-
- _mesa_delete_program(ctx, prog);
-}
-
-static GLboolean
-evergreenProgramStringNotify(struct gl_context * ctx, GLenum target, struct gl_program *prog)
-{
- struct evergreen_vertex_program_cont *vpc = (struct evergreen_vertex_program_cont *)prog;
- struct evergreen_fragment_program * fp = (struct evergreen_fragment_program*)prog;
-
- switch (target) {
- case GL_VERTEX_PROGRAM_ARB:
- evergreen_freeVertProgCache(ctx, (struct r700_vertex_program_cont *) vpc);
- vpc->progs = NULL;
- break;
- case GL_FRAGMENT_PROGRAM_ARB:
- r600DeleteShader(ctx, fp->shaderbo);
-
- if(NULL != fp->constbo0)
- {
- r600DeleteShader(ctx, fp->constbo0);
- fp->constbo0 = NULL;
- }
-
- Clean_Up_Assembler(&(fp->r700AsmCode));
- Clean_Up_Shader(&(fp->r700Shader));
- fp->translated = GL_FALSE;
- fp->loaded = GL_FALSE;
- fp->shaderbo = NULL;
- break;
- }
-
- /* XXX check if program is legal, within limits */
- return GL_TRUE;
-}
-
-static GLboolean evergreenIsProgramNative(struct gl_context * ctx, GLenum target, struct gl_program *prog)
-{
-
- return GL_TRUE;
-}
-
-void evergreenInitShaderFuncs(struct dd_function_table *functions)
-{
- functions->NewProgram = evergreenNewProgram;
- functions->DeleteProgram = evergreenDeleteProgram;
- functions->ProgramStringNotify = evergreenProgramStringNotify;
- functions->IsProgramNative = evergreenIsProgramNative;
-}
+++ /dev/null
-/*
- * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Authors:
- * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
- */
-
-#ifndef _EVERGREEN_OGLPROG_H_
-#define _EVERGREEN_OGLPROG_H_
-#include "r600_context.h"
-
-extern void evergreenInitShaderFuncs(struct dd_function_table *functions);
-
-#endif /*_EVERGREEN_OGLPROG_H_*/
+++ /dev/null
-/*
- * Copyright (C) 2008-2010 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Authors:
- * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
- */
-
-#include "main/glheader.h"
-#include "main/state.h"
-#include "main/imports.h"
-#include "main/enums.h"
-#include "main/macros.h"
-#include "main/context.h"
-#include "main/dd.h"
-#include "main/simple_list.h"
-#include "main/api_arrayelt.h"
-#include "swrast/swrast.h"
-#include "swrast_setup/swrast_setup.h"
-#include "vbo/vbo.h"
-
-#include "tnl/tnl.h"
-#include "tnl/t_vp_build.h"
-#include "tnl/t_context.h"
-#include "tnl/t_vertex.h"
-#include "vbo/vbo_context.h"
-
-#include "r600_context.h"
-#include "r600_cmdbuf.h"
-
-#include "evergreen_fragprog.h"
-#include "evergreen_vertprog.h"
-
-#include "evergreen_state.h"
-#include "evergreen_tex.h"
-
-#include "radeon_buffer_objects.h"
-#include "radeon_common_context.h"
-
-static unsigned int evergreenPrimitiveType(int prim) //same
-{
- switch (prim & PRIM_MODE_MASK)
- {
- case GL_POINTS:
- return DI_PT_POINTLIST;
- break;
- case GL_LINES:
- return DI_PT_LINELIST;
- break;
- case GL_LINE_STRIP:
- return DI_PT_LINESTRIP;
- break;
- case GL_LINE_LOOP:
- return DI_PT_LINELOOP;
- break;
- case GL_TRIANGLES:
- return DI_PT_TRILIST;
- break;
- case GL_TRIANGLE_STRIP:
- return DI_PT_TRISTRIP;
- break;
- case GL_TRIANGLE_FAN:
- return DI_PT_TRIFAN;
- break;
- case GL_QUADS:
- return DI_PT_QUADLIST;
- break;
- case GL_QUAD_STRIP:
- return DI_PT_QUADSTRIP;
- break;
- case GL_POLYGON:
- return DI_PT_POLYGON;
- break;
- default:
- assert(0);
- return -1;
- break;
- }
-}
-
-static int evergreenNumVerts(int num_verts, int prim) //same
-{
- int verts_off = 0;
-
- switch (prim & PRIM_MODE_MASK) {
- case GL_POINTS:
- verts_off = 0;
- break;
- case GL_LINES:
- verts_off = num_verts % 2;
- break;
- case GL_LINE_STRIP:
- if (num_verts < 2)
- verts_off = num_verts;
- break;
- case GL_LINE_LOOP:
- if (num_verts < 2)
- verts_off = num_verts;
- break;
- case GL_TRIANGLES:
- verts_off = num_verts % 3;
- break;
- case GL_TRIANGLE_STRIP:
- if (num_verts < 3)
- verts_off = num_verts;
- break;
- case GL_TRIANGLE_FAN:
- if (num_verts < 3)
- verts_off = num_verts;
- break;
- case GL_QUADS:
- verts_off = num_verts % 4;
- break;
- case GL_QUAD_STRIP:
- if (num_verts < 4)
- verts_off = num_verts;
- else
- verts_off = num_verts % 2;
- break;
- case GL_POLYGON:
- if (num_verts < 3)
- verts_off = num_verts;
- break;
- default:
- assert(0);
- return -1;
- break;
- }
-
- return num_verts - verts_off;
-}
-
-static void evergreenRunRenderPrimitive(struct gl_context * ctx, int start, int end, int prim,
- GLint basevertex) //same
-{
- context_t *context = EVERGREEN_CONTEXT(ctx);
- BATCH_LOCALS(&context->radeon);
- int type, total_emit;
- int num_indices;
- uint32_t vgt_draw_initiator = 0;
- uint32_t vgt_index_type = 0;
- uint32_t vgt_primitive_type = 0;
- uint32_t vgt_num_indices = 0;
-
- type = evergreenPrimitiveType(prim);
- num_indices = evergreenNumVerts(end - start, prim);
-
- radeon_print(RADEON_RENDER, RADEON_TRACE,
- "%s type %x num_indices %d\n",
- __func__, type, num_indices);
-
- if (type < 0 || num_indices <= 0)
- return;
-
- SETfield(vgt_primitive_type, type,
- VGT_PRIMITIVE_TYPE__PRIM_TYPE_shift, VGT_PRIMITIVE_TYPE__PRIM_TYPE_mask);
-
- SETfield(vgt_index_type, DI_INDEX_SIZE_32_BIT, INDEX_TYPE_shift, INDEX_TYPE_mask);
-
- if(GL_TRUE != context->ind_buf.is_32bit)
- {
- SETfield(vgt_index_type, DI_INDEX_SIZE_16_BIT, INDEX_TYPE_shift, INDEX_TYPE_mask);
- }
-
- /* 16-bit indexes are packed in a 32-bit value */
- SETfield(vgt_index_type,
-#if MESA_BIG_ENDIAN
- VGT_DMA_SWAP_32_BIT,
-#else
- VGT_DMA_SWAP_NONE,
-#endif
- SWAP_MODE_shift, SWAP_MODE_mask);
-
- vgt_num_indices = num_indices;
- SETfield(vgt_draw_initiator, DI_SRC_SEL_DMA, SOURCE_SELECT_shift, SOURCE_SELECT_mask);
- SETfield(vgt_draw_initiator, DI_MAJOR_MODE_0, MAJOR_MODE_shift, MAJOR_MODE_mask);
-
- total_emit = 3 /* VGT_PRIMITIVE_TYPE */
- + 2 /* VGT_INDEX_TYPE */
- + 2 /* NUM_INSTANCES */
- + 4 /* VTX_BASE_VTX_LOC + VTX_START_INST_LOC */
- + 5 + 2; /* DRAW_INDEX */
-
- BEGIN_BATCH_NO_AUTOSTATE(total_emit);
- // prim
- R600_OUT_BATCH_REGSEQ(VGT_PRIMITIVE_TYPE, 1);
- R600_OUT_BATCH(vgt_primitive_type);
- // index type
- R600_OUT_BATCH(CP_PACKET3(R600_IT_INDEX_TYPE, 0));
- R600_OUT_BATCH(vgt_index_type);
- // num instances
- R600_OUT_BATCH(CP_PACKET3(R600_IT_NUM_INSTANCES, 0));
- R600_OUT_BATCH(1);
- /* offset */
- R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 2));
- R600_OUT_BATCH(mmSQ_VTX_BASE_VTX_LOC - ASIC_CTL_CONST_BASE_INDEX);
- R600_OUT_BATCH(basevertex); //VTX_BASE_VTX_LOC
- R600_OUT_BATCH(0); //VTX_START_INST_LOC
- // draw packet
- R600_OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX, 3));
- R600_OUT_BATCH(context->ind_buf.bo_offset);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(vgt_num_indices);
- R600_OUT_BATCH(vgt_draw_initiator);
- R600_OUT_BATCH_RELOC(context->ind_buf.bo_offset,
- context->ind_buf.bo,
- context->ind_buf.bo_offset,
- RADEON_GEM_DOMAIN_GTT, 0, 0);
- END_BATCH();
- COMMIT_BATCH();
-}
-
-static void evergreenRunRenderPrimitiveImmediate(struct gl_context * ctx, int start, int end, int prim) //same
-{
- context_t *context = EVERGREEN_CONTEXT(ctx);
- BATCH_LOCALS(&context->radeon);
- int type, i;
- uint32_t num_indices, total_emit = 0;
- uint32_t vgt_draw_initiator = 0;
- uint32_t vgt_index_type = 0;
- uint32_t vgt_primitive_type = 0;
- uint32_t vgt_num_indices = 0;
-
- type = evergreenPrimitiveType(prim);
- num_indices = evergreenNumVerts(end - start, prim);
-
- radeon_print(RADEON_RENDER, RADEON_TRACE,
- "%s type %x num_indices %d\n",
- __func__, type, num_indices);
-
- if (type < 0 || num_indices <= 0)
- return;
-
- SETfield(vgt_primitive_type, type,
- VGT_PRIMITIVE_TYPE__PRIM_TYPE_shift, VGT_PRIMITIVE_TYPE__PRIM_TYPE_mask);
-
- if (num_indices > 0xffff)
- {
- SETfield(vgt_index_type, DI_INDEX_SIZE_32_BIT, INDEX_TYPE_shift, INDEX_TYPE_mask);
- }
- else
- {
- SETfield(vgt_index_type, DI_INDEX_SIZE_16_BIT, INDEX_TYPE_shift, INDEX_TYPE_mask);
- }
-
- /* 16-bit indexes are packed in a 32-bit value */
- SETfield(vgt_index_type,
-#if MESA_BIG_ENDIAN
- VGT_DMA_SWAP_32_BIT,
-#else
- VGT_DMA_SWAP_NONE,
-#endif
- SWAP_MODE_shift, SWAP_MODE_mask);
-
- vgt_num_indices = num_indices;
- SETfield(vgt_draw_initiator, DI_MAJOR_MODE_0, MAJOR_MODE_shift, MAJOR_MODE_mask);
-
- if (start == 0)
- {
- SETfield(vgt_draw_initiator, DI_SRC_SEL_AUTO_INDEX, SOURCE_SELECT_shift, SOURCE_SELECT_mask);
- }
- else
- {
- if (num_indices > 0xffff)
- {
- total_emit += num_indices;
- }
- else
- {
- total_emit += (num_indices + 1) / 2;
- }
- SETfield(vgt_draw_initiator, DI_SRC_SEL_IMMEDIATE, SOURCE_SELECT_shift, SOURCE_SELECT_mask);
- }
-
- total_emit += 3 /* VGT_PRIMITIVE_TYPE */
- + 2 /* VGT_INDEX_TYPE */
- + 2 /* NUM_INSTANCES */
- + 4 /* VTX_BASE_VTX_LOC + VTX_START_INST_LOC */
- + 3; /* DRAW */
-
- BEGIN_BATCH_NO_AUTOSTATE(total_emit);
- // prim
- R600_OUT_BATCH_REGSEQ(VGT_PRIMITIVE_TYPE, 1);
- R600_OUT_BATCH(vgt_primitive_type);
- // index type
- R600_OUT_BATCH(CP_PACKET3(R600_IT_INDEX_TYPE, 0));
- R600_OUT_BATCH(vgt_index_type);
- // num instances
- R600_OUT_BATCH(CP_PACKET3(R600_IT_NUM_INSTANCES, 0));
- R600_OUT_BATCH(1);
- /* offset */
- R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 2));
- R600_OUT_BATCH(mmSQ_VTX_BASE_VTX_LOC - ASIC_CTL_CONST_BASE_INDEX);
- R600_OUT_BATCH(0); //VTX_BASE_VTX_LOC
- R600_OUT_BATCH(0); //VTX_START_INST_LOC
- // draw packet
- if(start == 0)
- {
- R600_OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX_AUTO, 1));
- R600_OUT_BATCH(vgt_num_indices);
- R600_OUT_BATCH(vgt_draw_initiator);
- }
- else
- {
- if (num_indices > 0xffff)
- {
- R600_OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX_IMMD, (num_indices + 1)));
- R600_OUT_BATCH(vgt_num_indices);
- R600_OUT_BATCH(vgt_draw_initiator);
- for (i = start; i < (start + num_indices); i++)
- {
- R600_OUT_BATCH(i);
- }
- }
- else
- {
- R600_OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX_IMMD, (((num_indices + 1) / 2) + 1)));
- R600_OUT_BATCH(vgt_num_indices);
- R600_OUT_BATCH(vgt_draw_initiator);
- for (i = start; i < (start + num_indices); i += 2)
- {
- if ((i + 1) == (start + num_indices))
- {
- R600_OUT_BATCH(i);
- }
- else
- {
- R600_OUT_BATCH(((i + 1) << 16) | (i));
- }
- }
- }
- }
-
- END_BATCH();
- COMMIT_BATCH();
-}
-
-#define CONVERT( TYPE, MACRO ) do { \
- GLuint i, j, sz; \
- sz = input->Size; \
- if (input->Normalized) { \
- for (i = 0; i < count; i++) { \
- const TYPE *in = (TYPE *)src_ptr; \
- for (j = 0; j < sz; j++) { \
- *dst_ptr++ = MACRO(*in); \
- in++; \
- } \
- src_ptr += stride; \
- } \
- } else { \
- for (i = 0; i < count; i++) { \
- const TYPE *in = (TYPE *)src_ptr; \
- for (j = 0; j < sz; j++) { \
- *dst_ptr++ = (GLfloat)(*in); \
- in++; \
- } \
- src_ptr += stride; \
- } \
- } \
-} while (0)
-
-/**
- * Convert attribute data type to float
- * If the attribute uses named buffer object replace the bo with newly allocated bo
- */
-static void evergreenConvertAttrib(struct gl_context *ctx, int count,
- const struct gl_client_array *input,
- struct StreamDesc *attr)
-{
- context_t *context = R700_CONTEXT(ctx);
- const GLvoid *src_ptr;
- GLboolean mapped_named_bo = GL_FALSE;
- GLfloat *dst_ptr;
- GLuint stride;
-
- stride = (input->StrideB == 0) ? evergreen_getTypeSize(input->Type) * input->Size : input->StrideB;
-
- /* Convert value for first element only */
- if (input->StrideB == 0)
- {
- count = 1;
- }
-
- if (input->BufferObj->Name)
- {
- if (!input->BufferObj->Pointer)
- {
- ctx->Driver.MapBufferRange(ctx, 0, input->BufferObj->Size,
- GL_MAP_READ_BIT, input->BufferObj);
- mapped_named_bo = GL_TRUE;
- }
-
- src_ptr = ADD_POINTERS(input->BufferObj->Pointer, input->Ptr);
- }
- else
- {
- src_ptr = input->Ptr;
- }
-
- radeonAllocDmaRegion(&context->radeon, &attr->bo, &attr->bo_offset,
- sizeof(GLfloat) * input->Size * count, 32);
-
- radeon_bo_map(attr->bo, 1);
-
- dst_ptr = (GLfloat *)ADD_POINTERS(attr->bo->ptr, attr->bo_offset);
-
- assert(src_ptr != NULL);
-
- switch (input->Type)
- {
- case GL_DOUBLE:
- CONVERT(GLdouble, (GLfloat));
- break;
- case GL_UNSIGNED_INT:
- CONVERT(GLuint, UINT_TO_FLOAT);
- break;
- case GL_INT:
- CONVERT(GLint, INT_TO_FLOAT);
- break;
- case GL_UNSIGNED_SHORT:
- CONVERT(GLushort, USHORT_TO_FLOAT);
- break;
- case GL_SHORT:
- CONVERT(GLshort, SHORT_TO_FLOAT);
- break;
- case GL_UNSIGNED_BYTE:
- assert(input->Format != GL_BGRA);
- CONVERT(GLubyte, UBYTE_TO_FLOAT);
- break;
- case GL_BYTE:
- CONVERT(GLbyte, BYTE_TO_FLOAT);
- break;
- default:
- assert(0);
- break;
- }
-
- radeon_bo_unmap(attr->bo);
-
- if (mapped_named_bo)
- {
- ctx->Driver.UnmapBuffer(ctx, input->BufferObj);
- }
-}
-
-static void evergreenFixupIndexBuffer(struct gl_context *ctx, const struct _mesa_index_buffer *mesa_ind_buf)
-{
- context_t *context = EVERGREEN_CONTEXT(ctx);
- GLvoid *src_ptr;
- GLuint *out;
- int i;
- GLboolean mapped_named_bo = GL_FALSE;
-
- if (mesa_ind_buf->obj->Name && !mesa_ind_buf->obj->Pointer)
- {
- ctx->Driver.MapBufferRange(ctx, 0, mesa_ind_buf->obj->Size,
- GL_MAP_READ_BIT, mesa_ind_buf->obj);
- mapped_named_bo = GL_TRUE;
- assert(mesa_ind_buf->obj->Pointer != NULL);
- }
- src_ptr = ADD_POINTERS(mesa_ind_buf->obj->Pointer, mesa_ind_buf->ptr);
-
- if (mesa_ind_buf->type == GL_UNSIGNED_BYTE)
- {
- GLuint size = sizeof(GLushort) * ((mesa_ind_buf->count + 1) & ~1);
- GLubyte *in = (GLubyte *)src_ptr;
-
- radeonAllocDmaRegion(&context->radeon, &context->ind_buf.bo,
- &context->ind_buf.bo_offset, size, 4);
-
- radeon_bo_map(context->ind_buf.bo, 1);
- assert(context->ind_buf.bo->ptr != NULL);
- out = (GLuint *)ADD_POINTERS(context->ind_buf.bo->ptr, context->ind_buf.bo_offset);
-
- for (i = 0; i + 1 < mesa_ind_buf->count; i += 2)
- {
- *out++ = in[i] | in[i + 1] << 16;
- }
-
- if (i < mesa_ind_buf->count)
- {
- *out++ = in[i];
- }
-
- radeon_bo_unmap(context->ind_buf.bo);
-#if MESA_BIG_ENDIAN
- }
- else
- { /* if (mesa_ind_buf->type == GL_UNSIGNED_SHORT) */
- GLushort *in = (GLushort *)src_ptr;
- GLuint size = sizeof(GLushort) * ((mesa_ind_buf->count + 1) & ~1);
-
- radeonAllocDmaRegion(&context->radeon, &context->ind_buf.bo,
- &context->ind_buf.bo_offset, size, 4);
-
- radeon_bo_map(context->ind_buf.bo, 1);
- assert(context->ind_buf.bo->ptr != NULL);
- out = (GLuint *)ADD_POINTERS(context->ind_buf.bo->ptr, context->ind_buf.bo_offset);
-
- for (i = 0; i + 1 < mesa_ind_buf->count; i += 2)
- {
- *out++ = in[i] | in[i + 1] << 16;
- }
-
- if (i < mesa_ind_buf->count)
- {
- *out++ = in[i];
- }
- radeon_bo_unmap(context->ind_buf.bo);
-#endif
- }
-
- context->ind_buf.is_32bit = GL_FALSE;
- context->ind_buf.count = mesa_ind_buf->count;
-
- if (mapped_named_bo)
- {
- ctx->Driver.UnmapBuffer(ctx, mesa_ind_buf->obj);
- }
-}
-
-static GLboolean evergreen_check_fallbacks(struct gl_context *ctx) //same
-{
- if (ctx->RenderMode != GL_RENDER)
- return GL_TRUE;
-
- return GL_FALSE;
-}
-
-/* start 3d, idle, cb/db flush */
-#define PRE_EMIT_STATE_BUFSZ 5 + 5 + 14
-
-static GLuint evergreenPredictRenderSize(struct gl_context* ctx,
- const struct _mesa_prim *prim,
- const struct _mesa_index_buffer *ib,
- GLuint nr_prims)
-{
- context_t *context = EVERGREEN_CONTEXT(ctx);
- GLboolean flushed;
- GLuint dwords, i;
- GLuint state_size;
-
- dwords = PRE_EMIT_STATE_BUFSZ;
- if (ib)
- dwords += nr_prims * 18;
- else {
- for (i = 0; i < nr_prims; ++i)
- {
- if (prim[i].start == 0)
- dwords += 14;
- else if (prim[i].count > 0xffff)
- dwords += prim[i].count + 14;
- else
- dwords += ((prim[i].count + 1) / 2) + 14;
- }
- }
-
- state_size = radeonCountStateEmitSize(&context->radeon);
- flushed = rcommonEnsureCmdBufSpace(&context->radeon,
- dwords + state_size,
- __FUNCTION__);
- if (flushed)
- dwords += radeonCountStateEmitSize(&context->radeon);
- else
- dwords += state_size;
-
- radeon_print(RADEON_RENDER, RADEON_VERBOSE, "%s: total prediction size is %d.\n", __FUNCTION__, dwords);
- return dwords;
-
-}
-
-static void evergreenSetupIndexBuffer(struct gl_context *ctx, const struct _mesa_index_buffer *mesa_ind_buf)
-{
- context_t *context = EVERGREEN_CONTEXT(ctx);
-
- if (!mesa_ind_buf) {
- context->ind_buf.bo = NULL;
- return;
- }
-
-#if MESA_BIG_ENDIAN
- if (mesa_ind_buf->type == GL_UNSIGNED_INT)
-#else
- if (mesa_ind_buf->type != GL_UNSIGNED_BYTE)
-#endif
- {
- const GLvoid *src_ptr;
- GLvoid *dst_ptr;
- GLboolean mapped_named_bo = GL_FALSE;
-
- if (mesa_ind_buf->obj->Name && !mesa_ind_buf->obj->Pointer)
- {
- ctx->Driver.MapBufferRange(ctx, 0, mesa_ind_buf->obj->Size,
- GL_MAP_READ_BIT, mesa_ind_buf->obj);
- assert(mesa_ind_buf->obj->Pointer != NULL);
- mapped_named_bo = GL_TRUE;
- }
-
- src_ptr = ADD_POINTERS(mesa_ind_buf->obj->Pointer, mesa_ind_buf->ptr);
-
- const GLuint size = mesa_ind_buf->count * getTypeSize(mesa_ind_buf->type);
-
- radeonAllocDmaRegion(&context->radeon, &context->ind_buf.bo,
- &context->ind_buf.bo_offset, size, 4);
- radeon_bo_map(context->ind_buf.bo, 1);
- assert(context->ind_buf.bo->ptr != NULL);
- dst_ptr = ADD_POINTERS(context->ind_buf.bo->ptr, context->ind_buf.bo_offset);
-
- memcpy(dst_ptr, src_ptr, size);
-
- radeon_bo_unmap(context->ind_buf.bo);
- context->ind_buf.is_32bit = (mesa_ind_buf->type == GL_UNSIGNED_INT);
- context->ind_buf.count = mesa_ind_buf->count;
-
- if (mapped_named_bo)
- {
- ctx->Driver.UnmapBuffer(ctx, mesa_ind_buf->obj);
- }
- }
- else
- {
- evergreenFixupIndexBuffer(ctx, mesa_ind_buf);
- }
-}
-
-#if 0 /* unused */
-static void evergreenAlignDataToDword(struct gl_context *ctx,
- const struct gl_client_array *input,
- int count,
- struct StreamDesc *attr)
-{
- context_t *context = EVERGREEN_CONTEXT(ctx);
- const int dst_stride = (input->StrideB + 3) & ~3;
- const int size = getTypeSize(input->Type) * input->Size * count;
- GLboolean mapped_named_bo = GL_FALSE;
-
- radeonAllocDmaRegion(&context->radeon, &attr->bo, &attr->bo_offset, size, 32);
-
- radeon_bo_map(attr->bo, 1);
-
- if (!input->BufferObj->Pointer)
- {
- ctx->Driver.MapBufferRange(ctx, 0, input->BufferObj->Size,
- GL_MAP_READ_BIT, input->BufferObj->obj);
- mapped_named_bo = GL_TRUE;
- }
-
- {
- GLvoid *src_ptr = ADD_POINTERS(input->BufferObj->Pointer, input->Ptr);
- GLvoid *dst_ptr = ADD_POINTERS(attr->bo->ptr, attr->bo_offset);
- int i;
-
- for (i = 0; i < count; ++i)
- {
- memcpy(dst_ptr, src_ptr, input->StrideB);
- src_ptr += input->StrideB;
- dst_ptr += dst_stride;
- }
- }
-
- radeon_bo_unmap(attr->bo);
- if (mapped_named_bo)
- {
- ctx->Driver.UnmapBuffer(ctx, input->BufferObj);
- }
-
- attr->stride = dst_stride;
-}
-#endif
-
-static void evergreenSetupStreams(struct gl_context *ctx, const struct gl_client_array *input[], int count)
-{
- context_t *context = EVERGREEN_CONTEXT(ctx);
- GLuint stride;
- int ret;
- int i, index;
-
- EVERGREEN_STATECHANGE(context, vtx);
-
- for(index = 0; index < context->nNumActiveAos; index++)
- {
- struct radeon_aos *aos = &context->radeon.tcl.aos[index];
- i = context->stream_desc[index].element;
-
- stride = (input[i]->StrideB == 0) ? getTypeSize(input[i]->Type) * input[i]->Size : input[i]->StrideB;
-
- if (input[i]->Type == GL_DOUBLE || input[i]->Type == GL_UNSIGNED_INT || input[i]->Type == GL_INT
-#if MESA_BIG_ENDIAN
- || getTypeSize(input[i]->Type) != 4
-#endif
- )
- {
- evergreenConvertAttrib(ctx, count, input[i], &context->stream_desc[index]);
- }
- else
- {
- if (input[i]->BufferObj->Name)
- {
- context->stream_desc[index].stride = input[i]->StrideB;
- context->stream_desc[index].bo_offset = (intptr_t) input[i]->Ptr;
- context->stream_desc[index].bo = get_radeon_buffer_object(input[i]->BufferObj)->bo;
- context->stream_desc[index].is_named_bo = GL_TRUE;
- }
- else
- {
- int size;
- int local_count = count;
- uint32_t *dst;
-
- if (input[i]->StrideB == 0)
- {
- size = getTypeSize(input[i]->Type) * input[i]->Size;
- local_count = 1;
- }
- else
- {
- size = getTypeSize(input[i]->Type) * input[i]->Size * local_count;
- }
-
- radeonAllocDmaRegion(&context->radeon, &context->stream_desc[index].bo,
- &context->stream_desc[index].bo_offset, size, 32);
-
- radeon_bo_map(context->stream_desc[index].bo, 1);
- assert(context->stream_desc[index].bo->ptr != NULL);
-
-
- dst = (uint32_t *)ADD_POINTERS(context->stream_desc[index].bo->ptr,
- context->stream_desc[index].bo_offset);
-
- switch (context->stream_desc[index].dwords)
- {
- case 1:
- radeonEmitVec4(dst, input[i]->Ptr, input[i]->StrideB, local_count);
- break;
- case 2:
- radeonEmitVec8(dst, input[i]->Ptr, input[i]->StrideB, local_count);
- break;
- case 3:
- radeonEmitVec12(dst, input[i]->Ptr, input[i]->StrideB, local_count);
- break;
- case 4:
- radeonEmitVec16(dst, input[i]->Ptr, input[i]->StrideB, local_count);
- break;
- default:
- assert(0);
- break;
- }
-
- radeon_bo_unmap(context->stream_desc[index].bo);
- }
- }
-
- aos->count = context->stream_desc[index].stride == 0 ? 1 : count;
- aos->stride = context->stream_desc[index].stride / sizeof(float);
- aos->components = context->stream_desc[index].dwords;
- aos->bo = context->stream_desc[index].bo;
- aos->offset = context->stream_desc[index].bo_offset;
-
- if(context->stream_desc[index].is_named_bo)
- {
- radeon_cs_space_add_persistent_bo(context->radeon.cmdbuf.cs,
- context->stream_desc[index].bo,
- RADEON_GEM_DOMAIN_GTT, 0);
- }
- }
-
- ret = radeon_cs_space_check_with_bo(context->radeon.cmdbuf.cs,
- first_elem(&context->radeon.dma.reserved)->bo,
- RADEON_GEM_DOMAIN_GTT, 0);
-}
-
-static void evergreenFreeData(struct gl_context *ctx)
-{
- /* Need to zero tcl.aos[n].bo and tcl.elt_dma_bo
- * to prevent double unref in radeonReleaseArrays
- * called during context destroy
- */
- context_t *context = EVERGREEN_CONTEXT(ctx);
-
- int i;
-
- for (i = 0; i < context->nNumActiveAos; i++)
- {
- if (!context->stream_desc[i].is_named_bo)
- {
- radeon_bo_unref(context->stream_desc[i].bo);
- }
- context->radeon.tcl.aos[i].bo = NULL;
- }
-
- if(context->vp_Constbo != NULL)
- {
- radeon_bo_unref(context->vp_Constbo);
- context->vp_Constbo = NULL;
- }
- if(context->fp_Constbo != NULL)
- {
- radeon_bo_unref(context->fp_Constbo);
- context->fp_Constbo = NULL;
- }
-
- if (context->ind_buf.bo != NULL)
- {
- radeon_bo_unref(context->ind_buf.bo);
- }
-}
-
-static GLboolean evergreenTryDrawPrims(struct gl_context *ctx,
- const struct gl_client_array *arrays[],
- const struct _mesa_prim *prim,
- GLuint nr_prims,
- const struct _mesa_index_buffer *ib,
- GLuint min_index,
- GLuint max_index )
-{
- context_t *context = EVERGREEN_CONTEXT(ctx);
- radeonContextPtr radeon = &context->radeon;
- GLuint i, id = 0;
- struct radeon_renderbuffer *rrb;
-
- if (ctx->NewState)
- _mesa_update_state( ctx );
-
- if (evergreen_check_fallbacks(ctx))
- return GL_FALSE;
-
- _tnl_UpdateFixedFunctionProgram(ctx);
- evergreenSetVertexFormat(ctx, arrays, max_index + 1);
-
-
- /* shaders need to be updated before buffers are validated */
- evergreenUpdateShaders(ctx);
- if (!evergreenValidateBuffers(ctx))
- return GL_FALSE;
-
- /* always emit CB base to prevent
- * lock ups on some chips.
- */
- EVERGREEN_STATECHANGE(context, cb);
- /* mark vtx as dirty since it changes per-draw */
- EVERGREEN_STATECHANGE(context, vtx);
-
- evergreenSetScissor(context);
-
- evergreenSetupVertexProgram(ctx);
- evergreenSetupFragmentProgram(ctx);
- evergreenUpdateShaderStates(ctx);
-
- GLuint emit_end = evergreenPredictRenderSize(ctx, prim, ib, nr_prims)
- + context->radeon.cmdbuf.cs->cdw;
-
- /* evergreenPredictRenderSize will call radeonReleaseDmaRegions, so update VP/FP const buf after it. */
- evergreenSetupVPconstants(ctx);
- evergreenSetupFPconstants(ctx);
-
- evergreenSetupIndexBuffer(ctx, ib);
-
- evergreenSetupStreams(ctx, arrays, max_index + 1);
-
- radeonEmitState(radeon);
-
- radeon_debug_add_indent();
-
- for (i = 0; i < nr_prims; ++i)
- {
- if (context->ind_buf.bo)
- evergreenRunRenderPrimitive(ctx,
- prim[i].start,
- prim[i].start + prim[i].count,
- prim[i].mode,
- prim[i].basevertex);
- else
- evergreenRunRenderPrimitiveImmediate(ctx,
- prim[i].start,
- prim[i].start + prim[i].count,
- prim[i].mode);
- }
-
- radeon_debug_remove_indent();
-
- /* Flush render op cached for last several quads. */
- /* XXX drm should handle this in fence submit */
-
- //evergreeWaitForIdleClean(context);
-
- rrb = radeon_get_colorbuffer(&context->radeon);
- if (rrb && rrb->bo)
- r700SyncSurf(context, rrb->bo, 0, RADEON_GEM_DOMAIN_VRAM,
- CB_ACTION_ENA_bit | (1 << (id + 6)));
-
- rrb = radeon_get_depthbuffer(&context->radeon);
- if (rrb && rrb->bo)
- r700SyncSurf(context, rrb->bo, 0, RADEON_GEM_DOMAIN_VRAM,
- DB_ACTION_ENA_bit | DB_DEST_BASE_ENA_bit);
-
- evergreenFreeData(ctx);
-
- if (emit_end < context->radeon.cmdbuf.cs->cdw)
- {
- WARN_ONCE("Rendering was %d commands larger than predicted size."
- " We might overflow command buffer.\n", context->radeon.cmdbuf.cs->cdw - emit_end);
- }
-
- return GL_TRUE;
-}
-
-static void evergreenDrawPrims(struct gl_context *ctx,
- const struct gl_client_array *arrays[],
- const struct _mesa_prim *prim,
- GLuint nr_prims,
- const struct _mesa_index_buffer *ib,
- GLboolean index_bounds_valid,
- GLuint min_index,
- GLuint max_index)
-{
- GLboolean retval = GL_FALSE;
-
- context_t *context = EVERGREEN_CONTEXT(ctx);
- radeonContextPtr radeon = &context->radeon;
- radeon_prepare_render(radeon);
-
- /* This check should get folded into just the places that
- * min/max index are really needed.
- */
- if (!vbo_all_varyings_in_vbos(arrays)) {
- if (!index_bounds_valid)
- vbo_get_minmax_index(ctx, prim, ib, &min_index, &max_index);
- /* do we want to rebase, minimizes the
- * amount of data to upload? */
- if (min_index) {
- vbo_rebase_prims( ctx, arrays, prim, nr_prims, ib, min_index, max_index, evergreenDrawPrims );
- return;
- }
- }
- /* Make an attempt at drawing */
- retval = evergreenTryDrawPrims(ctx, arrays, prim, nr_prims, ib, min_index, max_index);
-
- /* If failed run tnl pipeline - it should take care of fallbacks */
- if (!retval) {
- _swsetup_Wakeup(ctx);
- _tnl_draw_prims(ctx, arrays, prim, nr_prims, ib, min_index, max_index);
- }
-}
-
-void evergreenInitDraw(struct gl_context *ctx)
-{
- struct vbo_context *vbo = vbo_context(ctx);
-
- /* to be enabled */
- vbo->draw_prims = evergreenDrawPrims;
-}
-
-
+++ /dev/null
-/*
- * Copyright (C) 2008-2010 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Authors:
- * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
- */
-
-#ifndef _EVERGREEN_SQ_H_
-#define _EVERGREEN_SQ_H_
-
-enum{
-//CF
- EG_CF_WORD0__ADDR_shift = 0,
- EG_CF_WORD0__ADDR_mask = 0xFFFFFF,
- EG_CF_WORD0__JUMPTABLE_SEL_shift = 24,
- EG_CF_WORD0__JUMPTABLE_SEL_mask = 0x7 << 24,
-
- EG_CF_WORD1__POP_COUNT_shift = 0, //3 bits
- EG_CF_WORD1__POP_COUNT_mask = 0x7,
- EG_CF_WORD1__CF_CONST_shift = 3, //5 bits
- EG_CF_WORD1__CF_CONST_mask = 0x1F << 3,
- EG_CF_WORD1__COND_shift = 8, //2 bits
- EG_CF_WORD1__COND_mask = 0x3 << 8,
- EG_CF_WORD1__COUNT_shift = 10,//6 bits
- EG_CF_WORD1__COUNT_mask = 0x3F << 10,
- EG_CF_WORD1__reserved_shift = 16,//4 bits
- EG_CF_WORD1__VPM_shift = 20,//1 bit
- EG_CF_WORD1__VPM_bit = 1 << 20,
- EG_CF_WORD1__EOP_shift = 21,//1 bit
- EG_CF_WORD1__EOP_bit = 1 << 21,
- EG_CF_WORD1__CF_INST_shift = 22,//8 bits
- EG_CF_WORD1__CF_INST_mask = 0xFF << 22,
- EG_CF_WORD1__WQM_shift = 30,//1 bit
- EG_CF_WORD1__WQM_bit = 1 << 30,
- EG_CF_WORD1__BARRIER_shift = 31,//1 bit
- EG_CF_WORD1__BARRIER_bit = 1 << 31,
-
- EG_CF_INST_NOP = 0,
- EG_CF_INST_TC = 1,
- EG_CF_INST_VC = 2,
- EG_CF_INST_GDS = 3,
- EG_CF_INST_LOOP_START = 4,
- EG_CF_INST_LOOP_END = 5,
- EG_CF_INST_LOOP_START_DX10 = 6,
- EG_CF_INST_LOOP_START_NO_AL = 7,
- EG_CF_INST_LOOP_CONTINUE = 8,
- EG_CF_INST_LOOP_BREAK = 9,
- EG_CF_INST_JUMP = 10,
- EG_CF_INST_PUSH = 11,
- EG_CF_INST_Reserved_12 = 12,
- EG_CF_INST_ELSE = 13,
- EG_CF_INST_POP = 14,
- EG_CF_INST_Reserved_15 = 15,
- EG_CF_INST_Reserved_16 = 16,
- EG_CF_INST_Reserved_17 = 17,
- EG_CF_INST_CALL = 18,
- EG_CF_INST_CALL_FS = 19,
- EG_CF_INST_RETURN = 20,
- EG_CF_INST_EMIT_VERTEX = 21,
- EG_CF_INST_EMIT_CUT_VERTEX = 22,
- EG_CF_INST_CUT_VERTEX = 23,
- EG_CF_INST_KILL = 24,
- EG_CF_INST_Reserved_25 = 25,
- EG_CF_INST_WAIT_ACK = 26,
- EG_CF_INST_TC_ACK = 27,
- EG_CF_INST_VC_ACK = 28,
- EG_CF_INST_JUMPTABLE = 29,
- EG_CF_INST_GLOBAL_WAVE_SYNC = 30,
- EG_CF_INST_HALT = 31,
-
-//TEX
- EG_TEX_WORD0__TEX_INST_shift = 0, //5 bits
- EG_TEX_WORD0__TEX_INST_mask = 0x1F,
- EG_TEX_WORD0__INST_MOD_shift = 5, //2 bits
- EG_TEX_WORD0__INST_MOD_mask = 0x3 << 5,
- EG_TEX_WORD0__FWQ_shift = 7, //1 bit
- EG_TEX_WORD0__FWQ_bit = 1 << 7,
- EG_TEX_WORD0__RESOURCE_ID_shift = 8, //8 bits
- EG_TEX_WORD0__RESOURCE_ID_mask = 0xFF << 8,
- EG_TEX_WORD0__SRC_GPR_shift = 16,//7 bits
- EG_TEX_WORD0__SRC_GPR_mask = 0x7F << 16,
- EG_TEX_WORD0__SRC_REL_shift = 23,//1 bit
- EG_TEX_WORD0__SRC_REL_bit = 1 << 23,
- EG_TEX_WORD0__ALT_CONST_shift = 24,//1 bit
- EG_TEX_WORD0__ALT_CONST_bit = 1 << 24,
- EG_TEX_WORD0__RIM_shift = 25,//2 bits
- EG_TEX_WORD0__RIM_mask = 0x3 << 25,
- EG_TEX_WORD0__SIM_shift = 27,//2 bits
- EG_TEX_WORD0__SIM_mask = 0x3 << 27,
- EG_TEX_WORD0__Reserved_shift = 29,//3 bits
- EG_TEX_WORD0__Reserved_mask = 0x7 << 29,
-
- EG_TEX_INST_Reserved_0 = 0,
- EG_TEX_INST_Reserved_1 = 1,
- EG_TEX_INST_Reserved_2 = 2,
- EG_TEX_INST_LD = 3,
- EG_TEX_INST_GET_TEXTURE_RESINFO = 4,
- EG_TEX_INST_GET_NUMBER_OF_SAMPLES= 5,
- EG_TEX_INST_GET_COMP_TEX_LOD = 6,
- EG_TEX_INST_GET_GRADIENTS_H = 7,
- EG_TEX_INST_GET_GRADIENTS_V = 8,
- EG_TEX_INST_SET_TEXTURE_OFFSETS = 9,
- EG_TEX_INST_KEEP_GRADIENTS = 10,
- EG_TEX_INST_SET_GRADIENTS_H = 11,
- EG_TEX_INST_SET_GRADIENTS_V = 12,
- EG_TEX_INST_Reserved_13 = 13,
- EG_TEX_INST_Reserved_14 = 14,
- EG_TEX_INST_Reserved_15 = 15,
- EG_TEX_INST_SAMPLE = 16,
- EG_TEX_INST_SAMPLE_L = 17,
- EG_TEX_INST_SAMPLE_LB = 18,
- EG_TEX_INST_SAMPLE_LZ = 19,
- EG_TEX_INST_SAMPLE_G = 20,
- EG_TEX_INST_GATHER4 = 21,
- EG_TEX_INST_SAMPLE_G_LB = 22,
- EG_TEX_INST_GATHER4_O = 23,
- EG_TEX_INST_SAMPLE_C = 24,
- EG_TEX_INST_SAMPLE_C_L = 25,
- EG_TEX_INST_SAMPLE_C_LB = 26,
- EG_TEX_INST_SAMPLE_C_LZ = 27,
- EG_TEX_INST_SAMPLE_C_G = 28,
- EG_TEX_INST_GATHER4_C = 29,
- EG_TEX_INST_SAMPLE_C_G_LB = 30,
- EG_TEX_INST_GATHER4_C_O = 31,
-
- EG_TEX_WORD1__DST_GPR_shift = 0, //7 bits
- EG_TEX_WORD1__DST_GPR_mask = 0x7F,
- EG_TEX_WORD1__DST_REL_shift = 7, //1 bit
- EG_TEX_WORD1__DST_REL_bit = 1 << 7,
- EG_TEX_WORD1__Reserved_shift = 8, //1 bit
- EG_TEX_WORD1__Reserved_bit = 1 << 8,
- EG_TEX_WORD1__DST_SEL_X_shift = 9, //3 bits
- EG_TEX_WORD1__DST_SEL_X_mask = 0x7 << 9,
- EG_TEX_WORD1__DST_SEL_Y_shift = 12,//3 bits
- EG_TEX_WORD1__DST_SEL_Y_mask = 0x7 << 12,
- EG_TEX_WORD1__DST_SEL_Z_shift = 15,//3 bits
- EG_TEX_WORD1__DST_SEL_Z_mask = 0x7 << 15,
- EG_TEX_WORD1__DST_SEL_W_shift = 18,//3 bits
- EG_TEX_WORD1__DST_SEL_W_mask = 0x7 << 18,
- EG_TEX_WORD1__LOD_BIAS_shift = 21,//7 bits
- EG_TEX_WORD1__LOD_BIAS_mask = 0x7F << 21,
- EG_TEX_WORD1__COORD_TYPE_X_shift = 28,//1 bit
- EG_TEX_WORD1__COORD_TYPE_X_bit = 1 << 28,
- EG_TEX_WORD1__COORD_TYPE_Y_shift = 29,//1 bit
- EG_TEX_WORD1__COORD_TYPE_Y_bit = 1 << 29,
- EG_TEX_WORD1__COORD_TYPE_Z_shift = 30,//1 bit
- EG_TEX_WORD1__COORD_TYPE_Z_bit = 1 << 30,
- EG_TEX_WORD1__COORD_TYPE_W_shift = 31,//1 bit
- EG_TEX_WORD1__COORD_TYPE_W_bit = 1 << 31,
-
- EG_TEX_WORD2__OFFSET_X_shift = 0, //5 bits
- EG_TEX_WORD2__OFFSET_X_mask = 0x1F,
- EG_TEX_WORD2__OFFSET_Y_shift = 5, //5 bits
- EG_TEX_WORD2__OFFSET_Y_mask = 0x1F << 5,
- EG_TEX_WORD2__OFFSET_Z_shift = 10,//5 bits
- EG_TEX_WORD2__OFFSET_Z_mask = 0x1F << 10,
- EG_TEX_WORD2__SAMPLER_ID_shift = 15,//5 bits
- EG_TEX_WORD2__SAMPLER_ID_mask = 0x1F << 15,
- EG_TEX_WORD2__SRC_SEL_X_shift = 20,//3 bits
- EG_TEX_WORD2__SRC_SEL_X_mask = 0x7 << 20,
- EG_TEX_WORD2__SRC_SEL_Y_shift = 23,//3 bits
- EG_TEX_WORD2__SRC_SEL_Y_mask = 0x7 << 23,
- EG_TEX_WORD2__SRC_SEL_Z_shift = 26,//3 bits
- EG_TEX_WORD2__SRC_SEL_Z_mask = 0x7 << 26,
- EG_TEX_WORD2__SRC_SEL_W_shift = 29,//3 bits
- EG_TEX_WORD2__SRC_SEL_W_mask = 0x7 << 29,
-
-//VTX
- EG_VTX_WORD0__VC_INST_shift = 0, //5 bits
- EG_VTX_WORD0__VC_INST_mask = 0x1F,
- EG_VTX_WORD0__FETCH_TYPE_shift = 5, //2 bits
- EG_VTX_WORD0__FETCH_TYPE_mask = 0x3 << 5,
- EG_VTX_WORD0__FWQ_shift = 7, //1 bit
- EG_VTX_WORD0__FWQ_bit = 1 << 7,
- EG_VTX_WORD0__BUFFER_ID_shift = 8, //8 bits
- EG_VTX_WORD0__BUFFER_ID_mask = 0xFF << 8,
- EG_VTX_WORD0__SRC_GPR_shift = 16,//7 bits
- EG_VTX_WORD0__SRC_GPR_mask = 0x7F << 16,
- EG_VTX_WORD0__SRC_REL_shift = 23,//1 bit
- EG_VTX_WORD0__SRC_REL_bit = 1 << 23,
- EG_VTX_WORD0__SRC_SEL_X_shift = 24,//2 bits
- EG_VTX_WORD0__SRC_SEL_X_mask = 0x3 << 24,
- EG_VTX_WORD0__MFC_shift = 26,//6 bits
- EG_VTX_WORD0__MFC_mask = 0x3F << 26,
-
- EG_VC_INST_FETCH = 0,
- EG_VC_INST_SEMANTIC = 1,
- EG_VC_INST_Reserved_2 = 2,
- EG_VC_INST_Reserved_3 = 3,
- EG_VC_INST_Reserved_4 = 4,
- EG_VC_INST_Reserved_5 = 5,
- EG_VC_INST_Reserved_6 = 6,
- EG_VC_INST_Reserved_7 = 7,
- EG_VC_INST_Reserved_8 = 8,
- EG_VC_INST_Reserved_9 = 9,
- EG_VC_INST_Reserved_10 = 10,
- EG_VC_INST_Reserved_11 = 11,
- EG_VC_INST_Reserved_12 = 12,
- EG_VC_INST_Reserved_13 = 13,
- EG_VC_INST_GET_BUFFER_RESINFO = 14,
-
- EG_VTX_FETCH_VERTEX_DATA = 0,
- EG_VTX_FETCH_INSTANCE_DATA = 1,
- EG_VTX_FETCH_NO_INDEX_OFFSET = 2,
-
- EG_VTX_WORD1_SEM__SEMANTIC_ID_shift = 0, //8 bits
- EG_VTX_WORD1_SEM__SEMANTIC_ID_mask = 0xFF,
- EG_VTX_WORD1_GPR__DST_GPR_shift = 0, //7 bits
- EG_VTX_WORD1_GPR__DST_GPR_mask = 0x7F,
- EG_VTX_WORD1_GPR__DST_REL_shift = 7, //1 bit
- EG_VTX_WORD1_GPR__DST_REL_bit = 1 << 7,
- EG_VTX_WORD1__Reserved_shift = 8, //1 bit
- EG_VTX_WORD1__Reserved_bit = 1 << 8,
- EG_VTX_WORD1__DST_SEL_X_shift = 9, //3 bits
- EG_VTX_WORD1__DST_SEL_X_mask = 0x7 << 9,
- EG_VTX_WORD1__DST_SEL_Y_shift = 12,//3 bits
- EG_VTX_WORD1__DST_SEL_Y_mask = 0x7 << 12,
- EG_VTX_WORD1__DST_SEL_Z_shift = 15,//3 bits
- EG_VTX_WORD1__DST_SEL_Z_mask = 0x7 << 15,
- EG_VTX_WORD1__DST_SEL_W_shift = 18,//3 bits
- EG_VTX_WORD1__DST_SEL_W_mask = 0x7 << 18,
- EG_VTX_WORD1__UCF_shift = 21,//1 bit
- EG_VTX_WORD1__UCF_bit = 1 << 21,
- EG_VTX_WORD1__DATA_FORMAT_shift = 22,//6 bits
- EG_VTX_WORD1__DATA_FORMAT_mask = 0x3F << 22,
- EG_VTX_WORD1__NFA_shift = 28,//2 bits
- EG_VTX_WORD1__NFA_mask = 0x3 << 28,
- EG_VTX_WORD1__FCA_shift = 30,//1 bit
- EG_VTX_WORD1__FCA_bit = 1 << 30,
- EG_VTX_WORD1__SMA_shift = 31,//1 bit
- EG_VTX_WORD1__SMA_bit = 1 << 31,
-
- EG_VTX_WORD2__OFFSET_shift = 0, //16 bits
- EG_VTX_WORD2__OFFSET_mask = 0xFFFF,
- EG_VTX_WORD2__ENDIAN_SWAP_shift = 16,//2 bits
- EG_VTX_WORD2__ENDIAN_SWAP_mask = 0x3 << 16,
- EG_VTX_WORD2__CBNS_shift = 18,//1 bit
- EG_VTX_WORD2__CBNS_bit = 1 << 18,
- EG_VTX_WORD2__MEGA_FETCH_shift = 19,//1 bit
- EG_VTX_WORD2__MEGA_FETCH_mask = 1 << 19,
- EG_VTX_WORD2__ALT_CONST_shift = 20,//1 bit
- EG_VTX_WORD2__ALT_CONST_mask = 1 << 20,
- EG_VTX_WORD2__BIM_shift = 21,//2 bits
- EG_VTX_WORD2__BIM_mask = 0x3 << 21,
- EG_VTX_WORD2__Reserved_shift = 23,//9 bits
- EG_VTX_WORD2__Reserved_mask = 0x1FF << 23,
-
-//CF_ALU
- EG_CF_ALU_WORD0__ADDR_shift = 0, //22 bits
- EG_CF_ALU_WORD0__ADDR_mask = 0x3FFFFF,
- EG_CF_ALU_WORD0__KCACHE_BANK0_shift = 22,//4 bits
- EG_CF_ALU_WORD0__KCACHE_BANK0_mask = 0xF << 22,
- EG_CF_ALU_WORD0__KCACHE_BANK1_shift = 26,//4 bits
- EG_CF_ALU_WORD0__KCACHE_BANK1_mask = 0xF << 26,
- EG_CF_ALU_WORD0__KCACHE_MODE0_shift = 30,//2 bits
- EG_CF_ALU_WORD0__KCACHE_MODE0_mask = 0x3 << 30,
-
- EG_CF_ALU_WORD1__KCACHE_MODE1_shift = 0, //2 bits
- EG_CF_ALU_WORD1__KCACHE_MODE1_mask = 0x3,
- EG_CF_ALU_WORD1__KCACHE_ADDR0_shift = 2, //8 bits
- EG_CF_ALU_WORD1__KCACHE_ADDR0_mask = 0xFF << 2,
- EG_CF_ALU_WORD1__KCACHE_ADDR1_shift = 10, //8 bits
- EG_CF_ALU_WORD1__KCACHE_ADDR1_mask = 0xFF << 10,
- EG_CF_ALU_WORD1__COUNT_shift = 18, //7 bits
- EG_CF_ALU_WORD1__COUNT_mask = 0x7F << 18,
- EG_CF_ALU_WORD1__ALT_CONST_shift = 25, //1 bit
- EG_CF_ALU_WORD1__ALT_CONST_bit = 1 << 25,
- EG_CF_ALU_WORD1__CF_INST_shift = 26, //4 bits
- EG_CF_ALU_WORD1__CF_INST_mask = 0xF << 26,
- EG_CF_ALU_WORD1__WQM_shift = 30, //1 bit
- EG_CF_ALU_WORD1__WQM_bit = 1 << 30,
- EG_CF_ALU_WORD1__BARRIER_shift = 31, //1 bit
- EG_CF_ALU_WORD1__BARRIER_bit = 1 << 31,
-
- EG_CF_INST_ALU = 8,
- EG_CF_INST_ALU_PUSH_BEFORE = 9,
- EG_CF_INST_ALU_POP_AFTER = 10,
- EG_CF_INST_ALU_POP2_AFTER = 11,
- EG_CF_INST_ALU_EXTENDED = 12,
- EG_CF_INST_ALU_CONTINUE = 13,
- EG_CF_INST_ALU_BREAK = 14,
- EG_CF_INST_ALU_ELSE_AFTER = 15,
-
- EG_CF_ALU_WORD0_EXT__Reserved0_shift = 0, //4 bits
- EG_CF_ALU_WORD0_EXT__Reserved0_mask = 0xF,
- EG_CF_ALU_WORD0_EXT__KBIM0_shift = 4, //2 bits
- EG_CF_ALU_WORD0_EXT__KBIM0_mask = 0x3 << 4,
- EG_CF_ALU_WORD0_EXT__KBIM1_shift = 6, //2 bits
- EG_CF_ALU_WORD0_EXT__KBIM1_mask = 0x3 << 6,
- EG_CF_ALU_WORD0_EXT__KBIM2_shift = 8, //2 bits
- EG_CF_ALU_WORD0_EXT__KBIM2_mask = 0x3 << 8,
- EG_CF_ALU_WORD0_EXT__KBIM3_shift = 10,//2 bits
- EG_CF_ALU_WORD0_EXT__KBIM3_mask = 0x3 << 10,
- EG_CF_ALU_WORD0_EXT__Reserved12_shift = 12,//10 bits
- EG_CF_ALU_WORD0_EXT__Reserved12_mask = 0x3FF << 12,
- EG_CF_ALU_WORD0_EXT__KCACHE_BANK2_shift = 22,//4 bits
- EG_CF_ALU_WORD0_EXT__KCACHE_BANK2_mask = 0xF << 22,
- EG_CF_ALU_WORD0_EXT__KCACHE_BANK3_shift = 26,//4 bits
- EG_CF_ALU_WORD0_EXT__KCACHE_BANK3_mask = 0xF << 26,
- EG_CF_ALU_WORD0_EXT__KCACHE_MODE2_shift = 30,//2 btis
- EG_CF_ALU_WORD0_EXT__KCACHE_MODE2_mask = 0x3 << 30,
-
- EG_CF_ALU_WORD1_EXT__KCACHE_MODE3_shift = 0, //2 bits
- EG_CF_ALU_WORD1_EXT__KCACHE_MODE3_mask = 0x3,
- EG_CF_ALU_WORD1_EXT__KCACHE_ADDR2_shift = 2, //8 bits
- EG_CF_ALU_WORD1_EXT__KCACHE_ADDR2_mask = 0xFF << 2,
- EG_CF_ALU_WORD1_EXT__KCACHE_ADDR3_shift = 10, //8 bits
- EG_CF_ALU_WORD1_EXT__KCACHE_ADDR3_mask = 0xFF << 10,
- EG_CF_ALU_WORD1_EXT__Reserved18_shift = 18, //8 bits
- EG_CF_ALU_WORD1_EXT__Reserved18_mask = 0xFF << 18,
- EG_CF_ALU_WORD1_EXT__CF_INST_shift = 26, //4 bits
- EG_CF_ALU_WORD1_EXT__CF_INST_mask = 0xF << 26,
- EG_CF_ALU_WORD1_EXT__Reserved30_shift = 30, //1 bit
- EG_CF_ALU_WORD1_EXT__Reserved30_bit = 1 << 30,
- EG_CF_ALU_WORD1_EXT__BARRIER_shift = 31, //1 bit
- EG_CF_ALU_WORD1_EXT__BARRIER_bit = 1 << 31,
-
-//ALU
- EG_ALU_WORD0__SRC0_SEL_shift = 0, //9 bits
- EG_ALU_WORD0__SRC0_SEL_mask = 0x1FF,
- EG_ALU_WORD0__SRC1_SEL_shift = 13,//9 bits
- EG_ALU_WORD0__SRC1_SEL_mask = 0x1FF << 13,
- EG_ALU_WORD0__SRC0_REL_shift = 9, //1 bit
- EG_ALU_WORD0__SRC0_REL_bit = 1 << 9,
- EG_ALU_WORD0__SRC1_REL_shift = 22,//1 bit
- EG_ALU_WORD0__SRC1_REL_bit = 1 << 22,
- EG_ALU_WORD0__SRC0_CHAN_shift = 10,//2 bits
- EG_ALU_WORD0__SRC0_CHAN_mask = 0x3 << 10,
- EG_ALU_WORD0__SRC1_CHAN_shift = 23,//2 bits
- EG_ALU_WORD0__SRC1_CHAN_mask = 0x3 << 23,
- EG_ALU_WORD0__SRC0_NEG_shift = 12,//1 bit
- EG_ALU_WORD0__SRC0_NEG_bit = 1 << 12,
- EG_ALU_WORD0__SRC1_NEG_shift = 25,//1 bit
- EG_ALU_WORD0__SRC1_NEG_bit = 1 << 25,
- EG_ALU_WORD0__INDEX_MODE_shift = 26,//3 bits
- EG_ALU_WORD0__INDEX_MODE_mask = 0x7 << 26,
- EG_ALU_WORD0__PRED_SEL_shift = 29,//2 bits
- EG_ALU_WORD0__PRED_SEL_mask = 0x3 << 29,
- EG_ALU_WORD0__LAST_shift = 31,//1 bit
- EG_ALU_WORD0__LAST_bit = 1 << 31,
-
- EG_ALU_WORD1_OP2__SRC0_ABS_shift = 0, //1 bit
- EG_ALU_WORD1_OP2__SRC0_ABS_bit = 1,
- EG_ALU_WORD1_OP2__SRC1_ABS_shift = 1, //1 bit
- EG_ALU_WORD1_OP2__SRC1_ABS_bit = 1 << 1,
- EG_ALU_WORD1_OP2__UEM_shift = 2, //1 bit
- EG_ALU_WORD1_OP2__UEM_bit = 1 << 2,
- EG_ALU_WORD1_OP2__UPDATE_PRED_shift = 3, //1 bit
- EG_ALU_WORD1_OP2__UPDATE_PRED_bit = 1 << 3,
- EG_ALU_WORD1_OP2__WRITE_MASK_shift = 4, //1 bit
- EG_ALU_WORD1_OP2__WRITE_MASK_bit = 1 << 4,
- EG_ALU_WORD1_OP2__OMOD_shift = 5, //2 bits
- EG_ALU_WORD1_OP2__OMOD_mask = 0x3 << 5,
- EG_ALU_WORD1_OP2__ALU_INST_shift = 7, //11 bits
- EG_ALU_WORD1_OP2__ALU_INST_mask = 0x7FF << 7,
-
- EG_ALU_WORD1__BANK_SWIZZLE_shift = 18,//3 bits
- EG_ALU_WORD1__BANK_SWIZZLE_mask = 0x7 << 18,
- EG_ALU_WORD1__DST_GPR_shift = 21,//7 bits
- EG_ALU_WORD1__DST_GPR_mask = 0x7F << 21,
- EG_ALU_WORD1__DST_REL_shift = 28,//1 bit
- EG_ALU_WORD1__DST_REL_mask = 1 << 28,
- EG_ALU_WORD1__DST_CHAN_shift = 29,//2 bits
- EG_ALU_WORD1__DST_CHAN_mask = 0x3 << 29,
- EG_ALU_WORD1__CLAMP_shift = 31,//1 bits
- EG_ALU_WORD1__CLAMP_mask = 1 << 31,
-
- EG_ALU_WORD1_OP3__SRC2_SEL_shift = 0, //9 bits
- EG_ALU_WORD1_OP3__SRC2_SEL_mask = 0x1FF,
- EG_ALU_WORD1_OP3__SRC2_REL_shift = 9, //1 bit
- EG_ALU_WORD1_OP3__SRC2_REL_bit = 1 << 9,
- EG_ALU_WORD1_OP3__SRC2_CHAN_shift = 10,//2 bits
- EG_ALU_WORD1_OP3__SRC2_CHAN_mask = 0x3 << 10,
- EG_ALU_WORD1_OP3__SRC2_NEG_shift = 12,//1 bit
- EG_ALU_WORD1_OP3__SRC2_NEG_bit = 1 << 12,
- EG_ALU_WORD1_OP3__ALU_INST_shift = 13,//5 bits
- EG_ALU_WORD1_OP3__ALU_INST_mask = 0x1F << 13,
-
- EG_OP3_INST_BFE_UINT = 4,
- EG_OP3_INST_BFE_INT = 5,
- EG_OP3_INST_BFI_INT = 6,
- EG_OP3_INST_FMA = 7,
- EG_OP3_INST_CNDNE_64 = 9,
- EG_OP3_INST_FMA_64 = 10,
- EG_OP3_INST_LERP_UINT = 11,
- EG_OP3_INST_BIT_ALIGN_INT = 12,
- EG_OP3_INST_BYTE_ALIGN_INT = 13,
- EG_OP3_INST_SAD_ACCUM_UINT = 14,
- EG_OP3_INST_SAD_ACCUM_HI_UINT = 15,
- EG_OP3_INST_MULADD_UINT24 = 16,
- EG_OP3_INST_LDS_IDX_OP = 17,
- EG_OP3_INST_MULADD = 20,
- EG_OP3_INST_MULADD_M2 = 21,
- EG_OP3_INST_MULADD_M4 = 22,
- EG_OP3_INST_MULADD_D2 = 23,
- EG_OP3_INST_MULADD_IEEE = 24,
- EG_OP3_INST_CNDE = 25,
- EG_OP3_INST_CNDGT = 26,
- EG_OP3_INST_CNDGE = 27,
- EG_OP3_INST_CNDE_INT = 28,
- EG_OP3_INST_CMNDGT_INT = 29,
- EG_OP3_INST_CMNDGE_INT = 30,
- EG_OP3_INST_MUL_LIT = 31,
-
- EG_OP2_INST_ADD = 0,
- EG_OP2_INST_MUL = 1,
- EG_OP2_INST_MUL_IEEE = 2,
- EG_OP2_INST_MAX = 3,
- EG_OP2_INST_MIN = 4,
- EG_OP2_INST_MAX_DX10 = 5,
- EG_OP2_INST_MIN_DX10 = 6,
- EG_OP2_INST_SETE = 8,
- EG_OP2_INST_SETGT = 9,
- EG_OP2_INST_SETGE = 10,
- EG_OP2_INST_SETNE = 11,
- EG_OP2_INST_SETE_DX10 = 12,
- EG_OP2_INST_SETGT_DX10 = 13,
- EG_OP2_INST_SETGE_DX10 = 14,
- EG_OP2_INST_SETNE_DX10 = 15,
- EG_OP2_INST_FRACT = 16,
- EG_OP2_INST_TRUNC = 17,
- EG_OP2_INST_CEIL = 18,
- EG_OP2_INST_RNDNE = 19,
- EG_OP2_INST_FLOOR = 20,
- EG_OP2_INST_ASHR_INT = 21,
- EG_OP2_INST_LSHR_INT = 22,
- EG_OP2_INST_LSHL_INT = 23,
- EG_OP2_INST_MOV = 25,
- EG_OP2_INST_NOP = 26,
- EG_OP2_INST_MUL_64 = 27,
- EG_OP2_INST_FLT64_TO_FLT32 = 28,
- EG_OP2_INST_FLT32_TO_FLT64 = 29,
- EG_OP2_INST_PRED_SETGT_UINT = 30,
- EG_OP2_INST_PRED_SETGE_UINT = 31,
- EG_OP2_INST_PRED_SETE = 32,
- EG_OP2_INST_PRED_SETGT = 33,
- EG_OP2_INST_PRED_SETGE = 34,
- EG_OP2_INST_PRED_SETNE = 35,
- EG_OP2_INST_PRED_SET_INV = 36,
- EG_OP2_INST_PRED_SET_POP = 37,
- EG_OP2_INST_PRED_SET_CLR = 38,
- EG_OP2_INST_PRED_SET_RESTORE = 39,
- EG_OP2_INST_PRED_SETE_PUSH = 40,
- EG_OP2_INST_PRED_SETGT_PUSH = 41,
- EG_OP2_INST_PRED_SETGE_PUSH = 42,
- EG_OP2_INST_PRED_SETNE_PUSH = 43,
- EG_OP2_INST_KILLE = 44,
- EG_OP2_INST_KILLGT = 45,
- EG_OP2_INST_KILLGE = 46,
- EG_OP2_INST_KILLNE = 47,
- EG_OP2_INST_AND_INT = 48,
- EG_OP2_INST_OR_INT = 49,
- EG_OP2_INST_XOR_INT = 50,
- EG_OP2_INST_NOT_INT = 51,
- EG_OP2_INST_ADD_INT = 52,
- EG_OP2_INST_SUB_INT = 53,
- EG_OP2_INST_MAX_INT = 54,
- EG_OP2_INST_MIN_INT = 55,
- EG_OP2_INST_MAX_UINT = 56,
- EG_OP2_INST_MIN_UINT = 57,
- EG_OP2_INST_SETE_INT = 58,
- EG_OP2_INST_SETGT_INT = 59,
- EG_OP2_INST_SETGE_INT = 60,
- EG_OP2_INST_SETNE_INT = 61,
- EG_OP2_INST_SETGT_UINT = 62,
- EG_OP2_INST_SETGE_UINT = 63,
- EG_OP2_INST_KILLGT_UINT = 64,
- EG_OP2_INST_KILLGE_UINT = 65,
- EG_OP2_INST_PREDE_INT = 66,
- EG_OP2_INST_PRED_SETGT_INT = 67,
- EG_OP2_INST_PRED_SETGE_INT = 68,
- EG_OP2_INST_PRED_SETNE_INT = 69,
- EG_OP2_INST_KILLE_INT = 70,
- EG_OP2_INST_KILLGT_INT = 71,
- EG_OP2_INST_KILLGE_INT = 72,
- EG_OP2_INST_KILLNE_INT = 73,
- EG_OP2_INST_PRED_SETE_PUSH_INT = 74,
- EG_OP2_INST_PRED_SETGT_PUSH_INT = 75,
- EG_OP2_INST_PRED_SETGE_PUSH_INT = 76,
- EG_OP2_INST_PRED_SETNE_PUSH_INT = 77,
- EG_OP2_INST_PRED_SETLT_PUSH_INT = 78,
- EG_OP2_INST_PRED_SETLE_PUSH_INT = 79,
- EG_OP2_INST_FLT_TO_INT = 80,
- EG_OP2_INST_BFREV_INT = 81,
- EG_OP2_INST_ADDC_UINT = 82,
- EG_OP2_INST_SUBB_UINT = 83,
- EG_OP2_INST_GROUP_BARRIER = 84,
- EG_OP2_INST_GROUP_SEQ_BEGIN = 85,
- EG_OP2_INST_GROUP_SEQ_END = 86,
- EG_OP2_INST_SET_MODE = 87,
- EG_OP2_INST_SET_CF_IDX0 = 88,
- EG_OP2_INST_SET_CF_IDX1 = 89,
- EG_OP2_INST_SET_LDS_SIZE = 90,
- EG_OP2_INST_EXP_IEEE = 129,
- EG_OP2_INST_LOG_CLAMPED = 130,
- EG_OP2_INST_LOG_IEEE = 131,
- EG_OP2_INST_RECIP_CLAMPED = 132,
- EG_OP2_INST_RECIP_FF = 133,
- EG_OP2_INST_RECIP_IEEE = 134,
- EG_OP2_INST_RECIPSQRT_CLAMPED = 135,
- EG_OP2_INST_RECIPSQRT_FF = 136,
- EG_OP2_INST_RECIPSQRT_IEEE = 137,
- EG_OP2_INST_SQRT_IEEE = 138,
- EG_OP2_INST_SIN = 141,
- EG_OP2_INST_COS = 142,
- EG_OP2_INST_MULLO_INT = 143,
- EG_OP2_INST_MULHI_INT = 144,
- EG_OP2_INST_MULLO_UINT = 145,
- EG_OP2_INST_MULHI_UINT = 146,
- EG_OP2_INST_RECIP_INT = 147,
- EG_OP2_INST_RECIP_UINT = 148,
- EG_OP2_INST_RECIP_64 = 149,
- EG_OP2_INST_RECIP_CLAMPED_64 = 150,
- EG_OP2_INST_RECIPSQRT_64 = 151,
- EG_OP2_INST_RECIPSQRT_CLAMPED_64 = 152,
- EG_OP2_INST_SQRT_64 = 153,
- EG_OP2_INST_FLT_TO_UINT = 154,
- EG_OP2_INST_INT_TO_FLT = 155,
- EG_OP2_INST_UINT_TO_FLT = 156,
- EG_OP2_INST_BFM_INT = 160,
- EG_OP2_INST_FLT32_TO_FLT16 = 162,
- EG_OP2_INST_FLT16_TO_FLT32 = 163,
- EG_OP2_INST_UBYTE0_FLT = 164,
- EG_OP2_INST_UBYTE1_FLT = 165,
- EG_OP2_INST_UBYTE2_FLT = 166,
- EG_OP2_INST_UBYTE3_FLT = 167,
- EG_OP2_INST_BCNT_INT = 170,
- EG_OP2_INST_FFBH_UINT = 171,
- EG_OP2_INST_FFBL_INT = 172,
- EG_OP2_INST_FFBH_INT = 173,
- EG_OP2_INST_FLT_TO_UINT4 = 174,
- EG_OP2_INST_DOT_IEEE = 175,
- EG_OP2_INST_FLT_TO_INT_RPI = 176,
- EG_OP2_INST_FLT_TO_INT_FLOOR = 177,
- EG_OP2_INST_MULHI_UINT24 = 178,
- EG_OP2_INST_MBCNT_32HI_INT = 179,
- EG_OP2_INST_OFFSET_TO_FLT = 180,
- EG_OP2_INST_MUL_UINT24 = 181,
- EG_OP2_INST_BCNT_ACCUM_PREV_INT = 182,
- EG_OP2_INST_MBCNT_32LO_ACCUM_PREV_INT = 183,
- EG_OP2_INST_SETE_64 = 184,
- EG_OP2_INST_SETNE_64 = 185,
- EG_OP2_INST_SETGT_64 = 186,
- EG_OP2_INST_SETGE_64 = 187,
- EG_OP2_INST_MIN_64 = 188,
- EG_OP2_INST_MAX_64 = 189,
- EG_OP2_INST_DOT4 = 190,
- EG_OP2_INST_DOT4_IEEE = 191,
- EG_OP2_INST_CUBE = 192,
- EG_OP2_INST_MAX4 = 193,
- EG_OP2_INST_FREXP_64 = 196,
- EG_OP2_INST_LDEXP_64 = 197,
- EG_OP2_INST_FRACT_64 = 198,
- EG_OP2_INST_PRED_SETGT_64 = 199,
- EG_OP2_INST_PRED_SETE_64 = 200,
- EG_OP2_INST_PRED_SETGE_64 = 201,
- EG_OP2_INST_MUL_64_2 = 202, //same as prev?
- EG_OP2_INST_ADD_64 = 203,
- EG_OP2_INST_MOVA_INT = 204,
- EG_OP2_INST_FLT64_TO_FLT32_2 = 205, //same as prev?
- EG_OP2_INST_FLT32_TO_FLT64_2 = 206, //same as prev?
- EG_OP2_INST_SAD_ACCUM_PREV_UINT = 207,
- EG_OP2_INST_DOT = 208,
- EG_OP2_INST_MUL_PREV = 209,
- EG_OP2_INST_MUL_IEEE_PREV = 210,
- EG_OP2_INST_ADD_PREV = 211,
- EG_OP2_INST_MULADD_PREV = 212,
- EG_OP2_INST_MULADD_IEEE_PREV = 213,
- EG_OP2_INST_INTERP_XY = 214,
- EG_OP2_INST_INTERP_ZW = 215,
- EG_OP2_INST_INTERP_X = 216,
- EG_OP2_INST_INTERP_Z = 217,
- EG_OP2_INST_STORE_FLAGS = 218,
- EG_OP2_INST_LOAD_STORE_FLAGS = 219,
- EG_OP2_INST_LDS_1A = 220,
- EG_OP2_INST_LDS_1A1D = 221,
- EG_OP2_INST_LDS_2A = 223,
- EG_OP2_INST_INTERP_LOAD_P0 = 224,
- EG_OP2_INST_INTERP_LOAD_P10 = 225,
- EG_OP2_INST_INTERP_LOAD_P20 = 226,
-
- EG_SRC_SEL__GPR_start = 0,
- EG_SRC_SEL__GPR_end = 127,
- EG_SRC_SEL__KCONST_BANK0_start = 128,
- EG_SRC_SEL__KCONST_BANK0_end = 159,
- EG_SRC_SEL__KCONST_BANK1_start = 160,
- EG_SRC_SEL__KCONST_BANK1_end = 191,
- EG_SRC_SEL__INLINE_satrt = 192,
- EG_SRC_SEL__INLINE_end = 255,
- EG_SRC_SEL__KCONST_BANK2_start = 256,
- EG_SRC_SEL__KCONST_BANK2_end = 287,
- EG_SRC_SEL__KCONST_BANK3_start = 288,
- EG_SRC_SEL__KCONST_BANK3_end = 319,
- EG_SRC_SEL__ALU_SRC_LDS_OQ_A = 219,
- EG_SRC_SEL__ALU_SRC_LDS_OQ_B = 220,
- EG_SRC_SEL__ALU_SRC_LDS_OQ_A_POP = 221,
- EG_SRC_SEL__ALU_SRC_LDS_OQ_B_POP = 222,
- EG_SRC_SEL__ALU_SRC_LDS_DIRECT_A = 223,
- EG_SRC_SEL__ALU_SRC_LDS_DIRECT_B = 224,
- EG_SRC_SEL__ALU_SRC_TIME_HI = 227,
- EG_SRC_SEL__ALU_SRC_TIME_LO = 228,
- EG_SRC_SEL__ALU_SRC_MASK_HI = 229,
- EG_SRC_SEL__ALU_SRC_MASK_LO = 230,
- EG_SRC_SEL__ALU_SRC_HW_WAVE_ID = 231,
- EG_SRC_SEL__ALU_SRC_SIMD_ID = 232,
- EG_SRC_SEL__ALU_SRC_SE_ID = 233,
- EG_SRC_SEL__ALU_SRC_HW_THREADGRP_ID = 234,
- EG_SRC_SEL__ALU_SRC_WAVE_ID_IN_GRP = 235,
- EG_SRC_SEL__ALU_SRC_NUM_THREADGRP_WAVES = 236,
- EG_SRC_SEL__ALU_SRC_HW_ALU_ODD = 237,
- EG_SRC_SEL__ALU_SRC_LOOP_IDX = 238,
- EG_SRC_SEL__ALU_SRC_PARAM_BASE_ADDR = 240,
- EG_SRC_SEL__ALU_SRC_NEW_PRIM_MASK = 241,
- EG_SRC_SEL__ALU_SRC_PRIM_MASK_HI = 242,
- EG_SRC_SEL__ALU_SRC_PRIM_MASK_LO = 243,
- EG_SRC_SEL__ALU_SRC_1_DBL_L = 244,
- EG_SRC_SEL__ALU_SRC_1_DBL_M = 245,
- EG_SRC_SEL__ALU_SRC_0_5_DBL_L = 246,
- EG_SRC_SEL__ALU_SRC_0_5_DBL_M = 247,
- EG_SRC_SEL__ALU_SRC_0 = 248,
- EG_SRC_SEL__ALU_SRC_1 = 249,
- EG_SRC_SEL__ALU_SRC_1_INT = 250,
- EG_SRC_SEL__ALU_SRC_M_1_INT = 251,
- EG_SRC_SEL__ALU_SRC_0_5 = 252,
- EG_SRC_SEL__ALU_SRC_LITERAL = 253,
- EG_SRC_SEL__ALU_SRC_PV = 254,
- EG_SRC_SEL__ALU_SRC_PS = 255,
-
-//ALLOC_EXPORT
- EG_CF_ALLOC_EXPORT_WORD0__ARRAY_BASE_shift = 0, //13 bits
- EG_CF_ALLOC_EXPORT_WORD0__ARRAY_BASE_mask = 0x1FFF,
- EG_CF_ALLOC_EXPORT_WORD0__TYPE_shift = 13,//2 bits
- EG_CF_ALLOC_EXPORT_WORD0__TYPE_mask = 0x3 << 13,
- EG_CF_ALLOC_EXPORT_WORD0__RW_GPR_shift = 15,//7 bits
- EG_CF_ALLOC_EXPORT_WORD0__RW_GPR_mask = 0x7F << 15,
- EG_CF_ALLOC_EXPORT_WORD0__RW_REL_shift = 22,//1 bit
- EG_CF_ALLOC_EXPORT_WORD0__RW_REL_bit = 1 << 22,
- EG_CF_ALLOC_EXPORT_WORD0__INDEX_GPR_shift = 23,//7 bits
- EG_CF_ALLOC_EXPORT_WORD0__INDEX_GPR_mask = 0x7F << 23,
- EG_CF_ALLOC_EXPORT_WORD0__ELEM_SIZE_shift = 30,//2 bits
- EG_CF_ALLOC_EXPORT_WORD0__ELEM_SIZE_mask = 0x3 << 30,
-
- EG_CF_ALLOC_EXPORT_WORD1_BUF__ARRAY_SIZE_shift = 0, //12 bits
- EG_CF_ALLOC_EXPORT_WORD1_BUF__ARRAY_SIZE_mask = 0xFFF,
- EG_CF_ALLOC_EXPORT_WORD1_BUF__COMP_MASK_shift = 12, //4 bits
- EG_CF_ALLOC_EXPORT_WORD1_BUF__COMP_MASK_mask = 0xF << 12,
-
- EG_CF_ALLOC_EXPORT_WORD1_SWIZ__SEL_X_shift = 0, //3 bits
- EG_CF_ALLOC_EXPORT_WORD1_SWIZ__SEL_X_mask = 0x7,
- EG_CF_ALLOC_EXPORT_WORD1_SWIZ__SEL_Y_shift = 3, //3 bits
- EG_CF_ALLOC_EXPORT_WORD1_SWIZ__SEL_Y_mask = 0x7 << 3,
- EG_CF_ALLOC_EXPORT_WORD1_SWIZ__SEL_Z_shift = 6, //3 bits
- EG_CF_ALLOC_EXPORT_WORD1_SWIZ__SEL_Z_mask = 0x7 << 6,
- EG_CF_ALLOC_EXPORT_WORD1_SWIZ__SEL_W_shift = 9, //3 bits
- EG_CF_ALLOC_EXPORT_WORD1_SWIZ__SEL_W_mask = 0x7 << 9,
- EG_CF_ALLOC_EXPORT_WORD1_SWIZ__Resreve_shift = 12,//4 bits
- EG_CF_ALLOC_EXPORT_WORD1_SWIZ__Resreve_mask = 0xF << 12,
-
- EG_CF_ALLOC_EXPORT_WORD1__BURST_COUNT_shift = 16, //4 bits
- EG_CF_ALLOC_EXPORT_WORD1__BURST_COUNT_mask = 0xF << 16,
- EG_CF_ALLOC_EXPORT_WORD1__VPM_shift = 20, //1 bit
- EG_CF_ALLOC_EXPORT_WORD1__VPM_bit = 1 << 20,
- EG_CF_ALLOC_EXPORT_WORD1__EOP_shift = 21, //1 bit
- EG_CF_ALLOC_EXPORT_WORD1__EOP_bit = 1 << 21,
- EG_CF_ALLOC_EXPORT_WORD1__CF_INST_shift = 22, //8 bits
- EG_CF_ALLOC_EXPORT_WORD1__CF_INST_mask = 0xFF << 22,
- EG_CF_ALLOC_EXPORT_WORD1__MARK_shift = 30, //1 bit
- EG_CF_ALLOC_EXPORT_WORD1__MARK_bit = 1 << 30,
- EG_CF_ALLOC_EXPORT_WORD1__BARRIER_shift = 31, //1 bit
- EG_CF_ALLOC_EXPORT_WORD1__BARRIER_bit = 1 << 31,
-
- EG_CF_INST_MEM_STREAM0_BUF0 = 64 ,
- EG_CF_INST_MEM_STREAM0_BUF1 = 65,
- EG_CF_INST_MEM_STREAM0_BUF2 = 66,
- EG_CF_INST_MEM_STREAM0_BUF3 = 67,
- EG_CF_INST_MEM_STREAM1_BUF0 = 68,
- EG_CF_INST_MEM_STREAM1_BUF1 = 69,
- EG_CF_INST_MEM_STREAM1_BUF2 = 70,
- EG_CF_INST_MEM_STREAM1_BUF3 = 71,
- EG_CF_INST_MEM_STREAM2_BUF0 = 72,
- EG_CF_INST_MEM_STREAM2_BUF1 = 73,
- EG_CF_INST_MEM_STREAM2_BUF2 = 74,
- EG_CF_INST_MEM_STREAM2_BUF3 = 75,
- EG_CF_INST_MEM_STREAM3_BUF0 = 76,
- EG_CF_INST_MEM_STREAM3_BUF1 = 77,
- EG_CF_INST_MEM_STREAM3_BUF2 = 78,
- EG_CF_INST_MEM_STREAM3_BUF3 = 79,
- EG_CF_INST_MEM_WR_SCRATCH = 80,
- EG_CF_INST_MEM_RING = 82,
- EG_CF_INST_EXPORT = 83,
- EG_CF_INST_EXPORT_DONE = 84,
- EG_CF_INST_MEM_EXPORT = 85,
- EG_CF_INST_MEM_RAT = 86,
- EG_CF_INST_MEM_RAT_CACHELESS = 87,
- EG_CF_INST_MEM_RING1 = 88,
- EG_CF_INST_MEM_RING2 = 89,
- EG_CF_INST_MEM_RING3 = 90,
- EG_CF_INST_MEM_EXPORT_COMBINED = 91,
- EG_CF_INST_MEM_RAT_COMBINED_CACHELESS = 92,
-
- EG_EXPORT_PIXEL = 0,
- EG_EXPORT_WRITE = 0,
- EG_EXPORT_POS = 1,
- EG_EXPORT_WRITE_IND = 1,
- EG_EXPORT_PARAM = 2,
- EG_EXPORT_WRITE_ACK = 2,
- EG_EXPORT_WRITE_IND_ACK = 3,
-
- /* PS interp param source */
- EG_ALU_SRC_PARAM_BASE = 0x000001c0,
- EG_ALU_SRC_PARAM_SIZE = 0x00000021,
-};
-
-#endif //_EVERGREEN_SQ_H_
-
-
+++ /dev/null
-/*
- * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Authors:
- * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
- */
-
-#include "main/glheader.h"
-#include "main/mtypes.h"
-#include "main/imports.h"
-#include "main/enums.h"
-#include "main/macros.h"
-#include "main/context.h"
-#include "main/dd.h"
-#include "main/simple_list.h"
-#include "main/state.h"
-
-#include "tnl/tnl.h"
-#include "tnl/t_pipeline.h"
-#include "swrast/swrast.h"
-#include "swrast_setup/swrast_setup.h"
-#include "main/api_arrayelt.h"
-#include "main/framebuffer.h"
-#include "drivers/common/meta.h"
-#include "program/prog_parameter.h"
-#include "program/prog_statevars.h"
-
-#include "vbo/vbo.h"
-
-#include "r600_context.h"
-
-#include "evergreen_state.h"
-#include "evergreen_diff.h"
-#include "evergreen_vertprog.h"
-#include "evergreen_fragprog.h"
-#include "evergreen_tex.h"
-
-void evergreenUpdateStateParameters(struct gl_context * ctx, GLuint new_state); //same
-
-void evergreenUpdateShaders(struct gl_context * ctx)
-{
- context_t *context = EVERGREEN_CONTEXT(ctx);
-
- /* should only happenen once, just after context is created */
- /* TODO: shouldn't we fallback to sw here? */
- if (!ctx->FragmentProgram._Current) {
- fprintf(stderr, "No ctx->FragmentProgram._Current!!\n");
- return;
- }
-
- evergreenSelectFragmentShader(ctx);
-
- evergreenSelectVertexShader(ctx);
- evergreenUpdateStateParameters(ctx, _NEW_PROGRAM | _NEW_PROGRAM_CONSTANTS);
- context->radeon.NewGLState = 0;
-}
-
-void evergreeUpdateShaders(struct gl_context * ctx)
-{
- context_t *context = R700_CONTEXT(ctx);
-
- /* should only happenen once, just after context is created */
- /* TODO: shouldn't we fallback to sw here? */
- if (!ctx->FragmentProgram._Current) {
- fprintf(stderr, "No ctx->FragmentProgram._Current!!\n");
- return;
- }
-
- evergreenSelectFragmentShader(ctx);
-
- evergreenSelectVertexShader(ctx);
- evergreenUpdateStateParameters(ctx, _NEW_PROGRAM | _NEW_PROGRAM_CONSTANTS);
- context->radeon.NewGLState = 0;
-}
-
-/*
- * To correctly position primitives:
- */
-void evergreenUpdateViewportOffset(struct gl_context * ctx) //------------------
-{
- context_t *context = R700_CONTEXT(ctx);
- EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
- __DRIdrawable *dPriv = radeon_get_drawable(&context->radeon);
- GLfloat xoffset = (GLfloat) dPriv->x;
- GLfloat yoffset = (GLfloat) dPriv->y + dPriv->h;
- const GLfloat *v = ctx->Viewport._WindowMap.m;
- int id = 0;
-
- GLfloat tx = v[MAT_TX] + xoffset;
- GLfloat ty = (-v[MAT_TY]) + yoffset;
-
- if (evergreen->viewport[id].PA_CL_VPORT_XOFFSET.f32All != tx ||
- evergreen->viewport[id].PA_CL_VPORT_YOFFSET.f32All != ty) {
- /* Note: this should also modify whatever data the context reset
- * code uses...
- */
- EVERGREEN_STATECHANGE(context, pa);
- evergreen->viewport[id].PA_CL_VPORT_XOFFSET.f32All = tx;
- evergreen->viewport[id].PA_CL_VPORT_YOFFSET.f32All = ty;
- }
-
- radeonUpdateScissor(ctx);
-}
-
-void evergreenUpdateStateParameters(struct gl_context * ctx, GLuint new_state) //same
-{
- struct evergreen_fragment_program *fp =
- (struct evergreen_fragment_program *)ctx->FragmentProgram._Current;
- struct gl_program_parameter_list *paramList;
-
- if (!(new_state & (_NEW_BUFFERS | _NEW_PROGRAM | _NEW_PROGRAM_CONSTANTS)))
- return;
-
- if (!ctx->FragmentProgram._Current || !fp)
- return;
-
- paramList = ctx->FragmentProgram._Current->Base.Parameters;
-
- if (!paramList)
- return;
-
- _mesa_load_state_parameters(ctx, paramList);
-
-}
-
-/**
- * Called by Mesa after an internal state update.
- */
-static void evergreenInvalidateState(struct gl_context * ctx, GLuint new_state) //same
-{
- context_t *context = EVERGREEN_CONTEXT(ctx);
-
- EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
-
- _swrast_InvalidateState(ctx, new_state);
- _swsetup_InvalidateState(ctx, new_state);
- _vbo_InvalidateState(ctx, new_state);
- _tnl_InvalidateState(ctx, new_state);
- _ae_invalidate_state(ctx, new_state);
-
- if (new_state & _NEW_BUFFERS) {
- _mesa_update_framebuffer(ctx);
- /* this updates the DrawBuffer's Width/Height if it's a FBO */
- _mesa_update_draw_buffer_bounds(ctx);
-
- EVERGREEN_STATECHANGE(context, cb);
- EVERGREEN_STATECHANGE(context, db);
- }
-
- if (new_state & (_NEW_LIGHT)) {
- EVERGREEN_STATECHANGE(context, pa);
- if (ctx->Light.ProvokingVertex == GL_LAST_VERTEX_CONVENTION)
- SETbit(evergreen->PA_SU_SC_MODE_CNTL.u32All, PROVOKING_VTX_LAST_bit);
- else
- CLEARbit(evergreen->PA_SU_SC_MODE_CNTL.u32All, PROVOKING_VTX_LAST_bit);
- }
-
- evergreenUpdateStateParameters(ctx, new_state);
-
- EVERGREEN_STATECHANGE(context, pa);
- EVERGREEN_STATECHANGE(context, spi);
-
- if(GL_TRUE == evergreen->bEnablePerspective)
- {
- /* Do scale XY and Z by 1/W0 for perspective correction on pos. For orthogonal case, set both to one. */
- CLEARbit(evergreen->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
- CLEARbit(evergreen->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
-
- SETbit(evergreen->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
-
- SETbit(evergreen->SPI_PS_IN_CONTROL_0.u32All, PERSP_GRADIENT_ENA_bit);
- CLEARbit(evergreen->SPI_PS_IN_CONTROL_0.u32All, LINEAR_GRADIENT_ENA_bit);
-
- SETfield(evergreen->SPI_BARYC_CNTL.u32All, 1,
- EG_SPI_BARYC_CNTL__PERSP_CENTROID_ENA_shift,
- EG_SPI_BARYC_CNTL__PERSP_CENTROID_ENA_mask);
- }
- else
- {
- /* For orthogonal case. */
- SETbit(evergreen->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
- SETbit(evergreen->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
-
- SETbit(evergreen->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
-
- CLEARbit(evergreen->SPI_PS_IN_CONTROL_0.u32All, PERSP_GRADIENT_ENA_bit);
- SETbit(evergreen->SPI_PS_IN_CONTROL_0.u32All, LINEAR_GRADIENT_ENA_bit);
-
- SETfield(evergreen->SPI_BARYC_CNTL.u32All, 1,
- EG_SPI_BARYC_CNTL__LINEAR_CENTROID_ENA_shift,
- EG_SPI_BARYC_CNTL__LINEAR_CENTROID_ENA_mask);
- }
-
- context->radeon.NewGLState |= new_state;
-}
-
-static void evergreenSetAlphaState(struct gl_context * ctx) //same
-{
- context_t *context = EVERGREEN_CONTEXT(ctx);
- EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
- uint32_t alpha_func = REF_ALWAYS;
- GLboolean really_enabled = ctx->Color.AlphaEnabled;
-
- EVERGREEN_STATECHANGE(context, sx);
-
- switch (ctx->Color.AlphaFunc) {
- case GL_NEVER:
- alpha_func = REF_NEVER;
- break;
- case GL_LESS:
- alpha_func = REF_LESS;
- break;
- case GL_EQUAL:
- alpha_func = REF_EQUAL;
- break;
- case GL_LEQUAL:
- alpha_func = REF_LEQUAL;
- break;
- case GL_GREATER:
- alpha_func = REF_GREATER;
- break;
- case GL_NOTEQUAL:
- alpha_func = REF_NOTEQUAL;
- break;
- case GL_GEQUAL:
- alpha_func = REF_GEQUAL;
- break;
- case GL_ALWAYS:
- /*alpha_func = REF_ALWAYS; */
- really_enabled = GL_FALSE;
- break;
- }
-
- if (really_enabled) {
- SETfield(evergreen->SX_ALPHA_TEST_CONTROL.u32All, alpha_func,
- ALPHA_FUNC_shift, ALPHA_FUNC_mask);
- SETbit(evergreen->SX_ALPHA_TEST_CONTROL.u32All, ALPHA_TEST_ENABLE_bit);
- evergreen->SX_ALPHA_REF.f32All = ctx->Color.AlphaRef;
- } else {
- CLEARbit(evergreen->SX_ALPHA_TEST_CONTROL.u32All, ALPHA_TEST_ENABLE_bit);
- }
-}
-
-static void evergreenAlphaFunc(struct gl_context * ctx, GLenum func, GLfloat ref) //same
-{
- (void)func;
- (void)ref;
- evergreenSetAlphaState(ctx);
-}
-
-static void evergreenBlendColor(struct gl_context * ctx, const GLfloat cf[4]) //same
-{
- context_t *context = EVERGREEN_CONTEXT(ctx);
- EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
-
- EVERGREEN_STATECHANGE(context, cb);
-
- evergreen->CB_BLEND_RED.f32All = cf[0];
- evergreen->CB_BLEND_GREEN.f32All = cf[1];
- evergreen->CB_BLEND_BLUE.f32All = cf[2];
- evergreen->CB_BLEND_ALPHA.f32All = cf[3];
-}
-
-static int evergreenblend_factor(GLenum factor, GLboolean is_src) //same
-{
- switch (factor) {
- case GL_ZERO:
- return BLEND_ZERO;
- break;
- case GL_ONE:
- return BLEND_ONE;
- break;
- case GL_DST_COLOR:
- return BLEND_DST_COLOR;
- break;
- case GL_ONE_MINUS_DST_COLOR:
- return BLEND_ONE_MINUS_DST_COLOR;
- break;
- case GL_SRC_COLOR:
- return BLEND_SRC_COLOR;
- break;
- case GL_ONE_MINUS_SRC_COLOR:
- return BLEND_ONE_MINUS_SRC_COLOR;
- break;
- case GL_SRC_ALPHA:
- return BLEND_SRC_ALPHA;
- break;
- case GL_ONE_MINUS_SRC_ALPHA:
- return BLEND_ONE_MINUS_SRC_ALPHA;
- break;
- case GL_DST_ALPHA:
- return BLEND_DST_ALPHA;
- break;
- case GL_ONE_MINUS_DST_ALPHA:
- return BLEND_ONE_MINUS_DST_ALPHA;
- break;
- case GL_SRC_ALPHA_SATURATE:
- return (is_src) ? BLEND_SRC_ALPHA_SATURATE : BLEND_ZERO;
- break;
- case GL_CONSTANT_COLOR:
- return BLEND_CONSTANT_COLOR;
- break;
- case GL_ONE_MINUS_CONSTANT_COLOR:
- return BLEND_ONE_MINUS_CONSTANT_COLOR;
- break;
- case GL_CONSTANT_ALPHA:
- return BLEND_CONSTANT_ALPHA;
- break;
- case GL_ONE_MINUS_CONSTANT_ALPHA:
- return BLEND_ONE_MINUS_CONSTANT_ALPHA;
- break;
- default:
- fprintf(stderr, "unknown blend factor %x\n", factor);
- return (is_src) ? BLEND_ONE : BLEND_ZERO;
- break;
- }
-}
-
-static void evergreenSetBlendState(struct gl_context * ctx) //diff : CB_COLOR_CONTROL, CB_BLEND0_CONTROL bits
-{
- context_t *context = EVERGREEN_CONTEXT(ctx);
- EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
- uint32_t blend_reg = 0, eqn, eqnA;
-
- EVERGREEN_STATECHANGE(context, cb);
-
- if (ctx->Color.ColorLogicOpEnabled || !ctx->Color.BlendEnabled) {
- SETfield(blend_reg,
- BLEND_ONE, COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
- SETfield(blend_reg,
- BLEND_ZERO, COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
- SETfield(blend_reg,
- COMB_DST_PLUS_SRC, COLOR_COMB_FCN_shift, COLOR_COMB_FCN_mask);
- SETfield(blend_reg,
- BLEND_ONE, ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
- SETfield(blend_reg,
- BLEND_ZERO, ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
- SETfield(blend_reg,
- COMB_DST_PLUS_SRC, ALPHA_COMB_FCN_shift, ALPHA_COMB_FCN_mask);
- //if (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_R600)
- // evergreen->CB_BLEND_CONTROL.u32All = blend_reg;
- //else
- evergreen->CB_BLEND0_CONTROL.u32All = blend_reg;
- return;
- }
-
- SETfield(blend_reg,
- evergreenblend_factor(ctx->Color.Blend[0].SrcRGB, GL_TRUE),
- COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
- SETfield(blend_reg,
- evergreenblend_factor(ctx->Color.Blend[0].DstRGB, GL_FALSE),
- COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
-
- switch (ctx->Color.Blend[0].EquationRGB) {
- case GL_FUNC_ADD:
- eqn = COMB_DST_PLUS_SRC;
- break;
- case GL_FUNC_SUBTRACT:
- eqn = COMB_SRC_MINUS_DST;
- break;
- case GL_FUNC_REVERSE_SUBTRACT:
- eqn = COMB_DST_MINUS_SRC;
- break;
- case GL_MIN:
- eqn = COMB_MIN_DST_SRC;
- SETfield(blend_reg,
- BLEND_ONE,
- COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
- SETfield(blend_reg,
- BLEND_ONE,
- COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
- break;
- case GL_MAX:
- eqn = COMB_MAX_DST_SRC;
- SETfield(blend_reg,
- BLEND_ONE,
- COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
- SETfield(blend_reg,
- BLEND_ONE,
- COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
- break;
-
- default:
- fprintf(stderr,
- "[%s:%u] Invalid RGB blend equation (0x%04x).\n",
- __FUNCTION__, __LINE__, ctx->Color.Blend[0].EquationRGB);
- return;
- }
- SETfield(blend_reg,
- eqn, COLOR_COMB_FCN_shift, COLOR_COMB_FCN_mask);
-
- SETfield(blend_reg,
- evergreenblend_factor(ctx->Color.Blend[0].SrcA, GL_TRUE),
- ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
- SETfield(blend_reg,
- evergreenblend_factor(ctx->Color.Blend[0].DstA, GL_FALSE),
- ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
-
- switch (ctx->Color.Blend[0].EquationA) {
- case GL_FUNC_ADD:
- eqnA = COMB_DST_PLUS_SRC;
- break;
- case GL_FUNC_SUBTRACT:
- eqnA = COMB_SRC_MINUS_DST;
- break;
- case GL_FUNC_REVERSE_SUBTRACT:
- eqnA = COMB_DST_MINUS_SRC;
- break;
- case GL_MIN:
- eqnA = COMB_MIN_DST_SRC;
- SETfield(blend_reg,
- BLEND_ONE,
- ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
- SETfield(blend_reg,
- BLEND_ONE,
- ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
- break;
- case GL_MAX:
- eqnA = COMB_MAX_DST_SRC;
- SETfield(blend_reg,
- BLEND_ONE,
- ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
- SETfield(blend_reg,
- BLEND_ONE,
- ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
- break;
- default:
- fprintf(stderr,
- "[%s:%u] Invalid A blend equation (0x%04x).\n",
- __FUNCTION__, __LINE__, ctx->Color.Blend[0].EquationA);
- return;
- }
-
- SETfield(blend_reg,
- eqnA, ALPHA_COMB_FCN_shift, ALPHA_COMB_FCN_mask);
-
- SETbit(blend_reg, SEPARATE_ALPHA_BLEND_bit);
-
- SETbit(blend_reg, EG_CB_BLENDX_CONTROL_ENABLE_bit);
-
- evergreen->CB_BLEND0_CONTROL.u32All = blend_reg;
-}
-
-static void evergreenBlendEquationSeparate(struct gl_context * ctx,
- GLenum modeRGB, GLenum modeA) //same
-{
- evergreenSetBlendState(ctx);
-}
-
-static void evergreenBlendFuncSeparate(struct gl_context * ctx,
- GLenum sfactorRGB, GLenum dfactorRGB,
- GLenum sfactorA, GLenum dfactorA) //same
-{
- evergreenSetBlendState(ctx);
-}
-
-static GLuint evergreen_translate_logicop(GLenum logicop) //same
-{
- switch (logicop) {
- case GL_CLEAR:
- return 0x00;
- case GL_SET:
- return 0xff;
- case GL_COPY:
- return 0xcc;
- case GL_COPY_INVERTED:
- return 0x33;
- case GL_NOOP:
- return 0xaa;
- case GL_INVERT:
- return 0x55;
- case GL_AND:
- return 0x88;
- case GL_NAND:
- return 0x77;
- case GL_OR:
- return 0xee;
- case GL_NOR:
- return 0x11;
- case GL_XOR:
- return 0x66;
- case GL_EQUIV:
- return 0x99;
- case GL_AND_REVERSE:
- return 0x44;
- case GL_AND_INVERTED:
- return 0x22;
- case GL_OR_REVERSE:
- return 0xdd;
- case GL_OR_INVERTED:
- return 0xbb;
- default:
- fprintf(stderr, "unknown blend logic operation %x\n", logicop);
- return 0xcc;
- }
-}
-
-static void evergreenSetLogicOpState(struct gl_context *ctx) //diff : CB_COLOR_CONTROL.ROP3 is actually same bits.
-{
- context_t *context = EVERGREEN_CONTEXT(ctx);
- EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
-
- EVERGREEN_STATECHANGE(context, cb);
-
- if (ctx->Color.ColorLogicOpEnabled)
- SETfield(evergreen->CB_COLOR_CONTROL.u32All,
- evergreen_translate_logicop(ctx->Color.LogicOp),
- EG_CB_COLOR_CONTROL__ROP3_shift,
- EG_CB_COLOR_CONTROL__ROP3_mask);
- else
- SETfield(evergreen->CB_COLOR_CONTROL.u32All, 0xCC,
- EG_CB_COLOR_CONTROL__ROP3_shift,
- EG_CB_COLOR_CONTROL__ROP3_mask);
-}
-
-static void evergreenClipPlane( struct gl_context *ctx, GLenum plane, const GLfloat *eq ) //same , but PA_CL_UCP_0_ offset diff
-{
- context_t *context = EVERGREEN_CONTEXT(ctx);
- EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
- GLint p;
- GLint *ip;
-
- p = (GLint) plane - (GLint) GL_CLIP_PLANE0;
- ip = (GLint *)ctx->Transform._ClipUserPlane[p];
-
- EVERGREEN_STATECHANGE(context, pa);
-
- evergreen->ucp[p].PA_CL_UCP_0_X.u32All = ip[0];
- evergreen->ucp[p].PA_CL_UCP_0_Y.u32All = ip[1];
- evergreen->ucp[p].PA_CL_UCP_0_Z.u32All = ip[2];
- evergreen->ucp[p].PA_CL_UCP_0_W.u32All = ip[3];
-}
-
-static void evergreenSetClipPlaneState(struct gl_context * ctx, GLenum cap, GLboolean state) //diff in func calls
-{
- context_t *context = EVERGREEN_CONTEXT(ctx);
- EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
- GLuint p;
-
- p = cap - GL_CLIP_PLANE0;
-
- EVERGREEN_STATECHANGE(context, pa);
-
- if (state) {
- evergreen->PA_CL_CLIP_CNTL.u32All |= (UCP_ENA_0_bit << p);
- evergreen->ucp[p].enabled = GL_TRUE;
- evergreenClipPlane(ctx, cap, NULL);
- } else {
- evergreen->PA_CL_CLIP_CNTL.u32All &= ~(UCP_ENA_0_bit << p);
- evergreen->ucp[p].enabled = GL_FALSE;
- }
-}
-
-static void evergreenSetDBRenderState(struct gl_context * ctx)
-{
- context_t *context = EVERGREEN_CONTEXT(ctx);
- EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
- struct evergreen_fragment_program *fp =
- (struct evergreen_fragment_program *)(ctx->FragmentProgram._Current);
-
- EVERGREEN_STATECHANGE(context, db);
-
- SETbit(evergreen->DB_SHADER_CONTROL.u32All,
- DUAL_EXPORT_ENABLE_bit);
- SETfield(evergreen->DB_SHADER_CONTROL.u32All, EARLY_Z_THEN_LATE_Z,
- Z_ORDER_shift,
- Z_ORDER_mask);
- /* XXX need to enable htile for hiz/s */
- SETfield(evergreen->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE,
- FORCE_HIZ_ENABLE_shift,
- FORCE_HIZ_ENABLE_mask);
- SETfield(evergreen->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE,
- FORCE_HIS_ENABLE0_shift,
- FORCE_HIS_ENABLE0_mask);
- SETfield(evergreen->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE,
- FORCE_HIS_ENABLE1_shift,
- FORCE_HIS_ENABLE1_mask);
-
- if (context->radeon.query.current)
- {
- SETbit(evergreen->DB_RENDER_OVERRIDE.u32All, NOOP_CULL_DISABLE_bit);
- SETbit(evergreen->DB_COUNT_CONTROL.u32All,
- EG_DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS_bit);
- }
- else
- {
- CLEARbit(evergreen->DB_RENDER_OVERRIDE.u32All, NOOP_CULL_DISABLE_bit);
- CLEARbit(evergreen->DB_COUNT_CONTROL.u32All,
- EG_DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS_bit);
- }
-
- if (fp)
- {
- if (fp->r700Shader.killIsUsed)
- {
- SETbit(evergreen->DB_SHADER_CONTROL.u32All, KILL_ENABLE_bit);
- }
- else
- {
- CLEARbit(evergreen->DB_SHADER_CONTROL.u32All, KILL_ENABLE_bit);
- }
-
- if (fp->r700Shader.depthIsExported)
- {
- SETbit(evergreen->DB_SHADER_CONTROL.u32All, Z_EXPORT_ENABLE_bit);
- }
- else
- {
- CLEARbit(evergreen->DB_SHADER_CONTROL.u32All, Z_EXPORT_ENABLE_bit);
- }
- }
-}
-
-void evergreenUpdateShaderStates(struct gl_context * ctx)
-{
- evergreenSetDBRenderState(ctx);
- evergreenUpdateTextureState(ctx);
-}
-
-static void evergreenSetDepthState(struct gl_context * ctx) //same
-{
- context_t *context = EVERGREEN_CONTEXT(ctx);
- EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
-
- EVERGREEN_STATECHANGE(context, db);
-
- if (ctx->Depth.Test)
- {
- SETbit(evergreen->DB_DEPTH_CONTROL.u32All, Z_ENABLE_bit);
- if (ctx->Depth.Mask)
- {
- SETbit(evergreen->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
- }
- else
- {
- CLEARbit(evergreen->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
- }
-
- switch (ctx->Depth.Func)
- {
- case GL_NEVER:
- SETfield(evergreen->DB_DEPTH_CONTROL.u32All, FRAG_NEVER,
- ZFUNC_shift, ZFUNC_mask);
- break;
- case GL_LESS:
- SETfield(evergreen->DB_DEPTH_CONTROL.u32All, FRAG_LESS,
- ZFUNC_shift, ZFUNC_mask);
- break;
- case GL_EQUAL:
- SETfield(evergreen->DB_DEPTH_CONTROL.u32All, FRAG_EQUAL,
- ZFUNC_shift, ZFUNC_mask);
- break;
- case GL_LEQUAL:
- SETfield(evergreen->DB_DEPTH_CONTROL.u32All, FRAG_LEQUAL,
- ZFUNC_shift, ZFUNC_mask);
- break;
- case GL_GREATER:
- SETfield(evergreen->DB_DEPTH_CONTROL.u32All, FRAG_GREATER,
- ZFUNC_shift, ZFUNC_mask);
- break;
- case GL_NOTEQUAL:
- SETfield(evergreen->DB_DEPTH_CONTROL.u32All, FRAG_NOTEQUAL,
- ZFUNC_shift, ZFUNC_mask);
- break;
- case GL_GEQUAL:
- SETfield(evergreen->DB_DEPTH_CONTROL.u32All, FRAG_GEQUAL,
- ZFUNC_shift, ZFUNC_mask);
- break;
- case GL_ALWAYS:
- SETfield(evergreen->DB_DEPTH_CONTROL.u32All, FRAG_ALWAYS,
- ZFUNC_shift, ZFUNC_mask);
- break;
- default:
- SETfield(evergreen->DB_DEPTH_CONTROL.u32All, FRAG_ALWAYS,
- ZFUNC_shift, ZFUNC_mask);
- break;
- }
- }
- else
- {
- CLEARbit(evergreen->DB_DEPTH_CONTROL.u32All, Z_ENABLE_bit);
- CLEARbit(evergreen->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
- }
-}
-
-static void evergreenSetStencilState(struct gl_context * ctx, GLboolean state) //same
-{
- context_t *context = EVERGREEN_CONTEXT(ctx);
- EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
- GLboolean hw_stencil = GL_FALSE;
-
- if (ctx->DrawBuffer) {
- struct radeon_renderbuffer *rrbStencil
- = radeon_get_renderbuffer(ctx->DrawBuffer, BUFFER_STENCIL);
- hw_stencil = (rrbStencil && rrbStencil->bo);
- }
-
- if (hw_stencil) {
- EVERGREEN_STATECHANGE(context, db);
- if (state) {
- SETbit(evergreen->DB_DEPTH_CONTROL.u32All, STENCIL_ENABLE_bit);
- SETbit(evergreen->DB_DEPTH_CONTROL.u32All, BACKFACE_ENABLE_bit);
- SETbit(evergreen->DB_STENCIL_INFO.u32All, EG_DB_STENCIL_INFO__FORMAT_bit);
- } else
- CLEARbit(evergreen->DB_DEPTH_CONTROL.u32All, STENCIL_ENABLE_bit);
- }
-}
-
-static void evergreenUpdateCulling(struct gl_context * ctx) //same
-{
- context_t *context = EVERGREEN_CONTEXT(ctx);
- EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
-
- EVERGREEN_STATECHANGE(context, pa);
-
- CLEARbit(evergreen->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
- CLEARbit(evergreen->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
- CLEARbit(evergreen->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
-
- if (ctx->Polygon.CullFlag)
- {
- switch (ctx->Polygon.CullFaceMode)
- {
- case GL_FRONT:
- SETbit(evergreen->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
- CLEARbit(evergreen->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
- break;
- case GL_BACK:
- CLEARbit(evergreen->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
- SETbit(evergreen->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
- break;
- case GL_FRONT_AND_BACK:
- SETbit(evergreen->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
- SETbit(evergreen->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
- break;
- default:
- CLEARbit(evergreen->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
- CLEARbit(evergreen->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
- break;
- }
- }
-
- switch (ctx->Polygon.FrontFace)
- {
- case GL_CW:
- SETbit(evergreen->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
- break;
- case GL_CCW:
- CLEARbit(evergreen->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
- break;
- default:
- CLEARbit(evergreen->PA_SU_SC_MODE_CNTL.u32All, FACE_bit); /* default: ccw */
- break;
- }
-
- /* Winding is inverted when rendering to FBO */
- if (ctx->DrawBuffer && ctx->DrawBuffer->Name)
- evergreen->PA_SU_SC_MODE_CNTL.u32All ^= FACE_bit;
-}
-
-static void evergreenSetPolygonOffsetState(struct gl_context * ctx, GLboolean state) //same
-{
- context_t *context = EVERGREEN_CONTEXT(ctx);
- EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
-
- EVERGREEN_STATECHANGE(context, pa);
-
- if (state) {
- SETbit(evergreen->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_FRONT_ENABLE_bit);
- SETbit(evergreen->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_BACK_ENABLE_bit);
- SETbit(evergreen->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_PARA_ENABLE_bit);
- } else {
- CLEARbit(evergreen->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_FRONT_ENABLE_bit);
- CLEARbit(evergreen->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_BACK_ENABLE_bit);
- CLEARbit(evergreen->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_PARA_ENABLE_bit);
- }
-}
-
-static void evergreenUpdateLineStipple(struct gl_context * ctx) //diff
-{
- /* TODO */
-}
-
-void evergreenSetScissor(context_t *context) //diff
-{
- EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
- unsigned x1, y1, x2, y2;
- int id = 0;
- struct radeon_renderbuffer *rrb;
-
- rrb = radeon_get_colorbuffer(&context->radeon);
- if (!rrb || !rrb->bo) {
- return;
- }
- if (context->radeon.state.scissor.enabled) {
- x1 = context->radeon.state.scissor.rect.x1;
- y1 = context->radeon.state.scissor.rect.y1;
- x2 = context->radeon.state.scissor.rect.x2;
- y2 = context->radeon.state.scissor.rect.y2;
- /* r600 has exclusive BR scissors */
- if (context->radeon.radeonScreen->kernel_mm) {
- x2++;
- y2++;
- }
- } else {
- if (context->radeon.radeonScreen->driScreen->dri2.enabled) {
- x1 = 0;
- y1 = 0;
- x2 = rrb->base.Width;
- y2 = rrb->base.Height;
- } else {
- x1 = rrb->dPriv->x;
- y1 = rrb->dPriv->y;
- x2 = rrb->dPriv->x + rrb->dPriv->w;
- y2 = rrb->dPriv->y + rrb->dPriv->h;
- }
- }
-
- EVERGREEN_STATECHANGE(context, pa);
-
- /* screen */
- /* TODO : check WINDOW_OFFSET_DISABLE */
- //SETbit(evergreen->PA_SC_SCREEN_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
- SETfield(evergreen->PA_SC_SCREEN_SCISSOR_TL.u32All, x1,
- PA_SC_SCREEN_SCISSOR_TL__TL_X_shift, EG_PA_SC_SCREEN_SCISSOR_TL__TL_X_mask);
- SETfield(evergreen->PA_SC_SCREEN_SCISSOR_TL.u32All, y1,
- PA_SC_SCREEN_SCISSOR_TL__TL_Y_shift, EG_PA_SC_SCREEN_SCISSOR_TL__TL_Y_mask);
-
- SETfield(evergreen->PA_SC_SCREEN_SCISSOR_BR.u32All, x2,
- PA_SC_SCREEN_SCISSOR_BR__BR_X_shift, EG_PA_SC_SCREEN_SCISSOR_BR__BR_X_mask);
- SETfield(evergreen->PA_SC_SCREEN_SCISSOR_BR.u32All, y2,
- PA_SC_SCREEN_SCISSOR_BR__BR_Y_shift, EG_PA_SC_SCREEN_SCISSOR_BR__BR_Y_mask);
-
- /* window */
- SETbit(evergreen->PA_SC_WINDOW_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
- SETfield(evergreen->PA_SC_WINDOW_SCISSOR_TL.u32All, x1,
- PA_SC_WINDOW_SCISSOR_TL__TL_X_shift, EG_PA_SC_WINDOW_SCISSOR_TL__TL_X_mask);
- SETfield(evergreen->PA_SC_WINDOW_SCISSOR_TL.u32All, y1,
- PA_SC_WINDOW_SCISSOR_TL__TL_Y_shift, EG_PA_SC_WINDOW_SCISSOR_TL__TL_Y_mask);
-
- SETfield(evergreen->PA_SC_WINDOW_SCISSOR_BR.u32All, x2,
- PA_SC_WINDOW_SCISSOR_BR__BR_X_shift, EG_PA_SC_WINDOW_SCISSOR_BR__BR_X_mask);
- SETfield(evergreen->PA_SC_WINDOW_SCISSOR_BR.u32All, y2,
- PA_SC_WINDOW_SCISSOR_BR__BR_Y_shift, EG_PA_SC_WINDOW_SCISSOR_BR__BR_Y_mask);
-
-
- SETfield(evergreen->PA_SC_CLIPRECT_0_TL.u32All, x1,
- PA_SC_CLIPRECT_0_TL__TL_X_shift, EG_PA_SC_CLIPRECT_0_TL__TL_X_mask);
- SETfield(evergreen->PA_SC_CLIPRECT_0_TL.u32All, y1,
- PA_SC_CLIPRECT_0_TL__TL_Y_shift, EG_PA_SC_CLIPRECT_0_TL__TL_Y_mask);
- SETfield(evergreen->PA_SC_CLIPRECT_0_BR.u32All, x2,
- PA_SC_CLIPRECT_0_BR__BR_X_shift, EG_PA_SC_CLIPRECT_0_BR__BR_X_mask);
- SETfield(evergreen->PA_SC_CLIPRECT_0_BR.u32All, y2,
- PA_SC_CLIPRECT_0_BR__BR_Y_shift, EG_PA_SC_CLIPRECT_0_BR__BR_Y_mask);
-
- evergreen->PA_SC_CLIPRECT_1_TL.u32All = evergreen->PA_SC_CLIPRECT_0_TL.u32All;
- evergreen->PA_SC_CLIPRECT_1_BR.u32All = evergreen->PA_SC_CLIPRECT_0_BR.u32All;
- evergreen->PA_SC_CLIPRECT_2_TL.u32All = evergreen->PA_SC_CLIPRECT_0_TL.u32All;
- evergreen->PA_SC_CLIPRECT_2_BR.u32All = evergreen->PA_SC_CLIPRECT_0_BR.u32All;
- evergreen->PA_SC_CLIPRECT_3_TL.u32All = evergreen->PA_SC_CLIPRECT_0_TL.u32All;
- evergreen->PA_SC_CLIPRECT_3_BR.u32All = evergreen->PA_SC_CLIPRECT_0_BR.u32All;
-
- /* more....2d clip */
- SETbit(evergreen->PA_SC_GENERIC_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
- SETfield(evergreen->PA_SC_GENERIC_SCISSOR_TL.u32All, x1,
- PA_SC_GENERIC_SCISSOR_TL__TL_X_shift, EG_PA_SC_GENERIC_SCISSOR_TL__TL_X_mask);
- SETfield(evergreen->PA_SC_GENERIC_SCISSOR_TL.u32All, y1,
- PA_SC_GENERIC_SCISSOR_TL__TL_Y_shift, EG_PA_SC_GENERIC_SCISSOR_TL__TL_Y_mask);
- SETfield(evergreen->PA_SC_GENERIC_SCISSOR_BR.u32All, x2,
- PA_SC_GENERIC_SCISSOR_BR__BR_X_shift, EG_PA_SC_GENERIC_SCISSOR_BR__BR_X_mask);
- SETfield(evergreen->PA_SC_GENERIC_SCISSOR_BR.u32All, y2,
- PA_SC_GENERIC_SCISSOR_BR__BR_Y_shift, EG_PA_SC_GENERIC_SCISSOR_BR__BR_Y_mask);
-
- SETbit(evergreen->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
- SETfield(evergreen->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, x1,
- PA_SC_VPORT_SCISSOR_0_TL__TL_X_shift, EG_PA_SC_VPORT_SCISSOR_0_TL__TL_X_mask);
- SETfield(evergreen->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, y1,
- PA_SC_VPORT_SCISSOR_0_TL__TL_Y_shift, EG_PA_SC_VPORT_SCISSOR_0_TL__TL_Y_mask);
- SETfield(evergreen->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All, x2,
- PA_SC_VPORT_SCISSOR_0_BR__BR_X_shift, EG_PA_SC_VPORT_SCISSOR_0_BR__BR_X_mask);
- SETfield(evergreen->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All, y2,
- PA_SC_VPORT_SCISSOR_0_BR__BR_Y_shift, EG_PA_SC_VPORT_SCISSOR_0_BR__BR_Y_mask);
-
- id = 1;
- SETbit(evergreen->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
- SETfield(evergreen->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, x1,
- PA_SC_VPORT_SCISSOR_0_TL__TL_X_shift, EG_PA_SC_VPORT_SCISSOR_0_TL__TL_X_mask);
- SETfield(evergreen->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, y1,
- PA_SC_VPORT_SCISSOR_0_TL__TL_Y_shift, EG_PA_SC_VPORT_SCISSOR_0_TL__TL_Y_mask);
- SETfield(evergreen->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All, x2,
- PA_SC_VPORT_SCISSOR_0_BR__BR_X_shift, EG_PA_SC_VPORT_SCISSOR_0_BR__BR_X_mask);
- SETfield(evergreen->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All, y2,
- PA_SC_VPORT_SCISSOR_0_BR__BR_Y_shift, EG_PA_SC_VPORT_SCISSOR_0_BR__BR_Y_mask);
-
- evergreen->viewport[id].enabled = GL_TRUE;
-}
-
-static void evergreenUpdateWindow(struct gl_context * ctx, int id) //diff in calling evergreenSetScissor
-{
- context_t *context = EVERGREEN_CONTEXT(ctx);
- EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
- __DRIdrawable *dPriv = radeon_get_drawable(&context->radeon);
- GLfloat xoffset = dPriv ? (GLfloat) dPriv->x : 0;
- GLfloat yoffset = dPriv ? (GLfloat) dPriv->y + dPriv->h : 0;
- const GLfloat *v = ctx->Viewport._WindowMap.m;
- const GLfloat depthScale = 1.0F / ctx->DrawBuffer->_DepthMaxF;
- const GLboolean render_to_fbo = (ctx->DrawBuffer->Name != 0);
- GLfloat y_scale, y_bias;
-
- if (render_to_fbo) {
- y_scale = 1.0;
- y_bias = 0;
- } else {
- y_scale = -1.0;
- y_bias = yoffset;
- }
-
- GLfloat sx = v[MAT_SX];
- GLfloat tx = v[MAT_TX] + xoffset;
- GLfloat sy = v[MAT_SY] * y_scale;
- GLfloat ty = (v[MAT_TY] * y_scale) + y_bias;
- GLfloat sz = v[MAT_SZ] * depthScale;
- GLfloat tz = v[MAT_TZ] * depthScale;
-
- EVERGREEN_STATECHANGE(context, pa);
-
-
- evergreen->viewport[id].PA_CL_VPORT_XSCALE.f32All = sx;
- evergreen->viewport[id].PA_CL_VPORT_XOFFSET.f32All = tx;
-
- evergreen->viewport[id].PA_CL_VPORT_YSCALE.f32All = sy;
- evergreen->viewport[id].PA_CL_VPORT_YOFFSET.f32All = ty;
-
- evergreen->viewport[id].PA_CL_VPORT_ZSCALE.f32All = sz;
- evergreen->viewport[id].PA_CL_VPORT_ZOFFSET.f32All = tz;
-
- if (ctx->Transform.DepthClamp) {
- evergreen->viewport[id].PA_SC_VPORT_ZMIN_0.f32All = MIN2(ctx->Viewport.Near, ctx->Viewport.Far);
- evergreen->viewport[id].PA_SC_VPORT_ZMAX_0.f32All = MAX2(ctx->Viewport.Near, ctx->Viewport.Far);
- SETbit(evergreen->PA_CL_CLIP_CNTL.u32All, ZCLIP_NEAR_DISABLE_bit);
- SETbit(evergreen->PA_CL_CLIP_CNTL.u32All, ZCLIP_FAR_DISABLE_bit);
- } else {
- evergreen->viewport[id].PA_SC_VPORT_ZMIN_0.f32All = 0.0;
- evergreen->viewport[id].PA_SC_VPORT_ZMAX_0.f32All = 1.0;
- CLEARbit(evergreen->PA_CL_CLIP_CNTL.u32All, ZCLIP_NEAR_DISABLE_bit);
- CLEARbit(evergreen->PA_CL_CLIP_CNTL.u32All, ZCLIP_FAR_DISABLE_bit);
- }
-
- evergreen->viewport[id].enabled = GL_TRUE;
-
- evergreenSetScissor(context);
-}
-
-static void evergreenEnable(struct gl_context * ctx, GLenum cap, GLboolean state) //diff in func calls
-{
- context_t *context = EVERGREEN_CONTEXT(ctx);
-
- switch (cap) {
- case GL_TEXTURE_1D:
- case GL_TEXTURE_2D:
- case GL_TEXTURE_3D:
- /* empty */
- break;
- case GL_FOG:
- /* empty */
- break;
- case GL_ALPHA_TEST:
- evergreenSetAlphaState(ctx);
- break;
- case GL_COLOR_LOGIC_OP:
- evergreenSetLogicOpState(ctx);
- /* fall-through, because logic op overrides blending */
- case GL_BLEND:
- evergreenSetBlendState(ctx);
- break;
- case GL_CLIP_PLANE0:
- case GL_CLIP_PLANE1:
- case GL_CLIP_PLANE2:
- case GL_CLIP_PLANE3:
- case GL_CLIP_PLANE4:
- case GL_CLIP_PLANE5:
- evergreenSetClipPlaneState(ctx, cap, state);
- break;
- case GL_DEPTH_TEST:
- evergreenSetDepthState(ctx);
- break;
- case GL_STENCIL_TEST:
- evergreenSetStencilState(ctx, state);
- break;
- case GL_CULL_FACE:
- evergreenUpdateCulling(ctx);
- break;
- case GL_POLYGON_OFFSET_POINT:
- case GL_POLYGON_OFFSET_LINE:
- case GL_POLYGON_OFFSET_FILL:
- evergreenSetPolygonOffsetState(ctx, state);
- break;
- case GL_SCISSOR_TEST:
- radeon_firevertices(&context->radeon);
- context->radeon.state.scissor.enabled = state;
- radeonUpdateScissor(ctx);
- break;
- case GL_LINE_STIPPLE:
- evergreenUpdateLineStipple(ctx);
- break;
- case GL_DEPTH_CLAMP:
- evergreenUpdateWindow(ctx, 0);
- break;
- default:
- break;
- }
-
-}
-
-static void evergreenColorMask(struct gl_context * ctx,
- GLboolean r, GLboolean g, GLboolean b, GLboolean a) //same
-{
- context_t *context = EVERGREEN_CONTEXT(ctx);
- EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
- unsigned int mask = ((r ? 1 : 0) |
- (g ? 2 : 0) |
- (b ? 4 : 0) |
- (a ? 8 : 0));
-
- if (mask != evergreen->CB_TARGET_MASK.u32All) {
- EVERGREEN_STATECHANGE(context, cb);
- SETfield(evergreen->CB_TARGET_MASK.u32All, mask, TARGET0_ENABLE_shift, TARGET0_ENABLE_mask);
- }
-}
-
-static void evergreenDepthFunc(struct gl_context * ctx, GLenum func) //same
-{
- evergreenSetDepthState(ctx);
-}
-
-static void evergreenDepthMask(struct gl_context * ctx, GLboolean mask) //same
-{
- evergreenSetDepthState(ctx);
-}
-
-static void evergreenCullFace(struct gl_context * ctx, GLenum mode) //same
-{
- evergreenUpdateCulling(ctx);
-}
-
-static void evergreenFogfv(struct gl_context * ctx, GLenum pname, const GLfloat * param) //same
-{
-}
-
-static void evergreenUpdatePolygonMode(struct gl_context * ctx) //same
-{
- context_t *context = EVERGREEN_CONTEXT(ctx);
- EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
-
- EVERGREEN_STATECHANGE(context, pa);
-
- SETfield(evergreen->PA_SU_SC_MODE_CNTL.u32All, X_DISABLE_POLY_MODE, POLY_MODE_shift, POLY_MODE_mask);
-
- /* Only do something if a polygon mode is wanted, default is GL_FILL */
- if (ctx->Polygon.FrontMode != GL_FILL ||
- ctx->Polygon.BackMode != GL_FILL) {
- GLenum f, b;
-
- /* Handle GL_CW (clock wise and GL_CCW (counter clock wise)
- * correctly by selecting the correct front and back face
- */
- f = ctx->Polygon.FrontMode;
- b = ctx->Polygon.BackMode;
-
- /* Enable polygon mode */
- SETfield(evergreen->PA_SU_SC_MODE_CNTL.u32All, X_DUAL_MODE, POLY_MODE_shift, POLY_MODE_mask);
-
- switch (f) {
- case GL_LINE:
- SETfield(evergreen->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_LINES,
- POLYMODE_FRONT_PTYPE_shift, POLYMODE_FRONT_PTYPE_mask);
- break;
- case GL_POINT:
- SETfield(evergreen->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_POINTS,
- POLYMODE_FRONT_PTYPE_shift, POLYMODE_FRONT_PTYPE_mask);
- break;
- case GL_FILL:
- SETfield(evergreen->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_TRIANGLES,
- POLYMODE_FRONT_PTYPE_shift, POLYMODE_FRONT_PTYPE_mask);
- break;
- }
-
- switch (b) {
- case GL_LINE:
- SETfield(evergreen->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_LINES,
- POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask);
- break;
- case GL_POINT:
- SETfield(evergreen->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_POINTS,
- POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask);
- break;
- case GL_FILL:
- SETfield(evergreen->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_TRIANGLES,
- POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask);
- break;
- }
- }
-}
-
-static void evergreenFrontFace(struct gl_context * ctx, GLenum mode) //same
-{
- evergreenUpdateCulling(ctx);
- evergreenUpdatePolygonMode(ctx);
-}
-
-static void evergreenShadeModel(struct gl_context * ctx, GLenum mode) //same
-{
- context_t *context = EVERGREEN_CONTEXT(ctx);
- EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
-
- EVERGREEN_STATECHANGE(context, spi);
-
- /* also need to set/clear FLAT_SHADE bit per param in SPI_PS_INPUT_CNTL_[0-31] */
- switch (mode) {
- case GL_FLAT:
- SETbit(evergreen->SPI_INTERP_CONTROL_0.u32All, FLAT_SHADE_ENA_bit);
- break;
- case GL_SMOOTH:
- CLEARbit(evergreen->SPI_INTERP_CONTROL_0.u32All, FLAT_SHADE_ENA_bit);
- break;
- default:
- return;
- }
-}
-
-static void evergreenLogicOpcode(struct gl_context *ctx, GLenum logicop) //diff
-{
- if (ctx->Color.ColorLogicOpEnabled)
- evergreenSetLogicOpState(ctx);
-}
-
-static void evergreenPointSize(struct gl_context * ctx, GLfloat size) //same
-{
- context_t *context = EVERGREEN_CONTEXT(ctx);
- EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
-
- EVERGREEN_STATECHANGE(context, pa);
-
- /* We need to clamp to user defined range here, because
- * the HW clamping happens only for per vertex point size. */
- size = CLAMP(size, ctx->Point.MinSize, ctx->Point.MaxSize);
-
- /* same size limits for AA, non-AA points */
- size = CLAMP(size, ctx->Const.MinPointSize, ctx->Const.MaxPointSize);
-
- /* format is 12.4 fixed point */
- SETfield(evergreen->PA_SU_POINT_SIZE.u32All, (int)(size * 8.0),
- PA_SU_POINT_SIZE__HEIGHT_shift, PA_SU_POINT_SIZE__HEIGHT_mask);
- SETfield(evergreen->PA_SU_POINT_SIZE.u32All, (int)(size * 8.0),
- PA_SU_POINT_SIZE__WIDTH_shift, PA_SU_POINT_SIZE__WIDTH_mask);
-
-}
-
-static void evergreenPointParameter(struct gl_context * ctx, GLenum pname, const GLfloat * param) //same
-{
- context_t *context = EVERGREEN_CONTEXT(ctx);
- EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
-
- EVERGREEN_STATECHANGE(context, pa);
-
- /* format is 12.4 fixed point */
- switch (pname) {
- case GL_POINT_SIZE_MIN:
- SETfield(evergreen->PA_SU_POINT_MINMAX.u32All, (int)(ctx->Point.MinSize * 8.0),
- MIN_SIZE_shift, MIN_SIZE_mask);
- evergreenPointSize(ctx, ctx->Point.Size);
- break;
- case GL_POINT_SIZE_MAX:
- SETfield(evergreen->PA_SU_POINT_MINMAX.u32All, (int)(ctx->Point.MaxSize * 8.0),
- MAX_SIZE_shift, MAX_SIZE_mask);
- evergreenPointSize(ctx, ctx->Point.Size);
- break;
- case GL_POINT_DISTANCE_ATTENUATION:
- break;
- case GL_POINT_FADE_THRESHOLD_SIZE:
- break;
- default:
- break;
- }
-}
-
-static int evergreen_translate_stencil_func(int func) //same
-{
- switch (func) {
- case GL_NEVER:
- return REF_NEVER;
- case GL_LESS:
- return REF_LESS;
- case GL_EQUAL:
- return REF_EQUAL;
- case GL_LEQUAL:
- return REF_LEQUAL;
- case GL_GREATER:
- return REF_GREATER;
- case GL_NOTEQUAL:
- return REF_NOTEQUAL;
- case GL_GEQUAL:
- return REF_GEQUAL;
- case GL_ALWAYS:
- return REF_ALWAYS;
- }
- return 0;
-}
-
-static void evergreenStencilFuncSeparate(struct gl_context * ctx, GLenum face,
- GLenum func, GLint ref, GLuint mask) //same
-{
- context_t *context = EVERGREEN_CONTEXT(ctx);
- EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
- const unsigned back = ctx->Stencil._BackFace;
-
-
- EVERGREEN_STATECHANGE(context, db);
-
- //front
- SETfield(evergreen->DB_STENCILREFMASK.u32All, ctx->Stencil.Ref[0],
- STENCILREF_shift, STENCILREF_mask);
- SETfield(evergreen->DB_STENCILREFMASK.u32All, ctx->Stencil.ValueMask[0],
- STENCILMASK_shift, STENCILMASK_mask);
-
- SETfield(evergreen->DB_DEPTH_CONTROL.u32All, evergreen_translate_stencil_func(ctx->Stencil.Function[0]),
- STENCILFUNC_shift, STENCILFUNC_mask);
-
- //back
- SETfield(evergreen->DB_STENCILREFMASK_BF.u32All, ctx->Stencil.Ref[back],
- STENCILREF_BF_shift, STENCILREF_BF_mask);
- SETfield(evergreen->DB_STENCILREFMASK_BF.u32All, ctx->Stencil.ValueMask[back],
- STENCILMASK_BF_shift, STENCILMASK_BF_mask);
-
- SETfield(evergreen->DB_DEPTH_CONTROL.u32All, evergreen_translate_stencil_func(ctx->Stencil.Function[back]),
- STENCILFUNC_BF_shift, STENCILFUNC_BF_mask);
-}
-
-static void evergreenStencilMaskSeparate(struct gl_context * ctx, GLenum face, GLuint mask) //same
-{
- context_t *context = EVERGREEN_CONTEXT(ctx);
- EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
- const unsigned back = ctx->Stencil._BackFace;
-
- EVERGREEN_STATECHANGE(context, db);
-
- // front
- SETfield(evergreen->DB_STENCILREFMASK.u32All, ctx->Stencil.WriteMask[0],
- STENCILWRITEMASK_shift, STENCILWRITEMASK_mask);
-
- // back
- SETfield(evergreen->DB_STENCILREFMASK_BF.u32All, ctx->Stencil.WriteMask[back],
- STENCILWRITEMASK_BF_shift, STENCILWRITEMASK_BF_mask);
-
-}
-
-static int evergreen_translate_stencil_op(int op) //same
-{
- switch (op) {
- case GL_KEEP:
- return STENCIL_KEEP;
- case GL_ZERO:
- return STENCIL_ZERO;
- case GL_REPLACE:
- return STENCIL_REPLACE;
- case GL_INCR:
- return STENCIL_INCR_CLAMP;
- case GL_DECR:
- return STENCIL_DECR_CLAMP;
- case GL_INCR_WRAP_EXT:
- return STENCIL_INCR_WRAP;
- case GL_DECR_WRAP_EXT:
- return STENCIL_DECR_WRAP;
- case GL_INVERT:
- return STENCIL_INVERT;
- default:
- WARN_ONCE("Do not know how to translate stencil op");
- return STENCIL_KEEP;
- }
- return 0;
-}
-
-static void evergreenStencilOpSeparate(struct gl_context * ctx, GLenum face,
- GLenum fail, GLenum zfail, GLenum zpass) //same
-{
- context_t *context = EVERGREEN_CONTEXT(ctx);
- EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
- const unsigned back = ctx->Stencil._BackFace;
-
- EVERGREEN_STATECHANGE(context, db);
-
- SETfield(evergreen->DB_DEPTH_CONTROL.u32All, evergreen_translate_stencil_op(ctx->Stencil.FailFunc[0]),
- STENCILFAIL_shift, STENCILFAIL_mask);
- SETfield(evergreen->DB_DEPTH_CONTROL.u32All, evergreen_translate_stencil_op(ctx->Stencil.ZFailFunc[0]),
- STENCILZFAIL_shift, STENCILZFAIL_mask);
- SETfield(evergreen->DB_DEPTH_CONTROL.u32All, evergreen_translate_stencil_op(ctx->Stencil.ZPassFunc[0]),
- STENCILZPASS_shift, STENCILZPASS_mask);
-
- SETfield(evergreen->DB_DEPTH_CONTROL.u32All, evergreen_translate_stencil_op(ctx->Stencil.FailFunc[back]),
- STENCILFAIL_BF_shift, STENCILFAIL_BF_mask);
- SETfield(evergreen->DB_DEPTH_CONTROL.u32All, evergreen_translate_stencil_op(ctx->Stencil.ZFailFunc[back]),
- STENCILZFAIL_BF_shift, STENCILZFAIL_BF_mask);
- SETfield(evergreen->DB_DEPTH_CONTROL.u32All, evergreen_translate_stencil_op(ctx->Stencil.ZPassFunc[back]),
- STENCILZPASS_BF_shift, STENCILZPASS_BF_mask);
-}
-
-static void evergreenViewport(struct gl_context * ctx,
- GLint x,
- GLint y,
- GLsizei width,
- GLsizei height) //diff in evergreenUpdateWindow
-{
- evergreenUpdateWindow(ctx, 0);
-
- radeon_viewport(ctx, x, y, width, height);
-}
-
-static void evergreenDepthRange(struct gl_context * ctx, GLclampd nearval, GLclampd farval) //diff in evergreenUpdateWindow
-{
- evergreenUpdateWindow(ctx, 0);
-}
-
-static void evergreenLineWidth(struct gl_context * ctx, GLfloat widthf) //same
-{
- context_t *context = EVERGREEN_CONTEXT(ctx);
- EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
- uint32_t lineWidth = (uint32_t)((widthf * 0.5) * (1 << 4));
-
- EVERGREEN_STATECHANGE(context, pa);
-
- if (lineWidth > 0xFFFF)
- lineWidth = 0xFFFF;
- SETfield(evergreen->PA_SU_LINE_CNTL.u32All,(uint16_t)lineWidth,
- PA_SU_LINE_CNTL__WIDTH_shift, PA_SU_LINE_CNTL__WIDTH_mask);
-}
-
-static void evergreenLineStipple(struct gl_context *ctx, GLint factor, GLushort pattern) //same
-{
- context_t *context = EVERGREEN_CONTEXT(ctx);
- EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
-
- EVERGREEN_STATECHANGE(context, pa);
-
- SETfield(evergreen->PA_SC_LINE_STIPPLE.u32All, pattern, LINE_PATTERN_shift, LINE_PATTERN_mask);
- SETfield(evergreen->PA_SC_LINE_STIPPLE.u32All, (factor-1), REPEAT_COUNT_shift, REPEAT_COUNT_mask);
- SETfield(evergreen->PA_SC_LINE_STIPPLE.u32All, 1, AUTO_RESET_CNTL_shift, AUTO_RESET_CNTL_mask);
-}
-
-static void evergreenPolygonOffset(struct gl_context * ctx, GLfloat factor, GLfloat units) //diff :
- //all register here offset diff, bits same
-{
- context_t *context = EVERGREEN_CONTEXT(ctx);
- EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
- GLfloat constant = units;
- GLchar depth = 0;
-
- EVERGREEN_STATECHANGE(context, pa);
-
- switch (ctx->Visual.depthBits) {
- case 16:
- constant *= 4.0;
- depth = -16;
- break;
- case 24:
- constant *= 2.0;
- depth = -24;
- break;
- }
-
- factor *= 12.0;
- SETfield(evergreen->PA_SU_POLY_OFFSET_DB_FMT_CNTL.u32All, depth,
- POLY_OFFSET_NEG_NUM_DB_BITS_shift, POLY_OFFSET_NEG_NUM_DB_BITS_mask);
- //evergreen->PA_SU_POLY_OFFSET_CLAMP.f32All = constant; //???
- evergreen->PA_SU_POLY_OFFSET_FRONT_SCALE.f32All = factor;
- evergreen->PA_SU_POLY_OFFSET_FRONT_OFFSET.f32All = constant;
- evergreen->PA_SU_POLY_OFFSET_BACK_SCALE.f32All = factor;
- evergreen->PA_SU_POLY_OFFSET_BACK_OFFSET.f32All = constant;
-}
-
-static void evergreenPolygonMode(struct gl_context * ctx, GLenum face, GLenum mode) //same
-{
- (void)face;
- (void)mode;
-
- evergreenUpdatePolygonMode(ctx);
-}
-
-static void evergreenRenderMode(struct gl_context * ctx, GLenum mode) //same
-{
-}
-
-//TODO : move to kernel.
-static void evergreenInitSQConfig(struct gl_context * ctx)
-{
- context_t *context = EVERGREEN_CONTEXT(ctx);
- EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
-
- uint32_t uSqNumCfInsts, uMaxGPRs, uMaxThreads, uMaxStackEntries, uPSThreadCount, uOtherThreadCount;
- uint32_t NUM_PS_GPRS, NUM_VS_GPRS, NUM_GS_GPRS, NUM_ES_GPRS, NUM_HS_GPRS, NUM_LS_GPRS, NUM_CLAUSE_TEMP_GPRS;
- GLboolean bVC_ENABLE = GL_TRUE;
-
- R600_STATECHANGE(context, sq);
-
- switch (context->radeon.radeonScreen->chip_family)
- {
- case CHIP_FAMILY_CEDAR:
- uSqNumCfInsts = 1;
- bVC_ENABLE = GL_FALSE;
- uMaxGPRs = 256;
- uPSThreadCount = 96;
- uMaxThreads = 192;
- uMaxStackEntries = 256;
- break;
- case CHIP_FAMILY_REDWOOD:
- uSqNumCfInsts = 2;
- bVC_ENABLE = GL_TRUE;
- uMaxGPRs = 256;
- uPSThreadCount = 128;
- uMaxThreads = 248;
- uMaxStackEntries = 256;
- break;
- case CHIP_FAMILY_JUNIPER:
- uSqNumCfInsts = 2;
- bVC_ENABLE = GL_TRUE;
- uMaxGPRs = 256;
- uPSThreadCount = 128;
- uMaxThreads = 248;
- uMaxStackEntries = 512;
- break;
- case CHIP_FAMILY_CYPRESS:
- uSqNumCfInsts = 2;
- bVC_ENABLE = GL_TRUE;
- uMaxGPRs = 256;
- uPSThreadCount = 128;
- uMaxThreads = 248;
- uMaxStackEntries = 512;
- break;
- case CHIP_FAMILY_HEMLOCK:
- uSqNumCfInsts = 2;//?
- bVC_ENABLE = GL_TRUE;
- uMaxGPRs = 256;
- uPSThreadCount = 128;
- uMaxThreads = 248;
- uMaxStackEntries = 512;
- break;
- case CHIP_FAMILY_PALM:
- uSqNumCfInsts = 1;
- bVC_ENABLE = GL_FALSE;
- uMaxGPRs = 256;
- uPSThreadCount = 96;
- uMaxThreads = 192;
- uMaxStackEntries = 256;
- break;
- case CHIP_FAMILY_SUMO:
- uSqNumCfInsts = 2;
- bVC_ENABLE = GL_FALSE;
- uMaxGPRs = 256;
- uPSThreadCount = 96;
- uMaxThreads = 248;
- uMaxStackEntries = 256;
- break;
- case CHIP_FAMILY_SUMO2:
- uSqNumCfInsts = 2;
- bVC_ENABLE = GL_FALSE;
- uMaxGPRs = 256;
- uPSThreadCount = 96;
- uMaxThreads = 248;
- uMaxStackEntries = 512;
- break;
- case CHIP_FAMILY_BARTS:
- uSqNumCfInsts = 2;
- bVC_ENABLE = GL_TRUE;
- uMaxGPRs = 256;
- uPSThreadCount = 128;
- uMaxThreads = 248;
- uMaxStackEntries = 512;
- break;
- case CHIP_FAMILY_TURKS:
- uSqNumCfInsts = 2;
- bVC_ENABLE = GL_TRUE;
- uMaxGPRs = 256;
- uPSThreadCount = 128;
- uMaxThreads = 248;
- uMaxStackEntries = 256;
- break;
- case CHIP_FAMILY_CAICOS:
- uSqNumCfInsts = 1;
- bVC_ENABLE = GL_FALSE;
- uMaxGPRs = 256;
- uPSThreadCount = 128;
- uMaxThreads = 192;
- uMaxStackEntries = 256;
- break;
- default:
- uSqNumCfInsts = 2;
- bVC_ENABLE = GL_TRUE;
- uMaxGPRs = 256;
- uPSThreadCount = 128;
- uMaxThreads = 248;
- uMaxStackEntries = 512;
- break;
- }
-
- evergreen->evergreen_config.SQ_DYN_GPR_CNTL_PS_FLUSH_REQ.u32All = 0;
-
- evergreen->evergreen_config.SPI_CONFIG_CNTL.u32All = 0;
- evergreen->evergreen_config.SPI_CONFIG_CNTL_1.u32All = 0;
- SETfield(evergreen->evergreen_config.SPI_CONFIG_CNTL_1.u32All, 4,
- EG_SPI_CONFIG_CNTL_1__VTX_DONE_DELAY_shift,
- EG_SPI_CONFIG_CNTL_1__VTX_DONE_DELAY_mask);
-
- evergreen->evergreen_config.CP_PERFMON_CNTL.u32All = 0;
-
- evergreen->evergreen_config.SQ_MS_FIFO_SIZES.u32All = 0;
- SETfield(evergreen->evergreen_config.SQ_MS_FIFO_SIZES.u32All, 16 * uSqNumCfInsts,
- EG_SQ_MS_FIFO_SIZES__CACHE_FIFO_SIZE_shift,
- EG_SQ_MS_FIFO_SIZES__CACHE_FIFO_SIZE_mask);
- SETfield(evergreen->evergreen_config.SQ_MS_FIFO_SIZES.u32All, 0x4,
- EG_SQ_MS_FIFO_SIZES__FETCH_FIFO_HIWATER_shift,
- EG_SQ_MS_FIFO_SIZES__FETCH_FIFO_HIWATER_mask);
- SETfield(evergreen->evergreen_config.SQ_MS_FIFO_SIZES.u32All, 0xE0,
- EG_SQ_MS_FIFO_SIZES__DONE_FIFO_HIWATER_shift,
- EG_SQ_MS_FIFO_SIZES__DONE_FIFO_HIWATER_mask);
- SETfield(evergreen->evergreen_config.SQ_MS_FIFO_SIZES.u32All, 0x8,
- EG_SQ_MS_FIFO_SIZES__ALU_UPDATE_FIFO_HIWATER_shift,
- EG_SQ_MS_FIFO_SIZES__ALU_UPDATE_FIFO_HIWATER_mask);
-
- if(bVC_ENABLE == GL_TRUE)
- {
- SETbit(evergreen->evergreen_config.SQ_CONFIG.u32All,
- EG_SQ_CONFIG__VC_ENABLE_bit);
- }
- else
- {
- CLEARbit(evergreen->evergreen_config.SQ_CONFIG.u32All,
- EG_SQ_CONFIG__VC_ENABLE_bit);
- }
- SETbit(evergreen->evergreen_config.SQ_CONFIG.u32All,
- EG_SQ_CONFIG__EXPORT_SRC_C_bit);
- SETfield(evergreen->evergreen_config.SQ_CONFIG.u32All, 0,
- EG_SQ_CONFIG__PS_PRIO_shift,
- EG_SQ_CONFIG__PS_PRIO_mask);
- SETfield(evergreen->evergreen_config.SQ_CONFIG.u32All, 1,
- EG_SQ_CONFIG__VS_PRIO_shift,
- EG_SQ_CONFIG__VS_PRIO_mask);
- SETfield(evergreen->evergreen_config.SQ_CONFIG.u32All, 2,
- EG_SQ_CONFIG__GS_PRIO_shift,
- EG_SQ_CONFIG__GS_PRIO_mask);
- SETfield(evergreen->evergreen_config.SQ_CONFIG.u32All, 3,
- EG_SQ_CONFIG__ES_PRIO_shift,
- EG_SQ_CONFIG__ES_PRIO_mask);
-
- NUM_CLAUSE_TEMP_GPRS = 4;
- NUM_PS_GPRS = ((uMaxGPRs-(4*2))*12/32); // 93
- NUM_VS_GPRS = ((uMaxGPRs-(4*2))*6/32); // 46
- NUM_GS_GPRS = ((uMaxGPRs-(4*2))*4/32); // 31
- NUM_ES_GPRS = ((uMaxGPRs-(4*2))*4/32); // 31
- NUM_HS_GPRS = ((uMaxGPRs-(4*2))*3/32); // 23
- NUM_LS_GPRS = ((uMaxGPRs-(4*2))*3/32); // 23
-
- evergreen->evergreen_config.SQ_GPR_RESOURCE_MGMT_1.u32All = 0;
- evergreen->evergreen_config.SQ_GPR_RESOURCE_MGMT_2.u32All = 0;
- evergreen->evergreen_config.SQ_GPR_RESOURCE_MGMT_3.u32All = 0;
-
- SETfield(evergreen->evergreen_config.SQ_GPR_RESOURCE_MGMT_1.u32All, NUM_PS_GPRS,
- NUM_PS_GPRS_shift, NUM_PS_GPRS_mask);
- SETfield(evergreen->evergreen_config.SQ_GPR_RESOURCE_MGMT_1.u32All, NUM_VS_GPRS,
- NUM_VS_GPRS_shift, NUM_VS_GPRS_mask);
- SETfield(evergreen->evergreen_config.SQ_GPR_RESOURCE_MGMT_1.u32All, NUM_CLAUSE_TEMP_GPRS,
- NUM_CLAUSE_TEMP_GPRS_shift, NUM_CLAUSE_TEMP_GPRS_mask);
- SETfield(evergreen->evergreen_config.SQ_GPR_RESOURCE_MGMT_2.u32All, NUM_GS_GPRS,
- NUM_GS_GPRS_shift, NUM_GS_GPRS_mask);
- SETfield(evergreen->evergreen_config.SQ_GPR_RESOURCE_MGMT_2.u32All, NUM_ES_GPRS,
- NUM_ES_GPRS_shift, NUM_ES_GPRS_mask);
- SETfield(evergreen->evergreen_config.SQ_GPR_RESOURCE_MGMT_3.u32All, NUM_HS_GPRS,
- NUM_PS_GPRS_shift, NUM_PS_GPRS_mask);
- SETfield(evergreen->evergreen_config.SQ_GPR_RESOURCE_MGMT_3.u32All, NUM_LS_GPRS,
- NUM_VS_GPRS_shift, NUM_VS_GPRS_mask);
-
- uOtherThreadCount = (((uMaxThreads-uPSThreadCount)/6)/8)*8;
- evergreen->evergreen_config.SQ_THREAD_RESOURCE_MGMT.u32All = 0;
- evergreen->evergreen_config.SQ_THREAD_RESOURCE_MGMT_2.u32All = 0;
- SETfield(evergreen->evergreen_config.SQ_THREAD_RESOURCE_MGMT.u32All, uPSThreadCount,
- NUM_PS_THREADS_shift, NUM_PS_THREADS_mask);
- SETfield(evergreen->evergreen_config.SQ_THREAD_RESOURCE_MGMT.u32All, uOtherThreadCount,
- NUM_VS_THREADS_shift, NUM_VS_THREADS_mask);
- SETfield(evergreen->evergreen_config.SQ_THREAD_RESOURCE_MGMT.u32All, uOtherThreadCount,
- NUM_GS_THREADS_shift, NUM_GS_THREADS_mask);
- SETfield(evergreen->evergreen_config.SQ_THREAD_RESOURCE_MGMT.u32All, uOtherThreadCount,
- NUM_ES_THREADS_shift, NUM_ES_THREADS_mask);
- SETfield(evergreen->evergreen_config.SQ_THREAD_RESOURCE_MGMT_2.u32All, uOtherThreadCount,
- NUM_PS_THREADS_shift, NUM_PS_THREADS_mask);
- SETfield(evergreen->evergreen_config.SQ_THREAD_RESOURCE_MGMT_2.u32All, uOtherThreadCount,
- NUM_VS_THREADS_shift, NUM_VS_THREADS_mask);
-
- uMaxStackEntries = ((uMaxStackEntries*1)/6);
- evergreen->evergreen_config.SQ_STACK_RESOURCE_MGMT_1.u32All = 0;
- evergreen->evergreen_config.SQ_STACK_RESOURCE_MGMT_2.u32All = 0;
- evergreen->evergreen_config.SQ_STACK_RESOURCE_MGMT_3.u32All = 0;
- SETfield(evergreen->evergreen_config.SQ_STACK_RESOURCE_MGMT_1.u32All, uMaxStackEntries,
- NUM_PS_STACK_ENTRIES_shift, NUM_PS_STACK_ENTRIES_mask);
- SETfield(evergreen->evergreen_config.SQ_STACK_RESOURCE_MGMT_1.u32All, uMaxStackEntries,
- NUM_VS_STACK_ENTRIES_shift, NUM_VS_STACK_ENTRIES_mask);
- SETfield(evergreen->evergreen_config.SQ_STACK_RESOURCE_MGMT_2.u32All, uMaxStackEntries,
- NUM_GS_STACK_ENTRIES_shift, NUM_GS_STACK_ENTRIES_mask);
- SETfield(evergreen->evergreen_config.SQ_STACK_RESOURCE_MGMT_2.u32All, uMaxStackEntries,
- NUM_ES_STACK_ENTRIES_shift, NUM_ES_STACK_ENTRIES_mask);
- SETfield(evergreen->evergreen_config.SQ_STACK_RESOURCE_MGMT_3.u32All, uMaxStackEntries,
- NUM_PS_STACK_ENTRIES_shift, NUM_PS_STACK_ENTRIES_mask);
- SETfield(evergreen->evergreen_config.SQ_STACK_RESOURCE_MGMT_3.u32All, uMaxStackEntries,
- NUM_VS_STACK_ENTRIES_shift, NUM_VS_STACK_ENTRIES_mask);
-
- evergreen->evergreen_config.PA_SC_FORCE_EOV_MAX_CNTS.u32All = 0;
- SETfield(evergreen->evergreen_config.PA_SC_FORCE_EOV_MAX_CNTS.u32All, 4095,
- EG_PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT_shift,
- EG_PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT_mask);
- SETfield(evergreen->evergreen_config.PA_SC_FORCE_EOV_MAX_CNTS.u32All, 255,
- EG_PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT_shift,
- EG_PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT_mask);
-
- evergreen->evergreen_config.VGT_CACHE_INVALIDATION.u32All = 0;
- SETfield(evergreen->evergreen_config.VGT_CACHE_INVALIDATION.u32All, 2,
- EG_VGT_CACHE_INVALIDATION__CACHE_INVALIDATION_shift,
- EG_VGT_CACHE_INVALIDATION__CACHE_INVALIDATION_mask);
-
- evergreen->evergreen_config.VGT_GS_VERTEX_REUSE.u32All = 0;
- SETfield(evergreen->evergreen_config.VGT_GS_VERTEX_REUSE.u32All, 16,
- VERT_REUSE_shift,
- VERT_REUSE_mask);
-
- evergreen->evergreen_config.PA_SC_LINE_STIPPLE_STATE.u32All = 0;
-
- evergreen->evergreen_config.PA_CL_ENHANCE.u32All = 0;
- SETbit(evergreen->evergreen_config.PA_CL_ENHANCE.u32All,
- CLIP_VTX_REORDER_ENA_bit);
- SETfield(evergreen->evergreen_config.PA_CL_ENHANCE.u32All, 3,
- NUM_CLIP_SEQ_shift,
- NUM_CLIP_SEQ_mask);
-}
-
-void evergreenInitState(struct gl_context * ctx) //diff
-{
- context_t *context = R700_CONTEXT(ctx);
- EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
-
- int id = 0;
-
- //calloc should have done this
- memset(evergreen, 0, sizeof(EVERGREEN_CHIP_CONTEXT));
-
- // Disable window clipping and offset:
- SETfield(evergreen->PA_SC_WINDOW_OFFSET.u32All, 0,
- EG_PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET_shift, EG_PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET_mask);
- SETfield(evergreen->PA_SC_WINDOW_OFFSET.u32All, 0,
- EG_PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET_shift, EG_PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET_mask);
-
- SETbit(evergreen->PA_SC_WINDOW_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
-
- evergreen->PA_SC_CLIPRECT_RULE.u32All = 0x0000FFFF;
-
- evergreen->PA_SC_EDGERULE.u32All = 0xAAAAAAAA;
-
- // Set up Z min/max:
- evergreen->viewport[id].PA_SC_VPORT_ZMIN_0.f32All = 0.0;
- evergreen->viewport[id].PA_SC_VPORT_ZMAX_0.f32All = 1.0;
-
- SETfield(evergreen->CB_TARGET_MASK.u32All, 0xF, TARGET0_ENABLE_shift, TARGET0_ENABLE_mask);
- SETfield(evergreen->CB_SHADER_MASK.u32All, 0xF, OUTPUT0_ENABLE_shift, OUTPUT0_ENABLE_mask);
-
- SETfield(evergreen->SPI_BARYC_CNTL.u32All, 1,
- EG_SPI_BARYC_CNTL__PERSP_CENTROID_ENA_shift,
- EG_SPI_BARYC_CNTL__PERSP_CENTROID_ENA_mask);
- SETfield(evergreen->SPI_BARYC_CNTL.u32All, 1,
- EG_SPI_BARYC_CNTL__LINEAR_CENTROID_ENA_shift,
- EG_SPI_BARYC_CNTL__LINEAR_CENTROID_ENA_mask);
-
- // Turn off vgt reuse:
- evergreen->VGT_REUSE_OFF.u32All = 0;
- SETbit(evergreen->VGT_REUSE_OFF.u32All, REUSE_OFF_bit);
-
- // Specify offsetting and clamp values for vertices:
- evergreen->VGT_MAX_VTX_INDX.u32All = 0xFFFFFF;
- evergreen->VGT_MIN_VTX_INDX.u32All = 0;
- evergreen->VGT_INDX_OFFSET.u32All = 0;
-
- evergreen->VGT_DMA_NUM_INSTANCES.u32All = 1;
-
- // Do not alpha blend:
- SETfield(evergreen->SX_ALPHA_TEST_CONTROL.u32All, REF_NEVER,
- ALPHA_FUNC_shift, ALPHA_FUNC_mask);
- CLEARbit(evergreen->SX_ALPHA_TEST_CONTROL.u32All, ALPHA_TEST_ENABLE_bit);
-
- evergreen->SPI_VS_OUT_ID_0.u32All = 0x03020100;
- evergreen->SPI_VS_OUT_ID_1.u32All = 0x07060504;
-
- evergreen->SPI_PS_INPUT_CNTL[0].u32All = 0x00000800;
- evergreen->SPI_PS_INPUT_CNTL[1].u32All = 0x00000801;
- evergreen->SPI_PS_INPUT_CNTL[2].u32All = 0x00000802;
-
-
- // Depth buffer currently disabled:
- evergreen->DB_DEPTH_CONTROL.u32All = 0;
- SETbit(evergreen->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
- SETfield(evergreen->DB_DEPTH_CONTROL.u32All, FRAG_ALWAYS,
- ZFUNC_shift, ZFUNC_mask);
-
- evergreen->DB_Z_READ_BASE.u32All = 0;
- evergreen->DB_Z_WRITE_BASE.u32All = 0;
-
- evergreen->DB_DEPTH_CLEAR.f32All = 1.0;
-
- evergreen->DB_DEPTH_VIEW.u32All = 0;
-
- evergreen->DB_SHADER_CONTROL.u32All = 0;
- SETbit(evergreen->DB_SHADER_CONTROL.u32All, EG_DB_SHADER_CONTROL__DUAL_EXPORT_ENABLE_bit);
-
- evergreen->DB_Z_INFO.u32All = 0;
- SETfield(evergreen->DB_Z_INFO.u32All , ARRAY_1D_TILED_THIN1,
- EG_DB_Z_INFO__ARRAY_MODE_shift, EG_DB_Z_INFO__ARRAY_MODE_mask);
- SETfield(evergreen->DB_Z_INFO.u32All , EG_Z_24,
- EG_DB_Z_INFO__FORMAT_shift, EG_DB_Z_INFO__FORMAT_mask);
- SETfield(evergreen->DB_Z_INFO.u32All , EG_ADDR_SURF_TILE_SPLIT_256B,
- EG_DB_Z_INFO__TILE_SPLIT_shift, EG_DB_Z_INFO__TILE_SPLIT_mask);
- SETfield(evergreen->DB_Z_INFO.u32All , EG_ADDR_SURF_8_BANK,
- EG_DB_Z_INFO__NUM_BANKS_shift, EG_DB_Z_INFO__NUM_BANKS_mask);
- SETfield(evergreen->DB_Z_INFO.u32All , EG_ADDR_SURF_BANK_WIDTH_1,
- EG_DB_Z_INFO__BANK_WIDTH_shift, EG_DB_Z_INFO__BANK_WIDTH_mask);
- SETfield(evergreen->DB_Z_INFO.u32All , EG_ADDR_SURF_BANK_HEIGHT_1,
- EG_DB_Z_INFO__BANK_HEIGHT_shift, EG_DB_Z_INFO__BANK_HEIGHT_mask);
-
- evergreen->DB_STENCIL_INFO.u32All = 0;
- CLEARbit(evergreen->DB_STENCIL_INFO.u32All, EG_DB_STENCIL_INFO__FORMAT_bit);
- SETfield(evergreen->DB_STENCIL_INFO.u32All, 0,
- EG_DB_STENCIL_INFO__TILE_SPLIT_shift, EG_DB_STENCIL_INFO__TILE_SPLIT_mask);
-
- evergreen->DB_RENDER_CONTROL.u32All = 0;
-
- evergreen->DB_RENDER_OVERRIDE.u32All = 0;
- SETfield(evergreen->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIZ_ENABLE_shift, FORCE_HIZ_ENABLE_mask);
- SETfield(evergreen->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE0_shift, FORCE_HIS_ENABLE0_mask);
- SETfield(evergreen->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE1_shift, FORCE_HIS_ENABLE1_mask);
-
- /* stencil */
- evergreenEnable(ctx, GL_STENCIL_TEST, ctx->Stencil._Enabled);
- evergreenStencilMaskSeparate(ctx, 0, ctx->Stencil.WriteMask[0]);
- evergreenStencilFuncSeparate(ctx, 0, ctx->Stencil.Function[0],
- ctx->Stencil.Ref[0], ctx->Stencil.ValueMask[0]);
- evergreenStencilOpSeparate(ctx, 0, ctx->Stencil.FailFunc[0],
- ctx->Stencil.ZFailFunc[0],
- ctx->Stencil.ZPassFunc[0]);
-
- // Disable ROP3 modes by setting src to dst copy:
- SETfield(evergreen->CB_COLOR_CONTROL.u32All, 0xCC,
- EG_CB_COLOR_CONTROL__ROP3_shift,
- EG_CB_COLOR_CONTROL__ROP3_mask);
- SETfield(evergreen->CB_COLOR_CONTROL.u32All, EG_CB_NORMAL,
- EG_CB_COLOR_CONTROL__MODE_shift,
- EG_CB_COLOR_CONTROL__MODE_mask);
-
- SETfield(evergreen->CB_BLEND0_CONTROL.u32All,
- BLEND_ONE, COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
-
- SETfield(evergreen->CB_BLEND0_CONTROL.u32All,
- BLEND_ONE, ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
-
- //evergreen->PA_CL_CLIP_CNTL.CLIP_DISABLE = 1;
-
- SETbit(evergreen->PA_CL_CLIP_CNTL.u32All, DX_LINEAR_ATTR_CLIP_ENA_bit);
-
- // Set up the culling control register:
- SETfield(evergreen->PA_SU_SC_MODE_CNTL.u32All, 2,
- POLYMODE_FRONT_PTYPE_shift, POLYMODE_FRONT_PTYPE_mask); // draw using triangles
- SETfield(evergreen->PA_SU_SC_MODE_CNTL.u32All, 2,
- POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask); // draw using triangles
-
- // Do scale XY or X by 1/W0. eg:
- evergreen->bEnablePerspective = GL_TRUE;
-
- CLEARbit(evergreen->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
- CLEARbit(evergreen->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
- SETbit(evergreen->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
-
- // Enable viewport scaling for all three axis:
- SETbit(evergreen->PA_CL_VTE_CNTL.u32All, VPORT_X_SCALE_ENA_bit);
- SETbit(evergreen->PA_CL_VTE_CNTL.u32All, VPORT_X_OFFSET_ENA_bit);
- SETbit(evergreen->PA_CL_VTE_CNTL.u32All, VPORT_Y_SCALE_ENA_bit);
- SETbit(evergreen->PA_CL_VTE_CNTL.u32All, VPORT_Y_OFFSET_ENA_bit);
- SETbit(evergreen->PA_CL_VTE_CNTL.u32All, VPORT_Z_SCALE_ENA_bit);
- SETbit(evergreen->PA_CL_VTE_CNTL.u32All, VPORT_Z_OFFSET_ENA_bit);
-
- // Set up point sizes and min/max values:
- SETfield(evergreen->PA_SU_POINT_SIZE.u32All, 0x8,
- PA_SU_POINT_SIZE__HEIGHT_shift, PA_SU_POINT_SIZE__HEIGHT_mask);
- SETfield(evergreen->PA_SU_POINT_SIZE.u32All, 0x8,
- PA_SU_POINT_SIZE__WIDTH_shift, PA_SU_POINT_SIZE__WIDTH_mask);
- CLEARfield(evergreen->PA_SU_POINT_MINMAX.u32All, MIN_SIZE_mask);
- SETfield(evergreen->PA_SU_POINT_MINMAX.u32All, 0x8000, MAX_SIZE_shift, MAX_SIZE_mask);
- SETfield(evergreen->PA_SU_LINE_CNTL.u32All,0x8,
- PA_SU_LINE_CNTL__WIDTH_shift, PA_SU_LINE_CNTL__WIDTH_mask);
-
- // Set up line control:
- evergreen->PA_SC_LINE_CNTL.u32All = 0;
- CLEARbit(evergreen->PA_SC_LINE_CNTL.u32All, EXPAND_LINE_WIDTH_bit);
- SETbit(evergreen->PA_SC_LINE_CNTL.u32All, LAST_PIXEL_bit);
-
- // Set up vertex control:
- evergreen->PA_SU_VTX_CNTL.u32All = 0;
- CLEARfield(evergreen->PA_SU_VTX_CNTL.u32All, QUANT_MODE_mask);
- SETbit(evergreen->PA_SU_VTX_CNTL.u32All, PIX_CENTER_bit);
- SETfield(evergreen->PA_SU_VTX_CNTL.u32All, X_ROUND_TO_EVEN,
- PA_SU_VTX_CNTL__ROUND_MODE_shift, PA_SU_VTX_CNTL__ROUND_MODE_mask);
-
- // to 1.0 = no guard band:
- evergreen->PA_CL_GB_VERT_CLIP_ADJ.u32All = 0x3F800000; // 1.0
- evergreen->PA_CL_GB_VERT_DISC_ADJ.u32All = 0x3F800000; // 1.0
- evergreen->PA_CL_GB_HORZ_CLIP_ADJ.u32All = 0x3F800000; // 1.0
- evergreen->PA_CL_GB_HORZ_DISC_ADJ.u32All = 0x3F800000; // 1.0
-
- // Diable color compares:
- SETfield(evergreen->CB_CLRCMP_CONTROL.u32All, CLRCMP_DRAW_ALWAYS,
- CLRCMP_FCN_SRC_shift, CLRCMP_FCN_SRC_mask);
- SETfield(evergreen->CB_CLRCMP_CONTROL.u32All, CLRCMP_DRAW_ALWAYS,
- CLRCMP_FCN_DST_shift, CLRCMP_FCN_DST_mask);
- SETfield(evergreen->CB_CLRCMP_CONTROL.u32All, CLRCMP_SEL_SRC,
- CLRCMP_FCN_SEL_shift, CLRCMP_FCN_SEL_mask);
-
- // Zero out source:
- evergreen->CB_CLRCMP_SRC.u32All = 0x00000000;
-
- // Put a compare color in for error checking:
- evergreen->CB_CLRCMP_DST.u32All = 0x000000FF;
-
- // Set up color compare mask:
- evergreen->CB_CLRCMP_MSK.u32All = 0xFFFFFFFF;
-
- // Enable all samples for multi-sample anti-aliasing:
- evergreen->PA_SC_AA_MASK.u32All = 0xFFFFFFFF;
- // Turn off AA:
- evergreen->PA_SC_AA_CONFIG.u32All = 0;
-
- SETfield(evergreen->VGT_OUT_DEALLOC_CNTL.u32All, 16,
- DEALLOC_DIST_shift, DEALLOC_DIST_mask);
- SETfield(evergreen->VGT_VERTEX_REUSE_BLOCK_CNTL.u32All, 14,
- VTX_REUSE_DEPTH_shift, VTX_REUSE_DEPTH_mask);
-
- evergreen->SX_MISC.u32All = 0;
-
- SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All, 1,
- EG_CB_COLOR0_INFO__SOURCE_FORMAT_shift, EG_CB_COLOR0_INFO__SOURCE_FORMAT_mask);
- SETbit(evergreen->render_target[id].CB_COLOR0_INFO.u32All, EG_CB_COLOR0_INFO__BLEND_CLAMP_bit);
- SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All, 0,
- EG_CB_COLOR0_INFO__NUMBER_TYPE_shift, EG_CB_COLOR0_INFO__NUMBER_TYPE_mask);
-
- SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All, SWAP_STD,
- EG_CB_COLOR0_INFO__COMP_SWAP_shift, EG_CB_COLOR0_INFO__COMP_SWAP_mask);
-
- evergreen->render_target[id].CB_COLOR0_VIEW.u32All = 0;
- evergreen->render_target[id].CB_COLOR0_CMASK.u32All = 0;
- evergreen->render_target[id].CB_COLOR0_FMASK.u32All = 0;
- evergreen->render_target[id].CB_COLOR0_FMASK_SLICE.u32All = 0;
-
- evergreenInitSQConfig(ctx);
-
- context->radeon.hw.all_dirty = GL_TRUE;
-}
-
-void evergreenInitStateFuncs(radeonContextPtr radeon, struct dd_function_table *functions)
-{
- functions->UpdateState = evergreenInvalidateState;
- functions->AlphaFunc = evergreenAlphaFunc;
- functions->BlendColor = evergreenBlendColor;
- functions->BlendEquationSeparate = evergreenBlendEquationSeparate;
- functions->BlendFuncSeparate = evergreenBlendFuncSeparate;
- functions->Enable = evergreenEnable;
- functions->ColorMask = evergreenColorMask;
- functions->DepthFunc = evergreenDepthFunc;
- functions->DepthMask = evergreenDepthMask;
- functions->CullFace = evergreenCullFace;
- functions->Fogfv = evergreenFogfv;
- functions->FrontFace = evergreenFrontFace;
- functions->ShadeModel = evergreenShadeModel;
- functions->LogicOpcode = evergreenLogicOpcode;
-
- /* ARB_point_parameters */
- functions->PointParameterfv = evergreenPointParameter;
-
- /* Stencil related */
- functions->StencilFuncSeparate = evergreenStencilFuncSeparate;
- functions->StencilMaskSeparate = evergreenStencilMaskSeparate;
- functions->StencilOpSeparate = evergreenStencilOpSeparate;
-
- /* Viewport related */
- functions->Viewport = evergreenViewport;
- functions->DepthRange = evergreenDepthRange;
- functions->PointSize = evergreenPointSize;
- functions->LineWidth = evergreenLineWidth;
- functions->LineStipple = evergreenLineStipple;
-
- functions->PolygonOffset = evergreenPolygonOffset;
- functions->PolygonMode = evergreenPolygonMode;
-
- functions->RenderMode = evergreenRenderMode;
-
- functions->ClipPlane = evergreenClipPlane;
-
- functions->Scissor = radeonScissor;
-
- functions->DrawBuffer = radeonDrawBuffer;
- functions->ReadBuffer = radeonReadBuffer;
-
- if (radeon->radeonScreen->kernel_mm) {
- functions->CopyPixels = _mesa_meta_CopyPixels;
- functions->DrawPixels = _mesa_meta_DrawPixels;
- functions->ReadPixels = radeonReadPixels;
- }
-}
-
-
+++ /dev/null
-/*
- * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Authors:
- * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
- */
-
-#ifndef _EVERGREEN_STATE_H_
-#define _EVERGREEN_STATE_H_
-
-#include "main/mtypes.h"
-
-#include "r600_context.h"
-
-extern void evergreenUpdateStateParameters(struct gl_context * ctx, GLuint new_state);
-extern void evergreenUpdateShaders(struct gl_context * ctx);
-extern void evergreenUpdateShaderStates(struct gl_context * ctx);
-
-extern void evergreeUpdateShaders(struct gl_context * ctx);
-
-extern void evergreenUpdateViewportOffset(struct gl_context * ctx);
-
-extern void evergreenInitState(struct gl_context * ctx);
-extern void evergreenInitStateFuncs (radeonContextPtr radeon, struct dd_function_table *functions);
-
-extern void evergreenSetScissor(context_t *context);
-
-#endif /* _EVERGREEN_STATE_H_ */
+++ /dev/null
-/*
- * Copyright (C) 2008-2010 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Authors:
- * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
- */
-
-#include "main/glheader.h"
-#include "main/imports.h"
-#include "main/colormac.h"
-#include "main/context.h"
-#include "main/enums.h"
-#include "main/image.h"
-#include "main/teximage.h"
-#include "main/simple_list.h"
-#include "main/texobj.h"
-
-#include "texmem.h"
-
-#include "r600_context.h"
-#include "radeon_mipmap_tree.h"
-#include "evergreen_diff.h"
-#include "evergreen_tex.h"
-#include "evergreen_fragprog.h"
-#include "evergreen_vertprog.h"
-
-#include "r600_tex.h"
-
-static unsigned int evergreen_translate_wrap_mode(GLenum wrapmode)
-{
- switch(wrapmode) {
- case GL_REPEAT: return SQ_TEX_WRAP;
- case GL_CLAMP: return SQ_TEX_CLAMP_HALF_BORDER;
- case GL_CLAMP_TO_EDGE: return SQ_TEX_CLAMP_LAST_TEXEL;
- case GL_CLAMP_TO_BORDER: return SQ_TEX_CLAMP_BORDER;
- case GL_MIRRORED_REPEAT: return SQ_TEX_MIRROR;
- case GL_MIRROR_CLAMP_EXT: return SQ_TEX_MIRROR_ONCE_HALF_BORDER;
- case GL_MIRROR_CLAMP_TO_EDGE_EXT: return SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
- case GL_MIRROR_CLAMP_TO_BORDER_EXT: return SQ_TEX_MIRROR_ONCE_BORDER;
- default:
- radeon_error("bad wrap mode in %s", __FUNCTION__);
- return 0;
- }
-}
-
-static GLboolean evergreenGetTexFormat(struct gl_texture_object *tObj, gl_format mesa_format)
-{
- radeonTexObj *t = radeon_tex_obj(tObj);
-
- CLEARfield(t->SQ_TEX_RESOURCE4, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- CLEARfield(t->SQ_TEX_RESOURCE4, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- CLEARfield(t->SQ_TEX_RESOURCE4, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- CLEARfield(t->SQ_TEX_RESOURCE4, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- CLEARbit(t->SQ_TEX_RESOURCE4, SQ_TEX_RESOURCE_WORD4_0__FORCE_DEGAMMA_bit);
-
- SETfield(t->SQ_TEX_RESOURCE4, SQ_FORMAT_COMP_UNSIGNED,
- FORMAT_COMP_X_shift,
- FORMAT_COMP_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_FORMAT_COMP_UNSIGNED,
- FORMAT_COMP_Y_shift,
- FORMAT_COMP_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_FORMAT_COMP_UNSIGNED,
- FORMAT_COMP_Z_shift,
- FORMAT_COMP_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_FORMAT_COMP_UNSIGNED,
- FORMAT_COMP_W_shift,
- FORMAT_COMP_W_mask);
-
- SETfield(t->SQ_TEX_RESOURCE1, ARRAY_LINEAR_GENERAL,
- EG_SQ_TEX_RESOURCE_WORD1_0__ARRAY_MODE_shift,
- EG_SQ_TEX_RESOURCE_WORD1_0__ARRAY_MODE_mask);
-
- switch (mesa_format) /* This is mesa format. */
- {
- case MESA_FORMAT_RGBA8888:
- case MESA_FORMAT_SIGNED_RGBA8888:
- SETfield(t->SQ_TEX_RESOURCE7, FMT_8_8_8_8,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
-
-#ifdef MESA_BIG_ENDIAN
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
-#else
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
-#endif
- if (mesa_format == MESA_FORMAT_SIGNED_RGBA8888) {
- SETfield(t->SQ_TEX_RESOURCE4, SQ_FORMAT_COMP_SIGNED,
- FORMAT_COMP_X_shift, FORMAT_COMP_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_FORMAT_COMP_SIGNED,
- FORMAT_COMP_Y_shift, FORMAT_COMP_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_FORMAT_COMP_SIGNED,
- FORMAT_COMP_Z_shift, FORMAT_COMP_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_FORMAT_COMP_SIGNED,
- FORMAT_COMP_W_shift, FORMAT_COMP_W_mask);
- }
- break;
- case MESA_FORMAT_RGBA8888_REV:
- case MESA_FORMAT_SIGNED_RGBA8888_REV:
- SETfield(t->SQ_TEX_RESOURCE7, FMT_8_8_8_8,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
-
-#ifdef MESA_BIG_ENDIAN
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
-#else
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
-#endif
- if (mesa_format == MESA_FORMAT_SIGNED_RGBA8888_REV) {
- SETfield(t->SQ_TEX_RESOURCE4, SQ_FORMAT_COMP_SIGNED,
- FORMAT_COMP_X_shift, FORMAT_COMP_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_FORMAT_COMP_SIGNED,
- FORMAT_COMP_Y_shift, FORMAT_COMP_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_FORMAT_COMP_SIGNED,
- FORMAT_COMP_Z_shift, FORMAT_COMP_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_FORMAT_COMP_SIGNED,
- FORMAT_COMP_W_shift, FORMAT_COMP_W_mask);
- }
- break;
- case MESA_FORMAT_ARGB8888:
- SETfield(t->SQ_TEX_RESOURCE7, FMT_8_8_8_8,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
-
-#ifdef MESA_BIG_ENDIAN
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
-#else
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
-#endif
- break;
- case MESA_FORMAT_XRGB8888:
- SETfield(t->SQ_TEX_RESOURCE7, FMT_8_8_8_8,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
-
-#ifdef MESA_BIG_ENDIAN
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
-#else
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
-#endif
- break;
- case MESA_FORMAT_XRGB8888_REV:
- SETfield(t->SQ_TEX_RESOURCE7, FMT_8_8_8_8,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
-
-#ifdef MESA_BIG_ENDIAN
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
-#else
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
-#endif
- break;
- case MESA_FORMAT_ARGB8888_REV:
- SETfield(t->SQ_TEX_RESOURCE7, FMT_8_8_8_8,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
-
-#ifdef MESA_BIG_ENDIAN
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
-#else
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
-#endif
- break;
- case MESA_FORMAT_RGB888:
- SETfield(t->SQ_TEX_RESOURCE7, FMT_8_8_8,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
-
-#ifdef MESA_BIG_ENDIAN
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
-#else
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
-#endif
- break;
- case MESA_FORMAT_RGB565:
- SETfield(t->SQ_TEX_RESOURCE7, FMT_5_6_5,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
-
-#ifdef MESA_BIG_ENDIAN
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
-#else
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
-#endif
- break;
- case MESA_FORMAT_RGB565_REV:
- SETfield(t->SQ_TEX_RESOURCE7, FMT_5_6_5,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
-
-#ifdef MESA_BIG_ENDIAN
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
-#else
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
-#endif
- break;
- case MESA_FORMAT_ARGB4444:
- SETfield(t->SQ_TEX_RESOURCE7, FMT_4_4_4_4,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
-
-#ifdef MESA_BIG_ENDIAN
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
-#else
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
-#endif
- break;
- case MESA_FORMAT_ARGB4444_REV:
- SETfield(t->SQ_TEX_RESOURCE7, FMT_4_4_4_4,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
-
-#ifdef MESA_BIG_ENDIAN
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
-#else
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
-#endif
- break;
- case MESA_FORMAT_ARGB1555:
- SETfield(t->SQ_TEX_RESOURCE7, FMT_1_5_5_5,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
-
-#ifdef MESA_BIG_ENDIAN
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
-#else
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
-#endif
- break;
- case MESA_FORMAT_ARGB1555_REV:
- SETfield(t->SQ_TEX_RESOURCE7, FMT_1_5_5_5,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
-
-#ifdef MESA_BIG_ENDIAN
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
-#else
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
-#endif
- break;
- case MESA_FORMAT_AL88:
- case MESA_FORMAT_AL88_REV: /* TODO : Check this. */
- SETfield(t->SQ_TEX_RESOURCE7, FMT_8_8,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
-
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_RGB332:
- SETfield(t->SQ_TEX_RESOURCE7, FMT_3_3_2,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
-
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_A8: /* ZERO, ZERO, ZERO, X */
- SETfield(t->SQ_TEX_RESOURCE7, FMT_8,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
-
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_0,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_0,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_0,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_L8: /* X, X, X, ONE */
- SETfield(t->SQ_TEX_RESOURCE7, FMT_8,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
-
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_I8: /* X, X, X, X */
- SETfield(t->SQ_TEX_RESOURCE7, FMT_8,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
-
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_RGB_DXT1: /* not supported yet */
- case MESA_FORMAT_RGBA_DXT1: /* not supported yet */
- case MESA_FORMAT_RGBA_DXT3: /* not supported yet */
- case MESA_FORMAT_RGBA_DXT5: /* not supported yet */
- return GL_FALSE;
-
- case MESA_FORMAT_RGBA_FLOAT32:
- SETfield(t->SQ_TEX_RESOURCE7, FMT_32_32_32_32_FLOAT,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
-
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_RGBA_FLOAT16:
- SETfield(t->SQ_TEX_RESOURCE7, FMT_16_16_16_16_FLOAT,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
-
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_RGB_FLOAT32: /* X, Y, Z, ONE */
- SETfield(t->SQ_TEX_RESOURCE7, FMT_32_32_32_FLOAT,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
-
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_RGB_FLOAT16:
- SETfield(t->SQ_TEX_RESOURCE7, FMT_16_16_16_FLOAT,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
-
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_ALPHA_FLOAT32: /* ZERO, ZERO, ZERO, X */
- SETfield(t->SQ_TEX_RESOURCE7, FMT_32_FLOAT,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
-
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_0,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_0,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_0,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_ALPHA_FLOAT16: /* ZERO, ZERO, ZERO, X */
- SETfield(t->SQ_TEX_RESOURCE7, FMT_16_FLOAT,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
-
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_0,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_0,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_0,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_LUMINANCE_FLOAT32: /* X, X, X, ONE */
- SETfield(t->SQ_TEX_RESOURCE7, FMT_32_FLOAT,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
-
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_LUMINANCE_FLOAT16: /* X, X, X, ONE */
- SETfield(t->SQ_TEX_RESOURCE7, FMT_16_FLOAT,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
-
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32:
- SETfield(t->SQ_TEX_RESOURCE7, FMT_32_32_FLOAT,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
-
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16:
- SETfield(t->SQ_TEX_RESOURCE7, FMT_16_16_FLOAT,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
-
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_INTENSITY_FLOAT32: /* X, X, X, X */
- SETfield(t->SQ_TEX_RESOURCE7, FMT_32_FLOAT,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
-
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_INTENSITY_FLOAT16: /* X, X, X, X */
- SETfield(t->SQ_TEX_RESOURCE7, FMT_16_FLOAT,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
-
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_Z16:
- case MESA_FORMAT_X8_Z24:
- case MESA_FORMAT_S8_Z24:
- case MESA_FORMAT_Z24_S8:
- case MESA_FORMAT_Z32:
- case MESA_FORMAT_S8:
- CLEARbit(t->SQ_TEX_RESOURCE0, EG_SQ_TEX_RESOURCE_WORD0_0__NDTO_bit);
- SETfield(t->SQ_TEX_RESOURCE1, ARRAY_1D_TILED_THIN1,
- EG_SQ_TEX_RESOURCE_WORD1_0__ARRAY_MODE_shift,
- EG_SQ_TEX_RESOURCE_WORD1_0__ARRAY_MODE_mask);
- switch (mesa_format) {
- case MESA_FORMAT_Z16:
- SETfield(t->SQ_TEX_RESOURCE7, FMT_16,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
- break;
- case MESA_FORMAT_X8_Z24:
- case MESA_FORMAT_S8_Z24:
- SETfield(t->SQ_TEX_RESOURCE7, FMT_8_24,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
- break;
- case MESA_FORMAT_Z24_S8:
- SETfield(t->SQ_TEX_RESOURCE7, FMT_24_8,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
- break;
- case MESA_FORMAT_Z32:
- SETfield(t->SQ_TEX_RESOURCE7, FMT_32,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
- break;
- case MESA_FORMAT_S8:
- SETfield(t->SQ_TEX_RESOURCE7, FMT_8,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
- break;
- default:
- break;
- };
- switch (tObj->Sampler.DepthMode) {
- case GL_LUMINANCE: /* X, X, X, ONE */
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case GL_INTENSITY: /* X, X, X, X */
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case GL_ALPHA: /* ZERO, ZERO, ZERO, X */
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_0,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_0,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_0,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- default:
- return GL_FALSE;
- }
- break;
- /* EXT_texture_sRGB */
- case MESA_FORMAT_SRGBA8:
- SETfield(t->SQ_TEX_RESOURCE7, FMT_8_8_8_8,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
-
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- SETbit(t->SQ_TEX_RESOURCE4, SQ_TEX_RESOURCE_WORD4_0__FORCE_DEGAMMA_bit);
- break;
- case MESA_FORMAT_SLA8:
- SETfield(t->SQ_TEX_RESOURCE7, FMT_8_8,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
-
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- SETbit(t->SQ_TEX_RESOURCE4, SQ_TEX_RESOURCE_WORD4_0__FORCE_DEGAMMA_bit);
- break;
- case MESA_FORMAT_SL8: /* X, X, X, ONE */
- SETfield(t->SQ_TEX_RESOURCE7, FMT_8,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
-
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- SETbit(t->SQ_TEX_RESOURCE4, SQ_TEX_RESOURCE_WORD4_0__FORCE_DEGAMMA_bit);
- break;
- default:
- /* Not supported format */
- return GL_FALSE;
- };
-
- return GL_TRUE;
-}
-
-static GLuint evergreen_translate_shadow_func(GLenum func)
-{
- switch (func) {
- case GL_NEVER:
- return SQ_TEX_DEPTH_COMPARE_NEVER;
- case GL_LESS:
- return SQ_TEX_DEPTH_COMPARE_LESS;
- case GL_LEQUAL:
- return SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
- case GL_GREATER:
- return SQ_TEX_DEPTH_COMPARE_GREATER;
- case GL_GEQUAL:
- return SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
- case GL_NOTEQUAL:
- return SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
- case GL_EQUAL:
- return SQ_TEX_DEPTH_COMPARE_EQUAL;
- case GL_ALWAYS:
- return SQ_TEX_DEPTH_COMPARE_ALWAYS;
- default:
- WARN_ONCE("Unknown shadow compare function! %d", func);
- return 0;
- }
-}
-
-static void evergreenUpdateTexWrap(radeonTexObjPtr t)
-{
- struct gl_texture_object *tObj = &t->base;
-
- SETfield(t->SQ_TEX_SAMPLER0, evergreen_translate_wrap_mode(tObj->Sampler.WrapS),
- EG_SQ_TEX_SAMPLER_WORD0_0__CLAMP_X_shift,
- EG_SQ_TEX_SAMPLER_WORD0_0__CLAMP_X_mask);
-
- if (tObj->Target != GL_TEXTURE_1D)
- {
- SETfield(t->SQ_TEX_SAMPLER0, evergreen_translate_wrap_mode(tObj->Sampler.WrapT),
- EG_SQ_TEX_SAMPLER_WORD0_0__CLAMP_Y_shift,
- EG_SQ_TEX_SAMPLER_WORD0_0__CLAMP_Y_mask);
-
- if (tObj->Target == GL_TEXTURE_3D)
- SETfield(t->SQ_TEX_SAMPLER0, evergreen_translate_wrap_mode(tObj->Sampler.WrapR),
- EG_SQ_TEX_SAMPLER_WORD0_0__CLAMP_Z_shift,
- EG_SQ_TEX_SAMPLER_WORD0_0__CLAMP_Z_mask);
- }
-}
-
-static void evergreenSetTexDefaultState(radeonTexObjPtr t)
-{
- /* Init text object to default states. */
- t->SQ_TEX_RESOURCE0 = 0;
- t->SQ_TEX_RESOURCE1 = 0;
- t->SQ_TEX_RESOURCE2 = 0;
- t->SQ_TEX_RESOURCE3 = 0;
- t->SQ_TEX_RESOURCE4 = 0;
- t->SQ_TEX_RESOURCE5 = 0;
- t->SQ_TEX_RESOURCE6 = 0;
- t->SQ_TEX_RESOURCE7 = 0;
-
- SETfield(t->SQ_TEX_RESOURCE0, SQ_TEX_DIM_2D,
- EG_SQ_TEX_RESOURCE_WORD0_0__DIM_shift,
- EG_SQ_TEX_RESOURCE_WORD0_0__DIM_mask);
-
- CLEARbit(t->SQ_TEX_RESOURCE0, EG_SQ_TEX_RESOURCE_WORD0_0__NDTO_bit);
-
- SETfield(t->SQ_TEX_RESOURCE1, ARRAY_LINEAR_GENERAL,
- EG_SQ_TEX_RESOURCE_WORD1_0__ARRAY_MODE_shift,
- EG_SQ_TEX_RESOURCE_WORD1_0__ARRAY_MODE_mask);
-
- SETfield(t->SQ_TEX_RESOURCE4, SQ_FORMAT_COMP_UNSIGNED,
- FORMAT_COMP_X_shift, FORMAT_COMP_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_FORMAT_COMP_UNSIGNED,
- FORMAT_COMP_Y_shift, FORMAT_COMP_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_FORMAT_COMP_UNSIGNED,
- FORMAT_COMP_Z_shift, FORMAT_COMP_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_FORMAT_COMP_UNSIGNED,
- FORMAT_COMP_W_shift, FORMAT_COMP_W_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_NUM_FORMAT_NORM,
- SQ_TEX_RESOURCE_WORD4_0__NUM_FORMAT_ALL_shift, SQ_TEX_RESOURCE_WORD4_0__NUM_FORMAT_ALL_mask);
- CLEARbit(t->SQ_TEX_RESOURCE4, SQ_TEX_RESOURCE_WORD4_0__SRF_MODE_ALL_bit);
- CLEARbit(t->SQ_TEX_RESOURCE4, SQ_TEX_RESOURCE_WORD4_0__FORCE_DEGAMMA_bit);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_ENDIAN_NONE,
- SQ_TEX_RESOURCE_WORD4_0__ENDIAN_SWAP_shift, SQ_TEX_RESOURCE_WORD4_0__ENDIAN_SWAP_mask);
-
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- SETfield(t->SQ_TEX_RESOURCE4, 0,
- BASE_LEVEL_shift,
- BASE_LEVEL_mask); /* mip-maps */
-
- SETfield(t->SQ_TEX_RESOURCE7, FMT_8_8_8_8,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
- SETfield(t->SQ_TEX_RESOURCE7, SQ_TEX_VTX_VALID_TEXTURE,
- EG_SQ_TEX_RESOURCE_WORD7_0__TYPE_shift,
- EG_SQ_TEX_RESOURCE_WORD7_0__TYPE_mask);
-
- /* Initialize sampler registers */
- t->SQ_TEX_SAMPLER0 = 0;
- SETfield(t->SQ_TEX_SAMPLER0, SQ_TEX_WRAP,
- EG_SQ_TEX_SAMPLER_WORD0_0__CLAMP_X_shift,
- EG_SQ_TEX_SAMPLER_WORD0_0__CLAMP_X_mask);
- SETfield(t->SQ_TEX_SAMPLER0, SQ_TEX_WRAP,
- EG_SQ_TEX_SAMPLER_WORD0_0__CLAMP_X_shift,
- EG_SQ_TEX_SAMPLER_WORD0_0__CLAMP_X_mask);
- SETfield(t->SQ_TEX_SAMPLER0, SQ_TEX_WRAP,
- EG_SQ_TEX_SAMPLER_WORD0_0__CLAMP_X_shift,
- EG_SQ_TEX_SAMPLER_WORD0_0__CLAMP_X_mask);
- SETfield(t->SQ_TEX_SAMPLER0, SQ_TEX_XY_FILTER_POINT,
- EG_SQ_TEX_SAMPLER_WORD0_0__XY_MAG_FILTER_shift,
- EG_SQ_TEX_SAMPLER_WORD0_0__XY_MAG_FILTER_mask);
- SETfield(t->SQ_TEX_SAMPLER0, SQ_TEX_XY_FILTER_POINT,
- EG_SQ_TEX_SAMPLER_WORD0_0__XY_MIN_FILTER_shift,
- EG_SQ_TEX_SAMPLER_WORD0_0__XY_MIN_FILTER_mask);
- SETfield(t->SQ_TEX_SAMPLER0, SQ_TEX_Z_FILTER_NONE,
- EG_SQ_TEX_SAMPLER_WORD0_0__Z_FILTER_shift,
- EG_SQ_TEX_SAMPLER_WORD0_0__Z_FILTER_mask);
- SETfield(t->SQ_TEX_SAMPLER0, SQ_TEX_Z_FILTER_NONE,
- EG_SQ_TEX_SAMPLER_WORD0_0__MIP_FILTER_shift,
- EG_SQ_TEX_SAMPLER_WORD0_0__MIP_FILTER_mask);
- SETfield(t->SQ_TEX_SAMPLER0, SQ_TEX_BORDER_COLOR_TRANS_BLACK,
- EG_SQ_TEX_SAMPLER_WORD0_0__BORDER_COLOR_TYPE_shift,
- EG_SQ_TEX_SAMPLER_WORD0_0__BORDER_COLOR_TYPE_mask);
-
- t->SQ_TEX_SAMPLER1 = 0;
- SETfield(t->SQ_TEX_SAMPLER1, 0x7ff,
- EG_SQ_TEX_SAMPLER_WORD1_0__MAX_LOD_shift,
- EG_SQ_TEX_SAMPLER_WORD1_0__MAX_LOD_mask);
-
- t->SQ_TEX_SAMPLER2 = 0;
- SETbit(t->SQ_TEX_SAMPLER2, EG_SQ_TEX_SAMPLER_WORD2_0__TYPE_bit);
-}
-
-static void evergreenSetTexFilter(radeonTexObjPtr t, GLenum minf, GLenum magf, GLfloat anisotropy)
-{
- /* Force revalidation to account for switches from/to mipmapping. */
- t->validated = GL_FALSE;
-
- /* Note that EXT_texture_filter_anisotropic is extremely vague about
- * how anisotropic filtering interacts with the "normal" filter modes.
- * When anisotropic filtering is enabled, we override min and mag
- * filter settings completely. This includes driconf's settings.
- */
- if (anisotropy >= 2.0 && (minf != GL_NEAREST) && (magf != GL_NEAREST)) {
- /*t->pp_txfilter |= R300_TX_MAG_FILTER_ANISO
- | R300_TX_MIN_FILTER_ANISO
- | R300_TX_MIN_FILTER_MIP_LINEAR
- | aniso_filter(anisotropy);*/
- radeon_print(RADEON_TEXTURE, RADEON_NORMAL, "Using maximum anisotropy of %f\n", anisotropy);
- return;
- }
-
- switch (minf)
- {
- case GL_NEAREST:
- SETfield(t->SQ_TEX_SAMPLER0, TEX_XYFilter_Point,
- EG_SQ_TEX_SAMPLER_WORD0_0__XY_MIN_FILTER_shift,
- EG_SQ_TEX_SAMPLER_WORD0_0__XY_MIN_FILTER_mask);
- SETfield(t->SQ_TEX_SAMPLER0, TEX_MipFilter_None,
- EG_SQ_TEX_SAMPLER_WORD0_0__MIP_FILTER_shift,
- EG_SQ_TEX_SAMPLER_WORD0_0__MIP_FILTER_mask);
- break;
- case GL_LINEAR:
- SETfield(t->SQ_TEX_SAMPLER0, TEX_XYFilter_Linear,
- EG_SQ_TEX_SAMPLER_WORD0_0__XY_MIN_FILTER_shift,
- EG_SQ_TEX_SAMPLER_WORD0_0__XY_MIN_FILTER_mask);
- SETfield(t->SQ_TEX_SAMPLER0, TEX_MipFilter_None,
- EG_SQ_TEX_SAMPLER_WORD0_0__MIP_FILTER_shift,
- EG_SQ_TEX_SAMPLER_WORD0_0__MIP_FILTER_mask);
- break;
- case GL_NEAREST_MIPMAP_NEAREST:
- SETfield(t->SQ_TEX_SAMPLER0, TEX_XYFilter_Point,
- EG_SQ_TEX_SAMPLER_WORD0_0__XY_MIN_FILTER_shift,
- EG_SQ_TEX_SAMPLER_WORD0_0__XY_MIN_FILTER_mask);
- SETfield(t->SQ_TEX_SAMPLER0, TEX_MipFilter_Point,
- EG_SQ_TEX_SAMPLER_WORD0_0__MIP_FILTER_shift,
- EG_SQ_TEX_SAMPLER_WORD0_0__MIP_FILTER_mask);
- break;
- case GL_NEAREST_MIPMAP_LINEAR:
- SETfield(t->SQ_TEX_SAMPLER0, TEX_XYFilter_Point,
- EG_SQ_TEX_SAMPLER_WORD0_0__XY_MIN_FILTER_shift,
- EG_SQ_TEX_SAMPLER_WORD0_0__XY_MIN_FILTER_mask);
- SETfield(t->SQ_TEX_SAMPLER0, TEX_MipFilter_Linear,
- EG_SQ_TEX_SAMPLER_WORD0_0__MIP_FILTER_shift,
- EG_SQ_TEX_SAMPLER_WORD0_0__MIP_FILTER_mask);
- break;
- case GL_LINEAR_MIPMAP_NEAREST:
- SETfield(t->SQ_TEX_SAMPLER0, TEX_XYFilter_Linear,
- EG_SQ_TEX_SAMPLER_WORD0_0__XY_MIN_FILTER_shift,
- EG_SQ_TEX_SAMPLER_WORD0_0__XY_MIN_FILTER_mask);
- SETfield(t->SQ_TEX_SAMPLER0, TEX_MipFilter_Point,
- EG_SQ_TEX_SAMPLER_WORD0_0__MIP_FILTER_shift,
- EG_SQ_TEX_SAMPLER_WORD0_0__MIP_FILTER_mask);
- break;
- case GL_LINEAR_MIPMAP_LINEAR:
- SETfield(t->SQ_TEX_SAMPLER0, TEX_XYFilter_Linear,
- EG_SQ_TEX_SAMPLER_WORD0_0__XY_MIN_FILTER_shift,
- EG_SQ_TEX_SAMPLER_WORD0_0__XY_MIN_FILTER_mask);
- SETfield(t->SQ_TEX_SAMPLER0, TEX_MipFilter_Linear,
- EG_SQ_TEX_SAMPLER_WORD0_0__MIP_FILTER_shift,
- EG_SQ_TEX_SAMPLER_WORD0_0__MIP_FILTER_mask);
- break;
- }
-
- /* Note we don't have 3D mipmaps so only use the mag filter setting
- * to set the 3D texture filter mode.
- */
- switch (magf)
- {
- case GL_NEAREST:
- SETfield(t->SQ_TEX_SAMPLER0, TEX_XYFilter_Point,
- EG_SQ_TEX_SAMPLER_WORD0_0__XY_MAG_FILTER_shift,
- EG_SQ_TEX_SAMPLER_WORD0_0__XY_MAG_FILTER_mask);
- break;
- case GL_LINEAR:
- SETfield(t->SQ_TEX_SAMPLER0, TEX_XYFilter_Linear,
- EG_SQ_TEX_SAMPLER_WORD0_0__XY_MAG_FILTER_shift,
- EG_SQ_TEX_SAMPLER_WORD0_0__XY_MAG_FILTER_mask);
- break;
- }
-}
-
-static void evergreenSetTexBorderColor(radeonTexObjPtr t, const GLfloat color[4])
-{
- t->TD_PS_SAMPLER0_BORDER_ALPHA = *((uint32_t*)&(color[3]));
- t->TD_PS_SAMPLER0_BORDER_RED = *((uint32_t*)&(color[2]));
- t->TD_PS_SAMPLER0_BORDER_GREEN = *((uint32_t*)&(color[1]));
- t->TD_PS_SAMPLER0_BORDER_BLUE = *((uint32_t*)&(color[0]));
-
- SETfield(t->SQ_TEX_SAMPLER0, SQ_TEX_BORDER_COLOR_REGISTER,
- EG_SQ_TEX_SAMPLER_WORD0_0__BORDER_COLOR_TYPE_shift,
- EG_SQ_TEX_SAMPLER_WORD0_0__BORDER_COLOR_TYPE_mask);
-}
-
-static void evergreenSetDepthTexMode(struct gl_texture_object *tObj)
-{
- radeonTexObjPtr t;
-
- if (!tObj)
- return;
-
- t = radeon_tex_obj(tObj);
-
- if(!evergreenGetTexFormat(tObj, tObj->Image[0][tObj->BaseLevel]->TexFormat))
- t->validated = GL_FALSE;
-}
-
-static INLINE uint32_t
-EG_S_FIXED(float value, uint32_t frac_bits)
-{
- return value * (1 << frac_bits);
-}
-
-static GLboolean evergreen_setup_hardware_state(struct gl_context * ctx, struct gl_texture_object *texObj, int unit)
-{
- context_t *context = EVERGREEN_CONTEXT(ctx);
- radeonTexObj *t = radeon_tex_obj(texObj);
- const struct gl_texture_image *firstImage;
- GLuint uTexelPitch, row_align;
-
- if (context->radeon.radeonScreen->driScreen->dri2.enabled &&
- t->image_override &&
- t->bo)
- return GL_TRUE;
-
- firstImage = t->base.Image[0][t->minLod];
-
- if (!t->image_override) {
- if (!evergreenGetTexFormat(texObj, firstImage->TexFormat)) {
- radeon_warning("unsupported texture format in %s\n",
- __FUNCTION__);
- return GL_FALSE;
- }
- }
-
- switch (texObj->Target)
- {
- case GL_TEXTURE_1D:
- SETfield(t->SQ_TEX_RESOURCE0, SQ_TEX_DIM_1D,
- EG_SQ_TEX_RESOURCE_WORD0_0__DIM_shift,
- EG_SQ_TEX_RESOURCE_WORD0_0__DIM_mask);
- SETfield(t->SQ_TEX_RESOURCE1, 0,
- EG_SQ_TEX_RESOURCE_WORD1_0__TEX_DEPTH_shift,
- EG_SQ_TEX_RESOURCE_WORD1_0__TEX_DEPTH_mask);
- break;
- case GL_TEXTURE_2D:
- case GL_TEXTURE_RECTANGLE_NV:
- SETfield(t->SQ_TEX_RESOURCE0, SQ_TEX_DIM_2D,
- EG_SQ_TEX_RESOURCE_WORD0_0__DIM_shift,
- EG_SQ_TEX_RESOURCE_WORD0_0__DIM_mask);
- SETfield(t->SQ_TEX_RESOURCE1, 0,
- EG_SQ_TEX_RESOURCE_WORD1_0__TEX_DEPTH_shift,
- EG_SQ_TEX_RESOURCE_WORD1_0__TEX_DEPTH_mask);
- break;
- case GL_TEXTURE_3D:
- SETfield(t->SQ_TEX_RESOURCE0, SQ_TEX_DIM_3D,
- EG_SQ_TEX_RESOURCE_WORD0_0__DIM_shift,
- EG_SQ_TEX_RESOURCE_WORD0_0__DIM_mask);
- SETfield(t->SQ_TEX_RESOURCE1, (firstImage->Depth - 1), // ???
- EG_SQ_TEX_RESOURCE_WORD1_0__TEX_DEPTH_shift,
- EG_SQ_TEX_RESOURCE_WORD1_0__TEX_DEPTH_mask);
- break;
- case GL_TEXTURE_CUBE_MAP:
- SETfield(t->SQ_TEX_RESOURCE0, SQ_TEX_DIM_CUBEMAP,
- EG_SQ_TEX_RESOURCE_WORD0_0__DIM_shift,
- EG_SQ_TEX_RESOURCE_WORD0_0__DIM_mask);
- SETfield(t->SQ_TEX_RESOURCE1, 0,
- EG_SQ_TEX_RESOURCE_WORD1_0__TEX_DEPTH_shift,
- EG_SQ_TEX_RESOURCE_WORD1_0__TEX_DEPTH_mask);
- break;
- default:
- radeon_error("unexpected texture target type in %s\n", __FUNCTION__);
- return GL_FALSE;
- }
-
- row_align = context->radeon.texture_row_align - 1;
- uTexelPitch = (_mesa_format_row_stride(firstImage->TexFormat, firstImage->Width) + row_align) & ~row_align;
- uTexelPitch = uTexelPitch / _mesa_get_format_bytes(firstImage->TexFormat);
- uTexelPitch = (uTexelPitch + R700_TEXEL_PITCH_ALIGNMENT_MASK)
- & ~R700_TEXEL_PITCH_ALIGNMENT_MASK;
-
- /* min pitch is 8 */
- if (uTexelPitch < 8)
- uTexelPitch = 8;
-
- SETfield(t->SQ_TEX_RESOURCE0, (uTexelPitch/8)-1,
- EG_SQ_TEX_RESOURCE_WORD0_0__PITCH_shift,
- EG_SQ_TEX_RESOURCE_WORD0_0__PITCH_mask);
- SETfield(t->SQ_TEX_RESOURCE0, firstImage->Width - 1,
- EG_SQ_TEX_RESOURCE_WORD0_0__TEX_WIDTH_shift,
- EG_SQ_TEX_RESOURCE_WORD0_0__TEX_WIDTH_mask);
- SETfield(t->SQ_TEX_RESOURCE1, firstImage->Height - 1,
- EG_SQ_TEX_RESOURCE_WORD1_0__TEX_HEIGHT_shift,
- EG_SQ_TEX_RESOURCE_WORD1_0__TEX_HEIGHT_mask);
-
- t->SQ_TEX_RESOURCE2 = get_base_teximage_offset(t) / 256;
-
- t->SQ_TEX_RESOURCE3 = radeon_miptree_image_offset(t->mt, 0, t->minLod + 1) / 256;
-
- SETfield(t->SQ_TEX_RESOURCE4, 0, BASE_LEVEL_shift, BASE_LEVEL_mask);
- SETfield(t->SQ_TEX_RESOURCE5, t->maxLod - t->minLod, LAST_LEVEL_shift, LAST_LEVEL_mask);
-
- SETfield(t->SQ_TEX_SAMPLER1,
- EG_S_FIXED(CLAMP(t->base.Sampler.MinLod - t->minLod, 0, 15), 8),
- EG_SQ_TEX_SAMPLER_WORD1_0__MIN_LOD_shift,
- EG_SQ_TEX_SAMPLER_WORD1_0__MIN_LOD_mask);
- SETfield(t->SQ_TEX_SAMPLER1,
- EG_S_FIXED(CLAMP(t->base.Sampler.MaxLod - t->minLod, 0, 15), 8),
- EG_SQ_TEX_SAMPLER_WORD1_0__MAX_LOD_shift,
- EG_SQ_TEX_SAMPLER_WORD1_0__MAX_LOD_mask);
- SETfield(t->SQ_TEX_SAMPLER2,
- EG_S_FIXED(CLAMP(ctx->Texture.Unit[unit].LodBias + t->base.Sampler.LodBias, -16, 16), 8),
- EG_SQ_TEX_SAMPLER_WORD2_0__LOD_BIAS_shift,
- EG_SQ_TEX_SAMPLER_WORD2_0__LOD_BIAS_mask);
-
- if(texObj->Sampler.CompareMode == GL_COMPARE_R_TO_TEXTURE_ARB)
- {
- SETfield(t->SQ_TEX_SAMPLER0, evergreen_translate_shadow_func(texObj->Sampler.CompareFunc),
- EG_SQ_TEX_SAMPLER_WORD0_0__DCF_shift,
- EG_SQ_TEX_SAMPLER_WORD0_0__DCF_mask);
- }
- else
- {
- CLEARfield(t->SQ_TEX_SAMPLER0, EG_SQ_TEX_SAMPLER_WORD0_0__DCF_mask);
- }
-
- return GL_TRUE;
-}
-
-void evergreenSetTexOffset(__DRIcontext * pDRICtx, GLint texname,
- unsigned long long offset, GLint depth, GLuint pitch)
-{
- context_t *rmesa = pDRICtx->driverPrivate;
- struct gl_texture_object *tObj =
- _mesa_lookup_texture(rmesa->radeon.glCtx, texname);
- radeonTexObjPtr t = radeon_tex_obj(tObj);
- const struct gl_texture_image *firstImage;
- uint32_t pitch_val, size, row_align;
-
- if (!tObj)
- return;
-
- t->image_override = GL_TRUE;
-
- if (!offset)
- return;
-
- firstImage = t->base.Image[0][t->minLod];
- row_align = rmesa->radeon.texture_row_align - 1;
- size = ((_mesa_format_row_stride(firstImage->TexFormat, firstImage->Width) + row_align) & ~row_align) * firstImage->Height;
- if (t->bo) {
- radeon_bo_unref(t->bo);
- t->bo = NULL;
- }
- t->bo = radeon_legacy_bo_alloc_fake(rmesa->radeon.radeonScreen->bom, size, offset);
- t->override_offset = offset;
- pitch_val = pitch;
- switch (depth) {
- case 32:
- SETfield(t->SQ_TEX_RESOURCE7, FMT_8_8_8_8,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
-
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- pitch_val /= 4;
- break;
- case 24:
- default:
- SETfield(t->SQ_TEX_RESOURCE7, FMT_8_8_8_8,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
-
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- pitch_val /= 4;
- break;
- case 16:
- SETfield(t->SQ_TEX_RESOURCE7, FMT_5_6_5,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
-
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- pitch_val /= 2;
- break;
- }
-
- pitch_val = (pitch_val + R700_TEXEL_PITCH_ALIGNMENT_MASK)
- & ~R700_TEXEL_PITCH_ALIGNMENT_MASK;
-
- /* min pitch is 8 */
- if (pitch_val < 8)
- pitch_val = 8;
-
- SETfield(t->SQ_TEX_RESOURCE0, (pitch_val/8)-1,
- EG_SQ_TEX_RESOURCE_WORD0_0__PITCH_shift,
- EG_SQ_TEX_RESOURCE_WORD0_0__PITCH_mask);
-}
-
-void evergreenSetTexBuffer(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_format, __DRIdrawable *dPriv)
-{
- struct gl_texture_unit *texUnit;
- struct gl_texture_object *texObj;
- struct gl_texture_image *texImage;
- struct radeon_renderbuffer *rb;
- radeon_texture_image *rImage;
- radeonContextPtr radeon;
- struct radeon_framebuffer *rfb;
- radeonTexObjPtr t;
- uint32_t pitch_val;
- gl_format texFormat;
-
- radeon = pDRICtx->driverPrivate;
-
- rfb = dPriv->driverPrivate;
- texUnit = &radeon->glCtx->Texture.Unit[radeon->glCtx->Texture.CurrentUnit];
- texObj = _mesa_select_tex_object(radeon->glCtx, texUnit, target);
- texImage = _mesa_get_tex_image(radeon->glCtx, texObj, target, 0);
-
- rImage = get_radeon_texture_image(texImage);
- t = radeon_tex_obj(texObj);
- if (t == NULL) {
- return;
- }
-
- radeon_update_renderbuffers(pDRICtx, dPriv, GL_TRUE);
- rb = rfb->color_rb[0];
- if (rb->bo == NULL) {
- /* Failed to BO for the buffer */
- return;
- }
-
- _mesa_lock_texture(radeon->glCtx, texObj);
- if (t->bo) {
- radeon_bo_unref(t->bo);
- t->bo = NULL;
- }
- if (rImage->bo) {
- radeon_bo_unref(rImage->bo);
- rImage->bo = NULL;
- }
-
- radeon_miptree_unreference(&t->mt);
- radeon_miptree_unreference(&rImage->mt);
-
- rImage->bo = rb->bo;
- radeon_bo_ref(rImage->bo);
- t->bo = rb->bo;
- radeon_bo_ref(t->bo);
- t->image_override = GL_TRUE;
- t->override_offset = 0;
- pitch_val = rb->pitch;
- switch (rb->cpp) {
- case 4:
- if (glx_texture_format == __DRI_TEXTURE_FORMAT_RGB) {
- texFormat = MESA_FORMAT_RGB888;
- SETfield(t->SQ_TEX_RESOURCE7, FMT_8_8_8_8,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
-
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- } else {
- texFormat = MESA_FORMAT_ARGB8888;
- SETfield(t->SQ_TEX_RESOURCE7, FMT_8_8_8_8,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
-
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- }
- pitch_val /= 4;
- break;
- case 3:
- default:
- // FMT_8_8_8 ???
- texFormat = MESA_FORMAT_RGB888;
- SETfield(t->SQ_TEX_RESOURCE7, FMT_8_8_8_8,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
-
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- pitch_val /= 4;
- break;
- case 2:
- texFormat = MESA_FORMAT_RGB565;
- SETfield(t->SQ_TEX_RESOURCE7, FMT_5_6_5,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
- EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
-
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- pitch_val /= 2;
- break;
- }
-
- _mesa_init_teximage_fields(radeon->glCtx, target, texImage,
- rb->base.Width, rb->base.Height, 1, 0,
- rb->cpp, texFormat);
- rImage->base.RowStride = rb->pitch / rb->cpp;
-
- pitch_val = (pitch_val + R700_TEXEL_PITCH_ALIGNMENT_MASK)
- & ~R700_TEXEL_PITCH_ALIGNMENT_MASK;
-
- /* min pitch is 8 */
- if (pitch_val < 8)
- pitch_val = 8;
-
- SETfield(t->SQ_TEX_RESOURCE0, (pitch_val/8)-1,
- EG_SQ_TEX_RESOURCE_WORD0_0__PITCH_shift,
- EG_SQ_TEX_RESOURCE_WORD0_0__PITCH_mask);
- SETfield(t->SQ_TEX_RESOURCE0, rb->base.Width - 1,
- EG_SQ_TEX_RESOURCE_WORD0_0__TEX_WIDTH_shift,
- EG_SQ_TEX_RESOURCE_WORD0_0__TEX_WIDTH_mask);
- SETfield(t->SQ_TEX_RESOURCE1, rb->base.Height - 1,
- EG_SQ_TEX_RESOURCE_WORD1_0__TEX_HEIGHT_shift,
- EG_SQ_TEX_RESOURCE_WORD1_0__TEX_HEIGHT_mask);
-
- t->validated = GL_TRUE;
- _mesa_unlock_texture(radeon->glCtx, texObj);
- return;
-}
-
-void evergreenUpdateTextureState(struct gl_context * ctx)
-{
- context_t *context = EVERGREEN_CONTEXT(ctx);
- EVERGREEN_CHIP_CONTEXT * evergreen = GET_EVERGREEN_CHIP(context);
- struct gl_texture_unit *texUnit;
- struct radeon_tex_obj *t;
- GLuint unit;
-
- EVERGREEN_STATECHANGE(context, tx);
-
- for (unit = 0; unit < R700_MAX_TEXTURE_UNITS; unit++) {
- texUnit = &ctx->Texture.Unit[unit];
- t = radeon_tex_obj(ctx->Texture.Unit[unit]._Current);
- evergreen->textures[unit] = NULL;
- if (texUnit->_ReallyEnabled) {
- if (!t)
- continue;
- evergreen->textures[unit] = t;
- }
- }
-}
-
-static GLboolean evergreen_validate_texture(struct gl_context * ctx, struct gl_texture_object *texObj, int unit)
-{
- radeonTexObj *t = radeon_tex_obj(texObj);
-
- if (!radeon_validate_texture_miptree(ctx, texObj))
- return GL_FALSE;
-
- /* Configure the hardware registers (more precisely, the cached version
- * of the hardware registers). */
- if (!evergreen_setup_hardware_state(ctx, texObj, unit))
- return GL_FALSE;
-
- t->validated = GL_TRUE;
- return GL_TRUE;
-}
-
-GLboolean evergreenValidateBuffers(struct gl_context * ctx)
-{
- context_t *rmesa = EVERGREEN_CONTEXT(ctx);
- struct radeon_renderbuffer *rrb;
- struct radeon_bo *pbo;
- int i;
- int ret;
-
- radeon_cs_space_reset_bos(rmesa->radeon.cmdbuf.cs);
-
- rrb = radeon_get_colorbuffer(&rmesa->radeon);
- /* color buffer */
- if (rrb && rrb->bo) {
- radeon_cs_space_add_persistent_bo(rmesa->radeon.cmdbuf.cs,
- rrb->bo, 0,
- RADEON_GEM_DOMAIN_VRAM);
- }
-
- /* depth buffer */
- rrb = radeon_get_depthbuffer(&rmesa->radeon);
- if (rrb && rrb->bo) {
- radeon_cs_space_add_persistent_bo(rmesa->radeon.cmdbuf.cs,
- rrb->bo, 0,
- RADEON_GEM_DOMAIN_VRAM);
- }
-
- for (i = 0; i < ctx->Const.MaxTextureImageUnits; ++i) {
- radeonTexObj *t;
-
- if (!ctx->Texture.Unit[i]._ReallyEnabled)
- continue;
-
- if (!evergreen_validate_texture(ctx, ctx->Texture.Unit[i]._Current, i)) {
- radeon_warning("failed to validate texture for unit %d.\n", i);
- }
- t = radeon_tex_obj(ctx->Texture.Unit[i]._Current);
- if (t->image_override && t->bo)
- radeon_cs_space_add_persistent_bo(rmesa->radeon.cmdbuf.cs,
- t->bo,
- RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
- else if (t->mt->bo)
- radeon_cs_space_add_persistent_bo(rmesa->radeon.cmdbuf.cs,
- t->mt->bo,
- RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
- }
-
- pbo = (struct radeon_bo *)evergreenGetActiveFpShaderBo(ctx);
- if (pbo) {
- radeon_cs_space_add_persistent_bo(rmesa->radeon.cmdbuf.cs, pbo,
- RADEON_GEM_DOMAIN_GTT, 0);
- }
-
- pbo = (struct radeon_bo *)evergreenGetActiveVpShaderBo(ctx);
- if (pbo) {
- radeon_cs_space_add_persistent_bo(rmesa->radeon.cmdbuf.cs, pbo,
- RADEON_GEM_DOMAIN_GTT, 0);
- }
-
- pbo = (struct radeon_bo *)evergreenGetActiveFpShaderConstBo(ctx);
- if (pbo) {
- radeon_cs_space_add_persistent_bo(rmesa->radeon.cmdbuf.cs, pbo,
- RADEON_GEM_DOMAIN_GTT, 0);
- }
-
- pbo = (struct radeon_bo *)evergreenGetActiveVpShaderConstBo(ctx);
- if (pbo) {
- radeon_cs_space_add_persistent_bo(rmesa->radeon.cmdbuf.cs, pbo,
- RADEON_GEM_DOMAIN_GTT, 0);
- }
-
- ret = radeon_cs_space_check_with_bo(rmesa->radeon.cmdbuf.cs, first_elem(&rmesa->radeon.dma.reserved)->bo, RADEON_GEM_DOMAIN_GTT, 0);
- if (ret)
- return GL_FALSE;
- return GL_TRUE;
-}
-
-static struct gl_texture_object *evergreenNewTextureObject(struct gl_context * ctx,
- GLuint name,
- GLenum target)
-{
- context_t* rmesa = EVERGREEN_CONTEXT(ctx);
- radeonTexObj * t = CALLOC_STRUCT(radeon_tex_obj);
-
-
- radeon_print(RADEON_STATE | RADEON_TEXTURE, RADEON_NORMAL,
- "%s( %p (target = %s) )\n", __FUNCTION__,
- t, _mesa_lookup_enum_by_nr(target));
-
- _mesa_initialize_texture_object(&t->base, name, target);
- t->base.Sampler.MaxAnisotropy = rmesa->radeon.initialMaxAnisotropy;
-
- evergreenSetTexDefaultState(t);
- evergreenUpdateTexWrap(t);
- evergreenSetTexFilter(t, t->base.Sampler.MinFilter, t->base.Sampler.MagFilter, t->base.Sampler.MaxAnisotropy);
- evergreenSetTexBorderColor(t, t->base.Sampler.BorderColor.f);
-
- return &t->base;
-}
-
-static void evergreenDeleteTexture(struct gl_context * ctx, struct gl_texture_object *texObj)
-{
- context_t * rmesa = EVERGREEN_CONTEXT(ctx);
- EVERGREEN_CHIP_CONTEXT * evergreen = GET_EVERGREEN_CHIP(rmesa);
- radeonTexObj* t = radeon_tex_obj(texObj);
-
- radeon_print(RADEON_STATE | RADEON_TEXTURE, RADEON_NORMAL,
- "%s( %p (target = %s) )\n", __FUNCTION__,
- (void *)texObj,
- _mesa_lookup_enum_by_nr(texObj->Target));
-
- if (rmesa) {
- int i;
- radeon_firevertices(&rmesa->radeon);
-
- for(i = 0; i < R700_MAX_TEXTURE_UNITS; ++i)
- if (evergreen->textures[i] == t)
- evergreen->textures[i] = 0;
- }
-
- if (t->bo) {
- radeon_bo_unref(t->bo);
- t->bo = NULL;
- }
-
- radeon_miptree_unreference(&t->mt);
-
- _mesa_delete_texture_object(ctx, texObj);
-}
-
-static void evergreenTexParameter(struct gl_context * ctx, GLenum target,
- struct gl_texture_object *texObj,
- GLenum pname, const GLfloat * params)
-{
- radeonTexObj* t = radeon_tex_obj(texObj);
- GLenum baseFormat;
-
- radeon_print(RADEON_STATE | RADEON_TEXTURE, RADEON_VERBOSE,
- "%s( %s )\n", __FUNCTION__,
- _mesa_lookup_enum_by_nr(pname));
-
- switch (pname) {
- case GL_TEXTURE_MIN_FILTER:
- case GL_TEXTURE_MAG_FILTER:
- case GL_TEXTURE_MAX_ANISOTROPY_EXT:
- evergreenSetTexFilter(t, texObj->Sampler.MinFilter, texObj->Sampler.MagFilter, texObj->Sampler.MaxAnisotropy);
- break;
-
- case GL_TEXTURE_WRAP_S:
- case GL_TEXTURE_WRAP_T:
- case GL_TEXTURE_WRAP_R:
- evergreenUpdateTexWrap(t);
- break;
-
- case GL_TEXTURE_BORDER_COLOR:
- evergreenSetTexBorderColor(t, texObj->Sampler.BorderColor.f);
- break;
-
- case GL_TEXTURE_BASE_LEVEL:
- case GL_TEXTURE_MAX_LEVEL:
- case GL_TEXTURE_MIN_LOD:
- case GL_TEXTURE_MAX_LOD:
- t->validated = GL_FALSE;
- break;
-
- case GL_DEPTH_TEXTURE_MODE:
- if (!texObj->Image[0][texObj->BaseLevel])
- return;
- baseFormat = texObj->Image[0][texObj->BaseLevel]->_BaseFormat;
- if (baseFormat == GL_DEPTH_COMPONENT ||
- baseFormat == GL_DEPTH_STENCIL) {
- evergreenSetDepthTexMode(texObj);
- break;
- } else {
- /* If the texture isn't a depth texture, changing this
- * state won't cause any changes to the hardware.
- * Don't force a flush of texture state.
- */
- return;
- }
-
- default:
- return;
- }
-}
-
-void evergreenInitTextureFuncs(radeonContextPtr radeon, struct dd_function_table *functions)
-{
- /* Note: we only plug in the functions we implement in the driver
- * since _mesa_init_driver_functions() was already called.
- */
-
- radeon_init_common_texture_funcs(radeon, functions);
-
- functions->NewTextureObject = evergreenNewTextureObject;
- functions->DeleteTexture = evergreenDeleteTexture;
- functions->IsTextureResident = driIsTextureResident;
-
- functions->TexParameter = evergreenTexParameter;
-}
+++ /dev/null
-/*
- * Copyright (C) 2008-2010 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Authors:
- * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
- */
-
-#ifndef _EVERGREEN_TEX_H_
-#define _EVERGREEN_TEX_H_
-
-extern GLboolean evergreenValidateBuffers(struct gl_context * ctx);
-
-extern void evergreenUpdateTextureState(struct gl_context * ctx);
-extern void evergreenInitTextureFuncs(radeonContextPtr radeon, struct dd_function_table *functions);
-extern void evergreenSetTexOffset(__DRIcontext * pDRICtx, GLint texname,
- unsigned long long offset, GLint depth, GLuint pitch);
-extern void evergreenSetTexBuffer(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_format, __DRIdrawable *dPriv);
-
-#endif /* _EVERGREEN_TEX_H_ */
+++ /dev/null
-/*
- * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Authors:
- * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
- */
-
-
-#include <stdio.h>
-#include <stdarg.h>
-#include <stdlib.h>
-#include <string.h>
-#include <math.h>
-
-#include "main/imports.h"
-#include "main/mtypes.h"
-
-#include "tnl/t_context.h"
-#include "program/program.h"
-#include "program/prog_parameter.h"
-#include "program/prog_statevars.h"
-
-#include "radeon_debug.h"
-#include "r600_context.h"
-#include "r600_cmdbuf.h"
-#include "r600_emit.h"
-#include "program/programopt.h"
-
-#include "evergreen_vertprog.h"
-
-unsigned int evergreen_Map_Vertex_Output(r700_AssemblerBase *pAsm,
- struct gl_vertex_program *mesa_vp,
- unsigned int unStart)
-{
- unsigned int i;
- unsigned int unBit;
- unsigned int unTotal = unStart;
-
- //!!!!!!! THE ORDER MATCH FS INPUT
-
- unBit = 1 << VERT_RESULT_HPOS;
- if(mesa_vp->Base.OutputsWritten & unBit)
- {
- pAsm->ucVP_OutputMap[VERT_RESULT_HPOS] = unTotal++;
- }
-
- unBit = 1 << VERT_RESULT_COL0;
- if(mesa_vp->Base.OutputsWritten & unBit)
- {
- pAsm->ucVP_OutputMap[VERT_RESULT_COL0] = unTotal++;
- }
-
- unBit = 1 << VERT_RESULT_COL1;
- if(mesa_vp->Base.OutputsWritten & unBit)
- {
- pAsm->ucVP_OutputMap[VERT_RESULT_COL1] = unTotal++;
- }
-
- //TODO : dealing back face.
- unBit = 1 << VERT_RESULT_BFC0;
- if(mesa_vp->Base.OutputsWritten & unBit)
- {
- pAsm->ucVP_OutputMap[VERT_RESULT_BFC0] = unTotal++;
- }
-
- unBit = 1 << VERT_RESULT_BFC1;
- if(mesa_vp->Base.OutputsWritten & unBit)
- {
- pAsm->ucVP_OutputMap[VERT_RESULT_BFC1] = unTotal++;
- }
-
- //TODO : dealing fog.
- unBit = 1 << VERT_RESULT_FOGC;
- if(mesa_vp->Base.OutputsWritten & unBit)
- {
- pAsm->ucVP_OutputMap[VERT_RESULT_FOGC] = unTotal++;
- }
-
- //TODO : dealing point size.
- unBit = 1 << VERT_RESULT_PSIZ;
- if(mesa_vp->Base.OutputsWritten & unBit)
- {
- pAsm->ucVP_OutputMap[VERT_RESULT_PSIZ] = unTotal++;
- }
-
- for(i=0; i<8; i++)
- {
- unBit = 1 << (VERT_RESULT_TEX0 + i);
- if(mesa_vp->Base.OutputsWritten & unBit)
- {
- pAsm->ucVP_OutputMap[VERT_RESULT_TEX0 + i] = unTotal++;
- }
- }
-
- for(i=VERT_RESULT_VAR0; i<VERT_RESULT_MAX; i++)
- {
- unBit = 1 << i;
- if(mesa_vp->Base.OutputsWritten & unBit)
- {
- pAsm->ucVP_OutputMap[i] = unTotal++;
- }
- }
-
- return (unTotal - unStart);
-}
-
-unsigned int evergreen_Map_Vertex_Input(r700_AssemblerBase *pAsm,
- struct gl_vertex_program *mesa_vp,
- unsigned int unStart)
-{
- int i;
- unsigned int unBit;
- unsigned int unTotal = unStart;
- for(i=0; i<VERT_ATTRIB_MAX; i++)
- {
- unBit = 1 << i;
- if(mesa_vp->Base.InputsRead & unBit)
- {
- pAsm->ucVP_AttributeMap[i] = unTotal++;
- }
- }
- return (unTotal - unStart);
-}
-
-GLboolean evergreen_Process_Vertex_Program_Vfetch_Instructions(
- struct evergreen_vertex_program *vp,
- struct gl_vertex_program *mesa_vp)
-{
- int i;
- unsigned int unBit;
- VTX_FETCH_METHOD vtxFetchMethod;
- vtxFetchMethod.bEnableMini = GL_FALSE;
- vtxFetchMethod.mega_fetch_remainder = 0;
-
- for(i=0; i<VERT_ATTRIB_MAX; i++)
- {
- unBit = 1 << i;
- if(mesa_vp->Base.InputsRead & unBit)
- {
- assemble_vfetch_instruction(&vp->r700AsmCode,
- i,
- vp->r700AsmCode.ucVP_AttributeMap[i],
- vp->aos_desc[i].size,
- vp->aos_desc[i].type,
- &vtxFetchMethod);
- }
- }
-
- return GL_TRUE;
-}
-
-GLboolean evergreen_Process_Vertex_Program_Vfetch_Instructions2(
- struct gl_context *ctx,
- struct evergreen_vertex_program *vp,
- struct gl_vertex_program *mesa_vp)
-{
- int i;
- context_t *context = R700_CONTEXT(ctx);
-
- VTX_FETCH_METHOD vtxFetchMethod;
- vtxFetchMethod.bEnableMini = GL_FALSE;
- vtxFetchMethod.mega_fetch_remainder = 0;
-
- for(i=0; i<context->nNumActiveAos; i++)
- {
- EG_assemble_vfetch_instruction(&vp->r700AsmCode,
- vp->r700AsmCode.ucVP_AttributeMap[context->stream_desc[i].element],
- context->stream_desc[i].type,
- context->stream_desc[i].size,
- context->stream_desc[i].element,
- context->stream_desc[i]._signed,
- context->stream_desc[i].normalize,
- context->stream_desc[i].format,
- &vtxFetchMethod);
- }
-
- return GL_TRUE;
-}
-
-void evergreen_Map_Vertex_Program(struct gl_context *ctx,
- struct evergreen_vertex_program *vp,
- struct gl_vertex_program *mesa_vp)
-{
- r700_AssemblerBase *pAsm = &(vp->r700AsmCode);
- unsigned int num_inputs;
-
- // R0 will always be used for index into vertex buffer
- pAsm->number_used_registers = 1;
- pAsm->starting_vfetch_register_number = pAsm->number_used_registers;
-
- // Map Inputs: Add 1 to mapping since R0 is used for index
- num_inputs = evergreen_Map_Vertex_Input(pAsm, mesa_vp, pAsm->number_used_registers);
- pAsm->number_used_registers += num_inputs;
-
- // Create VFETCH instructions for inputs
- if (GL_TRUE != evergreen_Process_Vertex_Program_Vfetch_Instructions2(ctx, vp, mesa_vp) )
- {
- radeon_error("Calling evergreen_Process_Vertex_Program_Vfetch_Instructions2 return error. \n");
- return;
- }
-
- // Map Outputs
- pAsm->number_of_exports = evergreen_Map_Vertex_Output(pAsm, mesa_vp, pAsm->number_used_registers);
-
- pAsm->starting_export_register_number = pAsm->number_used_registers;
-
- pAsm->number_used_registers += pAsm->number_of_exports;
-
- /* Map temporary registers (GPRs) */
- pAsm->starting_temp_register_number = pAsm->number_used_registers;
-
- if(mesa_vp->Base.NumNativeTemporaries >= mesa_vp->Base.NumTemporaries)
- { /* arb uses NumNativeTemporaries */
- pAsm->number_used_registers += mesa_vp->Base.NumNativeTemporaries;
- }
- else
- { /* fix func t_vp uses NumTemporaries */
- pAsm->number_used_registers += mesa_vp->Base.NumTemporaries;
- }
-
- pAsm->flag_reg_index = pAsm->number_used_registers++;
-
- pAsm->uFirstHelpReg = pAsm->number_used_registers;
-}
-
-GLboolean evergreen_Find_Instruction_Dependencies_vp(struct evergreen_vertex_program *vp,
- struct gl_vertex_program *mesa_vp)
-{
- GLuint i, j;
- GLint * puiTEMPwrites;
- struct prog_instruction *pILInst;
- InstDeps *pInstDeps;
-
- puiTEMPwrites = (GLint*) MALLOC(sizeof(GLuint)*mesa_vp->Base.NumTemporaries);
- for(i=0; i<mesa_vp->Base.NumTemporaries; i++)
- {
- puiTEMPwrites[i] = -1;
- }
-
- pInstDeps = (InstDeps*)MALLOC(sizeof(InstDeps)*mesa_vp->Base.NumInstructions);
-
- for(i=0; i<mesa_vp->Base.NumInstructions; i++)
- {
- pInstDeps[i].nDstDep = -1;
- pILInst = &(mesa_vp->Base.Instructions[i]);
-
- //Dst
- if(pILInst->DstReg.File == PROGRAM_TEMPORARY)
- {
- //Set lastwrite for the temp
- puiTEMPwrites[pILInst->DstReg.Index] = i;
- }
-
- //Src
- for(j=0; j<3; j++)
- {
- if(pILInst->SrcReg[j].File == PROGRAM_TEMPORARY)
- {
- //Set dep.
- pInstDeps[i].nSrcDeps[j] = puiTEMPwrites[pILInst->SrcReg[j].Index];
- }
- else
- {
- pInstDeps[i].nSrcDeps[j] = -1;
- }
- }
- }
-
- vp->r700AsmCode.pInstDeps = pInstDeps;
-
- FREE(puiTEMPwrites);
-
- return GL_TRUE;
-}
-
-struct evergreen_vertex_program* evergreenTranslateVertexShader(struct gl_context *ctx,
- struct gl_vertex_program *mesa_vp)
-{
- context_t *context = EVERGREEN_CONTEXT(ctx);
-
- struct evergreen_vertex_program *vp;
- unsigned int i;
-
- vp = calloc(1, sizeof(*vp));
- vp->mesa_program = _mesa_clone_vertex_program(ctx, mesa_vp);
-
- vp->constbo0 = NULL;
-
- if (mesa_vp->IsPositionInvariant)
- {
- _mesa_insert_mvp_code(ctx, vp->mesa_program);
- }
-
- for(i=0; i<context->nNumActiveAos; i++)
- {
- vp->aos_desc[i].size = context->stream_desc[i].size;
- vp->aos_desc[i].stride = context->stream_desc[i].stride;
- vp->aos_desc[i].type = context->stream_desc[i].type;
- vp->aos_desc[i].format = context->stream_desc[i].format;
- }
-
- if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
- {
- vp->r700AsmCode.bR6xx = 1;
- }
-
- //Init_Program
- Init_r700_AssemblerBase(SPT_VP, &(vp->r700AsmCode), &(vp->r700Shader) );
-
- vp->r700AsmCode.bUseMemConstant = GL_TRUE;
- vp->r700AsmCode.unAsic = 8;
-
- evergreen_Map_Vertex_Program(ctx, vp, vp->mesa_program );
-
- if(GL_FALSE == evergreen_Find_Instruction_Dependencies_vp(vp, vp->mesa_program))
- {
- return NULL;
- }
-
- InitShaderProgram(&(vp->r700AsmCode));
-
- for(i=0; i < MAX_SAMPLERS; i++)
- {
- vp->r700AsmCode.SamplerUnits[i] = vp->mesa_program->Base.SamplerUnits[i];
- }
-
- vp->r700AsmCode.unCurNumILInsts = vp->mesa_program->Base.NumInstructions;
-
- if(GL_FALSE == AssembleInstr(0,
- 0,
- vp->mesa_program->Base.NumInstructions,
- &(vp->mesa_program->Base.Instructions[0]),
- &(vp->r700AsmCode)) )
- {
- return NULL;
- }
-
- if(GL_FALSE == Process_Vertex_Exports(&(vp->r700AsmCode), vp->mesa_program->Base.OutputsWritten) )
- {
- return NULL;
- }
-
- if( GL_FALSE == RelocProgram(&(vp->r700AsmCode), &(vp->mesa_program->Base)) )
- {
- return GL_FALSE;
- }
-
- vp->r700Shader.nRegs = (vp->r700AsmCode.number_used_registers == 0) ? 0
- : (vp->r700AsmCode.number_used_registers - 1);
-
- vp->r700Shader.nParamExports = vp->r700AsmCode.number_of_exports;
-
- vp->translated = GL_TRUE;
-
- return vp;
-}
-
-void evergreenSelectVertexShader(struct gl_context *ctx)
-{
- context_t *context = EVERGREEN_CONTEXT(ctx);
- struct evergreen_vertex_program_cont *vpc;
- struct evergreen_vertex_program *vp;
- unsigned int i;
- GLboolean match;
- GLbitfield InputsRead;
-
- vpc = (struct evergreen_vertex_program_cont *)ctx->VertexProgram._Current;
-
- InputsRead = vpc->mesa_program.Base.InputsRead;
- if (vpc->mesa_program.IsPositionInvariant)
- {
- InputsRead |= VERT_BIT_POS;
- }
-
- for (vp = vpc->progs; vp; vp = vp->next)
- {
- match = GL_TRUE;
- for(i=0; i<context->nNumActiveAos; i++)
- {
- if (vp->aos_desc[i].size != context->stream_desc[i].size ||
- vp->aos_desc[i].format != context->stream_desc[i].format)
- {
- match = GL_FALSE;
- break;
- }
- }
- if (match)
- {
- context->selected_vp = (struct r700_vertex_program *) vp;
- return;
- }
- }
-
- vp = evergreenTranslateVertexShader(ctx, &(vpc->mesa_program));
- if(!vp)
- {
- radeon_error("Failed to translate vertex shader. \n");
- return;
- }
- vp->next = vpc->progs;
- vpc->progs = vp;
- context->selected_vp = (struct r700_vertex_program *) vp;
- return;
-}
-
-int evergreen_getTypeSize(GLenum type)
-{
- switch (type)
- {
- case GL_DOUBLE:
- return sizeof(GLdouble);
- case GL_FLOAT:
- return sizeof(GLfloat);
- case GL_INT:
- return sizeof(GLint);
- case GL_UNSIGNED_INT:
- return sizeof(GLuint);
- case GL_SHORT:
- return sizeof(GLshort);
- case GL_UNSIGNED_SHORT:
- return sizeof(GLushort);
- case GL_BYTE:
- return sizeof(GLbyte);
- case GL_UNSIGNED_BYTE:
- return sizeof(GLubyte);
- default:
- assert(0);
- return 0;
- }
-}
-
-static void evergreenTranslateAttrib(struct gl_context *ctx, GLuint unLoc, int count, const struct gl_client_array *input)
-{
- context_t *context = EVERGREEN_CONTEXT(ctx);
-
- StreamDesc * pStreamDesc = &(context->stream_desc[context->nNumActiveAos]);
-
- GLuint stride;
-
- stride = (input->StrideB == 0) ? evergreen_getTypeSize(input->Type) * input->Size
- : input->StrideB;
-
- if (input->Type == GL_DOUBLE || input->Type == GL_UNSIGNED_INT || input->Type == GL_INT
-#if MESA_BIG_ENDIAN
- || evergreen_getTypeSize(input->Type) != 4
-#endif
- )
- {
- pStreamDesc->type = GL_FLOAT;
-
- if (input->StrideB == 0)
- {
- pStreamDesc->stride = 0;
- }
- else
- {
- pStreamDesc->stride = sizeof(GLfloat) * input->Size;
- }
- pStreamDesc->dwords = input->Size;
- pStreamDesc->is_named_bo = GL_FALSE;
- }
- else
- {
- pStreamDesc->type = input->Type;
- pStreamDesc->dwords = (evergreen_getTypeSize(input->Type) * input->Size + 3)/ 4;
- if (!input->BufferObj->Name)
- {
- if (input->StrideB == 0)
- {
- pStreamDesc->stride = 0;
- }
- else
- {
- pStreamDesc->stride = (evergreen_getTypeSize(pStreamDesc->type) * input->Size + 3) & ~3;
- }
-
- pStreamDesc->is_named_bo = GL_FALSE;
- }
- }
-
- pStreamDesc->size = input->Size;
- pStreamDesc->dst_loc = context->nNumActiveAos;
- pStreamDesc->element = unLoc;
- pStreamDesc->format = input->Format;
-
- switch (pStreamDesc->type)
- { //GetSurfaceFormat
- case GL_FLOAT:
- pStreamDesc->_signed = 0;
- pStreamDesc->normalize = GL_FALSE;
- break;
- case GL_SHORT:
- pStreamDesc->_signed = 1;
- pStreamDesc->normalize = input->Normalized;
- break;
- case GL_BYTE:
- pStreamDesc->_signed = 1;
- pStreamDesc->normalize = input->Normalized;
- break;
- case GL_UNSIGNED_SHORT:
- pStreamDesc->_signed = 0;
- pStreamDesc->normalize = input->Normalized;
- break;
- case GL_UNSIGNED_BYTE:
- pStreamDesc->_signed = 0;
- pStreamDesc->normalize = input->Normalized;
- break;
- default:
- case GL_INT:
- case GL_UNSIGNED_INT:
- case GL_DOUBLE:
- assert(0);
- break;
- }
- context->nNumActiveAos++;
-}
-
-void evergreenSetVertexFormat(struct gl_context *ctx, const struct gl_client_array *arrays[], int count)
-{
- context_t *context = EVERGREEN_CONTEXT(ctx);
- struct evergreen_vertex_program *vpc
- = (struct evergreen_vertex_program *)ctx->VertexProgram._Current;
-
- struct gl_vertex_program * mesa_vp = (struct gl_vertex_program *)&(vpc->mesa_program);
- unsigned int unLoc = 0;
- unsigned int unBit = mesa_vp->Base.InputsRead;
- context->nNumActiveAos = 0;
-
- if (mesa_vp->IsPositionInvariant)
- {
- unBit |= VERT_BIT_POS;
- }
-
- while(unBit)
- {
- if(unBit & 1)
- {
- evergreenTranslateAttrib(ctx, unLoc, count, arrays[unLoc]);
- }
-
- unBit >>= 1;
- ++unLoc;
- }
- context->radeon.tcl.aos_count = context->nNumActiveAos;
-}
-
-void * evergreenGetActiveVpShaderBo(struct gl_context * ctx)
-{
- context_t *context = EVERGREEN_CONTEXT(ctx);
- struct evergreen_vertex_program *vp = (struct evergreen_vertex_program *) context->selected_vp;
-
- if (vp)
- return vp->shaderbo;
- else
- return NULL;
-}
-
-void * evergreenGetActiveVpShaderConstBo(struct gl_context * ctx)
-{
- context_t *context = EVERGREEN_CONTEXT(ctx);
- struct evergreen_vertex_program *vp = (struct evergreen_vertex_program *) context->selected_vp;
-
- if (vp)
- return vp->constbo0;
- else
- return NULL;
-}
-
-GLboolean evergreenSetupVertexProgram(struct gl_context * ctx)
-{
- context_t *context = EVERGREEN_CONTEXT(ctx);
- EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
- struct evergreen_vertex_program *vp = (struct evergreen_vertex_program *) context->selected_vp;
-
- if(GL_FALSE == vp->loaded)
- {
- if(vp->r700Shader.bNeedsAssembly == GL_TRUE)
- {
- Assemble( &(vp->r700Shader) );
- }
-
- /* Load vp to gpu */
- r600EmitShader(ctx,
- &(vp->shaderbo),
- (GLvoid *)(vp->r700Shader.pProgram),
- vp->r700Shader.uShaderBinaryDWORDSize,
- "VS");
-
- vp->loaded = GL_TRUE;
- }
-
- EVERGREEN_STATECHANGE(context, vs);
-
- /* TODO : enable this after MemUse fixed *=
- (context->chipobj.MemUse)(context, vp->shadercode.buf->id);
- */
-
- evergreen->SQ_PGM_RESOURCES_VS.u32All = 0;
- SETbit(evergreen->SQ_PGM_RESOURCES_VS.u32All, PGM_RESOURCES__PRIME_CACHE_ON_DRAW_bit);
-
- evergreen->vs.SQ_ALU_CONST_CACHE_VS_0.u32All = 0; /* set from buffer object. */
-
- evergreen->vs.SQ_PGM_START_VS.u32All = 0;
-
- SETfield(evergreen->SQ_PGM_RESOURCES_VS.u32All, vp->r700Shader.nRegs + 1,
- NUM_GPRS_shift, NUM_GPRS_mask);
-
- if(vp->r700Shader.uStackSize) /* we don't use branch for now, it should be zero. */
- {
- SETfield(evergreen->SQ_PGM_RESOURCES_VS.u32All, vp->r700Shader.uStackSize,
- STACK_SIZE_shift, STACK_SIZE_mask);
- }
-
- EVERGREEN_STATECHANGE(context, spi);
-
- SETfield(evergreen->SPI_VS_OUT_CONFIG.u32All,
- vp->r700Shader.nParamExports ? (vp->r700Shader.nParamExports - 1) : 0,
- VS_EXPORT_COUNT_shift, VS_EXPORT_COUNT_mask);
- SETfield(evergreen->SPI_PS_IN_CONTROL_0.u32All, vp->r700Shader.nParamExports,
- NUM_INTERP_shift, NUM_INTERP_mask);
-
- /*
- SETbit(evergreen->SPI_PS_IN_CONTROL_0.u32All, PERSP_GRADIENT_ENA_bit);
- CLEARbit(evergreen->SPI_PS_IN_CONTROL_0.u32All, LINEAR_GRADIENT_ENA_bit);
- */
-
- return GL_TRUE;
-}
-
-GLboolean evergreenSetupVPconstants(struct gl_context * ctx)
-{
- context_t *context = EVERGREEN_CONTEXT(ctx);
- EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
- struct evergreen_vertex_program *vp = (struct evergreen_vertex_program *) context->selected_vp;
-
- struct gl_program_parameter_list *paramList;
- unsigned int unNumParamData;
- unsigned int ui;
- int alloc_size;
-
- /* sent out shader constants. */
- paramList = vp->mesa_program->Base.Parameters;
-
- if(NULL != paramList) {
- /* vp->mesa_program was cloned, not updated by glsl shader api. */
- /* _mesa_reference_program has already checked glsl shProg is ok and set ctx->VertexProgem._Current */
- /* so, use ctx->VertexProgem._Current */
- struct gl_program_parameter_list *paramListOrginal =
- ctx->VertexProgram._Current->Base.Parameters;
-
- _mesa_load_state_parameters(ctx, paramList);
-
- if (paramList->NumParameters > EVERGREEN_MAX_DX9_CONSTS)
- return GL_FALSE;
-
- EVERGREEN_STATECHANGE(context, vs);
-
- evergreen->vs.num_consts = paramList->NumParameters;
-
- unNumParamData = paramList->NumParameters;
-
- /* alloc multiple of 16 constants */
- alloc_size = ((unNumParamData * 4 * 4) + 255) & ~255;
-
- for(ui=0; ui<unNumParamData; ui++) {
- if(paramList->Parameters[ui].Type == PROGRAM_UNIFORM)
- {
- evergreen->vs.consts[ui][0].f32All = paramListOrginal->ParameterValues[ui][0].f;
- evergreen->vs.consts[ui][1].f32All = paramListOrginal->ParameterValues[ui][1].f;
- evergreen->vs.consts[ui][2].f32All = paramListOrginal->ParameterValues[ui][2].f;
- evergreen->vs.consts[ui][3].f32All = paramListOrginal->ParameterValues[ui][3].f;
- }
- else
- {
- evergreen->vs.consts[ui][0].f32All = paramList->ParameterValues[ui][0].f;
- evergreen->vs.consts[ui][1].f32All = paramList->ParameterValues[ui][1].f;
- evergreen->vs.consts[ui][2].f32All = paramList->ParameterValues[ui][2].f;
- evergreen->vs.consts[ui][3].f32All = paramList->ParameterValues[ui][3].f;
- }
- }
-
- radeonAllocDmaRegion(&context->radeon,
- &context->vp_Constbo,
- &context->vp_bo_offset,
- alloc_size,
- 256);
- r600EmitShaderConsts(ctx,
- context->vp_Constbo,
- context->vp_bo_offset,
- (GLvoid *)&(evergreen->vs.consts[0][0]),
- unNumParamData * 4 * 4);
- } else
- evergreen->vs.num_consts = 0;
-
- COMPILED_SUB * pCompiledSub;
- GLuint uj;
- GLuint unConstOffset = evergreen->vs.num_consts;
- for(ui=0; ui<vp->r700AsmCode.unNumPresub; ui++)
- {
- pCompiledSub = vp->r700AsmCode.presubs[ui].pCompiledSub;
-
- evergreen->vs.num_consts += pCompiledSub->NumParameters;
-
- for(uj=0; uj<pCompiledSub->NumParameters; uj++)
- {
- evergreen->vs.consts[uj + unConstOffset][0].f32All = pCompiledSub->ParameterValues[uj][0];
- evergreen->vs.consts[uj + unConstOffset][1].f32All = pCompiledSub->ParameterValues[uj][1];
- evergreen->vs.consts[uj + unConstOffset][2].f32All = pCompiledSub->ParameterValues[uj][2];
- evergreen->vs.consts[uj + unConstOffset][3].f32All = pCompiledSub->ParameterValues[uj][3];
- }
- unConstOffset += pCompiledSub->NumParameters;
- }
-
- return GL_TRUE;
-}
-
+++ /dev/null
-/*
- * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Authors:
- * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
- */
-
-
-#ifndef _EVERGREEN_VERTPROG_H_
-#define _EVERGREEN_VERTPROG_H_
-
-#include "main/glheader.h"
-#include "main/mtypes.h"
-
-#include "r700_shader.h"
-#include "r700_assembler.h"
-
-typedef struct evergreenArrayDesc //TEMP
-{
- GLint size; //number of data element
- GLenum type; //data element type
- GLsizei stride;
- GLenum format; //GL_RGBA or GL_BGRA
-} evergreenArrayDesc;
-
-struct evergreen_vertex_program
-{
- struct gl_vertex_program *mesa_program; /* Must be first */
-
- struct evergreen_vertex_program *next;
-
- r700_AssemblerBase r700AsmCode;
- R700_Shader r700Shader;
-
- GLboolean translated;
- GLboolean loaded;
-
- void * shaderbo;
-
- GLuint K0used;
- void * constbo0;
-
- evergreenArrayDesc aos_desc[VERT_ATTRIB_MAX];
-};
-
-struct evergreen_vertex_program_cont
-{
- struct gl_vertex_program mesa_program;
-
- struct evergreen_vertex_program *progs;
-};
-
-//Internal
-unsigned int evergreen_Map_Vertex_Output(r700_AssemblerBase *pAsm,
- struct gl_vertex_program *mesa_vp,
- unsigned int unStart);
-unsigned int evergreen_Map_Vertex_Input(r700_AssemblerBase *pAsm,
- struct gl_vertex_program *mesa_vp,
- unsigned int unStart);
-GLboolean evergreen_Process_Vertex_Program_Vfetch_Instructions(
- struct evergreen_vertex_program *vp,
- struct gl_vertex_program *mesa_vp);
-GLboolean evergreen_Process_Vertex_Program_Vfetch_Instructions2(
- struct gl_context *ctx,
- struct evergreen_vertex_program *vp,
- struct gl_vertex_program *mesa_vp);
-void evergreen_Map_Vertex_Program(struct gl_context *ctx,
- struct evergreen_vertex_program *vp,
- struct gl_vertex_program *mesa_vp);
-GLboolean evergreen_Find_Instruction_Dependencies_vp(struct evergreen_vertex_program *vp,
- struct gl_vertex_program *mesa_vp);
-
-struct evergreen_vertex_program* evergreenTranslateVertexShader(struct gl_context *ctx,
- struct gl_vertex_program *mesa_vp);
-
-/* Interface */
-extern void evergreenSelectVertexShader(struct gl_context *ctx);
-extern void evergreenSetVertexFormat(struct gl_context *ctx, const struct gl_client_array *arrays[], int count);
-
-extern GLboolean evergreenSetupVertexProgram(struct gl_context * ctx);
-
-extern GLboolean evergreenSetupVPconstants(struct gl_context * ctx);
-
-extern void * evergreenGetActiveVpShaderBo(struct gl_context * ctx);
-
-extern void * evergreenGetActiveVpShaderConstBo(struct gl_context * ctx);
-
-extern int evergreen_getTypeSize(GLenum type);
-
-#endif /* _EVERGREEN_VERTPROG_H_ */
+++ /dev/null
-/*
- * Copyright (C) 2009 Advanced Micro Devices, Inc.
- *
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial
- * portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
- * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
- * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
- * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-
-#include "radeon_common.h"
-#include "r600_context.h"
-
-#include "r600_blit.h"
-#include "r600_blit_shaders.h"
-#include "r600_cmdbuf.h"
-
-/* common formats supported as both textures and render targets */
-unsigned r600_check_blit(gl_format mesa_format)
-{
- switch (mesa_format) {
- case MESA_FORMAT_RGBA8888:
- case MESA_FORMAT_SIGNED_RGBA8888:
- case MESA_FORMAT_RGBA8888_REV:
- case MESA_FORMAT_SIGNED_RGBA8888_REV:
- case MESA_FORMAT_ARGB8888:
- case MESA_FORMAT_XRGB8888:
- case MESA_FORMAT_ARGB8888_REV:
- case MESA_FORMAT_XRGB8888_REV:
- case MESA_FORMAT_RGB565:
- case MESA_FORMAT_RGB565_REV:
- case MESA_FORMAT_ARGB4444:
- case MESA_FORMAT_ARGB4444_REV:
- case MESA_FORMAT_ARGB1555:
- case MESA_FORMAT_ARGB1555_REV:
- case MESA_FORMAT_AL88:
- case MESA_FORMAT_AL88_REV:
- case MESA_FORMAT_RGB332:
- case MESA_FORMAT_A8:
- case MESA_FORMAT_I8:
- case MESA_FORMAT_L8:
- case MESA_FORMAT_RGBA_FLOAT32:
- case MESA_FORMAT_RGBA_FLOAT16:
- case MESA_FORMAT_ALPHA_FLOAT32:
- case MESA_FORMAT_ALPHA_FLOAT16:
- case MESA_FORMAT_LUMINANCE_FLOAT32:
- case MESA_FORMAT_LUMINANCE_FLOAT16:
- case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32:
- case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16:
- case MESA_FORMAT_INTENSITY_FLOAT32: /* X, X, X, X */
- case MESA_FORMAT_INTENSITY_FLOAT16: /* X, X, X, X */
- case MESA_FORMAT_X8_Z24:
- case MESA_FORMAT_S8_Z24:
- case MESA_FORMAT_Z24_S8:
- case MESA_FORMAT_Z16:
- case MESA_FORMAT_Z32:
- case MESA_FORMAT_SARGB8:
- case MESA_FORMAT_SLA8:
- case MESA_FORMAT_SL8:
- break;
- default:
- return 0;
- }
-
- /* ??? */
- /* not sure blit to depth works or not yet */
- if (_mesa_get_format_bits(mesa_format, GL_DEPTH_BITS) > 0)
- return 0;
-
- return 1;
-}
-
-static inline void
-set_render_target(context_t *context, struct radeon_bo *bo, gl_format mesa_format,
- int nPitchInPixel, int w, int h, intptr_t dst_offset)
-{
- uint32_t cb_color0_base, cb_color0_size = 0, cb_color0_info = 0, cb_color0_view = 0;
- int id = 0;
- uint32_t endian, comp_swap, format;
- BATCH_LOCALS(&context->radeon);
-
- cb_color0_base = dst_offset / 256;
- endian = ENDIAN_NONE;
-
- SETfield(cb_color0_size, (nPitchInPixel / 8) - 1,
- PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask);
- SETfield(cb_color0_size, ((nPitchInPixel * h) / 64) - 1,
- SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask);
-
- SETfield(cb_color0_info, ARRAY_LINEAR_GENERAL,
- CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
-
- SETbit(cb_color0_info, BLEND_BYPASS_bit);
-
- switch(mesa_format) {
- case MESA_FORMAT_RGBA8888:
-#ifdef MESA_BIG_ENDIAN
- endian = ENDIAN_8IN32;
-#endif
- format = COLOR_8_8_8_8;
- comp_swap = SWAP_STD_REV;
- SETbit(cb_color0_info, SOURCE_FORMAT_bit);
- SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
- break;
- case MESA_FORMAT_SIGNED_RGBA8888:
-#ifdef MESA_BIG_ENDIAN
- endian = ENDIAN_8IN32;
-#endif
- format = COLOR_8_8_8_8;
- comp_swap = SWAP_STD_REV;
- SETbit(cb_color0_info, SOURCE_FORMAT_bit);
- SETfield(cb_color0_info, NUMBER_SNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
- break;
- case MESA_FORMAT_RGBA8888_REV:
-#ifdef MESA_BIG_ENDIAN
- endian = ENDIAN_8IN32;
-#endif
- format = COLOR_8_8_8_8;
- comp_swap = SWAP_STD;
- SETbit(cb_color0_info, SOURCE_FORMAT_bit);
- SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
- break;
- case MESA_FORMAT_SIGNED_RGBA8888_REV:
-#ifdef MESA_BIG_ENDIAN
- endian = ENDIAN_8IN32;
-#endif
- format = COLOR_8_8_8_8;
- comp_swap = SWAP_STD;
- SETbit(cb_color0_info, SOURCE_FORMAT_bit);
- SETfield(cb_color0_info, NUMBER_SNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
- break;
- case MESA_FORMAT_ARGB8888:
- case MESA_FORMAT_XRGB8888:
-#ifdef MESA_BIG_ENDIAN
- endian = ENDIAN_8IN32;
-#endif
- format = COLOR_8_8_8_8;
- comp_swap = SWAP_ALT;
- SETbit(cb_color0_info, SOURCE_FORMAT_bit);
- SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
- break;
- case MESA_FORMAT_ARGB8888_REV:
- case MESA_FORMAT_XRGB8888_REV:
-#ifdef MESA_BIG_ENDIAN
- endian = ENDIAN_8IN32;
-#endif
- format = COLOR_8_8_8_8;
- comp_swap = SWAP_ALT_REV;
- SETbit(cb_color0_info, SOURCE_FORMAT_bit);
- SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
- break;
- case MESA_FORMAT_RGB565:
-#ifdef MESA_BIG_ENDIAN
- endian = ENDIAN_8IN16;
-#endif
- comp_swap = SWAP_STD_REV;
- format = COLOR_5_6_5;
- SETbit(cb_color0_info, SOURCE_FORMAT_bit);
- SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
- break;
- case MESA_FORMAT_RGB565_REV:
-#ifdef MESA_BIG_ENDIAN
- endian = ENDIAN_8IN16;
-#endif
- comp_swap = SWAP_STD;
- format = COLOR_5_6_5;
- SETbit(cb_color0_info, SOURCE_FORMAT_bit);
- SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
- break;
- case MESA_FORMAT_ARGB4444:
-#ifdef MESA_BIG_ENDIAN
- endian = ENDIAN_8IN16;
-#endif
- format = COLOR_4_4_4_4;
- comp_swap = SWAP_ALT;
- SETbit(cb_color0_info, SOURCE_FORMAT_bit);
- SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
- break;
- case MESA_FORMAT_ARGB4444_REV:
-#ifdef MESA_BIG_ENDIAN
- endian = ENDIAN_8IN16;
-#endif
- format = COLOR_4_4_4_4;
- comp_swap = SWAP_ALT_REV;
- SETbit(cb_color0_info, SOURCE_FORMAT_bit);
- SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
- break;
- case MESA_FORMAT_ARGB1555:
-#ifdef MESA_BIG_ENDIAN
- endian = ENDIAN_8IN16;
-#endif
- format = COLOR_1_5_5_5;
- comp_swap = SWAP_ALT;
- SETbit(cb_color0_info, SOURCE_FORMAT_bit);
- SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
- break;
- case MESA_FORMAT_ARGB1555_REV:
-#ifdef MESA_BIG_ENDIAN
- endian = ENDIAN_8IN16;
-#endif
- format = COLOR_1_5_5_5;
- comp_swap = SWAP_ALT_REV;
- SETbit(cb_color0_info, SOURCE_FORMAT_bit);
- SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
- break;
- case MESA_FORMAT_AL88:
-#ifdef MESA_BIG_ENDIAN
- endian = ENDIAN_8IN16;
-#endif
- format = COLOR_8_8;
- comp_swap = SWAP_STD;
- SETbit(cb_color0_info, SOURCE_FORMAT_bit);
- SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
- break;
- case MESA_FORMAT_AL88_REV:
-#ifdef MESA_BIG_ENDIAN
- endian = ENDIAN_8IN16;
-#endif
- format = COLOR_8_8;
- comp_swap = SWAP_STD_REV;
- SETbit(cb_color0_info, SOURCE_FORMAT_bit);
- SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
- break;
- case MESA_FORMAT_RGB332:
- format = COLOR_3_3_2;
- comp_swap = SWAP_STD_REV;
- SETbit(cb_color0_info, SOURCE_FORMAT_bit);
- SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
- break;
- case MESA_FORMAT_A8:
- format = COLOR_8;
- comp_swap = SWAP_ALT_REV;
- SETbit(cb_color0_info, SOURCE_FORMAT_bit);
- SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
- break;
- case MESA_FORMAT_I8:
- format = COLOR_8;
- comp_swap = SWAP_STD;
- SETbit(cb_color0_info, SOURCE_FORMAT_bit);
- SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
- break;
- case MESA_FORMAT_L8:
- format = COLOR_8;
- comp_swap = SWAP_ALT;
- SETbit(cb_color0_info, SOURCE_FORMAT_bit);
- SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
- break;
- case MESA_FORMAT_RGBA_FLOAT32:
-#ifdef MESA_BIG_ENDIAN
- endian = ENDIAN_8IN32;
-#endif
- format = COLOR_32_32_32_32_FLOAT;
- comp_swap = SWAP_STD;
- SETbit(cb_color0_info, BLEND_FLOAT32_bit);
- CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
- SETfield(cb_color0_info, NUMBER_FLOAT, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
- break;
- case MESA_FORMAT_RGBA_FLOAT16:
-#ifdef MESA_BIG_ENDIAN
- endian = ENDIAN_8IN16;
-#endif
- format = COLOR_16_16_16_16_FLOAT;
- comp_swap = SWAP_STD;
- CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
- SETfield(cb_color0_info, NUMBER_FLOAT, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
- break;
- case MESA_FORMAT_ALPHA_FLOAT32:
-#ifdef MESA_BIG_ENDIAN
- endian = ENDIAN_8IN32;
-#endif
- format = COLOR_32_FLOAT;
- comp_swap = SWAP_ALT_REV;
- SETbit(cb_color0_info, BLEND_FLOAT32_bit);
- CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
- SETfield(cb_color0_info, NUMBER_FLOAT, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
- break;
- case MESA_FORMAT_ALPHA_FLOAT16:
-#ifdef MESA_BIG_ENDIAN
- endian = ENDIAN_8IN16;
-#endif
- format = COLOR_16_FLOAT;
- comp_swap = SWAP_ALT_REV;
- CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
- SETfield(cb_color0_info, NUMBER_FLOAT, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
- break;
- case MESA_FORMAT_LUMINANCE_FLOAT32:
-#ifdef MESA_BIG_ENDIAN
- endian = ENDIAN_8IN32;
-#endif
- format = COLOR_32_FLOAT;
- comp_swap = SWAP_ALT;
- SETbit(cb_color0_info, BLEND_FLOAT32_bit);
- CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
- SETfield(cb_color0_info, NUMBER_FLOAT, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
- break;
- case MESA_FORMAT_LUMINANCE_FLOAT16:
-#ifdef MESA_BIG_ENDIAN
- endian = ENDIAN_8IN16;
-#endif
- format = COLOR_16_FLOAT;
- comp_swap = SWAP_ALT;
- CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
- SETfield(cb_color0_info, NUMBER_FLOAT, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
- break;
- case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32:
-#ifdef MESA_BIG_ENDIAN
- endian = ENDIAN_8IN32;
-#endif
- format = COLOR_32_32_FLOAT;
- comp_swap = SWAP_ALT_REV;
- SETbit(cb_color0_info, BLEND_FLOAT32_bit);
- CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
- SETfield(cb_color0_info, NUMBER_FLOAT, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
- break;
- case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16:
-#ifdef MESA_BIG_ENDIAN
- endian = ENDIAN_8IN16;
-#endif
- format = COLOR_16_16_FLOAT;
- comp_swap = SWAP_ALT_REV;
- CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
- SETfield(cb_color0_info, NUMBER_FLOAT, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
- break;
- case MESA_FORMAT_INTENSITY_FLOAT32: /* X, X, X, X */
-#ifdef MESA_BIG_ENDIAN
- endian = ENDIAN_8IN32;
-#endif
- format = COLOR_32_FLOAT;
- comp_swap = SWAP_STD;
- SETbit(cb_color0_info, BLEND_FLOAT32_bit);
- CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
- SETfield(cb_color0_info, NUMBER_FLOAT, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
- break;
- case MESA_FORMAT_INTENSITY_FLOAT16: /* X, X, X, X */
-#ifdef MESA_BIG_ENDIAN
- endian = ENDIAN_8IN16;
-#endif
- format = COLOR_16_FLOAT;
- comp_swap = SWAP_STD;
- CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
- SETfield(cb_color0_info, NUMBER_FLOAT, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
- break;
- case MESA_FORMAT_X8_Z24:
- case MESA_FORMAT_S8_Z24:
-#ifdef MESA_BIG_ENDIAN
- endian = ENDIAN_8IN32;
-#endif
- format = COLOR_8_24;
- comp_swap = SWAP_STD;
- SETfield(cb_color0_info, ARRAY_1D_TILED_THIN1,
- CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
- CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
- SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
- break;
- case MESA_FORMAT_Z24_S8:
-#ifdef MESA_BIG_ENDIAN
- endian = ENDIAN_8IN32;
-#endif
- format = COLOR_24_8;
- comp_swap = SWAP_STD;
- SETfield(cb_color0_info, ARRAY_1D_TILED_THIN1,
- CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
- CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
- SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
- break;
- case MESA_FORMAT_Z16:
-#ifdef MESA_BIG_ENDIAN
- endian = ENDIAN_8IN16;
-#endif
- format = COLOR_16;
- comp_swap = SWAP_STD;
- SETfield(cb_color0_info, ARRAY_1D_TILED_THIN1,
- CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
- CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
- SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
- break;
- case MESA_FORMAT_Z32:
-#ifdef MESA_BIG_ENDIAN
- endian = ENDIAN_8IN32;
-#endif
- format = COLOR_32;
- comp_swap = SWAP_STD;
- SETfield(cb_color0_info, ARRAY_1D_TILED_THIN1,
- CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
- CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
- SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
- break;
- case MESA_FORMAT_SARGB8:
-#ifdef MESA_BIG_ENDIAN
- endian = ENDIAN_8IN32;
-#endif
- format = COLOR_8_8_8_8;
- comp_swap = SWAP_ALT;
- SETbit(cb_color0_info, SOURCE_FORMAT_bit);
- SETfield(cb_color0_info, NUMBER_SRGB, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
- break;
- case MESA_FORMAT_SLA8:
-#ifdef MESA_BIG_ENDIAN
- endian = ENDIAN_8IN16;
-#endif
- format = COLOR_8_8;
- comp_swap = SWAP_ALT_REV;
- SETbit(cb_color0_info, SOURCE_FORMAT_bit);
- SETfield(cb_color0_info, NUMBER_SRGB, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
- break;
- case MESA_FORMAT_SL8:
- format = COLOR_8;
- comp_swap = SWAP_ALT_REV;
- SETbit(cb_color0_info, SOURCE_FORMAT_bit);
- SETfield(cb_color0_info, NUMBER_SRGB, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
- break;
- default:
- fprintf(stderr,"Invalid format for copy %s\n",_mesa_get_format_name(mesa_format));
- assert("Invalid format for US output\n");
- return;
- }
-
- /* must be 0 on r7xx */
- if (context->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV770)
- CLEARbit(cb_color0_info, BLEND_FLOAT32_bit);
-
- SETfield(cb_color0_info, endian, ENDIAN_shift, ENDIAN_mask);
- SETfield(cb_color0_info, format, CB_COLOR0_INFO__FORMAT_shift,
- CB_COLOR0_INFO__FORMAT_mask);
- SETfield(cb_color0_info, comp_swap, COMP_SWAP_shift, COMP_SWAP_mask);
-
- BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
- R600_OUT_BATCH_REGSEQ(CB_COLOR0_BASE + (4 * id), 1);
- R600_OUT_BATCH(cb_color0_base);
- R600_OUT_BATCH_RELOC(0,
- bo,
- 0,
- 0, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0);
- END_BATCH();
-
- if ((context->radeon.radeonScreen->chip_family > CHIP_FAMILY_R600) &&
- (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)) {
- BEGIN_BATCH_NO_AUTOSTATE(2);
- R600_OUT_BATCH(CP_PACKET3(R600_IT_SURFACE_BASE_UPDATE, 0));
- R600_OUT_BATCH((2 << id));
- END_BATCH();
- }
-
- /* Set CMASK & TILE buffer to the offset of color buffer as
- * we don't use those this shouldn't cause any issue and we
- * then have a valid cmd stream
- */
- BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
- R600_OUT_BATCH_REGSEQ(CB_COLOR0_TILE + (4 * id), 1);
- R600_OUT_BATCH(cb_color0_base);
- R600_OUT_BATCH_RELOC(0,
- bo,
- 0,
- 0, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0);
- END_BATCH();
- BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
- R600_OUT_BATCH_REGSEQ(CB_COLOR0_FRAG + (4 * id), 1);
- R600_OUT_BATCH(cb_color0_base);
- R600_OUT_BATCH_RELOC(0,
- bo,
- 0,
- 0, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0);
- END_BATCH();
-
- BEGIN_BATCH_NO_AUTOSTATE(9);
- R600_OUT_BATCH_REGVAL(CB_COLOR0_SIZE + (4 * id), cb_color0_size);
- R600_OUT_BATCH_REGVAL(CB_COLOR0_VIEW + (4 * id), cb_color0_view);
- R600_OUT_BATCH_REGVAL(CB_COLOR0_MASK + (4 * id), 0);
- END_BATCH();
-
- BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
- R600_OUT_BATCH_REGVAL(CB_COLOR0_INFO + (4 * id), cb_color0_info);
- R600_OUT_BATCH_RELOC(0,
- bo,
- 0,
- 0, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0);
- END_BATCH();
-
- COMMIT_BATCH();
-
-}
-
-static inline void load_shaders(struct gl_context * ctx)
-{
-
- radeonContextPtr radeonctx = RADEON_CONTEXT(ctx);
- context_t *context = R700_CONTEXT(ctx);
- int i, size;
- uint32_t *shader;
-
- if (context->blit_bo_loaded == 1)
- return;
-
- size = 4096;
- context->blit_bo = radeon_bo_open(radeonctx->radeonScreen->bom, 0,
- size, 256, RADEON_GEM_DOMAIN_GTT, 0);
- radeon_bo_map(context->blit_bo, 1);
- shader = context->blit_bo->ptr;
-
- for(i=0; i<sizeof(r6xx_vs)/4; i++) {
- shader[128+i] = CPU_TO_LE32(r6xx_vs[i]);
- }
- for(i=0; i<sizeof(r6xx_ps)/4; i++) {
- shader[256+i] = CPU_TO_LE32(r6xx_ps[i]);
- }
-
- radeon_bo_unmap(context->blit_bo);
- context->blit_bo_loaded = 1;
-
-}
-
-static inline void
-set_shaders(context_t *context)
-{
- struct radeon_bo * pbo = context->blit_bo;
- BATCH_LOCALS(&context->radeon);
-
- uint32_t sq_pgm_start_fs = (512 >> 8);
- uint32_t sq_pgm_resources_fs = 0;
- uint32_t sq_pgm_cf_offset_fs = 0;
-
- uint32_t sq_pgm_start_vs = (512 >> 8);
- uint32_t sq_pgm_resources_vs = (1 << NUM_GPRS_shift);
- uint32_t sq_pgm_cf_offset_vs = 0;
-
- uint32_t sq_pgm_start_ps = (1024 >> 8);
- uint32_t sq_pgm_resources_ps = (1 << NUM_GPRS_shift);
- uint32_t sq_pgm_cf_offset_ps = 0;
- uint32_t sq_pgm_exports_ps = (1 << 1);
-
- r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
-
- /* FS */
- BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
- R600_OUT_BATCH_REGSEQ(SQ_PGM_START_FS, 1);
- R600_OUT_BATCH(sq_pgm_start_fs);
- R600_OUT_BATCH_RELOC(sq_pgm_start_fs,
- pbo,
- sq_pgm_start_fs,
- RADEON_GEM_DOMAIN_GTT, 0, 0);
- END_BATCH();
-
- BEGIN_BATCH_NO_AUTOSTATE(6);
- R600_OUT_BATCH_REGVAL(SQ_PGM_RESOURCES_FS, sq_pgm_resources_fs);
- R600_OUT_BATCH_REGVAL(SQ_PGM_CF_OFFSET_FS, sq_pgm_cf_offset_fs);
- END_BATCH();
-
- /* VS */
- BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
- R600_OUT_BATCH_REGSEQ(SQ_PGM_START_VS, 1);
- R600_OUT_BATCH(sq_pgm_start_vs);
- R600_OUT_BATCH_RELOC(sq_pgm_start_vs,
- pbo,
- sq_pgm_start_vs,
- RADEON_GEM_DOMAIN_GTT, 0, 0);
- END_BATCH();
-
- BEGIN_BATCH_NO_AUTOSTATE(6);
- R600_OUT_BATCH_REGVAL(SQ_PGM_RESOURCES_VS, sq_pgm_resources_vs);
- R600_OUT_BATCH_REGVAL(SQ_PGM_CF_OFFSET_VS, sq_pgm_cf_offset_vs);
- END_BATCH();
-
- /* PS */
- BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
- R600_OUT_BATCH_REGSEQ(SQ_PGM_START_PS, 1);
- R600_OUT_BATCH(sq_pgm_start_ps);
- R600_OUT_BATCH_RELOC(sq_pgm_start_ps,
- pbo,
- sq_pgm_start_ps,
- RADEON_GEM_DOMAIN_GTT, 0, 0);
- END_BATCH();
-
- BEGIN_BATCH_NO_AUTOSTATE(9);
- R600_OUT_BATCH_REGVAL(SQ_PGM_RESOURCES_PS, sq_pgm_resources_ps);
- R600_OUT_BATCH_REGVAL(SQ_PGM_EXPORTS_PS, sq_pgm_exports_ps);
- R600_OUT_BATCH_REGVAL(SQ_PGM_CF_OFFSET_PS, sq_pgm_cf_offset_ps);
- END_BATCH();
-
- BEGIN_BATCH_NO_AUTOSTATE(18);
- R600_OUT_BATCH_REGVAL(SPI_VS_OUT_CONFIG, 0); //EXPORT_COUNT is - 1
- R600_OUT_BATCH_REGVAL(SPI_VS_OUT_ID_0, 0);
- R600_OUT_BATCH_REGVAL(SPI_PS_INPUT_CNTL_0, SEL_CENTROID_bit);
- R600_OUT_BATCH_REGVAL(SPI_PS_IN_CONTROL_0, (1 << NUM_INTERP_shift));
- R600_OUT_BATCH_REGVAL(SPI_PS_IN_CONTROL_1, 0);
- R600_OUT_BATCH_REGVAL(SPI_INTERP_CONTROL_0, 0);
- END_BATCH();
-
- COMMIT_BATCH();
-
-}
-
-static inline void
-set_vtx_resource(context_t *context)
-{
- struct radeon_bo *bo = context->blit_bo;
- uint32_t sq_vtx_constant_word2 = 0;
-
- BATCH_LOCALS(&context->radeon);
-
- BEGIN_BATCH_NO_AUTOSTATE(6);
- R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1));
- R600_OUT_BATCH(mmSQ_VTX_BASE_VTX_LOC - ASIC_CTL_CONST_BASE_INDEX);
- R600_OUT_BATCH(0);
-
- R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1));
- R600_OUT_BATCH(mmSQ_VTX_START_INST_LOC - ASIC_CTL_CONST_BASE_INDEX);
- R600_OUT_BATCH(0);
- END_BATCH();
- COMMIT_BATCH();
-
- if ((context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV610) ||
- (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV620) ||
- (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS780) ||
- (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS880) ||
- (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV710))
- r700SyncSurf(context, bo, RADEON_GEM_DOMAIN_GTT, 0, TC_ACTION_ENA_bit);
- else
- r700SyncSurf(context, bo, RADEON_GEM_DOMAIN_GTT, 0, VC_ACTION_ENA_bit);
-
- sq_vtx_constant_word2 = 0
-#ifdef MESA_BIG_ENDIAN
- | (SQ_ENDIAN_8IN32 << SQ_VTX_CONSTANT_WORD2_0__ENDIAN_SWAP_shift)
-#endif
- | (16 << SQ_VTX_CONSTANT_WORD2_0__STRIDE_shift);
-
- BEGIN_BATCH_NO_AUTOSTATE(9 + 2);
-
- R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 7));
- R600_OUT_BATCH(SQ_FETCH_RESOURCE_VS_OFFSET * FETCH_RESOURCE_STRIDE);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(48 - 1);
- R600_OUT_BATCH(sq_vtx_constant_word2);
- R600_OUT_BATCH(1 << MEM_REQUEST_SIZE_shift);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(SQ_TEX_VTX_VALID_BUFFER << SQ_TEX_RESOURCE_WORD6_0__TYPE_shift);
- R600_OUT_BATCH_RELOC(0,
- bo,
- 0,
- RADEON_GEM_DOMAIN_GTT, 0, 0);
- END_BATCH();
- COMMIT_BATCH();
-
-}
-
-static inline void
-set_tex_resource(context_t * context,
- gl_format mesa_format, struct radeon_bo *bo, int w, int h,
- int TexelPitch, intptr_t src_offset)
-{
- uint32_t sq_tex_resource0, sq_tex_resource1, sq_tex_resource2, sq_tex_resource4, sq_tex_resource6;
-
- sq_tex_resource0 = sq_tex_resource1 = sq_tex_resource2 = sq_tex_resource4 = sq_tex_resource6 = 0;
- BATCH_LOCALS(&context->radeon);
-
- SETfield(sq_tex_resource0, SQ_TEX_DIM_2D, DIM_shift, DIM_mask);
- SETfield(sq_tex_resource0, ARRAY_LINEAR_GENERAL,
- SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift,
- SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask);
-
- switch (mesa_format) {
- case MESA_FORMAT_RGBA8888:
- case MESA_FORMAT_SIGNED_RGBA8888:
- SETfield(sq_tex_resource1, FMT_8_8_8_8,
- SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
-
- SETfield(sq_tex_resource4, SQ_SEL_W,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(sq_tex_resource4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(sq_tex_resource4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- if (mesa_format == MESA_FORMAT_SIGNED_RGBA8888) {
- SETfield(sq_tex_resource4, SQ_FORMAT_COMP_SIGNED,
- FORMAT_COMP_X_shift, FORMAT_COMP_X_mask);
- SETfield(sq_tex_resource4, SQ_FORMAT_COMP_SIGNED,
- FORMAT_COMP_Y_shift, FORMAT_COMP_Y_mask);
- SETfield(sq_tex_resource4, SQ_FORMAT_COMP_SIGNED,
- FORMAT_COMP_Z_shift, FORMAT_COMP_Z_mask);
- SETfield(sq_tex_resource4, SQ_FORMAT_COMP_SIGNED,
- FORMAT_COMP_W_shift, FORMAT_COMP_W_mask);
- }
- break;
- case MESA_FORMAT_RGBA8888_REV:
- case MESA_FORMAT_SIGNED_RGBA8888_REV:
- SETfield(sq_tex_resource1, FMT_8_8_8_8,
- SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
-
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(sq_tex_resource4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(sq_tex_resource4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(sq_tex_resource4, SQ_SEL_W,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- if (mesa_format == MESA_FORMAT_SIGNED_RGBA8888_REV) {
- SETfield(sq_tex_resource4, SQ_FORMAT_COMP_SIGNED,
- FORMAT_COMP_X_shift, FORMAT_COMP_X_mask);
- SETfield(sq_tex_resource4, SQ_FORMAT_COMP_SIGNED,
- FORMAT_COMP_Y_shift, FORMAT_COMP_Y_mask);
- SETfield(sq_tex_resource4, SQ_FORMAT_COMP_SIGNED,
- FORMAT_COMP_Z_shift, FORMAT_COMP_Z_mask);
- SETfield(sq_tex_resource4, SQ_FORMAT_COMP_SIGNED,
- FORMAT_COMP_W_shift, FORMAT_COMP_W_mask);
- }
- break;
- case MESA_FORMAT_ARGB8888:
- SETfield(sq_tex_resource1, FMT_8_8_8_8,
- SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
-
- SETfield(sq_tex_resource4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(sq_tex_resource4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(sq_tex_resource4, SQ_SEL_W,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_XRGB8888:
- SETfield(sq_tex_resource1, FMT_8_8_8_8,
- SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
-
- SETfield(sq_tex_resource4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(sq_tex_resource4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(sq_tex_resource4, SQ_SEL_1,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_ARGB8888_REV:
- SETfield(sq_tex_resource1, FMT_8_8_8_8,
- SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
-
- SETfield(sq_tex_resource4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(sq_tex_resource4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(sq_tex_resource4, SQ_SEL_W,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_XRGB8888_REV:
- SETfield(sq_tex_resource1, FMT_8_8_8_8,
- SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
-
- SETfield(sq_tex_resource4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(sq_tex_resource4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(sq_tex_resource4, SQ_SEL_1,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_RGB565:
- SETfield(sq_tex_resource1, FMT_5_6_5,
- SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
-
- SETfield(sq_tex_resource4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(sq_tex_resource4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(sq_tex_resource4, SQ_SEL_1,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_RGB565_REV:
- SETfield(sq_tex_resource1, FMT_5_6_5,
- SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
-
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(sq_tex_resource4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(sq_tex_resource4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(sq_tex_resource4, SQ_SEL_1,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_ARGB4444:
- SETfield(sq_tex_resource1, FMT_4_4_4_4,
- SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
-
- SETfield(sq_tex_resource4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(sq_tex_resource4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(sq_tex_resource4, SQ_SEL_W,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_ARGB4444_REV:
- SETfield(sq_tex_resource1, FMT_4_4_4_4,
- SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
-
- SETfield(sq_tex_resource4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(sq_tex_resource4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(sq_tex_resource4, SQ_SEL_W,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_ARGB1555:
- SETfield(sq_tex_resource1, FMT_1_5_5_5,
- SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
-
- SETfield(sq_tex_resource4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(sq_tex_resource4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(sq_tex_resource4, SQ_SEL_W,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_ARGB1555_REV:
- SETfield(sq_tex_resource1, FMT_1_5_5_5,
- SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
-
- SETfield(sq_tex_resource4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(sq_tex_resource4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(sq_tex_resource4, SQ_SEL_W,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_AL88:
- case MESA_FORMAT_AL88_REV: /* TODO : Check this. */
- SETfield(sq_tex_resource1, FMT_8_8,
- SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
-
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(sq_tex_resource4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_RGB332:
- SETfield(sq_tex_resource1, FMT_3_3_2,
- SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
-
- SETfield(sq_tex_resource4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(sq_tex_resource4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(sq_tex_resource4, SQ_SEL_1,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_A8: /* ZERO, ZERO, ZERO, X */
- SETfield(sq_tex_resource1, FMT_8,
- SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
-
- SETfield(sq_tex_resource4, SQ_SEL_0,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(sq_tex_resource4, SQ_SEL_0,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(sq_tex_resource4, SQ_SEL_0,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_L8: /* X, X, X, ONE */
- SETfield(sq_tex_resource1, FMT_8,
- SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
-
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(sq_tex_resource4, SQ_SEL_1,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_I8: /* X, X, X, X */
- SETfield(sq_tex_resource1, FMT_8,
- SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
-
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_RGBA_FLOAT32:
- SETfield(sq_tex_resource1, FMT_32_32_32_32_FLOAT,
- SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
-
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(sq_tex_resource4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(sq_tex_resource4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(sq_tex_resource4, SQ_SEL_W,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_RGBA_FLOAT16:
- SETfield(sq_tex_resource1, FMT_16_16_16_16_FLOAT,
- SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
-
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(sq_tex_resource4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(sq_tex_resource4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(sq_tex_resource4, SQ_SEL_W,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_ALPHA_FLOAT32: /* ZERO, ZERO, ZERO, X */
- SETfield(sq_tex_resource1, FMT_32_FLOAT,
- SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
-
- SETfield(sq_tex_resource4, SQ_SEL_0,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(sq_tex_resource4, SQ_SEL_0,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(sq_tex_resource4, SQ_SEL_0,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_ALPHA_FLOAT16: /* ZERO, ZERO, ZERO, X */
- SETfield(sq_tex_resource1, FMT_16_FLOAT,
- SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
-
- SETfield(sq_tex_resource4, SQ_SEL_0,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(sq_tex_resource4, SQ_SEL_0,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(sq_tex_resource4, SQ_SEL_0,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_LUMINANCE_FLOAT32: /* X, X, X, ONE */
- SETfield(sq_tex_resource1, FMT_32_FLOAT,
- SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
-
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(sq_tex_resource4, SQ_SEL_1,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_LUMINANCE_FLOAT16: /* X, X, X, ONE */
- SETfield(sq_tex_resource1, FMT_16_FLOAT,
- SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
-
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(sq_tex_resource4, SQ_SEL_1,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32:
- SETfield(sq_tex_resource1, FMT_32_32_FLOAT,
- SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
-
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(sq_tex_resource4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16:
- SETfield(sq_tex_resource1, FMT_16_16_FLOAT,
- SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
-
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(sq_tex_resource4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_INTENSITY_FLOAT32: /* X, X, X, X */
- SETfield(sq_tex_resource1, FMT_32_FLOAT,
- SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
-
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_INTENSITY_FLOAT16: /* X, X, X, X */
- SETfield(sq_tex_resource1, FMT_16_FLOAT,
- SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
-
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_Z16:
- SETbit(sq_tex_resource0, TILE_TYPE_bit);
- SETfield(sq_tex_resource0, ARRAY_1D_TILED_THIN1,
- SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift,
- SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask);
- SETfield(sq_tex_resource1, FMT_16,
- SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_X8_Z24:
- SETbit(sq_tex_resource0, TILE_TYPE_bit);
- SETfield(sq_tex_resource0, ARRAY_1D_TILED_THIN1,
- SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift,
- SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask);
- SETfield(sq_tex_resource1, FMT_8_24,
- SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(sq_tex_resource4, SQ_SEL_1,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(sq_tex_resource4, SQ_SEL_0,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(sq_tex_resource4, SQ_SEL_1,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_S8_Z24:
- SETbit(sq_tex_resource0, TILE_TYPE_bit);
- SETfield(sq_tex_resource0, ARRAY_1D_TILED_THIN1,
- SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift,
- SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask);
- SETfield(sq_tex_resource1, FMT_8_24,
- SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(sq_tex_resource4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(sq_tex_resource4, SQ_SEL_0,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(sq_tex_resource4, SQ_SEL_1,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_Z24_S8:
- SETbit(sq_tex_resource0, TILE_TYPE_bit);
- SETfield(sq_tex_resource0, ARRAY_1D_TILED_THIN1,
- SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift,
- SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask);
- SETfield(sq_tex_resource1, FMT_24_8,
- SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(sq_tex_resource4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(sq_tex_resource4, SQ_SEL_0,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(sq_tex_resource4, SQ_SEL_1,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_Z32:
- SETbit(sq_tex_resource0, TILE_TYPE_bit);
- SETfield(sq_tex_resource0, ARRAY_1D_TILED_THIN1,
- SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift,
- SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask);
- SETfield(sq_tex_resource1, FMT_32,
- SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_S8:
- SETbit(sq_tex_resource0, TILE_TYPE_bit);
- SETfield(sq_tex_resource0, ARRAY_1D_TILED_THIN1,
- SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift,
- SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask);
- SETfield(sq_tex_resource1, FMT_8,
- SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_SARGB8:
- SETfield(sq_tex_resource1, FMT_8_8_8_8,
- SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
-
- SETfield(sq_tex_resource4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(sq_tex_resource4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(sq_tex_resource4, SQ_SEL_W,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- SETbit(sq_tex_resource4, SQ_TEX_RESOURCE_WORD4_0__FORCE_DEGAMMA_bit);
- break;
- case MESA_FORMAT_SLA8:
- SETfield(sq_tex_resource1, FMT_8_8,
- SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
-
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(sq_tex_resource4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- SETbit(sq_tex_resource4, SQ_TEX_RESOURCE_WORD4_0__FORCE_DEGAMMA_bit);
- break;
- case MESA_FORMAT_SL8: /* X, X, X, ONE */
- SETfield(sq_tex_resource1, FMT_8,
- SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
-
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(sq_tex_resource4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(sq_tex_resource4, SQ_SEL_1,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- SETbit(sq_tex_resource4, SQ_TEX_RESOURCE_WORD4_0__FORCE_DEGAMMA_bit);
- break;
- default:
- fprintf(stderr,"Invalid format for copy %s\n",_mesa_get_format_name(mesa_format));
- assert("Invalid format for US output\n");
- return;
- };
-
- SETfield(sq_tex_resource0, (TexelPitch/8)-1, PITCH_shift, PITCH_mask);
- SETfield(sq_tex_resource0, w - 1, TEX_WIDTH_shift, TEX_WIDTH_mask);
- SETfield(sq_tex_resource1, h - 1, TEX_HEIGHT_shift, TEX_HEIGHT_mask);
-
- sq_tex_resource2 = src_offset / 256;
-
- SETfield(sq_tex_resource6, SQ_TEX_VTX_VALID_TEXTURE,
- SQ_TEX_RESOURCE_WORD6_0__TYPE_shift,
- SQ_TEX_RESOURCE_WORD6_0__TYPE_mask);
-
- r700SyncSurf(context, bo,
- RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM,
- 0, TC_ACTION_ENA_bit);
-
- BEGIN_BATCH_NO_AUTOSTATE(9 + 4);
- R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 7));
- R600_OUT_BATCH(0 * 7);
-
- R600_OUT_BATCH(sq_tex_resource0);
- R600_OUT_BATCH(sq_tex_resource1);
- R600_OUT_BATCH(sq_tex_resource2);
- R600_OUT_BATCH(0); //SQ_TEX_RESOURCE3
- R600_OUT_BATCH(sq_tex_resource4);
- R600_OUT_BATCH(0); //SQ_TEX_RESOURCE5
- R600_OUT_BATCH(sq_tex_resource6);
- R600_OUT_BATCH_RELOC(0,
- bo,
- 0,
- RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
- R600_OUT_BATCH_RELOC(0,
- bo,
- 0,
- RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
- END_BATCH();
- COMMIT_BATCH();
-}
-
-static inline void
-set_tex_sampler(context_t * context)
-{
- uint32_t sq_tex_sampler_word0 = 0, sq_tex_sampler_word1 = 0, sq_tex_sampler_word2 = 0;
- int i = 0;
-
- SETbit(sq_tex_sampler_word2, SQ_TEX_SAMPLER_WORD2_0__TYPE_bit);
-
- BATCH_LOCALS(&context->radeon);
-
- BEGIN_BATCH_NO_AUTOSTATE(5);
- R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_SAMPLER, 3));
- R600_OUT_BATCH(i * 3);
- R600_OUT_BATCH(sq_tex_sampler_word0);
- R600_OUT_BATCH(sq_tex_sampler_word1);
- R600_OUT_BATCH(sq_tex_sampler_word2);
- END_BATCH();
-
-}
-
-static inline void
-set_scissors(context_t *context, int x1, int y1, int x2, int y2)
-{
- BATCH_LOCALS(&context->radeon);
-
- BEGIN_BATCH_NO_AUTOSTATE(17);
- R600_OUT_BATCH_REGSEQ(PA_SC_SCREEN_SCISSOR_TL, 2);
- R600_OUT_BATCH((x1 << 0) | (y1 << 16));
- R600_OUT_BATCH((x2 << 0) | (y2 << 16));
-
- R600_OUT_BATCH_REGSEQ(PA_SC_WINDOW_OFFSET, 3);
- R600_OUT_BATCH(0); //PA_SC_WINDOW_OFFSET
- R600_OUT_BATCH((x1 << 0) | (y1 << 16) | (WINDOW_OFFSET_DISABLE_bit)); //PA_SC_WINDOW_SCISSOR_TL
- R600_OUT_BATCH((x2 << 0) | (y2 << 16));
-
- R600_OUT_BATCH_REGSEQ(PA_SC_GENERIC_SCISSOR_TL, 2);
- R600_OUT_BATCH((x1 << 0) | (y1 << 16) | (WINDOW_OFFSET_DISABLE_bit));
- R600_OUT_BATCH((x2 << 0) | (y2 << 16));
-
- /* XXX 16 of these PA_SC_VPORT_SCISSOR_0_TL_num ... */
- R600_OUT_BATCH_REGSEQ(PA_SC_VPORT_SCISSOR_0_TL, 2 );
- R600_OUT_BATCH((x1 << 0) | (y1 << 16) | (WINDOW_OFFSET_DISABLE_bit));
- R600_OUT_BATCH((x2 << 0) | (y2 << 16));
- END_BATCH();
-
- COMMIT_BATCH();
-
-}
-
-static inline void
-set_vb_data(context_t * context, int src_x, int src_y, int dst_x, int dst_y,
- int w, int h, int src_h, unsigned flip_y)
-{
- float *vb;
- radeon_bo_map(context->blit_bo, 1);
- vb = context->blit_bo->ptr;
-
- vb[0] = (float)(dst_x);
- vb[1] = (float)(dst_y);
- vb[2] = (float)(src_x);
- vb[3] = (flip_y) ? (float)(src_h - src_y) : (float)src_y;
-
- vb[4] = (float)(dst_x);
- vb[5] = (float)(dst_y + h);
- vb[6] = (float)(src_x);
- vb[7] = (flip_y) ? (float)(src_h - (src_y + h)) : (float)(src_y + h);
-
- vb[8] = (float)(dst_x + w);
- vb[9] = (float)(dst_y + h);
- vb[10] = (float)(src_x + w);
- vb[11] = (flip_y) ? (float)(src_h - (src_y + h)) : (float)(src_y + h);
-
- radeon_bo_unmap(context->blit_bo);
-
-}
-
-static inline void
-draw_auto(context_t *context)
-{
- BATCH_LOCALS(&context->radeon);
- uint32_t vgt_primitive_type = 0, vgt_index_type = 0, vgt_draw_initiator = 0, vgt_num_indices;
-
- SETfield(vgt_primitive_type, DI_PT_RECTLIST,
- VGT_PRIMITIVE_TYPE__PRIM_TYPE_shift,
- VGT_PRIMITIVE_TYPE__PRIM_TYPE_mask);
- SETfield(vgt_index_type, DI_INDEX_SIZE_16_BIT, INDEX_TYPE_shift,
- INDEX_TYPE_mask);
- SETfield(vgt_draw_initiator, DI_MAJOR_MODE_0, MAJOR_MODE_shift,
- MAJOR_MODE_mask);
- SETfield(vgt_draw_initiator, DI_SRC_SEL_AUTO_INDEX, SOURCE_SELECT_shift,
- SOURCE_SELECT_mask);
-
- vgt_num_indices = 3;
-
- BEGIN_BATCH_NO_AUTOSTATE(10);
- // prim
- R600_OUT_BATCH_REGSEQ(VGT_PRIMITIVE_TYPE, 1);
- R600_OUT_BATCH(vgt_primitive_type);
- // index type
- R600_OUT_BATCH(CP_PACKET3(R600_IT_INDEX_TYPE, 0));
- R600_OUT_BATCH(vgt_index_type);
- // num instances
- R600_OUT_BATCH(CP_PACKET3(R600_IT_NUM_INSTANCES, 0));
- R600_OUT_BATCH(1);
- //
- R600_OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX_AUTO, 1));
- R600_OUT_BATCH(vgt_num_indices);
- R600_OUT_BATCH(vgt_draw_initiator);
-
- END_BATCH();
- COMMIT_BATCH();
-}
-
-static inline void
-set_default_state(context_t *context)
-{
- int ps_prio = 0;
- int vs_prio = 1;
- int gs_prio = 2;
- int es_prio = 3;
- int num_ps_gprs;
- int num_vs_gprs;
- int num_gs_gprs;
- int num_es_gprs;
- int num_temp_gprs;
- int num_ps_threads;
- int num_vs_threads;
- int num_gs_threads;
- int num_es_threads;
- int num_ps_stack_entries;
- int num_vs_stack_entries;
- int num_gs_stack_entries;
- int num_es_stack_entries;
- uint32_t sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2;
- uint32_t sq_thread_resource_mgmt, sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2;
- uint32_t ta_cntl_aux, db_watermarks, sq_dyn_gpr_cntl_ps_flush_req, db_debug;
- BATCH_LOCALS(&context->radeon);
-
- switch (context->radeon.radeonScreen->chip_family) {
- case CHIP_FAMILY_R600:
- num_ps_gprs = 192;
- num_vs_gprs = 56;
- num_temp_gprs = 4;
- num_gs_gprs = 0;
- num_es_gprs = 0;
- num_ps_threads = 136;
- num_vs_threads = 48;
- num_gs_threads = 4;
- num_es_threads = 4;
- num_ps_stack_entries = 128;
- num_vs_stack_entries = 128;
- num_gs_stack_entries = 0;
- num_es_stack_entries = 0;
- break;
- case CHIP_FAMILY_RV630:
- case CHIP_FAMILY_RV635:
- num_ps_gprs = 84;
- num_vs_gprs = 36;
- num_temp_gprs = 4;
- num_gs_gprs = 0;
- num_es_gprs = 0;
- num_ps_threads = 144;
- num_vs_threads = 40;
- num_gs_threads = 4;
- num_es_threads = 4;
- num_ps_stack_entries = 40;
- num_vs_stack_entries = 40;
- num_gs_stack_entries = 32;
- num_es_stack_entries = 16;
- break;
- case CHIP_FAMILY_RV610:
- case CHIP_FAMILY_RV620:
- case CHIP_FAMILY_RS780:
- case CHIP_FAMILY_RS880:
- default:
- num_ps_gprs = 84;
- num_vs_gprs = 36;
- num_temp_gprs = 4;
- num_gs_gprs = 0;
- num_es_gprs = 0;
- num_ps_threads = 136;
- num_vs_threads = 48;
- num_gs_threads = 4;
- num_es_threads = 4;
- num_ps_stack_entries = 40;
- num_vs_stack_entries = 40;
- num_gs_stack_entries = 32;
- num_es_stack_entries = 16;
- break;
- case CHIP_FAMILY_RV670:
- num_ps_gprs = 144;
- num_vs_gprs = 40;
- num_temp_gprs = 4;
- num_gs_gprs = 0;
- num_es_gprs = 0;
- num_ps_threads = 136;
- num_vs_threads = 48;
- num_gs_threads = 4;
- num_es_threads = 4;
- num_ps_stack_entries = 40;
- num_vs_stack_entries = 40;
- num_gs_stack_entries = 32;
- num_es_stack_entries = 16;
- break;
- case CHIP_FAMILY_RV770:
- num_ps_gprs = 192;
- num_vs_gprs = 56;
- num_temp_gprs = 4;
- num_gs_gprs = 0;
- num_es_gprs = 0;
- num_ps_threads = 188;
- num_vs_threads = 60;
- num_gs_threads = 0;
- num_es_threads = 0;
- num_ps_stack_entries = 256;
- num_vs_stack_entries = 256;
- num_gs_stack_entries = 0;
- num_es_stack_entries = 0;
- break;
- case CHIP_FAMILY_RV730:
- case CHIP_FAMILY_RV740:
- num_ps_gprs = 84;
- num_vs_gprs = 36;
- num_temp_gprs = 4;
- num_gs_gprs = 0;
- num_es_gprs = 0;
- num_ps_threads = 188;
- num_vs_threads = 60;
- num_gs_threads = 0;
- num_es_threads = 0;
- num_ps_stack_entries = 128;
- num_vs_stack_entries = 128;
- num_gs_stack_entries = 0;
- num_es_stack_entries = 0;
- break;
- case CHIP_FAMILY_RV710:
- num_ps_gprs = 192;
- num_vs_gprs = 56;
- num_temp_gprs = 4;
- num_gs_gprs = 0;
- num_es_gprs = 0;
- num_ps_threads = 144;
- num_vs_threads = 48;
- num_gs_threads = 0;
- num_es_threads = 0;
- num_ps_stack_entries = 128;
- num_vs_stack_entries = 128;
- num_gs_stack_entries = 0;
- num_es_stack_entries = 0;
- break;
- }
-
- sq_config = 0;
- if ((context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV610) ||
- (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV620) ||
- (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS780) ||
- (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS880) ||
- (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV710))
- CLEARbit(sq_config, VC_ENABLE_bit);
- else
- SETbit(sq_config, VC_ENABLE_bit);
- SETbit(sq_config, DX9_CONSTS_bit);
- SETbit(sq_config, ALU_INST_PREFER_VECTOR_bit);
- SETfield(sq_config, ps_prio, PS_PRIO_shift, PS_PRIO_mask);
- SETfield(sq_config, vs_prio, VS_PRIO_shift, VS_PRIO_mask);
- SETfield(sq_config, gs_prio, GS_PRIO_shift, GS_PRIO_mask);
- SETfield(sq_config, es_prio, ES_PRIO_shift, ES_PRIO_mask);
-
- sq_gpr_resource_mgmt_1 = 0;
- SETfield(sq_gpr_resource_mgmt_1, num_ps_gprs, NUM_PS_GPRS_shift, NUM_PS_GPRS_mask);
- SETfield(sq_gpr_resource_mgmt_1, num_vs_gprs, NUM_VS_GPRS_shift, NUM_VS_GPRS_mask);
- SETfield(sq_gpr_resource_mgmt_1, num_temp_gprs,
- NUM_CLAUSE_TEMP_GPRS_shift, NUM_CLAUSE_TEMP_GPRS_mask);
-
- sq_gpr_resource_mgmt_2 = 0;
- SETfield(sq_gpr_resource_mgmt_2, num_gs_gprs, NUM_GS_GPRS_shift, NUM_GS_GPRS_mask);
- SETfield(sq_gpr_resource_mgmt_2, num_es_gprs, NUM_ES_GPRS_shift, NUM_ES_GPRS_mask);
-
- sq_thread_resource_mgmt = 0;
- SETfield(sq_thread_resource_mgmt, num_ps_threads,
- NUM_PS_THREADS_shift, NUM_PS_THREADS_mask);
- SETfield(sq_thread_resource_mgmt, num_vs_threads,
- NUM_VS_THREADS_shift, NUM_VS_THREADS_mask);
- SETfield(sq_thread_resource_mgmt, num_gs_threads,
- NUM_GS_THREADS_shift, NUM_GS_THREADS_mask);
- SETfield(sq_thread_resource_mgmt, num_es_threads,
- NUM_ES_THREADS_shift, NUM_ES_THREADS_mask);
-
- sq_stack_resource_mgmt_1 = 0;
- SETfield(sq_stack_resource_mgmt_1, num_ps_stack_entries,
- NUM_PS_STACK_ENTRIES_shift, NUM_PS_STACK_ENTRIES_mask);
- SETfield(sq_stack_resource_mgmt_1, num_vs_stack_entries,
- NUM_VS_STACK_ENTRIES_shift, NUM_VS_STACK_ENTRIES_mask);
-
- sq_stack_resource_mgmt_2 = 0;
- SETfield(sq_stack_resource_mgmt_2, num_gs_stack_entries,
- NUM_GS_STACK_ENTRIES_shift, NUM_GS_STACK_ENTRIES_mask);
- SETfield(sq_stack_resource_mgmt_2, num_es_stack_entries,
- NUM_ES_STACK_ENTRIES_shift, NUM_ES_STACK_ENTRIES_mask);
-
- ta_cntl_aux = 0;
- SETfield(ta_cntl_aux, 28, TD_FIFO_CREDIT_shift, TD_FIFO_CREDIT_mask);
- db_watermarks = 0;
- SETfield(db_watermarks, 4, DEPTH_FREE_shift, DEPTH_FREE_mask);
- SETfield(db_watermarks, 16, DEPTH_FLUSH_shift, DEPTH_FLUSH_mask);
- SETfield(db_watermarks, 0, FORCE_SUMMARIZE_shift, FORCE_SUMMARIZE_mask);
- SETfield(db_watermarks, 4, DEPTH_PENDING_FREE_shift, DEPTH_PENDING_FREE_mask);
- sq_dyn_gpr_cntl_ps_flush_req = 0;
- db_debug = 0;
- if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) {
- SETfield(ta_cntl_aux, 3, GRADIENT_CREDIT_shift, GRADIENT_CREDIT_mask);
- db_debug = 0x82000000;
- SETfield(db_watermarks, 16, DEPTH_CACHELINE_FREE_shift, DEPTH_CACHELINE_FREE_mask);
- } else {
- SETfield(ta_cntl_aux, 2, GRADIENT_CREDIT_shift, GRADIENT_CREDIT_mask);
- SETfield(db_watermarks, 4, DEPTH_CACHELINE_FREE_shift, DEPTH_CACHELINE_FREE_mask);
- SETbit(sq_dyn_gpr_cntl_ps_flush_req, VS_PC_LIMIT_ENABLE_bit);
- }
-
- BEGIN_BATCH_NO_AUTOSTATE(120);
- R600_OUT_BATCH_REGSEQ(SQ_CONFIG, 6);
- R600_OUT_BATCH(sq_config);
- R600_OUT_BATCH(sq_gpr_resource_mgmt_1);
- R600_OUT_BATCH(sq_gpr_resource_mgmt_2);
- R600_OUT_BATCH(sq_thread_resource_mgmt);
- R600_OUT_BATCH(sq_stack_resource_mgmt_1);
- R600_OUT_BATCH(sq_stack_resource_mgmt_2);
-
- R600_OUT_BATCH_REGVAL(TA_CNTL_AUX, ta_cntl_aux);
- R600_OUT_BATCH_REGVAL(VC_ENHANCE, 0);
- R600_OUT_BATCH_REGVAL(R7xx_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, sq_dyn_gpr_cntl_ps_flush_req);
- R600_OUT_BATCH_REGVAL(DB_DEBUG, db_debug);
- R600_OUT_BATCH_REGVAL(DB_WATERMARKS, db_watermarks);
-
- R600_OUT_BATCH_REGSEQ(SQ_ESGS_RING_ITEMSIZE, 9);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
-
- R600_OUT_BATCH_REGVAL(CB_CLRCMP_CONTROL,
- (CLRCMP_SEL_SRC << CLRCMP_FCN_SEL_shift));
- R600_OUT_BATCH_REGVAL(SQ_VTX_BASE_VTX_LOC, 0);
- R600_OUT_BATCH_REGVAL(SQ_VTX_START_INST_LOC, 0);
- R600_OUT_BATCH_REGVAL(DB_DEPTH_CONTROL, 0);
- R600_OUT_BATCH_REGVAL(CB_SHADER_MASK, (OUTPUT0_ENABLE_mask));
- R600_OUT_BATCH_REGVAL(CB_TARGET_MASK, (TARGET0_ENABLE_mask));
- R600_OUT_BATCH_REGVAL(R7xx_CB_SHADER_CONTROL, (RT0_ENABLE_bit));
- R600_OUT_BATCH_REGVAL(CB_COLOR_CONTROL, (0xcc << ROP3_shift));
-
- R600_OUT_BATCH_REGVAL(PA_CL_VTE_CNTL, VTX_XY_FMT_bit);
- R600_OUT_BATCH_REGVAL(PA_CL_VS_OUT_CNTL, 0);
- R600_OUT_BATCH_REGVAL(PA_CL_CLIP_CNTL, CLIP_DISABLE_bit);
- R600_OUT_BATCH_REGVAL(PA_SU_SC_MODE_CNTL, (FACE_bit) |
- (POLYMODE_PTYPE__TRIANGLES << POLYMODE_FRONT_PTYPE_shift) |
- (POLYMODE_PTYPE__TRIANGLES << POLYMODE_BACK_PTYPE_shift));
- R600_OUT_BATCH_REGVAL(PA_SU_VTX_CNTL, (PIX_CENTER_bit) |
- (X_ROUND_TO_EVEN << PA_SU_VTX_CNTL__ROUND_MODE_shift) |
- (X_1_256TH << QUANT_MODE_shift));
- R600_OUT_BATCH_REGVAL(PA_SC_AA_CONFIG, 0);
-
- R600_OUT_BATCH_REGSEQ(VGT_MAX_VTX_INDX, 4);
- R600_OUT_BATCH(0xffffff);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
-
- R600_OUT_BATCH_REGSEQ(VGT_OUTPUT_PATH_CNTL, 13);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
-
- R600_OUT_BATCH_REGVAL(VGT_PRIMITIVEID_EN, 0);
- R600_OUT_BATCH_REGVAL(VGT_MULTI_PRIM_IB_RESET_EN, 0);
- R600_OUT_BATCH_REGVAL(VGT_INSTANCE_STEP_RATE_0, 0);
- R600_OUT_BATCH_REGVAL(VGT_INSTANCE_STEP_RATE_1, 0);
-
- R600_OUT_BATCH_REGSEQ(VGT_STRMOUT_EN, 3);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
-
- R600_OUT_BATCH_REGVAL(VGT_STRMOUT_BUFFER_EN, 0);
- R600_OUT_BATCH_REGVAL(SX_ALPHA_TEST_CONTROL, 0);
-
- END_BATCH();
- COMMIT_BATCH();
-}
-
-static GLboolean validate_buffers(context_t *rmesa,
- struct radeon_bo *src_bo,
- struct radeon_bo *dst_bo)
-{
- int ret;
-
- radeon_cs_space_reset_bos(rmesa->radeon.cmdbuf.cs);
-
- ret = radeon_cs_space_check_with_bo(rmesa->radeon.cmdbuf.cs,
- src_bo, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0);
- if (ret)
- return GL_FALSE;
-
- ret = radeon_cs_space_check_with_bo(rmesa->radeon.cmdbuf.cs,
- dst_bo, 0, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT);
- if (ret)
- return GL_FALSE;
-
- ret = radeon_cs_space_check_with_bo(rmesa->radeon.cmdbuf.cs,
- rmesa->blit_bo,
- RADEON_GEM_DOMAIN_GTT, 0);
- if (ret)
- return GL_FALSE;
-
- return GL_TRUE;
-}
-
-unsigned r600_blit(struct gl_context *ctx,
- struct radeon_bo *src_bo,
- intptr_t src_offset,
- gl_format src_mesaformat,
- unsigned src_pitch,
- unsigned src_width,
- unsigned src_height,
- unsigned src_x,
- unsigned src_y,
- struct radeon_bo *dst_bo,
- intptr_t dst_offset,
- gl_format dst_mesaformat,
- unsigned dst_pitch,
- unsigned dst_width,
- unsigned dst_height,
- unsigned dst_x,
- unsigned dst_y,
- unsigned w,
- unsigned h,
- unsigned flip_y)
-{
- context_t *context = R700_CONTEXT(ctx);
- int id = 0;
-
- if (!r600_check_blit(dst_mesaformat))
- return GL_FALSE;
-
- if (src_bo == dst_bo) {
- return GL_FALSE;
- }
-
- if (src_offset % 256 || dst_offset % 256) {
- return GL_FALSE;
- }
-
- if (0) {
- fprintf(stderr, "src: width %d, height %d, pitch %d vs %d, format %s\n",
- src_width, src_height, src_pitch,
- _mesa_format_row_stride(src_mesaformat, src_width),
- _mesa_get_format_name(src_mesaformat));
- fprintf(stderr, "dst: width %d, height %d, pitch %d, format %s\n",
- dst_width, dst_height,
- _mesa_format_row_stride(dst_mesaformat, dst_width),
- _mesa_get_format_name(dst_mesaformat));
- }
-
- /* Flush is needed to make sure that source buffer has correct data */
- radeonFlush(ctx);
-
- rcommonEnsureCmdBufSpace(&context->radeon, 311, __FUNCTION__);
-
- /* load shaders */
- load_shaders(context->radeon.glCtx);
-
- if (!validate_buffers(context, src_bo, dst_bo))
- return GL_FALSE;
-
- /* set clear state */
- /* 120 */
- set_default_state(context);
-
- /* shaders */
- /* 72 */
- set_shaders(context);
-
- /* src */
- /* 20 */
- set_tex_resource(context, src_mesaformat, src_bo,
- src_width, src_height, src_pitch, src_offset);
-
- /* 5 */
- set_tex_sampler(context);
-
- /* dst */
- /* 31 */
- set_render_target(context, dst_bo, dst_mesaformat,
- dst_pitch, dst_width, dst_height, dst_offset);
- /* scissors */
- /* 17 */
- set_scissors(context, dst_x, dst_y, dst_x + dst_width, dst_y + dst_height);
-
- set_vb_data(context, src_x, src_y, dst_x, dst_y, w, h, src_height, flip_y);
- /* Vertex buffer setup */
- /* 24 */
- set_vtx_resource(context);
-
- /* draw */
- /* 10 */
- draw_auto(context);
-
- /* 7 */
- r700SyncSurf(context, dst_bo, 0,
- RADEON_GEM_DOMAIN_VRAM|RADEON_GEM_DOMAIN_GTT,
- CB_ACTION_ENA_bit | (1 << (id + 6)));
-
- /* 5 */
- /* XXX drm should handle this in fence submit */
- r700WaitForIdleClean(context);
-
- radeonFlush(ctx);
-
- return GL_TRUE;
-}
+++ /dev/null
-/*
- * Copyright (C) 2009 Advanced Micro Devices, Inc.
- *
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial
- * portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
- * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
- * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
- * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-
-#ifndef R600_BLIT_H
-#define R600_BLIT_H
-
-unsigned r600_check_blit(gl_format mesa_format);
-
-unsigned r600_blit(struct gl_context *ctx,
- struct radeon_bo *src_bo,
- intptr_t src_offset,
- gl_format src_mesaformat,
- unsigned src_pitch,
- unsigned src_width,
- unsigned src_height,
- unsigned src_x_offset,
- unsigned src_y_offset,
- struct radeon_bo *dst_bo,
- intptr_t dst_offset,
- gl_format dst_mesaformat,
- unsigned dst_pitch,
- unsigned dst_width,
- unsigned dst_height,
- unsigned dst_x_offset,
- unsigned dst_y_offset,
- unsigned w,
- unsigned h,
- unsigned flip_y);
-
-#endif // R600_BLIT_H
+++ /dev/null
-const uint32_t r6xx_vs[] =
-{
- 0x00000004, // CF_DWORD0(ADDR(4))
- 0x81000000, // SQ_CF_INST_VTX COUNT(1)
- 0x0000203c, // CF_EXP_IMP CF_POS0 SQ_EXPORT_POS RW_GPR(0) ELEM_SIZE(0)
- 0x94000b08, // SQ_CF_INST_EXPORT_DONE SWZ XY01 BARRIER(1)
- 0x00004000, // CF_EXP_IMP 0 SQ_EXPORT_PARAM RW_GPR(0) ELEM_SIZE(0)
- 0x14200b1a, // SQ_CF_INST_EXPORT_DONE SWZ ZW01 EOP(1) BARRIER(0)
- 0x00000000,
- 0x00000000,
- 0x3c000000, // SQ_VTX_INST_FETCH BUFFER_ID(0) MEGA_FETCH_COUNT(16)
- 0x68cd1000, // DST_GPR(0) DST_SWZ: XYZW DATA_FORMAT(35) SQ_NUM_FORMAT_SCALED SQ_FORMAT_COMP_SIGNED
-#ifdef MESA_BIG_ENDIAN
- 0x000a0000, // ENDIAN_SWAP(SQ_ENDIAN_8IN32) MEGA_FETCH(1)
-#else
- 0x00080000, // ENDIAN_SWAP(SQ_ENDIAN_NONE) MEGA_FETCH(1)
-#endif
- 0x00000000, // VTX_DWORD_PAD
-};
-
-const uint32_t r6xx_ps[] =
-{
- 0x00000002, // CF_DWORD0 AADR(2)
- 0x80800000, // SQ_CF_INST_TEX COUNT(1)
- 0x00000000, // CF_ALLOC_IMP_EXP0 SQ_EXPORT_PIXEL RW_GPR(0) ELEM_SIZE(0)
- 0x94200688, // SQ_CF_INST_EXPORT_DONE EOP(1) BARRIER(1) SWZ: XYZW
- 0x00000010, // SQ_TEX_INST_SAMPLE SRC_GPR(0) RESOURCE_ID(0)
- 0x000d1000, // DST_GPR(0) SWZ: XYZW TEX_UNNORMALIZED
- 0xb0800000, // SAMPLER_ID(0) SRC_SWZ XYZW
- 0x00000000, // TEX_DWORD_PAD
-};
-
+++ /dev/null
-/*
-Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
-
-The Weather Channel (TM) funded Tungsten Graphics to develop the
-initial release of the Radeon 8500 driver under the XFree86 license.
-This notice must be preserved.
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-**************************************************************************/
-
-/**
- * Mostly coppied from \radeon\radeon_cs_legacy.c
- */
-
-#include <errno.h>
-
-#include "main/glheader.h"
-#include "main/state.h"
-#include "main/imports.h"
-#include "main/macros.h"
-#include "main/context.h"
-#include "main/simple_list.h"
-
-#include "drm.h"
-#include "radeon_drm.h"
-
-#include "r600_context.h"
-#include "radeon_reg.h"
-#include "r600_cmdbuf.h"
-#include "radeon_bocs_wrapper.h"
-
-#ifdef HAVE_LIBDRM_RADEON
-#include "radeon_cs_int.h"
-#else
-#include "radeon_cs_int_drm.h"
-#endif
-
-struct r600_cs_manager_legacy
-{
- struct radeon_cs_manager base;
- struct radeon_context *ctx;
- /* hack for scratch stuff */
- uint32_t pending_age;
- uint32_t pending_count;
-};
-
-struct r600_cs_reloc_legacy {
- struct radeon_cs_reloc base;
- uint32_t cindices;
- uint32_t *indices;
- uint32_t *reloc_indices;
-};
-
-static struct radeon_cs_int *r600_cs_create(struct radeon_cs_manager *csm,
- uint32_t ndw)
-{
- struct radeon_cs_int *csi;
-
- csi = (struct radeon_cs_int*)calloc(1, sizeof(struct radeon_cs_int));
- if (csi == NULL) {
- return NULL;
- }
- csi->csm = csm;
- csi->ndw = (ndw + 0x3FF) & (~0x3FF);
- csi->packets = (uint32_t*)malloc(4*csi->ndw);
- if (csi->packets == NULL) {
- free(csi);
- return NULL;
- }
- csi->relocs_total_size = 0;
- return csi;
-}
-
-static int r600_cs_write_reloc(struct radeon_cs_int *csi,
- struct radeon_bo *bo,
- uint32_t read_domain,
- uint32_t write_domain,
- uint32_t flags)
-{
- struct r600_cs_reloc_legacy *relocs;
- int i;
-
- relocs = (struct r600_cs_reloc_legacy *)csi->relocs;
- /* check domains */
- if ((read_domain && write_domain) || (!read_domain && !write_domain)) {
- /* in one CS a bo can only be in read or write domain but not
- * in read & write domain at the same sime
- */
- return -EINVAL;
- }
- if (read_domain == RADEON_GEM_DOMAIN_CPU) {
- return -EINVAL;
- }
- if (write_domain == RADEON_GEM_DOMAIN_CPU) {
- return -EINVAL;
- }
- /* check if bo is already referenced */
- for(i = 0; i < csi->crelocs; i++) {
- uint32_t *indices;
- uint32_t *reloc_indices;
-
- if (relocs[i].base.bo->handle == bo->handle) {
- /* Check domains must be in read or write. As we check already
- * checked that in argument one of the read or write domain was
- * set we only need to check that if previous reloc as the read
- * domain set then the read_domain should also be set for this
- * new relocation.
- */
- if (relocs[i].base.read_domain && !read_domain) {
- return -EINVAL;
- }
- if (relocs[i].base.write_domain && !write_domain) {
- return -EINVAL;
- }
- relocs[i].base.read_domain |= read_domain;
- relocs[i].base.write_domain |= write_domain;
- /* save indice */
- relocs[i].cindices++;
- indices = (uint32_t*)realloc(relocs[i].indices,
- relocs[i].cindices * 4);
- reloc_indices = (uint32_t*)realloc(relocs[i].reloc_indices,
- relocs[i].cindices * 4);
- if ( (indices == NULL) || (reloc_indices == NULL) ) {
- relocs[i].cindices -= 1;
- return -ENOMEM;
- }
- relocs[i].indices = indices;
- relocs[i].reloc_indices = reloc_indices;
- relocs[i].indices[relocs[i].cindices - 1] = csi->cdw;
- relocs[i].reloc_indices[relocs[i].cindices - 1] = csi->cdw;
- csi->section_cdw += 2;
- csi->cdw += 2;
-
- return 0;
- }
- }
- /* add bo to reloc */
- relocs = (struct r600_cs_reloc_legacy*)
- realloc(csi->relocs,
- sizeof(struct r600_cs_reloc_legacy) * (csi->crelocs + 1));
- if (relocs == NULL) {
- return -ENOMEM;
- }
- csi->relocs = relocs;
- relocs[csi->crelocs].base.bo = bo;
- relocs[csi->crelocs].base.read_domain = read_domain;
- relocs[csi->crelocs].base.write_domain = write_domain;
- relocs[csi->crelocs].base.flags = flags;
- relocs[csi->crelocs].indices = (uint32_t*)malloc(4);
- relocs[csi->crelocs].reloc_indices = (uint32_t*)malloc(4);
- if ( (relocs[csi->crelocs].indices == NULL) || (relocs[csi->crelocs].reloc_indices == NULL) )
- {
- return -ENOMEM;
- }
-
- relocs[csi->crelocs].indices[0] = csi->cdw;
- relocs[csi->crelocs].reloc_indices[0] = csi->cdw;
- csi->section_cdw += 2;
- csi->cdw += 2;
- relocs[csi->crelocs].cindices = 1;
- csi->relocs_total_size += radeon_bo_legacy_relocs_size(bo);
- csi->crelocs++;
-
- radeon_bo_ref(bo);
-
- return 0;
-}
-
-static int r600_cs_begin(struct radeon_cs_int *csi,
- uint32_t ndw,
- const char *file,
- const char *func,
- int line)
-{
- if (csi->section_ndw) {
- fprintf(stderr, "CS already in a section(%s,%s,%d)\n",
- csi->section_file, csi->section_func, csi->section_line);
- fprintf(stderr, "CS can't start section(%s,%s,%d)\n",
- file, func, line);
- return -EPIPE;
- }
-
- csi->section_ndw = ndw;
- csi->section_cdw = 0;
- csi->section_file = file;
- csi->section_func = func;
- csi->section_line = line;
-
- if (csi->cdw + ndw > csi->ndw) {
- uint32_t tmp, *ptr;
- int num = (ndw > 0x400) ? ndw : 0x400;
-
- tmp = (csi->cdw + num + 0x3FF) & (~0x3FF);
- ptr = (uint32_t*)realloc(csi->packets, 4 * tmp);
- if (ptr == NULL) {
- return -ENOMEM;
- }
- csi->packets = ptr;
- csi->ndw = tmp;
- }
-
- return 0;
-}
-
-static int r600_cs_end(struct radeon_cs_int *csi,
- const char *file,
- const char *func,
- int line)
-
-{
- if (!csi->section_ndw) {
- fprintf(stderr, "CS no section to end at (%s,%s,%d)\n",
- file, func, line);
- return -EPIPE;
- }
-
- if ( csi->section_ndw != csi->section_cdw ) {
- fprintf(stderr, "CS section size missmatch start at (%s,%s,%d) %d vs %d\n",
- csi->section_file, csi->section_func, csi->section_line, csi->section_ndw, csi->section_cdw);
- fprintf(stderr, "csi->section_ndw = %d, csi->cdw = %d, csi->section_cdw = %d \n",
- csi->section_ndw, csi->cdw, csi->section_cdw);
- fprintf(stderr, "CS section end at (%s,%s,%d)\n",
- file, func, line);
- return -EPIPE;
- }
- csi->section_ndw = 0;
-
- if (csi->cdw > csi->ndw) {
- fprintf(stderr, "CS section overflow at (%s,%s,%d) cdw %d ndw %d\n",
- csi->section_file, csi->section_func, csi->section_line,csi->cdw,csi->ndw);
- fprintf(stderr, "CS section end at (%s,%s,%d)\n",
- file, func, line);
- assert(0);
- }
-
- return 0;
-}
-
-static int r600_cs_process_relocs(struct radeon_cs_int *csi,
- uint32_t * reloc_chunk,
- uint32_t * length_dw_reloc_chunk)
-{
- struct r600_cs_reloc_legacy *relocs;
- int i, j, r;
-
- uint32_t offset_dw = 0;
-
- relocs = (struct r600_cs_reloc_legacy *)csi->relocs;
-restart:
- for (i = 0; i < csi->crelocs; i++) {
- uint32_t soffset, eoffset;
-
- r = radeon_bo_legacy_validate(relocs[i].base.bo,
- &soffset, &eoffset);
- if (r == -EAGAIN) {
- goto restart;
- }
- if (r) {
- fprintf(stderr, "invalid bo(%p) [0x%08X, 0x%08X]\n",
- relocs[i].base.bo, soffset, eoffset);
- return r;
- }
-
- for (j = 0; j < relocs[i].cindices; j++) {
- /* pkt3 nop header in ib chunk */
- csi->packets[relocs[i].reloc_indices[j]] = 0xC0001000;
- /* reloc index in ib chunk */
- csi->packets[relocs[i].reloc_indices[j] + 1] = offset_dw;
- }
-
- /* asic offset in reloc chunk */ /* see alex drm r600_nomm_relocate */
- reloc_chunk[offset_dw] = soffset;
- reloc_chunk[offset_dw + 3] = 0;
-
- offset_dw += 4;
- }
-
- *length_dw_reloc_chunk = offset_dw;
-
- return 0;
-}
-
-static int r600_cs_set_age(struct radeon_cs_int *csi) /* -------------- */
-{
- struct r600_cs_manager_legacy *csm = (struct r600_cs_manager_legacy*)csi->csm;
- struct r600_cs_reloc_legacy *relocs;
- int i;
-
- relocs = (struct r600_cs_reloc_legacy *)csi->relocs;
- for (i = 0; i < csi->crelocs; i++) {
- radeon_bo_legacy_pending(relocs[i].base.bo, csm->pending_age);
- radeon_bo_unref(relocs[i].base.bo);
- }
- return 0;
-}
-
-#if 0
-static void dump_cmdbuf(struct radeon_cs_int *csi)
-{
- int i;
- fprintf(stderr,"--start--\n");
- for (i = 0; i < csi->cdw; i++){
- fprintf(stderr,"0x%08x\n", csi->packets[i]);
- }
- fprintf(stderr,"--end--\n");
-
-}
-#endif
-
-static int r600_cs_emit(struct radeon_cs_int *csi)
-{
- struct r600_cs_manager_legacy *csm = (struct r600_cs_manager_legacy*)csi->csm;
- struct drm_radeon_cs cs_cmd;
- struct drm_radeon_cs_chunk cs_chunk[2];
- uint32_t length_dw_reloc_chunk;
- uint64_t chunk_ptrs[2];
- uint32_t *reloc_chunk;
- int r;
- int retry = 0;
-
- /* TODO : put chip level things here if need. */
- /* csm->ctx->vtbl.emit_cs_header(cs, csm->ctx); */
-
- csm->pending_count = 1;
-
- reloc_chunk = (uint32_t*)calloc(1, csi->crelocs * 4 * 4);
-
- r = r600_cs_process_relocs(csi, reloc_chunk, &length_dw_reloc_chunk);
- if (r) {
- free(reloc_chunk);
- return 0;
- }
-
- /* raw ib chunk */
- cs_chunk[0].chunk_id = RADEON_CHUNK_ID_IB;
- cs_chunk[0].length_dw = csi->cdw;
- cs_chunk[0].chunk_data = (unsigned long)(csi->packets);
-
- /* reloc chaunk */
- cs_chunk[1].chunk_id = RADEON_CHUNK_ID_RELOCS;
- cs_chunk[1].length_dw = length_dw_reloc_chunk;
- cs_chunk[1].chunk_data = (unsigned long)reloc_chunk;
-
- chunk_ptrs[0] = (uint64_t)(unsigned long)&(cs_chunk[0]);
- chunk_ptrs[1] = (uint64_t)(unsigned long)&(cs_chunk[1]);
-
- cs_cmd.num_chunks = 2;
- /* cs_cmd.cs_id = 0; */
- cs_cmd.chunks = (uint64_t)(unsigned long)chunk_ptrs;
-
- //dump_cmdbuf(cs);
-
- do
- {
- r = drmCommandWriteRead(csi->csm->fd, DRM_RADEON_CS, &cs_cmd, sizeof(cs_cmd));
- retry++;
- } while (r == -EAGAIN && retry < 1000);
-
- if (r) {
- free(reloc_chunk);
- return r;
- }
-
- csm->pending_age = cs_cmd.cs_id;
-
- r600_cs_set_age(csi);
-
- csi->csm->read_used = 0;
- csi->csm->vram_write_used = 0;
- csi->csm->gart_write_used = 0;
-
- free(reloc_chunk);
-
- return 0;
-}
-
-static void inline r600_cs_free_reloc(void *relocs_p, int crelocs)
-{
- struct r600_cs_reloc_legacy *relocs = relocs_p;
- int i;
- if (!relocs_p)
- return;
- for (i = 0; i < crelocs; i++)
- {
- free(relocs[i].indices);
- free(relocs[i].reloc_indices);
- }
-}
-
-static int r600_cs_destroy(struct radeon_cs_int *csi)
-{
- r600_cs_free_reloc(csi->relocs, csi->crelocs);
- free(csi->relocs);
- free(csi->packets);
- free(csi);
- return 0;
-}
-
-static int r600_cs_erase(struct radeon_cs_int *csi)
-{
- r600_cs_free_reloc(csi->relocs, csi->crelocs);
- free(csi->relocs);
- csi->relocs_total_size = 0;
- csi->relocs = NULL;
- csi->crelocs = 0;
- csi->cdw = 0;
- return 0;
-}
-
-static int r600_cs_need_flush(struct radeon_cs_int *csi)
-{
- /* this function used to flush when the BO usage got to
- * a certain size, now the higher levels handle this better */
- return 0;
-}
-
-static void r600_cs_print(struct radeon_cs_int *csi, FILE *file)
-{
-}
-
-static struct radeon_cs_funcs r600_cs_funcs = {
- r600_cs_create,
- r600_cs_write_reloc,
- r600_cs_begin,
- r600_cs_end,
- r600_cs_emit,
- r600_cs_destroy,
- r600_cs_erase,
- r600_cs_need_flush,
- r600_cs_print
-};
-
-struct radeon_cs_manager * r600_radeon_cs_manager_legacy_ctor(struct radeon_context *ctx)
-{
- struct r600_cs_manager_legacy *csm;
-
- csm = (struct r600_cs_manager_legacy*)
- calloc(1, sizeof(struct r600_cs_manager_legacy));
- if (csm == NULL) {
- return NULL;
- }
- csm->base.funcs = &r600_cs_funcs;
- csm->base.fd = ctx->dri.fd;
- csm->ctx = ctx;
- csm->pending_age = 1;
- return (struct radeon_cs_manager*)csm;
-}
-
-void r600InitCmdBuf(context_t *r600) /* from rcommonInitCmdBuf */
-{
- radeonContextPtr rmesa = &r600->radeon;
- GLuint size;
-
- if(r600->radeon.radeonScreen->chip_family >= CHIP_FAMILY_CEDAR)
- {
- evergreenInitAtoms(r600);
- }
- else
- {
- r600InitAtoms(r600);
- }
-
- /* Initialize command buffer */
- size = 256 * driQueryOptioni(&rmesa->optionCache,
- "command_buffer_size");
- if (size < 2 * rmesa->hw.max_state_size) {
- size = 2 * rmesa->hw.max_state_size + 65535;
- }
- if (size > 64 * 256)
- size = 64 * 256;
-
- if (rmesa->radeonScreen->kernel_mm) {
- int fd = rmesa->radeonScreen->driScreen->fd;
- rmesa->cmdbuf.csm = radeon_cs_manager_gem_ctor(fd);
- } else {
- rmesa->cmdbuf.csm = r600_radeon_cs_manager_legacy_ctor(rmesa);
- }
- if (rmesa->cmdbuf.csm == NULL) {
- /* FIXME: fatal error */
- return;
- }
- rmesa->cmdbuf.cs = radeon_cs_create(rmesa->cmdbuf.csm, size);
- assert(rmesa->cmdbuf.cs != NULL);
- rmesa->cmdbuf.size = size;
-
- radeon_cs_space_set_flush(rmesa->cmdbuf.cs,
- (void (*)(void *))rmesa->glCtx->Driver.Flush, rmesa->glCtx);
-
- if (!rmesa->radeonScreen->kernel_mm) {
- radeon_cs_set_limit(rmesa->cmdbuf.cs, RADEON_GEM_DOMAIN_VRAM, rmesa->radeonScreen->texSize[0]);
- radeon_cs_set_limit(rmesa->cmdbuf.cs, RADEON_GEM_DOMAIN_GTT, rmesa->radeonScreen->gartTextures.size);
- } else {
- struct drm_radeon_gem_info mminfo;
-
- if (!drmCommandWriteRead(rmesa->dri.fd, DRM_RADEON_GEM_INFO, &mminfo, sizeof(mminfo)))
- {
- radeon_cs_set_limit(rmesa->cmdbuf.cs, RADEON_GEM_DOMAIN_VRAM, mminfo.vram_visible);
- radeon_cs_set_limit(rmesa->cmdbuf.cs, RADEON_GEM_DOMAIN_GTT, mminfo.gart_size);
- }
- }
-}
-
+++ /dev/null
-/*
-Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
-
-The Weather Channel (TM) funded Tungsten Graphics to develop the
-initial release of the Radeon 8500 driver under the XFree86 license.
-This notice must be preserved.
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-**************************************************************************/
-
-/**
- * \file
- *
- * \author Nicolai Haehnle <prefect_@gmx.net>
- */
-
-#ifndef __R600_CMDBUF_H__
-#define __R600_CMDBUF_H__
-
-#include "r600_context.h"
-
-#define RADEON_CP_PACKET3_NOP 0xC0001000
-#define RADEON_CP_PACKET3_NEXT_CHAR 0xC0001900
-#define RADEON_CP_PACKET3_PLY_NEXTSCAN 0xC0001D00
-#define RADEON_CP_PACKET3_SET_SCISSORS 0xC0001E00
-#define RADEON_CP_PACKET3_3D_RNDR_GEN_INDX_PRIM 0xC0002300
-#define RADEON_CP_PACKET3_LOAD_MICROCODE 0xC0002400
-#define RADEON_CP_PACKET3_WAIT_FOR_IDLE 0xC0002600
-#define RADEON_CP_PACKET3_3D_DRAW_VBUF 0xC0002800
-#define RADEON_CP_PACKET3_3D_DRAW_IMMD 0xC0002900
-#define RADEON_CP_PACKET3_3D_DRAW_INDX 0xC0002A00
-#define RADEON_CP_PACKET3_LOAD_PALETTE 0xC0002C00
-#define RADEON_CP_PACKET3_3D_LOAD_VBPNTR 0xC0002F00
-#define RADEON_CP_PACKET3_CNTL_PAINT 0xC0009100
-#define RADEON_CP_PACKET3_CNTL_BITBLT 0xC0009200
-#define RADEON_CP_PACKET3_CNTL_SMALLTEXT 0xC0009300
-#define RADEON_CP_PACKET3_CNTL_HOSTDATA_BLT 0xC0009400
-#define RADEON_CP_PACKET3_CNTL_POLYLINE 0xC0009500
-#define RADEON_CP_PACKET3_CNTL_POLYSCANLINES 0xC0009800
-#define RADEON_CP_PACKET3_CNTL_PAINT_MULTI 0xC0009A00
-#define RADEON_CP_PACKET3_CNTL_BITBLT_MULTI 0xC0009B00
-#define RADEON_CP_PACKET3_CNTL_TRANS_BITBLT 0xC0009C00
-
-/* r6xx/r7xx packet 3 type offsets */
-#define R600_SET_CONFIG_REG_OFFSET 0x00008000
-#define R600_SET_CONFIG_REG_END 0x0000ac00
-#define R600_SET_CONTEXT_REG_OFFSET 0x00028000
-#define R600_SET_CONTEXT_REG_END 0x00029000
-#define R600_SET_ALU_CONST_OFFSET 0x00030000
-#define R600_SET_ALU_CONST_END 0x00032000
-#define R600_SET_RESOURCE_OFFSET 0x00038000
-#define R600_SET_RESOURCE_END 0x0003c000
-#define R600_SET_SAMPLER_OFFSET 0x0003c000
-#define R600_SET_SAMPLER_END 0x0003cff0
-#define R600_SET_CTL_CONST_OFFSET 0x0003cff0
-#define R600_SET_CTL_CONST_END 0x0003e200
-#define R600_SET_LOOP_CONST_OFFSET 0x0003e200
-#define R600_SET_LOOP_CONST_END 0x0003e380
-#define R600_SET_BOOL_CONST_OFFSET 0x0003e380
-#define R600_SET_BOOL_CONST_END 0x00040000
-
-/* r6xx/r7xx packet 3 types */
-#define R600_IT_INDIRECT_BUFFER_END 0x00001700
-#define R600_IT_SET_PREDICATION 0x00002000
-#define R600_IT_REG_RMW 0x00002100
-#define R600_IT_COND_EXEC 0x00002200
-#define R600_IT_PRED_EXEC 0x00002300
-#define R600_IT_START_3D_CMDBUF 0x00002400
-#define R600_IT_DRAW_INDEX_2 0x00002700
-#define R600_IT_CONTEXT_CONTROL 0x00002800
-#define R600_IT_DRAW_INDEX_IMMD_BE 0x00002900
-#define R600_IT_INDEX_TYPE 0x00002A00
-#define R600_IT_DRAW_INDEX 0x00002B00
-#define R600_IT_DRAW_INDEX_AUTO 0x00002D00
-#define R600_IT_DRAW_INDEX_IMMD 0x00002E00
-#define R600_IT_NUM_INSTANCES 0x00002F00
-#define R600_IT_STRMOUT_BUFFER_UPDATE 0x00003400
-#define R600_IT_INDIRECT_BUFFER_MP 0x00003800
-#define R600_IT_MEM_SEMAPHORE 0x00003900
-#define R600_IT_MPEG_INDEX 0x00003A00
-#define R600_IT_WAIT_REG_MEM 0x00003C00
-#define R600_IT_MEM_WRITE 0x00003D00
-#define R600_IT_INDIRECT_BUFFER 0x00003200
-#define R600_IT_CP_INTERRUPT 0x00004000
-#define R600_IT_SURFACE_SYNC 0x00004300
-#define R600_IT_ME_INITIALIZE 0x00004400
-#define R600_IT_COND_WRITE 0x00004500
-#define R600_IT_EVENT_WRITE 0x00004600
-# define R600_EVENT_TYPE(x) ((x) << 0)
-# define R600_EVENT_INDEX(x) ((x) << 8)
-#define R600_IT_EVENT_WRITE_EOP 0x00004700
-#define R600_IT_ONE_REG_WRITE 0x00005700
-#define R600_IT_SET_CONFIG_REG 0x00006800
-#define R600_IT_SET_CONTEXT_REG 0x00006900
-#define R600_IT_SET_ALU_CONST 0x00006A00
-#define R600_IT_SET_BOOL_CONST 0x00006B00
-#define R600_IT_SET_LOOP_CONST 0x00006C00
-#define R600_IT_SET_RESOURCE 0x00006D00
-#define R600_IT_SET_SAMPLER 0x00006E00
-#define R600_IT_SET_CTL_CONST 0x00006F00
-#define R600_IT_SURFACE_BASE_UPDATE 0x00007300
-
-struct radeon_cs_manager * r600_radeon_cs_manager_legacy_ctor(struct radeon_context *ctx);
-
-/**
- * Write one dword to the command buffer.
- */
-#define R600_OUT_BATCH(data) \
-do { \
- radeon_cs_write_dword(b_l_rmesa->cmdbuf.cs, data); \
-} while(0)
-
-/**
- * Write n dwords from ptr to the command buffer.
- */
-#define R600_OUT_BATCH_TABLE(ptr,n) \
-do { \
- radeon_cs_write_table(b_l_rmesa->cmdbuf.cs, ptr, n); \
-} while(0)
-
-/**
- * Write a relocated dword to the command buffer.
- */
-#define R600_OUT_BATCH_RELOC(data, bo, offset, rd, wd, flags) \
- do { \
- if (0 && offset) { \
- fprintf(stderr, "(%s:%s:%d) offset : %d\n", \
- __FILE__, __FUNCTION__, __LINE__, offset); \
- } \
- radeon_cs_write_reloc(b_l_rmesa->cmdbuf.cs, \
- bo, rd, wd, flags); \
- } while(0)
-
-/* R600/R700 */
-#define R600_OUT_BATCH_REGS(reg, num) \
-do { \
- if ((reg) >= R600_SET_CONFIG_REG_OFFSET && (reg) < R600_SET_CONFIG_REG_END) { \
- R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG, (num))); \
- R600_OUT_BATCH(((reg) - R600_SET_CONFIG_REG_OFFSET) >> 2); \
- } else if ((reg) >= R600_SET_CONTEXT_REG_OFFSET && (reg) < R600_SET_CONTEXT_REG_END) { \
- R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CONTEXT_REG, (num))); \
- R600_OUT_BATCH(((reg) - R600_SET_CONTEXT_REG_OFFSET) >> 2); \
- } else if ((reg) >= R600_SET_ALU_CONST_OFFSET && (reg) < R600_SET_ALU_CONST_END) { \
- R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_ALU_CONST, (num))); \
- R600_OUT_BATCH(((reg) - R600_SET_ALU_CONST_OFFSET) >> 2); \
- } else if ((reg) >= R600_SET_RESOURCE_OFFSET && (reg) < R600_SET_RESOURCE_END) { \
- R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, (num))); \
- R600_OUT_BATCH(((reg) - R600_SET_RESOURCE_OFFSET) >> 2); \
- } else if ((reg) >= R600_SET_SAMPLER_OFFSET && (reg) < R600_SET_SAMPLER_END) { \
- R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_SAMPLER, (num))); \
- R600_OUT_BATCH(((reg) - R600_SET_SAMPLER_OFFSET) >> 2); \
- } else if ((reg) >= R600_SET_CTL_CONST_OFFSET && (reg) < R600_SET_CTL_CONST_END) { \
- R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, (num))); \
- R600_OUT_BATCH(((reg) - R600_SET_CTL_CONST_OFFSET) >> 2); \
- } else if ((reg) >= R600_SET_LOOP_CONST_OFFSET && (reg) < R600_SET_LOOP_CONST_END) { \
- R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_LOOP_CONST, (num))); \
- R600_OUT_BATCH(((reg) - R600_SET_LOOP_CONST_OFFSET) >> 2); \
- } else if ((reg) >= R600_SET_BOOL_CONST_OFFSET && (reg) < R600_SET_BOOL_CONST_END) { \
- R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_BOOL_CONST, (num))); \
- R600_OUT_BATCH(((reg) - R600_SET_BOOL_CONST_OFFSET) >> 2); \
- } else { \
- R600_OUT_BATCH(CP_PACKET0((reg), (num))); \
- } \
-} while (0)
-
-/** Single register write to command buffer; requires 3 dwords for most things. */
-#define R600_OUT_BATCH_REGVAL(reg, val) \
- R600_OUT_BATCH_REGS((reg), 1); \
- R600_OUT_BATCH((val))
-
-/** Continuous register range write to command buffer; requires 1 dword,
- * expects count dwords afterwards for register contents. */
-#define R600_OUT_BATCH_REGSEQ(reg, count) \
- R600_OUT_BATCH_REGS((reg), (count))
-
-/* evergreen */
-#define EVERGREEN_OUT_BATCH_REGS(reg, num) \
-do { \
- if ((reg) >= R600_SET_CONFIG_REG_OFFSET && (reg) < R600_SET_CONFIG_REG_END) { \
- R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG, (num))); \
- R600_OUT_BATCH(((reg) - R600_SET_CONFIG_REG_OFFSET) >> 2); \
- } else if ((reg) >= R600_SET_CONTEXT_REG_OFFSET && (reg) < R600_SET_CONTEXT_REG_END) { \
- R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CONTEXT_REG, (num))); \
- R600_OUT_BATCH(((reg) - R600_SET_CONTEXT_REG_OFFSET) >> 2); \
- } else if ((reg) >= EG_SET_RESOURCE_OFFSET && (reg) < EG_SET_RESOURCE_END) { \
- R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, (num))); \
- R600_OUT_BATCH(((reg) - EG_SET_RESOURCE_OFFSET) >> 2); \
- } else if ((reg) >= EG_SET_LOOP_CONST_OFFSET && (reg) < EG_SET_LOOP_CONST_END) { \
- R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_LOOP_CONST, (num))); \
- R600_OUT_BATCH(((reg) - EG_SET_LOOP_CONST_OFFSET) >> 2); \
- } else if ((reg) >= R600_SET_SAMPLER_OFFSET && (reg) < R600_SET_SAMPLER_END) { \
- R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_SAMPLER, (num))); \
- R600_OUT_BATCH(((reg) - R600_SET_SAMPLER_OFFSET) >> 2); \
- } else if ((reg) >= R600_SET_CTL_CONST_OFFSET && (reg) < R600_SET_CTL_CONST_END) { \
- R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, (num))); \
- R600_OUT_BATCH(((reg) - R600_SET_CTL_CONST_OFFSET) >> 2); \
- } else if ((reg) >= EG_SET_BOOL_CONST_OFFSET && (reg) < EG_SET_BOOL_CONST_END) { \
- R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_BOOL_CONST, (num))); \
- R600_OUT_BATCH(((reg) - EG_SET_BOOL_CONST_OFFSET) >> 2); \
- } else { \
- R600_OUT_BATCH(CP_PACKET0((reg), (num))); \
- } \
-} while (0)
-
-/** Single register write to command buffer; requires 3 dwords for most things. */
-#define EVERGREEN_OUT_BATCH_REGVAL(reg, val) \
- EVERGREEN_OUT_BATCH_REGS((reg), 1); \
- R600_OUT_BATCH((val))
-
-/** Continuous register range write to command buffer; requires 1 dword,
- * expects count dwords afterwards for register contents. */
-#define EVERGREEN_OUT_BATCH_REGSEQ(reg, count) \
- EVERGREEN_OUT_BATCH_REGS((reg), (count))
-
-
-extern void r600InitCmdBuf(context_t *r600);
-
-#endif /* __R600_CMDBUF_H__ */
+++ /dev/null
-/*
-Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
-
-The Weather Channel (TM) funded Tungsten Graphics to develop the
-initial release of the Radeon 8500 driver under the XFree86 license.
-This notice must be preserved.
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-**************************************************************************/
-
-/**
- * \file
- *
- * \author Keith Whitwell <keith@tungstengraphics.com>
- *
- * \author Nicolai Haehnle <prefect_@gmx.net>
- */
-
-#include <stdbool.h>
-#include "main/glheader.h"
-#include "main/api_arrayelt.h"
-#include "main/context.h"
-#include "main/simple_list.h"
-#include "main/imports.h"
-#include "main/extensions.h"
-#include "main/bufferobj.h"
-#include "main/texobj.h"
-#include "main/points.h"
-#include "main/mfeatures.h"
-#include "main/version.h"
-
-#include "swrast/swrast.h"
-#include "swrast_setup/swrast_setup.h"
-#include "vbo/vbo.h"
-
-#include "tnl/tnl.h"
-#include "tnl/t_pipeline.h"
-
-#include "drivers/common/driverfuncs.h"
-
-#include "radeon_debug.h"
-#include "r600_context.h"
-#include "radeon_common_context.h"
-#include "radeon_buffer_objects.h"
-#include "radeon_span.h"
-#include "r600_cmdbuf.h"
-#include "radeon_bocs_wrapper.h"
-#include "radeon_queryobj.h"
-#include "r600_blit.h"
-
-#include "r700_state.h"
-#include "r700_ioctl.h"
-
-#include "evergreen_context.h"
-#include "evergreen_state.h"
-#include "evergreen_tex.h"
-#include "evergreen_ioctl.h"
-#include "evergreen_oglprog.h"
-
-#include "utils.h"
-
-#define R600_ENABLE_GLSL_TEST 1
-
-static const struct tnl_pipeline_stage *r600_pipeline[] = {
- /* Catch any t&l fallbacks
- */
- &_tnl_vertex_transform_stage,
- &_tnl_normal_transform_stage,
- &_tnl_lighting_stage,
- &_tnl_fog_coordinate_stage,
- &_tnl_texgen_stage,
- &_tnl_texture_transform_stage,
- &_tnl_point_attenuation_stage,
- &_tnl_vertex_program_stage,
- &_tnl_render_stage,
- 0,
-};
-
-static void r600_get_lock(radeonContextPtr rmesa)
-{
- drm_radeon_sarea_t *sarea = rmesa->sarea;
-
- if (sarea->ctx_owner != rmesa->dri.hwContext) {
- sarea->ctx_owner = rmesa->dri.hwContext;
- if (!rmesa->radeonScreen->kernel_mm)
- radeon_bo_legacy_texture_age(rmesa->radeonScreen->bom);
- }
-}
-
-static void r600_vtbl_emit_cs_header(struct radeon_cs *cs, radeonContextPtr rmesa)
-{
- /* please flush pipe do all pending work */
- /* to be enabled */
-}
-
-static void r600_vtbl_pre_emit_atoms(radeonContextPtr radeon)
-{
- r700Start3D((context_t *)radeon);
-}
-
-static void r600_fallback(struct gl_context *ctx, GLuint bit, GLboolean mode)
-{
- context_t *context = R700_CONTEXT(ctx);
- if (mode)
- context->radeon.Fallback |= bit;
- else
- context->radeon.Fallback &= ~bit;
-}
-
-static void r600_emit_query_finish(radeonContextPtr radeon)
-{
- context_t *context = (context_t*) radeon;
- BATCH_LOCALS(&context->radeon);
-
- struct radeon_query_object *query = radeon->query.current;
-
- BEGIN_BATCH_NO_AUTOSTATE(4 + 2);
- R600_OUT_BATCH(CP_PACKET3(R600_IT_EVENT_WRITE, 2));
- R600_OUT_BATCH(R600_EVENT_TYPE(ZPASS_DONE) | R600_EVENT_INDEX(1));
- R600_OUT_BATCH(query->curr_offset + 8); /* hw writes qwords */
- R600_OUT_BATCH(0x00000000);
- R600_OUT_BATCH_RELOC(VGT_EVENT_INITIATOR, query->bo, 0, 0, RADEON_GEM_DOMAIN_GTT, 0);
- END_BATCH();
- assert(query->curr_offset < RADEON_QUERY_PAGE_SIZE);
- query->emitted_begin = GL_FALSE;
-}
-
-static void r600_init_vtbl(radeonContextPtr radeon)
-{
- radeon->vtbl.get_lock = r600_get_lock;
- radeon->vtbl.update_viewport_offset = r700UpdateViewportOffset;
- radeon->vtbl.emit_cs_header = r600_vtbl_emit_cs_header;
- radeon->vtbl.swtcl_flush = NULL;
- radeon->vtbl.pre_emit_atoms = r600_vtbl_pre_emit_atoms;
- radeon->vtbl.fallback = r600_fallback;
- radeon->vtbl.emit_query_finish = r600_emit_query_finish;
- radeon->vtbl.check_blit = r600_check_blit;
- radeon->vtbl.blit = r600_blit;
- radeon->vtbl.is_format_renderable = r600IsFormatRenderable;
-}
-
-static void r600InitConstValues(struct gl_context *ctx, radeonScreenPtr screen)
-{
- context_t *context = R700_CONTEXT(ctx);
- R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
-
- if( (context->radeon.radeonScreen->chip_family >= CHIP_FAMILY_CEDAR)
- &&(context->radeon.radeonScreen->chip_family <= CHIP_FAMILY_CAICOS) )
- {
- r700->bShaderUseMemConstant = GL_TRUE;
- }
- else
- {
- r700->bShaderUseMemConstant = GL_FALSE;
- }
-
- ctx->Const.GLSLVersion = 120;
- _mesa_override_glsl_version(ctx);
-
- ctx->Const.MaxTextureImageUnits = 16;
- /* 8 per clause on r6xx, 16 on r7xx
- * but I think mesa only supports 8 at the moment
- */
- ctx->Const.MaxTextureCoordUnits = 8;
- ctx->Const.MaxTextureUnits =
- MIN2(ctx->Const.MaxTextureImageUnits,
- ctx->Const.MaxTextureCoordUnits);
- ctx->Const.MaxCombinedTextureImageUnits =
- ctx->Const.MaxVertexTextureImageUnits +
- ctx->Const.MaxTextureImageUnits;
-
- ctx->Const.MaxTextureMaxAnisotropy = 16.0;
- ctx->Const.MaxTextureLodBias = 16.0;
-
- if (screen->chip_family >= CHIP_FAMILY_CEDAR) {
- ctx->Const.MaxTextureLevels = 15;
- ctx->Const.MaxTextureRectSize = 16384;
- } else {
- ctx->Const.MaxTextureLevels = 14;
- ctx->Const.MaxTextureRectSize = 8192;
- }
-
- ctx->Const.MinPointSize = 0x0001 / 8.0;
- ctx->Const.MinPointSizeAA = 0x0001 / 8.0;
- ctx->Const.MaxPointSize = 0xffff / 8.0;
- ctx->Const.MaxPointSizeAA = 0xffff / 8.0;
-
- ctx->Const.MinLineWidth = 0x0001 / 8.0;
- ctx->Const.MinLineWidthAA = 0x0001 / 8.0;
- ctx->Const.MaxLineWidth = 0xffff / 8.0;
- ctx->Const.MaxLineWidthAA = 0xffff / 8.0;
-
- ctx->Const.MaxDrawBuffers = 1; /* hw supports 8 */
- ctx->Const.MaxColorAttachments = 1;
- ctx->Const.MaxRenderbufferSize = 4096;
-
- /* 256 for reg-based consts, inline consts also supported */
- ctx->Const.VertexProgram.MaxInstructions = 8192; /* in theory no limit */
- ctx->Const.VertexProgram.MaxNativeInstructions = 8192;
- ctx->Const.VertexProgram.MaxNativeAttribs = 160;
- ctx->Const.VertexProgram.MaxTemps = 128;
- ctx->Const.VertexProgram.MaxNativeTemps = 128;
- ctx->Const.VertexProgram.MaxNativeParameters = 256;
- ctx->Const.VertexProgram.MaxNativeAddressRegs = 1; /* ??? */
-
- ctx->Const.FragmentProgram.MaxNativeTemps = 128;
- ctx->Const.FragmentProgram.MaxNativeAttribs = 32;
- ctx->Const.FragmentProgram.MaxNativeParameters = 256;
- ctx->Const.FragmentProgram.MaxNativeAluInstructions = 8192;
- /* 8 per clause on r6xx, 16 on r7xx */
- if (screen->chip_family >= CHIP_FAMILY_RV770)
- ctx->Const.FragmentProgram.MaxNativeTexInstructions = 16;
- else
- ctx->Const.FragmentProgram.MaxNativeTexInstructions = 8;
- ctx->Const.FragmentProgram.MaxNativeInstructions = 8192;
- ctx->Const.FragmentProgram.MaxNativeTexIndirections = 8; /* ??? */
- ctx->Const.FragmentProgram.MaxNativeAddressRegs = 0; /* and these are?? */
-}
-
-static void r600ParseOptions(context_t *r600, radeonScreenPtr screen)
-{
- /* Parse configuration files.
- * Do this here so that initialMaxAnisotropy is set before we create
- * the default textures.
- */
- driParseConfigFiles(&r600->radeon.optionCache, &screen->optionCache,
- screen->driScreen->myNum, "r600");
-
- r600->radeon.initialMaxAnisotropy = driQueryOptionf(&r600->radeon.optionCache,
- "def_max_anisotropy");
-
-}
-
-static void r600InitGLExtensions(struct gl_context *ctx)
-{
- context_t *r600 = R700_CONTEXT(ctx);
-#ifdef R600_ENABLE_GLSL_TEST
- unsigned i;
-#endif
-
- ctx->Extensions.ARB_depth_clamp = true;
- ctx->Extensions.ARB_depth_texture = true;
- ctx->Extensions.ARB_draw_elements_base_vertex = true;
- ctx->Extensions.ARB_fragment_program = true;
- ctx->Extensions.ARB_fragment_program_shadow = true;
- ctx->Extensions.ARB_occlusion_query = true;
- ctx->Extensions.ARB_shadow = true;
- ctx->Extensions.ARB_shadow_ambient = true;
- ctx->Extensions.ARB_texture_border_clamp = true;
- ctx->Extensions.ARB_texture_cube_map = true;
- ctx->Extensions.ARB_texture_env_combine = true;
- ctx->Extensions.ARB_texture_env_crossbar = true;
- ctx->Extensions.ARB_texture_env_dot3 = true;
- ctx->Extensions.ARB_texture_non_power_of_two = true;
- ctx->Extensions.ARB_vertex_program = true;
- ctx->Extensions.EXT_blend_color = true;
- ctx->Extensions.EXT_blend_equation_separate = true;
- ctx->Extensions.EXT_blend_func_separate = true;
- ctx->Extensions.EXT_blend_minmax = true;
- ctx->Extensions.EXT_packed_depth_stencil = true;
- ctx->Extensions.EXT_fog_coord = true;
- ctx->Extensions.EXT_gpu_program_parameters = true;
- ctx->Extensions.EXT_pixel_buffer_object = true;
- ctx->Extensions.EXT_point_parameters = true;
- ctx->Extensions.EXT_provoking_vertex = true;
- ctx->Extensions.EXT_secondary_color = true;
- ctx->Extensions.EXT_shadow_funcs = true;
- ctx->Extensions.EXT_stencil_two_side = true;
- ctx->Extensions.EXT_texture_env_dot3 = true;
- ctx->Extensions.EXT_texture_filter_anisotropic = true;
- ctx->Extensions.EXT_texture_mirror_clamp = true;
- ctx->Extensions.EXT_vertex_array_bgra = true;
- ctx->Extensions.EXT_texture_sRGB = true;
- ctx->Extensions.ATI_separate_stencil = true;
- ctx->Extensions.ATI_texture_env_combine3 = true;
- ctx->Extensions.ATI_texture_mirror_once = true;
- ctx->Extensions.MESA_pack_invert = true;
- ctx->Extensions.MESA_ycbcr_texture = true;
- ctx->Extensions.NV_blend_square = true;
- ctx->Extensions.NV_texture_rectangle = true;
- ctx->Extensions.NV_vertex_program = true;
-#if FEATURE_OES_EGL_image
- ctx->Extensions.OES_EGL_image = true;
-#endif
-
- if (r600->radeon.radeonScreen->kernel_mm)
- ctx->Extensions.EXT_framebuffer_object = true;
-
-#ifdef R600_ENABLE_GLSL_TEST
- ctx->Extensions.ARB_shading_language_100 = true;
- _mesa_enable_2_0_extensions(ctx);
-
- /* glsl compiler has problem if this is not GL_TRUE */
- for (i = 0; i <= MESA_SHADER_FRAGMENT; i++)
- ctx->ShaderCompilerOptions[i].EmitCondCodes = GL_TRUE;
-#endif /* R600_ENABLE_GLSL_TEST */
-
- if (driQueryOptionb
- (&r600->radeon.optionCache, "disable_stencil_two_side"))
- ctx->Extensions.EXT_stencil_two_side = false;
-
- if (r600->radeon.glCtx->Mesa_DXTn
- && !driQueryOptionb(&r600->radeon.optionCache, "disable_s3tc")) {
- ctx->Extensions.EXT_texture_compression_s3tc = true;
- ctx->Extensions.S3_s3tc = true;
- } else
- if (driQueryOptionb(&r600->radeon.optionCache, "force_s3tc_enable"))
- {
- ctx->Extensions.EXT_texture_compression_s3tc = true;
- }
-
- /* RV740 had a broken pipe config prior to drm 1.32 */
- if (!r600->radeon.radeonScreen->kernel_mm) {
- if ((r600->radeon.dri.drmMinor < 32) &&
- (r600->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV740))
- ctx->Extensions.ARB_occlusion_query = false;
- }
-}
-
-/* Create the device specific rendering context.
- */
-GLboolean r600CreateContext(gl_api api,
- const struct gl_config * glVisual,
- __DRIcontext * driContextPriv,
- void *sharedContextPrivate)
-{
- __DRIscreen *sPriv = driContextPriv->driScreenPriv;
- radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private);
- struct dd_function_table functions;
- context_t *r600;
- struct gl_context *ctx;
-
- assert(glVisual);
- assert(driContextPriv);
- assert(screen);
-
- /* Allocate the R600 context */
- r600 = (context_t*) CALLOC(sizeof(*r600));
- if (!r600) {
- radeon_error("Failed to allocate memory for context.\n");
- return GL_FALSE;
- }
-
- r600ParseOptions(r600, screen);
-
- r600->radeon.radeonScreen = screen;
-
- if(screen->chip_family >= CHIP_FAMILY_CEDAR)
- {
- evergreen_init_vtbl(&r600->radeon);
- }
- else
- {
- r600_init_vtbl(&r600->radeon);
- }
-
- /* Init default driver functions then plug in our R600-specific functions
- * (the texture functions are especially important)
- */
- _mesa_init_driver_functions(&functions);
-
- if(screen->chip_family >= CHIP_FAMILY_CEDAR)
- {
- evergreenCreateChip(r600);
- evergreenInitStateFuncs(&r600->radeon, &functions);
- evergreenInitTextureFuncs(&r600->radeon, &functions);
- evergreenInitShaderFuncs(&functions);
- }
- else
- {
- r700InitStateFuncs(&r600->radeon, &functions);
- r600InitTextureFuncs(&r600->radeon, &functions);
- r700InitShaderFuncs(&functions);
- }
-
- radeonInitQueryObjFunctions(&functions);
-
- if(screen->chip_family >= CHIP_FAMILY_CEDAR)
- {
- evergreenInitIoctlFuncs(&functions);
- }
- else
- {
- r700InitIoctlFuncs(&functions);
- }
- radeonInitBufferObjectFuncs(&functions);
-
- if (!radeonInitContext(&r600->radeon, &functions,
- glVisual, driContextPriv,
- sharedContextPrivate)) {
- radeon_error("Initializing context failed.\n");
- FREE(r600);
- return GL_FALSE;
- }
-
- ctx = r600->radeon.glCtx;
-
- ctx->VertexProgram._MaintainTnlProgram = GL_TRUE;
- ctx->FragmentProgram._MaintainTexEnvProgram = GL_TRUE;
-
- r600InitConstValues(ctx, screen);
-
- /* reinit, it depends on consts above */
- _mesa_init_point(ctx);
-
- _mesa_set_mvp_with_dp4( ctx, GL_TRUE );
-
- /* Initialize the software rasterizer and helper modules.
- */
- _swrast_CreateContext(ctx);
- _vbo_CreateContext(ctx);
- _tnl_CreateContext(ctx);
- _swsetup_CreateContext(ctx);
- _swsetup_Wakeup(ctx);
-
- /* Install the customized pipeline:
- */
- _tnl_destroy_pipeline(ctx);
- _tnl_install_pipeline(ctx, r600_pipeline);
- TNL_CONTEXT(ctx)->Driver.RunPipeline = _tnl_run_pipeline;
-
- /* Configure swrast and TNL to match hardware characteristics:
- */
- _swrast_allow_pixel_fog(ctx, GL_FALSE);
- _swrast_allow_vertex_fog(ctx, GL_TRUE);
- _tnl_allow_pixel_fog(ctx, GL_FALSE);
- _tnl_allow_vertex_fog(ctx, GL_TRUE);
-
- radeon_init_debug();
-
- if(screen->chip_family >= CHIP_FAMILY_CEDAR)
- {
- evergreenInitDraw(ctx);
- }
- else
- {
- r700InitDraw(ctx);
- }
-
- radeon_fbo_init(&r600->radeon);
- radeonInitSpanFuncs( ctx );
- r600InitCmdBuf(r600);
-
- if(screen->chip_family >= CHIP_FAMILY_CEDAR)
- {
- evergreenInitState(r600->radeon.glCtx);
- }
- else
- {
- r700InitState(r600->radeon.glCtx);
- }
-
- r600InitGLExtensions(ctx);
-
- return GL_TRUE;
-}
-
-void r600DestroyContext(__DRIcontext *driContextPriv )
-{
- void *pChip;
- context_t *context = (context_t *) driContextPriv->driverPrivate;
-
- assert(context);
-
- pChip = context->pChip;
-
- /* destroy context first, free pChip, in case there are things flush to asic. */
- radeonDestroyContext(driContextPriv);
-
- FREE(pChip);
-}
-
-
+++ /dev/null
-/*
-Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
-
-The Weather Channel (TM) funded Tungsten Graphics to develop the
-initial release of the Radeon 8500 driver under the XFree86 license.
-This notice must be preserved.
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-**************************************************************************/
-
-/**
- * \file
- *
- * \author Keith Whitwell <keith@tungstengraphics.com>
- * \author Nicolai Haehnle <prefect_@gmx.net>
- */
-
-#ifndef __R600_CONTEXT_H__
-#define __R600_CONTEXT_H__
-
-#include "tnl/t_vertex.h"
-#include "drm.h"
-#include "radeon_drm.h"
-#include "dri_util.h"
-#include "texmem.h"
-#include "radeon_common.h"
-
-#include "main/macros.h"
-#include "main/mtypes.h"
-#include "main/colormac.h"
-
-#include "r700_chip.h"
-#include "r600_tex.h"
-#include "r700_oglprog.h"
-#include "r700_vertprog.h"
-
-#include "evergreen_chip.h"
-
-struct r600_context;
-typedef struct r600_context context_t;
-
-#include "main/mm.h"
-
-#define COLOR_IS_RGBA
-#define TAG(x) r600##x
-#include "tnl_dd/t_dd_vertex.h"
-#undef TAG
-
-#define FORCE_CF_TEX_BARRIER 1
-
-/* #define GENERATE_SHADER_FOR_2D 1 */
-
-#define R600_FALLBACK_NONE 0
-#define R600_FALLBACK_TCL 1
-#define R600_FALLBACK_RAST 2
-
-struct r600_hw_state {
- struct radeon_state_atom sq;
- struct radeon_state_atom db;
- struct radeon_state_atom stencil;
- struct radeon_state_atom db_target;
- struct radeon_state_atom sc;
- struct radeon_state_atom scissor;
- struct radeon_state_atom aa;
- struct radeon_state_atom cl;
- struct radeon_state_atom gb;
- struct radeon_state_atom ucp;
- struct radeon_state_atom su;
- struct radeon_state_atom poly;
- struct radeon_state_atom cb;
- struct radeon_state_atom clrcmp;
- struct radeon_state_atom blnd;
- struct radeon_state_atom blnd_clr;
- struct radeon_state_atom cb_target;
- struct radeon_state_atom sx;
- struct radeon_state_atom vgt;
- struct radeon_state_atom spi;
- struct radeon_state_atom vpt;
-
- struct radeon_state_atom fs;
- struct radeon_state_atom vs;
- struct radeon_state_atom ps;
-
- struct radeon_state_atom vs_consts;
- struct radeon_state_atom ps_consts;
-
- struct radeon_state_atom vtx;
- struct radeon_state_atom tx;
- struct radeon_state_atom tx_smplr;
- struct radeon_state_atom tx_brdr_clr;
-};
-
-struct evergreen_hw_state {
- struct radeon_state_atom one_time_init;
- struct radeon_state_atom init;
- struct radeon_state_atom pa;
- struct radeon_state_atom vgt;
- struct radeon_state_atom tp;
- struct radeon_state_atom sq;
- struct radeon_state_atom vs;
- struct radeon_state_atom spi;
- struct radeon_state_atom sx;
- struct radeon_state_atom tx;
- struct radeon_state_atom db;
- struct radeon_state_atom cb;
- struct radeon_state_atom vtx;
- struct radeon_state_atom cp;
- struct radeon_state_atom timestamp;
-};
-
-typedef struct StreamDesc
-{
- GLint size; //number of data element
- GLenum type; //data element type
- GLsizei stride;
- GLenum format; // GL_RGBA,GLBGRA
-
- struct radeon_bo *bo;
- GLint bo_offset;
-
- GLuint dwords;
- GLuint dst_loc;
- GLuint _signed;
- GLboolean normalize;
- GLboolean is_named_bo;
- GLubyte element;
-} StreamDesc;
-
-typedef struct r700_index_buffer
-{
- struct radeon_bo *bo;
- int bo_offset;
-
- GLboolean is_32bit;
- GLuint count;
-} r700_index_buffer;
-
-/**
- * \brief R600 context structure.
- */
-struct r600_context {
- struct radeon_context radeon; /* parent class, must be first */
-
- /* ------ */
- R700_CHIP_CONTEXT hw;
-
- struct r600_hw_state atoms;
-
- struct evergreen_hw_state evergreen_atoms;
- void * pChip;
-
- struct r700_vertex_program *selected_vp;
-
- /* Vertex buffers
- */
- GLint nNumActiveAos;
- StreamDesc stream_desc[VERT_ATTRIB_MAX];
- struct r700_index_buffer ind_buf;
- struct radeon_bo *blit_bo;
- GLboolean blit_bo_loaded;
-
- /* Shader const buffer */
- struct radeon_bo * vp_Constbo;
- int vp_bo_offset;
- struct radeon_bo * fp_Constbo;
- int fp_bo_offset;
-};
-
-#define EVERGREEN_CONTEXT(ctx) ((context_t *)(ctx->DriverCtx))
-
-#define R700_CONTEXT(ctx) ((context_t *)(ctx->DriverCtx))
-#define GL_CONTEXT(context) ((struct gl_context *)(context->radeon.glCtx))
-
-#define GET_EVERGREEN_CHIP(context) ((EVERGREEN_CHIP_CONTEXT*)(context->pChip))
-
-extern GLboolean r600CreateContext(gl_api api,
- const struct gl_config * glVisual,
- __DRIcontext * driContextPriv,
- void *sharedContextPrivate);
-
-extern void r600DestroyContext(__DRIcontext *driContextPriv );
-extern void evergreenCreateChip(context_t *context);
-
-#define R700_CONTEXT_STATES(context) ((R700_CHIP_CONTEXT *)(&context->hw))
-
-#define R600_NEWPRIM( rmesa ) \
-do { \
- if ( rmesa->radeon.dma.flush ) \
- rmesa->radeon.dma.flush( rmesa->radeon.glCtx ); \
-} while (0)
-
-#define R600_STATECHANGE(r600, ATOM) \
-do { \
- R600_NEWPRIM(r600); \
- r600->atoms.ATOM.dirty = GL_TRUE; \
- r600->radeon.hw.is_dirty = GL_TRUE; \
-} while(0)
-
-#define EVERGREEN_STATECHANGE(r600, ATOM) \
-do { \
- R600_NEWPRIM(r600); \
- r600->evergreen_atoms.ATOM.dirty = GL_TRUE; \
- r600->radeon.hw.is_dirty = GL_TRUE; \
-} while(0)
-
-extern GLboolean r700SyncSurf(context_t *context,
- struct radeon_bo *pbo,
- uint32_t read_domain,
- uint32_t write_domain,
- uint32_t sync_type);
-
-extern void r700WaitForIdleClean(context_t *context);
-
-extern void r700Start3D(context_t *context);
-extern void r600InitAtoms(context_t *context);
-extern void r700InitDraw(struct gl_context *ctx);
-
-extern void evergreenInitAtoms(context_t *context);
-extern void evergreenInitDraw(struct gl_context *ctx);
-
-#define RADEON_D_CAPTURE 0
-#define RADEON_D_PLAYBACK 1
-#define RADEON_D_PLAYBACK_RAW 2
-#define RADEON_D_T 3
-
-#endif /* __R600_CONTEXT_H__ */
+++ /dev/null
-/**************************************************************************
-
-Copyright 2008, 2009 Advanced Micro Devices Inc. (AMD)
-
-Copyright (C) Advanced Micro Devices Inc. (AMD) 2009. All Rights Reserved.
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-**************************************************************************/
-
-/*
- * Authors:
- * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
- * CooperYuan <cooper.yuan@amd.com>, <cooperyuan@gmail.com>
- */
-
-#include "main/glheader.h"
-#include "main/mtypes.h"
-#include "main/colormac.h"
-#include "main/imports.h"
-#include "main/macros.h"
-
-#include "swrast_setup/swrast_setup.h"
-#include "tnl/tnl.h"
-#include "tnl/t_context.h"
-
-#include "r600_context.h"
-#include "r600_emit.h"
-
-void r600EmitCacheFlush(context_t *rmesa)
-{
-}
-
-GLboolean r600AllocShaderConsts(struct gl_context * ctx,
- void ** constbo,
- int sizeinBYTE,
- char * szShaderUsage)
-{
- radeonContextPtr radeonctx = RADEON_CONTEXT(ctx);
- struct radeon_bo * pbo;
-
- if(sizeinBYTE < 64) /* SQ_ALU_CONST_BUFFER_SIZE need 64 bytes at least to be non 0 */
- {
- sizeinBYTE = 64;
- }
-
-shader_again_alloc:
- pbo = radeon_bo_open(radeonctx->radeonScreen->bom,
- 0,
- sizeinBYTE,
- 256,
- RADEON_GEM_DOMAIN_GTT,
- 0);
-
- radeon_print(RADEON_SHADER, RADEON_NORMAL, "%s %p size %d: %s\n", __func__, pbo, sizeinBYTE, szShaderUsage);
-
- if (!pbo) {
- radeon_print(RADEON_MEMORY | RADEON_CS, RADEON_IMPORTANT, "No memory for buffer object. Flushing command buffer.\n");
- rcommonFlushCmdBuf(radeonctx, __FUNCTION__);
- goto shader_again_alloc;
- }
-
- radeon_cs_space_add_persistent_bo(radeonctx->cmdbuf.cs,
- pbo,
- RADEON_GEM_DOMAIN_GTT, 0);
-
- if (radeon_cs_space_check_with_bo(radeonctx->cmdbuf.cs,
- pbo,
- RADEON_GEM_DOMAIN_GTT, 0)) {
- radeon_error("failure to revalidate BOs - badness\n");
- return GL_FALSE;
- }
-
- *constbo = (void*)pbo;
-
- return GL_TRUE;
-}
-GLboolean r600EmitShaderConsts(struct gl_context * ctx,
- void * constbo,
- int bo_offset,
- GLvoid * data,
- int sizeinBYTE)
-{
- struct radeon_bo * pbo = (struct radeon_bo *)constbo;
- uint32_t *out;
- int i;
-
- radeon_bo_map(pbo, 1);
-
- out = (uint32_t*)(pbo->ptr);
- out = (uint32_t*)ADD_POINTERS(pbo->ptr, bo_offset);
-
- for(i = 0; i < sizeinBYTE / 4; i++) {
- out[i] = CPU_TO_LE32(*((uint32_t *)data + i));
- }
-
- radeon_bo_unmap(pbo);
-
- return GL_TRUE;
-}
-
-GLboolean r600EmitShader(struct gl_context * ctx,
- void ** shaderbo,
- GLvoid * data,
- int sizeinDWORD,
- char * szShaderUsage)
-{
- radeonContextPtr radeonctx = RADEON_CONTEXT(ctx);
- struct radeon_bo * pbo;
- uint32_t *out;
- int i;
-shader_again_alloc:
- pbo = radeon_bo_open(radeonctx->radeonScreen->bom,
- 0,
- sizeinDWORD * 4,
- 256,
- RADEON_GEM_DOMAIN_GTT,
- 0);
-
- radeon_print(RADEON_SHADER, RADEON_NORMAL, "%s %p size %d: %s\n", __func__, pbo, sizeinDWORD, szShaderUsage);
-
- if (!pbo) {
- radeon_print(RADEON_MEMORY | RADEON_CS, RADEON_IMPORTANT, "No memory for buffer object. Flushing command buffer.\n");
- rcommonFlushCmdBuf(radeonctx, __FUNCTION__);
- goto shader_again_alloc;
- }
-
- radeon_cs_space_add_persistent_bo(radeonctx->cmdbuf.cs,
- pbo,
- RADEON_GEM_DOMAIN_GTT, 0);
-
- if (radeon_cs_space_check_with_bo(radeonctx->cmdbuf.cs,
- pbo,
- RADEON_GEM_DOMAIN_GTT, 0)) {
- radeon_error("failure to revalidate BOs - badness\n");
- return GL_FALSE;
- }
-
- radeon_bo_map(pbo, 1);
-
- out = (uint32_t*)(pbo->ptr);
-
- for(i = 0; i < sizeinDWORD; i++) {
- out[i] = CPU_TO_LE32(*((uint32_t *)data + i));
- }
-
- radeon_bo_unmap(pbo);
-
- *shaderbo = (void*)pbo;
-
- return GL_TRUE;
-}
-
-GLboolean r600DeleteShader(struct gl_context * ctx,
- void * shaderbo)
-{
- struct radeon_bo * pbo = (struct radeon_bo *)shaderbo;
-
- radeon_print(RADEON_SHADER, RADEON_NORMAL, "%s: %p\n", __func__, pbo);
-
- if (pbo) {
- if (pbo->ptr)
- radeon_bo_unmap(pbo);
- radeon_bo_unref(pbo); /* when bo->cref <= 0, bo will be bo_free */
- }
-
- return GL_TRUE;
-}
+++ /dev/null
-/**************************************************************************
-
-Copyright 2008, 2009 Advanced Micro Devices Inc. (AMD)
-
-Copyright (C) Advanced Micro Devices Inc. (AMD) 2009. All Rights Reserved.
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-**************************************************************************/
-
-/*
- * Authors:
- * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
- * CooperYuan <cooper.yuan@amd.com>, <cooperyuan@gmail.com>
- */
-
-
-#ifndef __R600_EMIT_H__
-#define __R600_EMIT_H__
-
-#include "main/glheader.h"
-#include "r600_context.h"
-#include "r600_cmdbuf.h"
-#include "radeon_reg.h"
-
-void r600EmitCacheFlush(context_t *rmesa);
-
-extern GLboolean r600EmitShader(struct gl_context * ctx,
- void ** shaderbo,
- GLvoid * data,
- int sizeinDWORD,
- char * szShaderUsage);
-
-extern GLboolean r600DeleteShader(struct gl_context * ctx,
- void * shaderbo);
-
-extern GLboolean r600AllocShaderConsts(struct gl_context * ctx,
- void ** constbo,
- int sizeinBYTE,
- char * szShaderUsage);
-GLboolean r600EmitShaderConsts(struct gl_context * ctx,
- void * constbo,
- int bo_offset,
- GLvoid * data,
- int sizeinBYTE);
-
-#endif
+++ /dev/null
-/*
- * RadeonHD R6xx, R7xx Register documentation
- *
- * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
- * Copyright (C) 2008-2009 Matthias Hopf
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef _R600_REG_H_
-#define _R600_REG_H_
-
-/*
- * Register definitions
- */
-
-#include "r600_reg_auto_r6xx.h"
-#include "r600_reg_r6xx.h"
-#include "r600_reg_r7xx.h"
-
-
-/* SET_*_REG offsets + ends */
-enum
-{
- SET_CONFIG_REG_offset = 0x00008000,
- SET_CONFIG_REG_end = 0x0000ac00,
- SET_CONTEXT_REG_offset = 0x00028000,
- SET_CONTEXT_REG_end = 0x00029000,
- SET_ALU_CONST_offset = 0x00030000,
- SET_ALU_CONST_end = 0x00032000,
- SET_RESOURCE_offset = 0x00038000,
- SET_RESOURCE_end = 0x0003c000,
- SET_SAMPLER_offset = 0x0003c000,
- SET_SAMPLER_end = 0x0003cff0,
- SET_CTL_CONST_offset = 0x0003cff0,
- SET_CTL_CONST_end = 0x0003e200,
- SET_LOOP_CONST_offset = 0x0003e200,
- SET_LOOP_CONST_end = 0x0003e380,
- SET_BOOL_CONST_offset = 0x0003e380,
- SET_BOOL_CONST_end = 0x00040000,
-};
-
-/* packet3 IT_SURFACE_BASE_UPDATE bits */
-enum
-{
- DEPTH_BASE = (1 << 0),
- COLOR0_BASE = (1 << 1),
- COLOR1_BASE = (1 << 2),
- COLOR2_BASE = (1 << 3),
- COLOR3_BASE = (1 << 4),
- COLOR4_BASE = (1 << 5),
- COLOR5_BASE = (1 << 6),
- COLOR6_BASE = (1 << 7),
- COLOR7_BASE = (1 << 8),
- STRMOUT_BASE0 = (1 << 9),
- STRMOUT_BASE1 = (1 << 10),
- STRMOUT_BASE2 = (1 << 11),
- STRMOUT_BASE3 = (1 << 12),
- COHER_BASE0 = (1 << 13),
- COHER_BASE1 = (1 << 14),
-};
-
-/* Packet3 commands */
-enum
-{
- IT_NOP = 0x10,
- IT_INDIRECT_BUFFER_END = 0x17,
- IT_SET_PREDICATION = 0x20,
- IT_REG_RMW = 0x21,
- IT_COND_EXEC = 0x22,
- IT_PRED_EXEC = 0x23,
- IT_START_3D_CMDBUF = 0x24,
- IT_DRAW_INDEX_2 = 0x27,
- IT_CONTEXT_CONTROL = 0x28,
- IT_DRAW_INDEX_IMMD_BE = 0x29,
- IT_INDEX_TYPE = 0x2A,
- IT_DRAW_INDEX = 0x2B,
- IT_DRAW_INDEX_AUTO = 0x2D,
- IT_DRAW_INDEX_IMMD = 0x2E,
- IT_NUM_INSTANCES = 0x2F,
- IT_STRMOUT_BUFFER_UPDATE = 0x34,
- IT_INDIRECT_BUFFER_MP = 0x38,
- IT_MEM_SEMAPHORE = 0x39,
- IT_MPEG_INDEX = 0x3A,
- IT_WAIT_REG_MEM = 0x3C,
- IT_MEM_WRITE = 0x3D,
- IT_INDIRECT_BUFFER = 0x32,
- IT_CP_INTERRUPT = 0x40,
- IT_SURFACE_SYNC = 0x43,
- IT_ME_INITIALIZE = 0x44,
- IT_COND_WRITE = 0x45,
- IT_EVENT_WRITE = 0x46,
- IT_EVENT_WRITE_EOP = 0x47,
- IT_ONE_REG_WRITE = 0x57,
- IT_SET_CONFIG_REG = 0x68,
- IT_SET_CONTEXT_REG = 0x69,
- IT_SET_ALU_CONST = 0x6A,
- IT_SET_BOOL_CONST = 0x6B,
- IT_SET_LOOP_CONST = 0x6C,
- IT_SET_RESOURCE = 0x6D,
- IT_SET_SAMPLER = 0x6E,
- IT_SET_CTL_CONST = 0x6F,
- IT_SURFACE_BASE_UPDATE = 0x73,
-};
-
-#endif
+++ /dev/null
-/*
- * RadeonHD R6xx, R7xx Register documentation
- *
- * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
- * Copyright (C) 2008-2009 Matthias Hopf
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef _AUTOREGS
-#define _AUTOREGS
-
-enum {
-
- VGT_VTX_VECT_EJECT_REG = 0x000088b0,
- PRIM_COUNT_mask = 0x3ff << 0,
- PRIM_COUNT_shift = 0,
- VGT_LAST_COPY_STATE = 0x000088c0,
- SRC_STATE_ID_mask = 0x07 << 0,
- SRC_STATE_ID_shift = 0,
- DST_STATE_ID_mask = 0x07 << 16,
- DST_STATE_ID_shift = 16,
- VGT_CACHE_INVALIDATION = 0x000088c4,
- CACHE_INVALIDATION_mask = 0x03 << 0,
- CACHE_INVALIDATION_shift = 0,
- VC_ONLY = 0x00,
- TC_ONLY = 0x01,
- VC_AND_TC = 0x02,
- VS_NO_EXTRA_BUFFER_bit = 1 << 5,
- VGT_GS_PER_ES = 0x000088c8,
- VGT_ES_PER_GS = 0x000088cc,
- VGT_GS_VERTEX_REUSE = 0x000088d4,
- VERT_REUSE_mask = 0x1f << 0,
- VERT_REUSE_shift = 0,
- VGT_MC_LAT_CNTL = 0x000088d8,
- MC_TIME_STAMP_RES_mask = 0x03 << 0,
- MC_TIME_STAMP_RES_shift = 0,
- X_0_992_MAX_LATENCY = 0x00,
- X_0_496_MAX_LATENCY = 0x01,
- X_0_248_MAX_LATENCY = 0x02,
- X_0_124_MAX_LATENCY = 0x03,
- VGT_GS_PER_VS = 0x000088e8,
- GS_PER_VS_mask = 0x0f << 0,
- GS_PER_VS_shift = 0,
- VGT_CNTL_STATUS = 0x000088f0,
- VGT_OUT_INDX_BUSY_bit = 1 << 0,
- VGT_OUT_BUSY_bit = 1 << 1,
- VGT_PT_BUSY_bit = 1 << 2,
- VGT_TE_BUSY_bit = 1 << 3,
- VGT_VR_BUSY_bit = 1 << 4,
- VGT_GRP_BUSY_bit = 1 << 5,
- VGT_DMA_REQ_BUSY_bit = 1 << 6,
- VGT_DMA_BUSY_bit = 1 << 7,
- VGT_GS_BUSY_bit = 1 << 8,
- VGT_BUSY_bit = 1 << 9,
- VGT_PRIMITIVE_TYPE = 0x00008958,
- VGT_PRIMITIVE_TYPE__PRIM_TYPE_mask = 0x3f << 0,
- VGT_PRIMITIVE_TYPE__PRIM_TYPE_shift = 0,
- DI_PT_NONE = 0x00,
- DI_PT_POINTLIST = 0x01,
- DI_PT_LINELIST = 0x02,
- DI_PT_LINESTRIP = 0x03,
- DI_PT_TRILIST = 0x04,
- DI_PT_TRIFAN = 0x05,
- DI_PT_TRISTRIP = 0x06,
- DI_PT_UNUSED_0 = 0x07,
- DI_PT_UNUSED_1 = 0x08,
- DI_PT_UNUSED_2 = 0x09,
- DI_PT_LINELIST_ADJ = 0x0a,
- DI_PT_LINESTRIP_ADJ = 0x0b,
- DI_PT_TRILIST_ADJ = 0x0c,
- DI_PT_TRISTRIP_ADJ = 0x0d,
- DI_PT_UNUSED_3 = 0x0e,
- DI_PT_UNUSED_4 = 0x0f,
- DI_PT_TRI_WITH_WFLAGS = 0x10,
- DI_PT_RECTLIST = 0x11,
- DI_PT_LINELOOP = 0x12,
- DI_PT_QUADLIST = 0x13,
- DI_PT_QUADSTRIP = 0x14,
- DI_PT_POLYGON = 0x15,
- DI_PT_2D_COPY_RECT_LIST_V0 = 0x16,
- DI_PT_2D_COPY_RECT_LIST_V1 = 0x17,
- DI_PT_2D_COPY_RECT_LIST_V2 = 0x18,
- DI_PT_2D_COPY_RECT_LIST_V3 = 0x19,
- DI_PT_2D_FILL_RECT_LIST = 0x1a,
- DI_PT_2D_LINE_STRIP = 0x1b,
- DI_PT_2D_TRI_STRIP = 0x1c,
- VGT_INDEX_TYPE = 0x0000895c,
- INDEX_TYPE_mask = 0x03 << 0,
- INDEX_TYPE_shift = 0,
- DI_INDEX_SIZE_16_BIT = 0x00,
- DI_INDEX_SIZE_32_BIT = 0x01,
- VGT_STRMOUT_BUFFER_FILLED_SIZE_0 = 0x00008960,
- VGT_STRMOUT_BUFFER_FILLED_SIZE_1 = 0x00008964,
- VGT_STRMOUT_BUFFER_FILLED_SIZE_2 = 0x00008968,
- VGT_STRMOUT_BUFFER_FILLED_SIZE_3 = 0x0000896c,
- VGT_NUM_INDICES = 0x00008970,
- VGT_NUM_INSTANCES = 0x00008974,
- PA_CL_CNTL_STATUS = 0x00008a10,
- CL_BUSY_bit = 1 << 31,
- PA_CL_ENHANCE = 0x00008a14,
- CLIP_VTX_REORDER_ENA_bit = 1 << 0,
- NUM_CLIP_SEQ_mask = 0x03 << 1,
- NUM_CLIP_SEQ_shift = 1,
- CLIPPED_PRIM_SEQ_STALL_bit = 1 << 3,
- VE_NAN_PROC_DISABLE_bit = 1 << 4,
- PA_SU_CNTL_STATUS = 0x00008a50,
- SU_BUSY_bit = 1 << 31,
- PA_SC_LINE_STIPPLE_STATE = 0x00008b10,
- CURRENT_PTR_mask = 0x0f << 0,
- CURRENT_PTR_shift = 0,
- CURRENT_COUNT_mask = 0xff << 8,
- CURRENT_COUNT_shift = 8,
- PA_SC_MULTI_CHIP_CNTL = 0x00008b20,
- LOG2_NUM_CHIPS_mask = 0x07 << 0,
- LOG2_NUM_CHIPS_shift = 0,
- MULTI_CHIP_TILE_SIZE_mask = 0x03 << 3,
- MULTI_CHIP_TILE_SIZE_shift = 3,
- X_16_X_16_PIXEL_TILE_PER_CHIP = 0x00,
- X_32_X_32_PIXEL_TILE_PER_CHIP = 0x01,
- X_64_X_64_PIXEL_TILE_PER_CHIP = 0x02,
- X_128X128_PIXEL_TILE_PER_CHIP = 0x03,
- CHIP_TILE_X_LOC_mask = 0x07 << 5,
- CHIP_TILE_X_LOC_shift = 5,
- CHIP_TILE_Y_LOC_mask = 0x07 << 8,
- CHIP_TILE_Y_LOC_shift = 8,
- CHIP_SUPER_TILE_B_bit = 1 << 11,
- PA_SC_AA_SAMPLE_LOCS_2S = 0x00008b40,
- S0_X_mask = 0x0f << 0,
- S0_X_shift = 0,
- S0_Y_mask = 0x0f << 4,
- S0_Y_shift = 4,
- S1_X_mask = 0x0f << 8,
- S1_X_shift = 8,
- S1_Y_mask = 0x0f << 12,
- S1_Y_shift = 12,
- PA_SC_AA_SAMPLE_LOCS_4S = 0x00008b44,
-/* S0_X_mask = 0x0f << 0, */
-/* S0_X_shift = 0, */
-/* S0_Y_mask = 0x0f << 4, */
-/* S0_Y_shift = 4, */
-/* S1_X_mask = 0x0f << 8, */
-/* S1_X_shift = 8, */
-/* S1_Y_mask = 0x0f << 12, */
-/* S1_Y_shift = 12, */
- S2_X_mask = 0x0f << 16,
- S2_X_shift = 16,
- S2_Y_mask = 0x0f << 20,
- S2_Y_shift = 20,
- S3_X_mask = 0x0f << 24,
- S3_X_shift = 24,
- S3_Y_mask = 0x0f << 28,
- S3_Y_shift = 28,
- PA_SC_AA_SAMPLE_LOCS_8S_WD0 = 0x00008b48,
-/* S0_X_mask = 0x0f << 0, */
-/* S0_X_shift = 0, */
-/* S0_Y_mask = 0x0f << 4, */
-/* S0_Y_shift = 4, */
-/* S1_X_mask = 0x0f << 8, */
-/* S1_X_shift = 8, */
-/* S1_Y_mask = 0x0f << 12, */
-/* S1_Y_shift = 12, */
-/* S2_X_mask = 0x0f << 16, */
-/* S2_X_shift = 16, */
-/* S2_Y_mask = 0x0f << 20, */
-/* S2_Y_shift = 20, */
-/* S3_X_mask = 0x0f << 24, */
-/* S3_X_shift = 24, */
-/* S3_Y_mask = 0x0f << 28, */
-/* S3_Y_shift = 28, */
- PA_SC_AA_SAMPLE_LOCS_8S_WD1 = 0x00008b4c,
- S4_X_mask = 0x0f << 0,
- S4_X_shift = 0,
- S4_Y_mask = 0x0f << 4,
- S4_Y_shift = 4,
- S5_X_mask = 0x0f << 8,
- S5_X_shift = 8,
- S5_Y_mask = 0x0f << 12,
- S5_Y_shift = 12,
- S6_X_mask = 0x0f << 16,
- S6_X_shift = 16,
- S6_Y_mask = 0x0f << 20,
- S6_Y_shift = 20,
- S7_X_mask = 0x0f << 24,
- S7_X_shift = 24,
- S7_Y_mask = 0x0f << 28,
- S7_Y_shift = 28,
- PA_SC_CNTL_STATUS = 0x00008be0,
- MPASS_OVERFLOW_bit = 1 << 30,
- PA_SC_ENHANCE = 0x00008bf0,
- FORCE_EOV_MAX_CLK_CNT_mask = 0xfff << 0,
- FORCE_EOV_MAX_CLK_CNT_shift = 0,
- FORCE_EOV_MAX_TILE_CNT_mask = 0xfff << 12,
- FORCE_EOV_MAX_TILE_CNT_shift = 12,
- SQ_CONFIG = 0x00008c00,
- VC_ENABLE_bit = 1 << 0,
- EXPORT_SRC_C_bit = 1 << 1,
- DX9_CONSTS_bit = 1 << 2,
- ALU_INST_PREFER_VECTOR_bit = 1 << 3,
- SQ_CONFIG__DX10_CLAMP_bit = 1 << 4,
- ALU_PREFER_ONE_WATERFALL_bit = 1 << 5,
- ALU_MAX_ONE_WATERFALL_bit = 1 << 6,
- CLAUSE_SEQ_PRIO_mask = 0x03 << 8,
- CLAUSE_SEQ_PRIO_shift = 8,
- SQ_CL_PRIO_RND_ROBIN = 0x00,
- SQ_CL_PRIO_MACRO_SEQ = 0x01,
- SQ_CL_PRIO_NONE = 0x02,
- PS_PRIO_mask = 0x03 << 24,
- PS_PRIO_shift = 24,
- VS_PRIO_mask = 0x03 << 26,
- VS_PRIO_shift = 26,
- GS_PRIO_mask = 0x03 << 28,
- GS_PRIO_shift = 28,
- ES_PRIO_mask = 0x03 << 30,
- ES_PRIO_shift = 30,
- SQ_GPR_RESOURCE_MGMT_1 = 0x00008c04,
- NUM_PS_GPRS_mask = 0xff << 0,
- NUM_PS_GPRS_shift = 0,
- NUM_VS_GPRS_mask = 0xff << 16,
- NUM_VS_GPRS_shift = 16,
- NUM_CLAUSE_TEMP_GPRS_mask = 0x0f << 28,
- NUM_CLAUSE_TEMP_GPRS_shift = 28,
- SQ_GPR_RESOURCE_MGMT_2 = 0x00008c08,
- NUM_GS_GPRS_mask = 0xff << 0,
- NUM_GS_GPRS_shift = 0,
- NUM_ES_GPRS_mask = 0xff << 16,
- NUM_ES_GPRS_shift = 16,
- SQ_THREAD_RESOURCE_MGMT = 0x00008c0c,
- NUM_PS_THREADS_mask = 0xff << 0,
- NUM_PS_THREADS_shift = 0,
- NUM_VS_THREADS_mask = 0xff << 8,
- NUM_VS_THREADS_shift = 8,
- NUM_GS_THREADS_mask = 0xff << 16,
- NUM_GS_THREADS_shift = 16,
- NUM_ES_THREADS_mask = 0xff << 24,
- NUM_ES_THREADS_shift = 24,
- SQ_STACK_RESOURCE_MGMT_1 = 0x00008c10,
- NUM_PS_STACK_ENTRIES_mask = 0xfff << 0,
- NUM_PS_STACK_ENTRIES_shift = 0,
- NUM_VS_STACK_ENTRIES_mask = 0xfff << 16,
- NUM_VS_STACK_ENTRIES_shift = 16,
- SQ_STACK_RESOURCE_MGMT_2 = 0x00008c14,
- NUM_GS_STACK_ENTRIES_mask = 0xfff << 0,
- NUM_GS_STACK_ENTRIES_shift = 0,
- NUM_ES_STACK_ENTRIES_mask = 0xfff << 16,
- NUM_ES_STACK_ENTRIES_shift = 16,
- SQ_ESGS_RING_BASE = 0x00008c40,
- SQ_ESGS_RING_SIZE = 0x00008c44,
- SQ_GSVS_RING_BASE = 0x00008c48,
- SQ_GSVS_RING_SIZE = 0x00008c4c,
- SQ_ESTMP_RING_BASE = 0x00008c50,
- SQ_ESTMP_RING_SIZE = 0x00008c54,
- SQ_GSTMP_RING_BASE = 0x00008c58,
- SQ_GSTMP_RING_SIZE = 0x00008c5c,
- SQ_VSTMP_RING_BASE = 0x00008c60,
- SQ_VSTMP_RING_SIZE = 0x00008c64,
- SQ_PSTMP_RING_BASE = 0x00008c68,
- SQ_PSTMP_RING_SIZE = 0x00008c6c,
- SQ_FBUF_RING_BASE = 0x00008c70,
- SQ_FBUF_RING_SIZE = 0x00008c74,
- SQ_REDUC_RING_BASE = 0x00008c78,
- SQ_REDUC_RING_SIZE = 0x00008c7c,
- SQ_ALU_WORD1_OP3 = 0x00008dfc,
- SRC2_SEL_mask = 0x1ff << 0,
- SRC2_SEL_shift = 0,
- SQ_ALU_SRC_0 = 0xf8,
- SQ_ALU_SRC_1 = 0xf9,
- SQ_ALU_SRC_1_INT = 0xfa,
- SQ_ALU_SRC_M_1_INT = 0xfb,
- SQ_ALU_SRC_0_5 = 0xfc,
- SQ_ALU_SRC_LITERAL = 0xfd,
- SQ_ALU_SRC_PV = 0xfe,
- SQ_ALU_SRC_PS = 0xff,
- SRC2_REL_bit = 1 << 9,
- SRC2_CHAN_mask = 0x03 << 10,
- SRC2_CHAN_shift = 10,
- SQ_CHAN_X = 0x00,
- SQ_CHAN_Y = 0x01,
- SQ_CHAN_Z = 0x02,
- SQ_CHAN_W = 0x03,
- SRC2_NEG_bit = 1 << 12,
- SQ_ALU_WORD1_OP3__ALU_INST_mask = 0x1f << 13,
- SQ_ALU_WORD1_OP3__ALU_INST_shift = 13,
- SQ_OP3_INST_MUL_LIT = 0x0c,
- SQ_OP3_INST_MUL_LIT_M2 = 0x0d,
- SQ_OP3_INST_MUL_LIT_M4 = 0x0e,
- SQ_OP3_INST_MUL_LIT_D2 = 0x0f,
- SQ_OP3_INST_MULADD = 0x10,
- SQ_OP3_INST_MULADD_M2 = 0x11,
- SQ_OP3_INST_MULADD_M4 = 0x12,
- SQ_OP3_INST_MULADD_D2 = 0x13,
- SQ_OP3_INST_MULADD_IEEE = 0x14,
- SQ_OP3_INST_MULADD_IEEE_M2 = 0x15,
- SQ_OP3_INST_MULADD_IEEE_M4 = 0x16,
- SQ_OP3_INST_MULADD_IEEE_D2 = 0x17,
- SQ_OP3_INST_CNDE = 0x18,
- SQ_OP3_INST_CNDGT = 0x19,
- SQ_OP3_INST_CNDGE = 0x1a,
- SQ_OP3_INST_CNDE_INT = 0x1c,
- SQ_OP3_INST_CNDGT_INT = 0x1d,
- SQ_OP3_INST_CNDGE_INT = 0x1e,
- SQ_TEX_WORD2 = 0x00008dfc,
- OFFSET_X_mask = 0x1f << 0,
- OFFSET_X_shift = 0,
- OFFSET_Y_mask = 0x1f << 5,
- OFFSET_Y_shift = 5,
- OFFSET_Z_mask = 0x1f << 10,
- OFFSET_Z_shift = 10,
- SAMPLER_ID_mask = 0x1f << 15,
- SAMPLER_ID_shift = 15,
- SQ_TEX_WORD2__SRC_SEL_X_mask = 0x07 << 20,
- SQ_TEX_WORD2__SRC_SEL_X_shift = 20,
- SQ_SEL_X = 0x00,
- SQ_SEL_Y = 0x01,
- SQ_SEL_Z = 0x02,
- SQ_SEL_W = 0x03,
- SQ_SEL_0 = 0x04,
- SQ_SEL_1 = 0x05,
- SRC_SEL_Y_mask = 0x07 << 23,
- SRC_SEL_Y_shift = 23,
-/* SQ_SEL_X = 0x00, */
-/* SQ_SEL_Y = 0x01, */
-/* SQ_SEL_Z = 0x02, */
-/* SQ_SEL_W = 0x03, */
-/* SQ_SEL_0 = 0x04, */
-/* SQ_SEL_1 = 0x05, */
- SRC_SEL_Z_mask = 0x07 << 26,
- SRC_SEL_Z_shift = 26,
-/* SQ_SEL_X = 0x00, */
-/* SQ_SEL_Y = 0x01, */
-/* SQ_SEL_Z = 0x02, */
-/* SQ_SEL_W = 0x03, */
-/* SQ_SEL_0 = 0x04, */
-/* SQ_SEL_1 = 0x05, */
- SRC_SEL_W_mask = 0x07 << 29,
- SRC_SEL_W_shift = 29,
-/* SQ_SEL_X = 0x00, */
-/* SQ_SEL_Y = 0x01, */
-/* SQ_SEL_Z = 0x02, */
-/* SQ_SEL_W = 0x03, */
-/* SQ_SEL_0 = 0x04, */
-/* SQ_SEL_1 = 0x05, */
- SQ_CF_ALLOC_EXPORT_WORD1 = 0x00008dfc,
- BURST_COUNT_mask = 0x0f << 17,
- BURST_COUNT_shift = 17,
- END_OF_PROGRAM_bit = 1 << 21,
- VALID_PIXEL_MODE_bit = 1 << 22,
- SQ_CF_ALLOC_EXPORT_WORD1__CF_INST_mask = 0x7f << 23,
- SQ_CF_ALLOC_EXPORT_WORD1__CF_INST_shift = 23,
- SQ_CF_INST_MEM_STREAM0 = 0x20,
- SQ_CF_INST_MEM_STREAM1 = 0x21,
- SQ_CF_INST_MEM_STREAM2 = 0x22,
- SQ_CF_INST_MEM_STREAM3 = 0x23,
- SQ_CF_INST_MEM_SCRATCH = 0x24,
- SQ_CF_INST_MEM_REDUCTION = 0x25,
- SQ_CF_INST_MEM_RING = 0x26,
- SQ_CF_INST_EXPORT = 0x27,
- SQ_CF_INST_EXPORT_DONE = 0x28,
- WHOLE_QUAD_MODE_bit = 1 << 30,
- BARRIER_bit = 1 << 31,
- SQ_CF_ALU_WORD1 = 0x00008dfc,
- KCACHE_MODE1_mask = 0x03 << 0,
- KCACHE_MODE1_shift = 0,
- SQ_CF_KCACHE_NOP = 0x00,
- SQ_CF_KCACHE_LOCK_1 = 0x01,
- SQ_CF_KCACHE_LOCK_2 = 0x02,
- SQ_CF_KCACHE_LOCK_LOOP_INDEX = 0x03,
- KCACHE_ADDR0_mask = 0xff << 2,
- KCACHE_ADDR0_shift = 2,
- KCACHE_ADDR1_mask = 0xff << 10,
- KCACHE_ADDR1_shift = 10,
- SQ_CF_ALU_WORD1__COUNT_mask = 0x7f << 18,
- SQ_CF_ALU_WORD1__COUNT_shift = 18,
- SQ_CF_ALU_WORD1__ALT_CONST_bit = 1 << 25,
- SQ_CF_ALU_WORD1__CF_INST_mask = 0x0f << 26,
- SQ_CF_ALU_WORD1__CF_INST_shift = 26,
- SQ_CF_INST_ALU = 0x08,
- SQ_CF_INST_ALU_PUSH_BEFORE = 0x09,
- SQ_CF_INST_ALU_POP_AFTER = 0x0a,
- SQ_CF_INST_ALU_POP2_AFTER = 0x0b,
- SQ_CF_INST_ALU_CONTINUE = 0x0d,
- SQ_CF_INST_ALU_BREAK = 0x0e,
- SQ_CF_INST_ALU_ELSE_AFTER = 0x0f,
-/* WHOLE_QUAD_MODE_bit = 1 << 30, */
-/* BARRIER_bit = 1 << 31, */
- SQ_TEX_WORD1 = 0x00008dfc,
- SQ_TEX_WORD1__DST_GPR_mask = 0x7f << 0,
- SQ_TEX_WORD1__DST_GPR_shift = 0,
- SQ_TEX_WORD1__DST_REL_bit = 1 << 7,
- SQ_TEX_WORD1__DST_SEL_X_mask = 0x07 << 9,
- SQ_TEX_WORD1__DST_SEL_X_shift = 9,
-/* SQ_SEL_X = 0x00, */
-/* SQ_SEL_Y = 0x01, */
-/* SQ_SEL_Z = 0x02, */
-/* SQ_SEL_W = 0x03, */
-/* SQ_SEL_0 = 0x04, */
-/* SQ_SEL_1 = 0x05, */
- SQ_SEL_MASK = 0x07,
- SQ_TEX_WORD1__DST_SEL_Y_mask = 0x07 << 12,
- SQ_TEX_WORD1__DST_SEL_Y_shift = 12,
-/* SQ_SEL_X = 0x00, */
-/* SQ_SEL_Y = 0x01, */
-/* SQ_SEL_Z = 0x02, */
-/* SQ_SEL_W = 0x03, */
-/* SQ_SEL_0 = 0x04, */
-/* SQ_SEL_1 = 0x05, */
-/* SQ_SEL_MASK = 0x07, */
- SQ_TEX_WORD1__DST_SEL_Z_mask = 0x07 << 15,
- SQ_TEX_WORD1__DST_SEL_Z_shift = 15,
-/* SQ_SEL_X = 0x00, */
-/* SQ_SEL_Y = 0x01, */
-/* SQ_SEL_Z = 0x02, */
-/* SQ_SEL_W = 0x03, */
-/* SQ_SEL_0 = 0x04, */
-/* SQ_SEL_1 = 0x05, */
-/* SQ_SEL_MASK = 0x07, */
- SQ_TEX_WORD1__DST_SEL_W_mask = 0x07 << 18,
- SQ_TEX_WORD1__DST_SEL_W_shift = 18,
-/* SQ_SEL_X = 0x00, */
-/* SQ_SEL_Y = 0x01, */
-/* SQ_SEL_Z = 0x02, */
-/* SQ_SEL_W = 0x03, */
-/* SQ_SEL_0 = 0x04, */
-/* SQ_SEL_1 = 0x05, */
-/* SQ_SEL_MASK = 0x07, */
- SQ_TEX_WORD1__LOD_BIAS_mask = 0x7f << 21,
- SQ_TEX_WORD1__LOD_BIAS_shift = 21,
- COORD_TYPE_X_bit = 1 << 28,
- COORD_TYPE_Y_bit = 1 << 29,
- COORD_TYPE_Z_bit = 1 << 30,
- COORD_TYPE_W_bit = 1 << 31,
- SQ_VTX_WORD0 = 0x00008dfc,
- VTX_INST_mask = 0x1f << 0,
- VTX_INST_shift = 0,
- SQ_VTX_INST_FETCH = 0x00,
- SQ_VTX_INST_SEMANTIC = 0x01,
- FETCH_TYPE_mask = 0x03 << 5,
- FETCH_TYPE_shift = 5,
- SQ_VTX_FETCH_VERTEX_DATA = 0x00,
- SQ_VTX_FETCH_INSTANCE_DATA = 0x01,
- SQ_VTX_FETCH_NO_INDEX_OFFSET = 0x02,
- FETCH_WHOLE_QUAD_bit = 1 << 7,
- BUFFER_ID_mask = 0xff << 8,
- BUFFER_ID_shift = 8,
- SRC_GPR_mask = 0x7f << 16,
- SRC_GPR_shift = 16,
- SRC_REL_bit = 1 << 23,
- SQ_VTX_WORD0__SRC_SEL_X_mask = 0x03 << 24,
- SQ_VTX_WORD0__SRC_SEL_X_shift = 24,
-/* SQ_SEL_X = 0x00, */
-/* SQ_SEL_Y = 0x01, */
-/* SQ_SEL_Z = 0x02, */
-/* SQ_SEL_W = 0x03, */
- MEGA_FETCH_COUNT_mask = 0x3f << 26,
- MEGA_FETCH_COUNT_shift = 26,
- SQ_CF_ALLOC_EXPORT_WORD1_SWIZ = 0x00008dfc,
- SEL_X_mask = 0x07 << 0,
- SEL_X_shift = 0,
-/* SQ_SEL_X = 0x00, */
-/* SQ_SEL_Y = 0x01, */
-/* SQ_SEL_Z = 0x02, */
-/* SQ_SEL_W = 0x03, */
-/* SQ_SEL_0 = 0x04, */
-/* SQ_SEL_1 = 0x05, */
-/* SQ_SEL_MASK = 0x07, */
- SEL_Y_mask = 0x07 << 3,
- SEL_Y_shift = 3,
-/* SQ_SEL_X = 0x00, */
-/* SQ_SEL_Y = 0x01, */
-/* SQ_SEL_Z = 0x02, */
-/* SQ_SEL_W = 0x03, */
-/* SQ_SEL_0 = 0x04, */
-/* SQ_SEL_1 = 0x05, */
-/* SQ_SEL_MASK = 0x07, */
- SEL_Z_mask = 0x07 << 6,
- SEL_Z_shift = 6,
-/* SQ_SEL_X = 0x00, */
-/* SQ_SEL_Y = 0x01, */
-/* SQ_SEL_Z = 0x02, */
-/* SQ_SEL_W = 0x03, */
-/* SQ_SEL_0 = 0x04, */
-/* SQ_SEL_1 = 0x05, */
-/* SQ_SEL_MASK = 0x07, */
- SEL_W_mask = 0x07 << 9,
- SEL_W_shift = 9,
-/* SQ_SEL_X = 0x00, */
-/* SQ_SEL_Y = 0x01, */
-/* SQ_SEL_Z = 0x02, */
-/* SQ_SEL_W = 0x03, */
-/* SQ_SEL_0 = 0x04, */
-/* SQ_SEL_1 = 0x05, */
-/* SQ_SEL_MASK = 0x07, */
- SQ_ALU_WORD1 = 0x00008dfc,
- ENCODING_mask = 0x07 << 15,
- ENCODING_shift = 15,
- BANK_SWIZZLE_mask = 0x07 << 18,
- BANK_SWIZZLE_shift = 18,
- SQ_ALU_VEC_012 = 0x00,
- SQ_ALU_VEC_021 = 0x01,
- SQ_ALU_VEC_120 = 0x02,
- SQ_ALU_VEC_102 = 0x03,
- SQ_ALU_VEC_201 = 0x04,
- SQ_ALU_VEC_210 = 0x05,
- SQ_ALU_WORD1__DST_GPR_mask = 0x7f << 21,
- SQ_ALU_WORD1__DST_GPR_shift = 21,
- SQ_ALU_WORD1__DST_REL_bit = 1 << 28,
- DST_CHAN_mask = 0x03 << 29,
- DST_CHAN_shift = 29,
- CHAN_X = 0x00,
- CHAN_Y = 0x01,
- CHAN_Z = 0x02,
- CHAN_W = 0x03,
- SQ_ALU_WORD1__CLAMP_bit = 1 << 31,
- SQ_CF_ALU_WORD0 = 0x00008dfc,
- SQ_CF_ALU_WORD0__ADDR_mask = 0x3fffff << 0,
- SQ_CF_ALU_WORD0__ADDR_shift = 0,
- KCACHE_BANK0_mask = 0x0f << 22,
- KCACHE_BANK0_shift = 22,
- KCACHE_BANK1_mask = 0x0f << 26,
- KCACHE_BANK1_shift = 26,
- KCACHE_MODE0_mask = 0x03 << 30,
- KCACHE_MODE0_shift = 30,
-/* SQ_CF_KCACHE_NOP = 0x00, */
-/* SQ_CF_KCACHE_LOCK_1 = 0x01, */
-/* SQ_CF_KCACHE_LOCK_2 = 0x02, */
-/* SQ_CF_KCACHE_LOCK_LOOP_INDEX = 0x03, */
- SQ_VTX_WORD2 = 0x00008dfc,
- SQ_VTX_WORD2__OFFSET_mask = 0xffff << 0,
- SQ_VTX_WORD2__OFFSET_shift = 0,
- SQ_VTX_WORD2__ENDIAN_SWAP_mask = 0x03 << 16,
- SQ_VTX_WORD2__ENDIAN_SWAP_shift = 16,
- SQ_ENDIAN_NONE = 0x00,
- SQ_ENDIAN_8IN16 = 0x01,
- SQ_ENDIAN_8IN32 = 0x02,
- CONST_BUF_NO_STRIDE_bit = 1 << 18,
- MEGA_FETCH_bit = 1 << 19,
- SQ_VTX_WORD2__ALT_CONST_bit = 1 << 20,
- SQ_ALU_WORD1_OP2_V2 = 0x00008dfc,
- SRC0_ABS_bit = 1 << 0,
- SRC1_ABS_bit = 1 << 1,
- UPDATE_EXECUTE_MASK_bit = 1 << 2,
- UPDATE_PRED_bit = 1 << 3,
- WRITE_MASK_bit = 1 << 4,
- SQ_ALU_WORD1_OP2_V2__OMOD_mask = 0x03 << 5,
- SQ_ALU_WORD1_OP2_V2__OMOD_shift = 5,
- SQ_ALU_OMOD_OFF = 0x00,
- SQ_ALU_OMOD_M2 = 0x01,
- SQ_ALU_OMOD_M4 = 0x02,
- SQ_ALU_OMOD_D2 = 0x03,
- SQ_ALU_WORD1_OP2_V2__ALU_INST_mask = 0x7ff << 7,
- SQ_ALU_WORD1_OP2_V2__ALU_INST_shift = 7,
- SQ_OP2_INST_ADD = 0x00,
- SQ_OP2_INST_MUL = 0x01,
- SQ_OP2_INST_MUL_IEEE = 0x02,
- SQ_OP2_INST_MAX = 0x03,
- SQ_OP2_INST_MIN = 0x04,
- SQ_OP2_INST_MAX_DX10 = 0x05,
- SQ_OP2_INST_MIN_DX10 = 0x06,
- SQ_OP2_INST_SETE = 0x08,
- SQ_OP2_INST_SETGT = 0x09,
- SQ_OP2_INST_SETGE = 0x0a,
- SQ_OP2_INST_SETNE = 0x0b,
- SQ_OP2_INST_SETE_DX10 = 0x0c,
- SQ_OP2_INST_SETGT_DX10 = 0x0d,
- SQ_OP2_INST_SETGE_DX10 = 0x0e,
- SQ_OP2_INST_SETNE_DX10 = 0x0f,
- SQ_OP2_INST_FRACT = 0x10,
- SQ_OP2_INST_TRUNC = 0x11,
- SQ_OP2_INST_CEIL = 0x12,
- SQ_OP2_INST_RNDNE = 0x13,
- SQ_OP2_INST_FLOOR = 0x14,
- SQ_OP2_INST_MOVA = 0x15,
- SQ_OP2_INST_MOVA_FLOOR = 0x16,
- SQ_OP2_INST_MOVA_INT = 0x18,
- SQ_OP2_INST_MOV = 0x19,
- SQ_OP2_INST_NOP = 0x1a,
- SQ_OP2_INST_PRED_SETGT_UINT = 0x1e,
- SQ_OP2_INST_PRED_SETGE_UINT = 0x1f,
- SQ_OP2_INST_PRED_SETE = 0x20,
- SQ_OP2_INST_PRED_SETGT = 0x21,
- SQ_OP2_INST_PRED_SETGE = 0x22,
- SQ_OP2_INST_PRED_SETNE = 0x23,
- SQ_OP2_INST_PRED_SET_INV = 0x24,
- SQ_OP2_INST_PRED_SET_POP = 0x25,
- SQ_OP2_INST_PRED_SET_CLR = 0x26,
- SQ_OP2_INST_PRED_SET_RESTORE = 0x27,
- SQ_OP2_INST_PRED_SETE_PUSH = 0x28,
- SQ_OP2_INST_PRED_SETGT_PUSH = 0x29,
- SQ_OP2_INST_PRED_SETGE_PUSH = 0x2a,
- SQ_OP2_INST_PRED_SETNE_PUSH = 0x2b,
- SQ_OP2_INST_KILLE = 0x2c,
- SQ_OP2_INST_KILLGT = 0x2d,
- SQ_OP2_INST_KILLGE = 0x2e,
- SQ_OP2_INST_KILLNE = 0x2f,
- SQ_OP2_INST_AND_INT = 0x30,
- SQ_OP2_INST_OR_INT = 0x31,
- SQ_OP2_INST_XOR_INT = 0x32,
- SQ_OP2_INST_NOT_INT = 0x33,
- SQ_OP2_INST_ADD_INT = 0x34,
- SQ_OP2_INST_SUB_INT = 0x35,
- SQ_OP2_INST_MAX_INT = 0x36,
- SQ_OP2_INST_MIN_INT = 0x37,
- SQ_OP2_INST_MAX_UINT = 0x38,
- SQ_OP2_INST_MIN_UINT = 0x39,
- SQ_OP2_INST_SETE_INT = 0x3a,
- SQ_OP2_INST_SETGT_INT = 0x3b,
- SQ_OP2_INST_SETGE_INT = 0x3c,
- SQ_OP2_INST_SETNE_INT = 0x3d,
- SQ_OP2_INST_SETGT_UINT = 0x3e,
- SQ_OP2_INST_SETGE_UINT = 0x3f,
- SQ_OP2_INST_KILLGT_UINT = 0x40,
- SQ_OP2_INST_KILLGE_UINT = 0x41,
- SQ_OP2_INST_PRED_SETE_INT = 0x42,
- SQ_OP2_INST_PRED_SETGT_INT = 0x43,
- SQ_OP2_INST_PRED_SETGE_INT = 0x44,
- SQ_OP2_INST_PRED_SETNE_INT = 0x45,
- SQ_OP2_INST_KILLE_INT = 0x46,
- SQ_OP2_INST_KILLGT_INT = 0x47,
- SQ_OP2_INST_KILLGE_INT = 0x48,
- SQ_OP2_INST_KILLNE_INT = 0x49,
- SQ_OP2_INST_PRED_SETE_PUSH_INT = 0x4a,
- SQ_OP2_INST_PRED_SETGT_PUSH_INT = 0x4b,
- SQ_OP2_INST_PRED_SETGE_PUSH_INT = 0x4c,
- SQ_OP2_INST_PRED_SETNE_PUSH_INT = 0x4d,
- SQ_OP2_INST_PRED_SETLT_PUSH_INT = 0x4e,
- SQ_OP2_INST_PRED_SETLE_PUSH_INT = 0x4f,
- SQ_OP2_INST_DOT4 = 0x50,
- SQ_OP2_INST_DOT4_IEEE = 0x51,
- SQ_OP2_INST_CUBE = 0x52,
- SQ_OP2_INST_MAX4 = 0x53,
- SQ_OP2_INST_MOVA_GPR_INT = 0x60,
- SQ_OP2_INST_EXP_IEEE = 0x61,
- SQ_OP2_INST_LOG_CLAMPED = 0x62,
- SQ_OP2_INST_LOG_IEEE = 0x63,
- SQ_OP2_INST_RECIP_CLAMPED = 0x64,
- SQ_OP2_INST_RECIP_FF = 0x65,
- SQ_OP2_INST_RECIP_IEEE = 0x66,
- SQ_OP2_INST_RECIPSQRT_CLAMPED = 0x67,
- SQ_OP2_INST_RECIPSQRT_FF = 0x68,
- SQ_OP2_INST_RECIPSQRT_IEEE = 0x69,
- SQ_OP2_INST_SQRT_IEEE = 0x6a,
- SQ_OP2_INST_FLT_TO_INT = 0x6b,
- SQ_OP2_INST_INT_TO_FLT = 0x6c,
- SQ_OP2_INST_UINT_TO_FLT = 0x6d,
- SQ_OP2_INST_SIN = 0x6e,
- SQ_OP2_INST_COS = 0x6f,
- SQ_OP2_INST_ASHR_INT = 0x70,
- SQ_OP2_INST_LSHR_INT = 0x71,
- SQ_OP2_INST_LSHL_INT = 0x72,
- SQ_OP2_INST_MULLO_INT = 0x73,
- SQ_OP2_INST_MULHI_INT = 0x74,
- SQ_OP2_INST_MULLO_UINT = 0x75,
- SQ_OP2_INST_MULHI_UINT = 0x76,
- SQ_OP2_INST_RECIP_INT = 0x77,
- SQ_OP2_INST_RECIP_UINT = 0x78,
- SQ_OP2_INST_FLT_TO_UINT = 0x79,
- SQ_CF_ALLOC_EXPORT_WORD1_BUF = 0x00008dfc,
- ARRAY_SIZE_mask = 0xfff << 0,
- ARRAY_SIZE_shift = 0,
- COMP_MASK_mask = 0x0f << 12,
- COMP_MASK_shift = 12,
- SQ_CF_WORD0 = 0x00008dfc,
- SQ_CF_ALLOC_EXPORT_WORD0 = 0x00008dfc,
- ARRAY_BASE_mask = 0x1fff << 0,
- ARRAY_BASE_shift = 0,
- SQ_CF_ALLOC_EXPORT_WORD0__TYPE_mask = 0x03 << 13,
- SQ_CF_ALLOC_EXPORT_WORD0__TYPE_shift = 13,
- SQ_EXPORT_PIXEL = 0x00,
- SQ_EXPORT_POS = 0x01,
- SQ_EXPORT_PARAM = 0x02,
- X_UNUSED_FOR_SX_EXPORTS = 0x03,
- RW_GPR_mask = 0x7f << 15,
- RW_GPR_shift = 15,
- RW_REL_bit = 1 << 22,
- INDEX_GPR_mask = 0x7f << 23,
- INDEX_GPR_shift = 23,
- ELEM_SIZE_mask = 0x03 << 30,
- ELEM_SIZE_shift = 30,
- SQ_VTX_WORD1 = 0x00008dfc,
- SQ_VTX_WORD1__DST_SEL_X_mask = 0x07 << 9,
- SQ_VTX_WORD1__DST_SEL_X_shift = 9,
-/* SQ_SEL_X = 0x00, */
-/* SQ_SEL_Y = 0x01, */
-/* SQ_SEL_Z = 0x02, */
-/* SQ_SEL_W = 0x03, */
-/* SQ_SEL_0 = 0x04, */
-/* SQ_SEL_1 = 0x05, */
-/* SQ_SEL_MASK = 0x07, */
- SQ_VTX_WORD1__DST_SEL_Y_mask = 0x07 << 12,
- SQ_VTX_WORD1__DST_SEL_Y_shift = 12,
-/* SQ_SEL_X = 0x00, */
-/* SQ_SEL_Y = 0x01, */
-/* SQ_SEL_Z = 0x02, */
-/* SQ_SEL_W = 0x03, */
-/* SQ_SEL_0 = 0x04, */
-/* SQ_SEL_1 = 0x05, */
-/* SQ_SEL_MASK = 0x07, */
- SQ_VTX_WORD1__DST_SEL_Z_mask = 0x07 << 15,
- SQ_VTX_WORD1__DST_SEL_Z_shift = 15,
-/* SQ_SEL_X = 0x00, */
-/* SQ_SEL_Y = 0x01, */
-/* SQ_SEL_Z = 0x02, */
-/* SQ_SEL_W = 0x03, */
-/* SQ_SEL_0 = 0x04, */
-/* SQ_SEL_1 = 0x05, */
-/* SQ_SEL_MASK = 0x07, */
- SQ_VTX_WORD1__DST_SEL_W_mask = 0x07 << 18,
- SQ_VTX_WORD1__DST_SEL_W_shift = 18,
-/* SQ_SEL_X = 0x00, */
-/* SQ_SEL_Y = 0x01, */
-/* SQ_SEL_Z = 0x02, */
-/* SQ_SEL_W = 0x03, */
-/* SQ_SEL_0 = 0x04, */
-/* SQ_SEL_1 = 0x05, */
-/* SQ_SEL_MASK = 0x07, */
- USE_CONST_FIELDS_bit = 1 << 21,
- SQ_VTX_WORD1__DATA_FORMAT_mask = 0x3f << 22,
- SQ_VTX_WORD1__DATA_FORMAT_shift = 22,
- SQ_VTX_WORD1__NUM_FORMAT_ALL_mask = 0x03 << 28,
- SQ_VTX_WORD1__NUM_FORMAT_ALL_shift = 28,
- SQ_NUM_FORMAT_NORM = 0x00,
- SQ_NUM_FORMAT_INT = 0x01,
- SQ_NUM_FORMAT_SCALED = 0x02,
- SQ_VTX_WORD1__FORMAT_COMP_ALL_bit = 1 << 30,
- SQ_VTX_WORD1__SRF_MODE_ALL_bit = 1 << 31,
- SQ_ALU_WORD1_OP2 = 0x00008dfc,
-/* SRC0_ABS_bit = 1 << 0, */
-/* SRC1_ABS_bit = 1 << 1, */
-/* UPDATE_EXECUTE_MASK_bit = 1 << 2, */
-/* UPDATE_PRED_bit = 1 << 3, */
-/* WRITE_MASK_bit = 1 << 4, */
- FOG_MERGE_bit = 1 << 5,
- SQ_ALU_WORD1_OP2__OMOD_mask = 0x03 << 6,
- SQ_ALU_WORD1_OP2__OMOD_shift = 6,
-/* SQ_ALU_OMOD_OFF = 0x00, */
-/* SQ_ALU_OMOD_M2 = 0x01, */
-/* SQ_ALU_OMOD_M4 = 0x02, */
-/* SQ_ALU_OMOD_D2 = 0x03, */
- SQ_ALU_WORD1_OP2__ALU_INST_mask = 0x3ff << 8,
- SQ_ALU_WORD1_OP2__ALU_INST_shift = 8,
-/* SQ_OP2_INST_ADD = 0x00, */
-/* SQ_OP2_INST_MUL = 0x01, */
-/* SQ_OP2_INST_MUL_IEEE = 0x02, */
-/* SQ_OP2_INST_MAX = 0x03, */
-/* SQ_OP2_INST_MIN = 0x04, */
-/* SQ_OP2_INST_MAX_DX10 = 0x05, */
-/* SQ_OP2_INST_MIN_DX10 = 0x06, */
-/* SQ_OP2_INST_SETE = 0x08, */
-/* SQ_OP2_INST_SETGT = 0x09, */
-/* SQ_OP2_INST_SETGE = 0x0a, */
-/* SQ_OP2_INST_SETNE = 0x0b, */
-/* SQ_OP2_INST_SETE_DX10 = 0x0c, */
-/* SQ_OP2_INST_SETGT_DX10 = 0x0d, */
-/* SQ_OP2_INST_SETGE_DX10 = 0x0e, */
-/* SQ_OP2_INST_SETNE_DX10 = 0x0f, */
-/* SQ_OP2_INST_FRACT = 0x10, */
-/* SQ_OP2_INST_TRUNC = 0x11, */
-/* SQ_OP2_INST_CEIL = 0x12, */
-/* SQ_OP2_INST_RNDNE = 0x13, */
-/* SQ_OP2_INST_FLOOR = 0x14, */
-/* SQ_OP2_INST_MOVA = 0x15, */
-/* SQ_OP2_INST_MOVA_FLOOR = 0x16, */
-/* SQ_OP2_INST_MOVA_INT = 0x18, */
-/* SQ_OP2_INST_MOV = 0x19, */
-/* SQ_OP2_INST_NOP = 0x1a, */
-/* SQ_OP2_INST_PRED_SETGT_UINT = 0x1e, */
-/* SQ_OP2_INST_PRED_SETGE_UINT = 0x1f, */
-/* SQ_OP2_INST_PRED_SETE = 0x20, */
-/* SQ_OP2_INST_PRED_SETGT = 0x21, */
-/* SQ_OP2_INST_PRED_SETGE = 0x22, */
-/* SQ_OP2_INST_PRED_SETNE = 0x23, */
-/* SQ_OP2_INST_PRED_SET_INV = 0x24, */
-/* SQ_OP2_INST_PRED_SET_POP = 0x25, */
-/* SQ_OP2_INST_PRED_SET_CLR = 0x26, */
-/* SQ_OP2_INST_PRED_SET_RESTORE = 0x27, */
-/* SQ_OP2_INST_PRED_SETE_PUSH = 0x28, */
-/* SQ_OP2_INST_PRED_SETGT_PUSH = 0x29, */
-/* SQ_OP2_INST_PRED_SETGE_PUSH = 0x2a, */
-/* SQ_OP2_INST_PRED_SETNE_PUSH = 0x2b, */
-/* SQ_OP2_INST_KILLE = 0x2c, */
-/* SQ_OP2_INST_KILLGT = 0x2d, */
-/* SQ_OP2_INST_KILLGE = 0x2e, */
-/* SQ_OP2_INST_KILLNE = 0x2f, */
-/* SQ_OP2_INST_AND_INT = 0x30, */
-/* SQ_OP2_INST_OR_INT = 0x31, */
-/* SQ_OP2_INST_XOR_INT = 0x32, */
-/* SQ_OP2_INST_NOT_INT = 0x33, */
-/* SQ_OP2_INST_ADD_INT = 0x34, */
-/* SQ_OP2_INST_SUB_INT = 0x35, */
-/* SQ_OP2_INST_MAX_INT = 0x36, */
-/* SQ_OP2_INST_MIN_INT = 0x37, */
-/* SQ_OP2_INST_MAX_UINT = 0x38, */
-/* SQ_OP2_INST_MIN_UINT = 0x39, */
-/* SQ_OP2_INST_SETE_INT = 0x3a, */
-/* SQ_OP2_INST_SETGT_INT = 0x3b, */
-/* SQ_OP2_INST_SETGE_INT = 0x3c, */
-/* SQ_OP2_INST_SETNE_INT = 0x3d, */
-/* SQ_OP2_INST_SETGT_UINT = 0x3e, */
-/* SQ_OP2_INST_SETGE_UINT = 0x3f, */
-/* SQ_OP2_INST_KILLGT_UINT = 0x40, */
-/* SQ_OP2_INST_KILLGE_UINT = 0x41, */
-/* SQ_OP2_INST_PRED_SETE_INT = 0x42, */
-/* SQ_OP2_INST_PRED_SETGT_INT = 0x43, */
-/* SQ_OP2_INST_PRED_SETGE_INT = 0x44, */
-/* SQ_OP2_INST_PRED_SETNE_INT = 0x45, */
-/* SQ_OP2_INST_KILLE_INT = 0x46, */
-/* SQ_OP2_INST_KILLGT_INT = 0x47, */
-/* SQ_OP2_INST_KILLGE_INT = 0x48, */
-/* SQ_OP2_INST_KILLNE_INT = 0x49, */
-/* SQ_OP2_INST_PRED_SETE_PUSH_INT = 0x4a, */
-/* SQ_OP2_INST_PRED_SETGT_PUSH_INT = 0x4b, */
-/* SQ_OP2_INST_PRED_SETGE_PUSH_INT = 0x4c, */
-/* SQ_OP2_INST_PRED_SETNE_PUSH_INT = 0x4d, */
-/* SQ_OP2_INST_PRED_SETLT_PUSH_INT = 0x4e, */
-/* SQ_OP2_INST_PRED_SETLE_PUSH_INT = 0x4f, */
-/* SQ_OP2_INST_DOT4 = 0x50, */
-/* SQ_OP2_INST_DOT4_IEEE = 0x51, */
-/* SQ_OP2_INST_CUBE = 0x52, */
-/* SQ_OP2_INST_MAX4 = 0x53, */
-/* SQ_OP2_INST_MOVA_GPR_INT = 0x60, */
-/* SQ_OP2_INST_EXP_IEEE = 0x61, */
-/* SQ_OP2_INST_LOG_CLAMPED = 0x62, */
-/* SQ_OP2_INST_LOG_IEEE = 0x63, */
-/* SQ_OP2_INST_RECIP_CLAMPED = 0x64, */
-/* SQ_OP2_INST_RECIP_FF = 0x65, */
-/* SQ_OP2_INST_RECIP_IEEE = 0x66, */
-/* SQ_OP2_INST_RECIPSQRT_CLAMPED = 0x67, */
-/* SQ_OP2_INST_RECIPSQRT_FF = 0x68, */
-/* SQ_OP2_INST_RECIPSQRT_IEEE = 0x69, */
-/* SQ_OP2_INST_SQRT_IEEE = 0x6a, */
-/* SQ_OP2_INST_FLT_TO_INT = 0x6b, */
-/* SQ_OP2_INST_INT_TO_FLT = 0x6c, */
-/* SQ_OP2_INST_UINT_TO_FLT = 0x6d, */
-/* SQ_OP2_INST_SIN = 0x6e, */
-/* SQ_OP2_INST_COS = 0x6f, */
-/* SQ_OP2_INST_ASHR_INT = 0x70, */
-/* SQ_OP2_INST_LSHR_INT = 0x71, */
-/* SQ_OP2_INST_LSHL_INT = 0x72, */
-/* SQ_OP2_INST_MULLO_INT = 0x73, */
-/* SQ_OP2_INST_MULHI_INT = 0x74, */
-/* SQ_OP2_INST_MULLO_UINT = 0x75, */
-/* SQ_OP2_INST_MULHI_UINT = 0x76, */
-/* SQ_OP2_INST_RECIP_INT = 0x77, */
-/* SQ_OP2_INST_RECIP_UINT = 0x78, */
-/* SQ_OP2_INST_FLT_TO_UINT = 0x79, */
- SQ_CF_WORD1 = 0x00008dfc,
- POP_COUNT_mask = 0x07 << 0,
- POP_COUNT_shift = 0,
- CF_CONST_mask = 0x1f << 3,
- CF_CONST_shift = 3,
- COND_mask = 0x03 << 8,
- COND_shift = 8,
- SQ_CF_COND_ACTIVE = 0x00,
- SQ_CF_COND_FALSE = 0x01,
- SQ_CF_COND_BOOL = 0x02,
- SQ_CF_COND_NOT_BOOL = 0x03,
- SQ_CF_WORD1__COUNT_mask = 0x07 << 10,
- SQ_CF_WORD1__COUNT_shift = 10,
- CALL_COUNT_mask = 0x3f << 13,
- CALL_COUNT_shift = 13,
- COUNT_3_bit = 1 << 19,
-/* END_OF_PROGRAM_bit = 1 << 21, */
-/* VALID_PIXEL_MODE_bit = 1 << 22, */
- SQ_CF_WORD1__CF_INST_mask = 0x7f << 23,
- SQ_CF_WORD1__CF_INST_shift = 23,
- SQ_CF_INST_NOP = 0x00,
- SQ_CF_INST_TEX = 0x01,
- SQ_CF_INST_VTX = 0x02,
- SQ_CF_INST_VTX_TC = 0x03,
- SQ_CF_INST_LOOP_START = 0x04,
- SQ_CF_INST_LOOP_END = 0x05,
- SQ_CF_INST_LOOP_START_DX10 = 0x06,
- SQ_CF_INST_LOOP_START_NO_AL = 0x07,
- SQ_CF_INST_LOOP_CONTINUE = 0x08,
- SQ_CF_INST_LOOP_BREAK = 0x09,
- SQ_CF_INST_JUMP = 0x0a,
- SQ_CF_INST_PUSH = 0x0b,
- SQ_CF_INST_PUSH_ELSE = 0x0c,
- SQ_CF_INST_ELSE = 0x0d,
- SQ_CF_INST_POP = 0x0e,
- SQ_CF_INST_POP_JUMP = 0x0f,
- SQ_CF_INST_POP_PUSH = 0x10,
- SQ_CF_INST_POP_PUSH_ELSE = 0x11,
- SQ_CF_INST_CALL = 0x12,
- SQ_CF_INST_CALL_FS = 0x13,
- SQ_CF_INST_RETURN = 0x14,
- SQ_CF_INST_EMIT_VERTEX = 0x15,
- SQ_CF_INST_EMIT_CUT_VERTEX = 0x16,
- SQ_CF_INST_CUT_VERTEX = 0x17,
- SQ_CF_INST_KILL = 0x18,
-/* WHOLE_QUAD_MODE_bit = 1 << 30, */
-/* BARRIER_bit = 1 << 31, */
- SQ_VTX_WORD1_SEM = 0x00008dfc,
- SEMANTIC_ID_mask = 0xff << 0,
- SEMANTIC_ID_shift = 0,
- SQ_TEX_WORD0 = 0x00008dfc,
- TEX_INST_mask = 0x1f << 0,
- TEX_INST_shift = 0,
- SQ_TEX_INST_VTX_FETCH = 0x00,
- SQ_TEX_INST_VTX_SEMANTIC = 0x01,
- SQ_TEX_INST_LD = 0x03,
- SQ_TEX_INST_GET_TEXTURE_RESINFO = 0x04,
- SQ_TEX_INST_GET_NUMBER_OF_SAMPLES = 0x05,
- SQ_TEX_INST_GET_LOD = 0x06,
- SQ_TEX_INST_GET_GRADIENTS_H = 0x07,
- SQ_TEX_INST_GET_GRADIENTS_V = 0x08,
- SQ_TEX_INST_GET_LERP = 0x09,
- SQ_TEX_INST_RESERVED_10 = 0x0a,
- SQ_TEX_INST_SET_GRADIENTS_H = 0x0b,
- SQ_TEX_INST_SET_GRADIENTS_V = 0x0c,
- SQ_TEX_INST_PASS = 0x0d,
- X_Z_SET_INDEX_FOR_ARRAY_OF_CUBEMAPS = 0x0e,
- SQ_TEX_INST_SAMPLE = 0x10,
- SQ_TEX_INST_SAMPLE_L = 0x11,
- SQ_TEX_INST_SAMPLE_LB = 0x12,
- SQ_TEX_INST_SAMPLE_LZ = 0x13,
- SQ_TEX_INST_SAMPLE_G = 0x14,
- SQ_TEX_INST_SAMPLE_G_L = 0x15,
- SQ_TEX_INST_SAMPLE_G_LB = 0x16,
- SQ_TEX_INST_SAMPLE_G_LZ = 0x17,
- SQ_TEX_INST_SAMPLE_C = 0x18,
- SQ_TEX_INST_SAMPLE_C_L = 0x19,
- SQ_TEX_INST_SAMPLE_C_LB = 0x1a,
- SQ_TEX_INST_SAMPLE_C_LZ = 0x1b,
- SQ_TEX_INST_SAMPLE_C_G = 0x1c,
- SQ_TEX_INST_SAMPLE_C_G_L = 0x1d,
- SQ_TEX_INST_SAMPLE_C_G_LB = 0x1e,
- SQ_TEX_INST_SAMPLE_C_G_LZ = 0x1f,
- BC_FRAC_MODE_bit = 1 << 5,
-/* FETCH_WHOLE_QUAD_bit = 1 << 7, */
- RESOURCE_ID_mask = 0xff << 8,
- RESOURCE_ID_shift = 8,
-/* SRC_GPR_mask = 0x7f << 16, */
-/* SRC_GPR_shift = 16, */
-/* SRC_REL_bit = 1 << 23, */
- SQ_TEX_WORD0__ALT_CONST_bit = 1 << 24,
- SQ_VTX_WORD1_GPR = 0x00008dfc,
- SQ_VTX_WORD1_GPR__DST_GPR_mask = 0x7f << 0,
- SQ_VTX_WORD1_GPR__DST_GPR_shift = 0,
- SQ_VTX_WORD1_GPR__DST_REL_bit = 1 << 7,
- SQ_ALU_WORD0 = 0x00008dfc,
- SRC0_SEL_mask = 0x1ff << 0,
- SRC0_SEL_shift = 0,
-/* SQ_ALU_SRC_0 = 0xf8, */
-/* SQ_ALU_SRC_1 = 0xf9, */
-/* SQ_ALU_SRC_1_INT = 0xfa, */
-/* SQ_ALU_SRC_M_1_INT = 0xfb, */
-/* SQ_ALU_SRC_0_5 = 0xfc, */
-/* SQ_ALU_SRC_LITERAL = 0xfd, */
-/* SQ_ALU_SRC_PV = 0xfe, */
-/* SQ_ALU_SRC_PS = 0xff, */
- SRC0_REL_bit = 1 << 9,
- SRC0_CHAN_mask = 0x03 << 10,
- SRC0_CHAN_shift = 10,
-/* SQ_CHAN_X = 0x00, */
-/* SQ_CHAN_Y = 0x01, */
-/* SQ_CHAN_Z = 0x02, */
-/* SQ_CHAN_W = 0x03, */
- SRC0_NEG_bit = 1 << 12,
- SRC1_SEL_mask = 0x1ff << 13,
- SRC1_SEL_shift = 13,
-/* SQ_ALU_SRC_0 = 0xf8, */
-/* SQ_ALU_SRC_1 = 0xf9, */
-/* SQ_ALU_SRC_1_INT = 0xfa, */
-/* SQ_ALU_SRC_M_1_INT = 0xfb, */
-/* SQ_ALU_SRC_0_5 = 0xfc, */
-/* SQ_ALU_SRC_LITERAL = 0xfd, */
-/* SQ_ALU_SRC_PV = 0xfe, */
-/* SQ_ALU_SRC_PS = 0xff, */
- SRC1_REL_bit = 1 << 22,
- SRC1_CHAN_mask = 0x03 << 23,
- SRC1_CHAN_shift = 23,
-/* SQ_CHAN_X = 0x00, */
-/* SQ_CHAN_Y = 0x01, */
-/* SQ_CHAN_Z = 0x02, */
-/* SQ_CHAN_W = 0x03, */
- SRC1_NEG_bit = 1 << 25,
- INDEX_MODE_mask = 0x07 << 26,
- INDEX_MODE_shift = 26,
- SQ_INDEX_AR_X = 0x00,
- SQ_INDEX_AR_Y = 0x01,
- SQ_INDEX_AR_Z = 0x02,
- SQ_INDEX_AR_W = 0x03,
- SQ_INDEX_LOOP = 0x04,
- PRED_SEL_mask = 0x03 << 29,
- PRED_SEL_shift = 29,
- SQ_PRED_SEL_OFF = 0x00,
- SQ_PRED_SEL_ZERO = 0x02,
- SQ_PRED_SEL_ONE = 0x03,
- LAST_bit = 1 << 31,
- SX_EXPORT_BUFFER_SIZES = 0x0000900c,
- COLOR_BUFFER_SIZE_mask = 0xff << 0,
- COLOR_BUFFER_SIZE_shift = 0,
- POSITION_BUFFER_SIZE_mask = 0xff << 8,
- POSITION_BUFFER_SIZE_shift = 8,
- SMX_BUFFER_SIZE_mask = 0xff << 16,
- SMX_BUFFER_SIZE_shift = 16,
- SX_MEMORY_EXPORT_BASE = 0x00009010,
- SX_MEMORY_EXPORT_SIZE = 0x00009014,
- SPI_CONFIG_CNTL = 0x00009100,
- GPR_WRITE_PRIORITY_mask = 0x1f << 0,
- GPR_WRITE_PRIORITY_shift = 0,
- X_PRIORITY_ORDER = 0x00,
- X_PRIORITY_ORDER_VS = 0x01,
- DISABLE_INTERP_1_bit = 1 << 5,
- DEBUG_THREAD_TYPE_SEL_mask = 0x03 << 6,
- DEBUG_THREAD_TYPE_SEL_shift = 6,
- DEBUG_GROUP_SEL_mask = 0x1f << 8,
- DEBUG_GROUP_SEL_shift = 8,
- DEBUG_GRBM_OVERRIDE_bit = 1 << 13,
- SPI_CONFIG_CNTL_1 = 0x0000913c,
- VTX_DONE_DELAY_mask = 0x0f << 0,
- VTX_DONE_DELAY_shift = 0,
- X_DELAY_10_CLKS = 0x00,
- X_DELAY_11_CLKS = 0x01,
- X_DELAY_12_CLKS = 0x02,
- X_DELAY_13_CLKS = 0x03,
- X_DELAY_14_CLKS = 0x04,
- X_DELAY_15_CLKS = 0x05,
- X_DELAY_16_CLKS = 0x06,
- X_DELAY_17_CLKS = 0x07,
- X_DELAY_2_CLKS = 0x08,
- X_DELAY_3_CLKS = 0x09,
- X_DELAY_4_CLKS = 0x0a,
- X_DELAY_5_CLKS = 0x0b,
- X_DELAY_6_CLKS = 0x0c,
- X_DELAY_7_CLKS = 0x0d,
- X_DELAY_8_CLKS = 0x0e,
- X_DELAY_9_CLKS = 0x0f,
- INTERP_ONE_PRIM_PER_ROW_bit = 1 << 4,
- TD_FILTER4 = 0x00009400,
- WEIGHT_1_mask = 0x7ff << 0,
- WEIGHT_1_shift = 0,
- WEIGHT_0_mask = 0x7ff << 11,
- WEIGHT_0_shift = 11,
- WEIGHT_PAIR_bit = 1 << 22,
- PHASE_mask = 0x0f << 23,
- PHASE_shift = 23,
- DIRECTION_bit = 1 << 27,
- TD_FILTER4_1 = 0x00009404,
- TD_FILTER4_1_num = 35,
-/* WEIGHT_1_mask = 0x7ff << 0, */
-/* WEIGHT_1_shift = 0, */
-/* WEIGHT_0_mask = 0x7ff << 11, */
-/* WEIGHT_0_shift = 11, */
- TD_CNTL = 0x00009490,
- SYNC_PHASE_SH_mask = 0x03 << 0,
- SYNC_PHASE_SH_shift = 0,
- SYNC_PHASE_VC_SMX_mask = 0x03 << 4,
- SYNC_PHASE_VC_SMX_shift = 4,
- TD0_CNTL = 0x00009494,
- TD0_CNTL_num = 4,
- ID_OVERRIDE_mask = 0x03 << 28,
- ID_OVERRIDE_shift = 28,
- TD0_STATUS = 0x000094a4,
- TD0_STATUS_num = 4,
- BUSY_bit = 1 << 31,
- TA_CNTL = 0x00009504,
- GRADIENT_CREDIT_mask = 0x1f << 0,
- GRADIENT_CREDIT_shift = 0,
- WALKER_CREDIT_mask = 0x1f << 8,
- WALKER_CREDIT_shift = 8,
- ALIGNER_CREDIT_mask = 0x1f << 16,
- ALIGNER_CREDIT_shift = 16,
- TD_FIFO_CREDIT_mask = 0x3ff << 22,
- TD_FIFO_CREDIT_shift = 22,
- TA_CNTL_AUX = 0x00009508,
- DISABLE_CUBE_WRAP_bit = 1 << 0,
- SYNC_GRADIENT_bit = 1 << 24,
- SYNC_WALKER_bit = 1 << 25,
- SYNC_ALIGNER_bit = 1 << 26,
- BILINEAR_PRECISION_bit = 1 << 31,
- TA0_CNTL = 0x00009510,
-/* ID_OVERRIDE_mask = 0x03 << 28, */
-/* ID_OVERRIDE_shift = 28, */
- TA1_CNTL = 0x00009514,
-/* ID_OVERRIDE_mask = 0x03 << 28, */
-/* ID_OVERRIDE_shift = 28, */
- TA2_CNTL = 0x00009518,
-/* ID_OVERRIDE_mask = 0x03 << 28, */
-/* ID_OVERRIDE_shift = 28, */
- TA3_CNTL = 0x0000951c,
-/* ID_OVERRIDE_mask = 0x03 << 28, */
-/* ID_OVERRIDE_shift = 28, */
- TA0_STATUS = 0x00009520,
- FG_PFIFO_EMPTYB_bit = 1 << 12,
- FG_LFIFO_EMPTYB_bit = 1 << 13,
- FG_SFIFO_EMPTYB_bit = 1 << 14,
- FL_PFIFO_EMPTYB_bit = 1 << 16,
- FL_LFIFO_EMPTYB_bit = 1 << 17,
- FL_SFIFO_EMPTYB_bit = 1 << 18,
- FA_PFIFO_EMPTYB_bit = 1 << 20,
- FA_LFIFO_EMPTYB_bit = 1 << 21,
- FA_SFIFO_EMPTYB_bit = 1 << 22,
- IN_BUSY_bit = 1 << 24,
- FG_BUSY_bit = 1 << 25,
- FL_BUSY_bit = 1 << 27,
- TA_BUSY_bit = 1 << 28,
- FA_BUSY_bit = 1 << 29,
- AL_BUSY_bit = 1 << 30,
-/* BUSY_bit = 1 << 31, */
- TA1_STATUS = 0x00009524,
-/* FG_PFIFO_EMPTYB_bit = 1 << 12, */
-/* FG_LFIFO_EMPTYB_bit = 1 << 13, */
-/* FG_SFIFO_EMPTYB_bit = 1 << 14, */
-/* FL_PFIFO_EMPTYB_bit = 1 << 16, */
-/* FL_LFIFO_EMPTYB_bit = 1 << 17, */
-/* FL_SFIFO_EMPTYB_bit = 1 << 18, */
-/* FA_PFIFO_EMPTYB_bit = 1 << 20, */
-/* FA_LFIFO_EMPTYB_bit = 1 << 21, */
-/* FA_SFIFO_EMPTYB_bit = 1 << 22, */
-/* IN_BUSY_bit = 1 << 24, */
-/* FG_BUSY_bit = 1 << 25, */
-/* FL_BUSY_bit = 1 << 27, */
-/* TA_BUSY_bit = 1 << 28, */
-/* FA_BUSY_bit = 1 << 29, */
-/* AL_BUSY_bit = 1 << 30, */
-/* BUSY_bit = 1 << 31, */
- TA2_STATUS = 0x00009528,
-/* FG_PFIFO_EMPTYB_bit = 1 << 12, */
-/* FG_LFIFO_EMPTYB_bit = 1 << 13, */
-/* FG_SFIFO_EMPTYB_bit = 1 << 14, */
-/* FL_PFIFO_EMPTYB_bit = 1 << 16, */
-/* FL_LFIFO_EMPTYB_bit = 1 << 17, */
-/* FL_SFIFO_EMPTYB_bit = 1 << 18, */
-/* FA_PFIFO_EMPTYB_bit = 1 << 20, */
-/* FA_LFIFO_EMPTYB_bit = 1 << 21, */
-/* FA_SFIFO_EMPTYB_bit = 1 << 22, */
-/* IN_BUSY_bit = 1 << 24, */
-/* FG_BUSY_bit = 1 << 25, */
-/* FL_BUSY_bit = 1 << 27, */
-/* TA_BUSY_bit = 1 << 28, */
-/* FA_BUSY_bit = 1 << 29, */
-/* AL_BUSY_bit = 1 << 30, */
-/* BUSY_bit = 1 << 31, */
- TA3_STATUS = 0x0000952c,
-/* FG_PFIFO_EMPTYB_bit = 1 << 12, */
-/* FG_LFIFO_EMPTYB_bit = 1 << 13, */
-/* FG_SFIFO_EMPTYB_bit = 1 << 14, */
-/* FL_PFIFO_EMPTYB_bit = 1 << 16, */
-/* FL_LFIFO_EMPTYB_bit = 1 << 17, */
-/* FL_SFIFO_EMPTYB_bit = 1 << 18, */
-/* FA_PFIFO_EMPTYB_bit = 1 << 20, */
-/* FA_LFIFO_EMPTYB_bit = 1 << 21, */
-/* FA_SFIFO_EMPTYB_bit = 1 << 22, */
-/* IN_BUSY_bit = 1 << 24, */
-/* FG_BUSY_bit = 1 << 25, */
-/* FL_BUSY_bit = 1 << 27, */
-/* TA_BUSY_bit = 1 << 28, */
-/* FA_BUSY_bit = 1 << 29, */
-/* AL_BUSY_bit = 1 << 30, */
-/* BUSY_bit = 1 << 31, */
- TC_STATUS = 0x00009600,
- TC_BUSY_bit = 1 << 0,
- TC_INVALIDATE = 0x00009604,
- START_bit = 1 << 0,
- TC_CNTL = 0x00009608,
- FORCE_HIT_bit = 1 << 0,
- FORCE_MISS_bit = 1 << 1,
- L2_SIZE_mask = 0x0f << 5,
- L2_SIZE_shift = 5,
- _256K = 0x00,
- _224K = 0x01,
- _192K = 0x02,
- _160K = 0x03,
- _128K = 0x04,
- _96K = 0x05,
- _64K = 0x06,
- _32K = 0x07,
- L2_DISABLE_LATE_HIT_bit = 1 << 9,
- DISABLE_VERT_PERF_bit = 1 << 10,
- DISABLE_INVAL_BUSY_bit = 1 << 11,
- DISABLE_INVAL_SAME_SURFACE_bit = 1 << 12,
- PARTITION_MODE_mask = 0x03 << 13,
- PARTITION_MODE_shift = 13,
- X_VERTEX = 0x00,
- MISS_ARB_MODE_bit = 1 << 15,
- HIT_ARB_MODE_bit = 1 << 16,
- DISABLE_WRITE_DELAY_bit = 1 << 17,
- HIT_FIFO_DEPTH_bit = 1 << 18,
- VC_CNTL = 0x00009700,
- L2_INVALIDATE_bit = 1 << 0,
- RESERVED_bit = 1 << 1,
- CC_FORCE_MISS_bit = 1 << 2,
- MI_CHAN_SEL_mask = 0x03 << 3,
- MI_CHAN_SEL_shift = 3,
- X_MC0_USES_CH_0_1 = 0x00,
- X_MC0_USES_CH_0_3 = 0x01,
- X_VC_MC0_IS_ACTIVE = 0x02,
- X_VC_MC1_IS_DISABLED = 0x03,
- MI_STEER_DISABLE_bit = 1 << 5,
- MI_CREDIT_CTR_mask = 0x0f << 6,
- MI_CREDIT_CTR_shift = 6,
- MI_CREDIT_WE_bit = 1 << 10,
- MI_REQ_STALL_THLD_mask = 0x07 << 11,
- MI_REQ_STALL_THLD_shift = 11,
- X_LATENCY_EXCEEDS_399_CLOCKS = 0x00,
- X_LATENCY_EXCEEDS_415_CLOCKS = 0x01,
- X_LATENCY_EXCEEDS_431_CLOCKS = 0x02,
- X_LATENCY_EXCEEDS_447_CLOCKS = 0x03,
- X_LATENCY_EXCEEDS_463_CLOCKS = 0x04,
- X_LATENCY_EXCEEDS_479_CLOCKS = 0x05,
- X_LATENCY_EXCEEDS_495_CLOCKS = 0x06,
- X_LATENCY_EXCEEDS_511_CLOCKS = 0x07,
- VC_CNTL__MI_TIMESTAMP_RES_mask = 0x1f << 14,
- VC_CNTL__MI_TIMESTAMP_RES_shift = 14,
- X_1X_SYSTEM_CLOCK = 0x00,
- X_2X_SYSTEM_CLOCK = 0x01,
- X_4X_SYSTEM_CLOCK = 0x02,
- X_8X_SYSTEM_CLOCK = 0x03,
- X_16X_SYSTEM_CLOCK = 0x04,
- X_32X_SYSTEM_CLOCK = 0x05,
- X_64X_SYSTEM_CLOCK = 0x06,
- X_128X_SYSTEM_CLOCK = 0x07,
- X_256X_SYSTEM_CLOCK = 0x08,
- X_512X_SYSTEM_CLOCK = 0x09,
- X_1024X_SYSTEM_CLOCK = 0x0a,
- X_2048X_SYSTEM_CLOCK = 0x0b,
- X_4092X_SYSTEM_CLOCK = 0x0c,
- X_8192X_SYSTEM_CLOCK = 0x0d,
- X_16384X_SYSTEM_CLOCK = 0x0e,
- X_32768X_SYSTEM_CLOCK = 0x0f,
- VC_CNTL_STATUS = 0x00009704,
- RP_BUSY_bit = 1 << 0,
- RG_BUSY_bit = 1 << 1,
- VC_BUSY_bit = 1 << 2,
- CLAMP_DETECT_bit = 1 << 3,
- VC_CONFIG = 0x00009718,
- WRITE_DIS_bit = 1 << 0,
- GPR_DATA_PHASE_ADJ_mask = 0x07 << 1,
- GPR_DATA_PHASE_ADJ_shift = 1,
- X_LATENCY_BASE_0_CYCLES = 0x00,
- X_LATENCY_BASE_1_CYCLES = 0x01,
- X_LATENCY_BASE_2_CYCLES = 0x02,
- X_LATENCY_BASE_3_CYCLES = 0x03,
- TD_SIMD_SYNC_ADJ_mask = 0x07 << 4,
- TD_SIMD_SYNC_ADJ_shift = 4,
- X_0_CYCLES_DELAY = 0x00,
- X_1_CYCLES_DELAY = 0x01,
- X_2_CYCLES_DELAY = 0x02,
- X_3_CYCLES_DELAY = 0x03,
- X_4_CYCLES_DELAY = 0x04,
- X_5_CYCLES_DELAY = 0x05,
- X_6_CYCLES_DELAY = 0x06,
- X_7_CYCLES_DELAY = 0x07,
- SMX_DC_CTL0 = 0x0000a020,
- WR_GATHER_STREAM0_bit = 1 << 0,
- WR_GATHER_STREAM1_bit = 1 << 1,
- WR_GATHER_STREAM2_bit = 1 << 2,
- WR_GATHER_STREAM3_bit = 1 << 3,
- WR_GATHER_SCRATCH_bit = 1 << 4,
- WR_GATHER_REDUC_BUF_bit = 1 << 5,
- WR_GATHER_RING_BUF_bit = 1 << 6,
- WR_GATHER_F_BUF_bit = 1 << 7,
- DISABLE_CACHES_bit = 1 << 8,
- AUTO_FLUSH_INVAL_EN_bit = 1 << 10,
- AUTO_FLUSH_EN_bit = 1 << 11,
- AUTO_FLUSH_CNT_mask = 0xffff << 12,
- AUTO_FLUSH_CNT_shift = 12,
- MC_RD_STALL_FACTOR_mask = 0x03 << 28,
- MC_RD_STALL_FACTOR_shift = 28,
- MC_WR_STALL_FACTOR_mask = 0x03 << 30,
- MC_WR_STALL_FACTOR_shift = 30,
- SMX_DC_CTL1 = 0x0000a024,
- OP_FIFO_SKID_mask = 0x7f << 0,
- OP_FIFO_SKID_shift = 0,
- CACHE_LINE_SIZE_bit = 1 << 8,
- MULTI_FLUSH_MODE_bit = 1 << 9,
- MULTI_FLUSH_REQ_ABORT_IDX_FIFO_SKID_mask = 0x0f << 10,
- MULTI_FLUSH_REQ_ABORT_IDX_FIFO_SKID_shift = 10,
- DISABLE_WR_GATHER_RD_HIT_FORCE_EVICT_bit = 1 << 16,
- DISABLE_WR_GATHER_RD_HIT_COMP_VLDS_CHECK_bit = 1 << 17,
- DISABLE_FLUSH_ES_ALSO_INVALS_bit = 1 << 18,
- DISABLE_FLUSH_GS_ALSO_INVALS_bit = 1 << 19,
- SMX_DC_CTL2 = 0x0000a028,
- INVALIDATE_CACHES_bit = 1 << 0,
- CACHES_INVALID_bit = 1 << 1,
- CACHES_DIRTY_bit = 1 << 2,
- FLUSH_ALL_bit = 1 << 4,
- FLUSH_GS_THREADS_bit = 1 << 8,
- FLUSH_ES_THREADS_bit = 1 << 9,
- SMX_DC_MC_INTF_CTL = 0x0000a02c,
- MC_RD_REQ_CRED_mask = 0xff << 0,
- MC_RD_REQ_CRED_shift = 0,
- MC_WR_REQ_CRED_mask = 0xff << 16,
- MC_WR_REQ_CRED_shift = 16,
- TD_PS_SAMPLER0_BORDER_RED = 0x0000a400,
- TD_PS_SAMPLER0_BORDER_RED_num = 18,
- TD_PS_SAMPLER0_BORDER_RED_offset = 16,
- TD_PS_SAMPLER0_BORDER_GREEN = 0x0000a404,
- TD_PS_SAMPLER0_BORDER_GREEN_num = 18,
- TD_PS_SAMPLER0_BORDER_GREEN_offset = 16,
- TD_PS_SAMPLER0_BORDER_BLUE = 0x0000a408,
- TD_PS_SAMPLER0_BORDER_BLUE_num = 18,
- TD_PS_SAMPLER0_BORDER_BLUE_offset = 16,
- TD_PS_SAMPLER0_BORDER_ALPHA = 0x0000a40c,
- TD_PS_SAMPLER0_BORDER_ALPHA_num = 18,
- TD_PS_SAMPLER0_BORDER_ALPHA_offset = 16,
- TD_VS_SAMPLER0_BORDER_RED = 0x0000a600,
- TD_VS_SAMPLER0_BORDER_RED_num = 18,
- TD_VS_SAMPLER0_BORDER_RED_offset = 16,
- TD_VS_SAMPLER0_BORDER_GREEN = 0x0000a604,
- TD_VS_SAMPLER0_BORDER_GREEN_num = 18,
- TD_VS_SAMPLER0_BORDER_GREEN_offset = 16,
- TD_VS_SAMPLER0_BORDER_BLUE = 0x0000a608,
- TD_VS_SAMPLER0_BORDER_BLUE_num = 18,
- TD_VS_SAMPLER0_BORDER_BLUE_offset = 16,
- TD_VS_SAMPLER0_BORDER_ALPHA = 0x0000a60c,
- TD_VS_SAMPLER0_BORDER_ALPHA_num = 18,
- TD_VS_SAMPLER0_BORDER_ALPHA_offset = 16,
- TD_GS_SAMPLER0_BORDER_RED = 0x0000a800,
- TD_GS_SAMPLER0_BORDER_RED_num = 18,
- TD_GS_SAMPLER0_BORDER_RED_offset = 16,
- TD_GS_SAMPLER0_BORDER_GREEN = 0x0000a804,
- TD_GS_SAMPLER0_BORDER_GREEN_num = 18,
- TD_GS_SAMPLER0_BORDER_GREEN_offset = 16,
- TD_GS_SAMPLER0_BORDER_BLUE = 0x0000a808,
- TD_GS_SAMPLER0_BORDER_BLUE_num = 18,
- TD_GS_SAMPLER0_BORDER_BLUE_offset = 16,
- TD_GS_SAMPLER0_BORDER_ALPHA = 0x0000a80c,
- TD_GS_SAMPLER0_BORDER_ALPHA_num = 18,
- TD_GS_SAMPLER0_BORDER_ALPHA_offset = 16,
- TD_PS_SAMPLER0_CLEARTYPE_KERNEL = 0x0000aa00,
- TD_PS_SAMPLER0_CLEARTYPE_KERNEL_num = 18,
- TD_PS_SAMPLER0_CLEARTYPE_KERNEL__WIDTH_mask = 0x07 << 0,
- TD_PS_SAMPLER0_CLEARTYPE_KERNEL__WIDTH_shift = 0,
- TD_PS_SAMPLER0_CLEARTYPE_KERNEL__HEIGHT_mask = 0x07 << 3,
- TD_PS_SAMPLER0_CLEARTYPE_KERNEL__HEIGHT_shift = 3,
- DB_DEPTH_SIZE = 0x00028000,
- PITCH_TILE_MAX_mask = 0x3ff << 0,
- PITCH_TILE_MAX_shift = 0,
- SLICE_TILE_MAX_mask = 0xfffff << 10,
- SLICE_TILE_MAX_shift = 10,
- DB_DEPTH_VIEW = 0x00028004,
- SLICE_START_mask = 0x7ff << 0,
- SLICE_START_shift = 0,
- SLICE_MAX_mask = 0x7ff << 13,
- SLICE_MAX_shift = 13,
- DB_DEPTH_BASE = 0x0002800c,
- DB_DEPTH_INFO = 0x00028010,
- DB_DEPTH_INFO__FORMAT_mask = 0x07 << 0,
- DB_DEPTH_INFO__FORMAT_shift = 0,
- DEPTH_INVALID = 0x00,
- DEPTH_16 = 0x01,
- DEPTH_X8_24 = 0x02,
- DEPTH_8_24 = 0x03,
- DEPTH_X8_24_FLOAT = 0x04,
- DEPTH_8_24_FLOAT = 0x05,
- DEPTH_32_FLOAT = 0x06,
- DEPTH_X24_8_32_FLOAT = 0x07,
- DB_DEPTH_INFO__READ_SIZE_bit = 1 << 3,
- DB_DEPTH_INFO__ARRAY_MODE_mask = 0x0f << 15,
- DB_DEPTH_INFO__ARRAY_MODE_shift = 15,
- ARRAY_1D_TILED_THIN1 = 0x02,
- ARRAY_2D_TILED_THIN1 = 0x04,
- TILE_SURFACE_ENABLE_bit = 1 << 25,
- TILE_COMPACT_bit = 1 << 26,
- ZRANGE_PRECISION_bit = 1 << 31,
- DB_HTILE_DATA_BASE = 0x00028014,
- DB_STENCIL_CLEAR = 0x00028028,
- DB_STENCIL_CLEAR__CLEAR_mask = 0xff << 0,
- DB_STENCIL_CLEAR__CLEAR_shift = 0,
- MIN_mask = 0xff << 16,
- MIN_shift = 16,
- DB_DEPTH_CLEAR = 0x0002802c,
- PA_SC_SCREEN_SCISSOR_TL = 0x00028030,
- PA_SC_SCREEN_SCISSOR_TL__TL_X_mask = 0x7fff << 0,
- PA_SC_SCREEN_SCISSOR_TL__TL_X_shift = 0,
- PA_SC_SCREEN_SCISSOR_TL__TL_Y_mask = 0x7fff << 16,
- PA_SC_SCREEN_SCISSOR_TL__TL_Y_shift = 16,
- PA_SC_SCREEN_SCISSOR_BR = 0x00028034,
- PA_SC_SCREEN_SCISSOR_BR__BR_X_mask = 0x7fff << 0,
- PA_SC_SCREEN_SCISSOR_BR__BR_X_shift = 0,
- PA_SC_SCREEN_SCISSOR_BR__BR_Y_mask = 0x7fff << 16,
- PA_SC_SCREEN_SCISSOR_BR__BR_Y_shift = 16,
- CB_COLOR0_BASE = 0x00028040,
- CB_COLOR0_BASE_num = 8,
- CB_COLOR0_SIZE = 0x00028060,
- CB_COLOR0_SIZE_num = 8,
-/* PITCH_TILE_MAX_mask = 0x3ff << 0, */
-/* PITCH_TILE_MAX_shift = 0, */
-/* SLICE_TILE_MAX_mask = 0xfffff << 10, */
-/* SLICE_TILE_MAX_shift = 10, */
- CB_COLOR0_VIEW = 0x00028080,
- CB_COLOR0_VIEW_num = 8,
-/* SLICE_START_mask = 0x7ff << 0, */
-/* SLICE_START_shift = 0, */
-/* SLICE_MAX_mask = 0x7ff << 13, */
-/* SLICE_MAX_shift = 13, */
- CB_COLOR0_INFO = 0x000280a0,
- CB_COLOR0_INFO_num = 8,
- ENDIAN_mask = 0x03 << 0,
- ENDIAN_shift = 0,
- ENDIAN_NONE = 0x00,
- ENDIAN_8IN16 = 0x01,
- ENDIAN_8IN32 = 0x02,
- ENDIAN_8IN64 = 0x03,
- CB_COLOR0_INFO__FORMAT_mask = 0x3f << 2,
- CB_COLOR0_INFO__FORMAT_shift = 2,
- COLOR_INVALID = 0x00,
- COLOR_8 = 0x01,
- COLOR_4_4 = 0x02,
- COLOR_3_3_2 = 0x03,
- COLOR_16 = 0x05,
- COLOR_16_FLOAT = 0x06,
- COLOR_8_8 = 0x07,
- COLOR_5_6_5 = 0x08,
- COLOR_6_5_5 = 0x09,
- COLOR_1_5_5_5 = 0x0a,
- COLOR_4_4_4_4 = 0x0b,
- COLOR_5_5_5_1 = 0x0c,
- COLOR_32 = 0x0d,
- COLOR_32_FLOAT = 0x0e,
- COLOR_16_16 = 0x0f,
- COLOR_16_16_FLOAT = 0x10,
- COLOR_8_24 = 0x11,
- COLOR_8_24_FLOAT = 0x12,
- COLOR_24_8 = 0x13,
- COLOR_24_8_FLOAT = 0x14,
- COLOR_10_11_11 = 0x15,
- COLOR_10_11_11_FLOAT = 0x16,
- COLOR_11_11_10 = 0x17,
- COLOR_11_11_10_FLOAT = 0x18,
- COLOR_2_10_10_10 = 0x19,
- COLOR_8_8_8_8 = 0x1a,
- COLOR_10_10_10_2 = 0x1b,
- COLOR_X24_8_32_FLOAT = 0x1c,
- COLOR_32_32 = 0x1d,
- COLOR_32_32_FLOAT = 0x1e,
- COLOR_16_16_16_16 = 0x1f,
- COLOR_16_16_16_16_FLOAT = 0x20,
- COLOR_32_32_32_32 = 0x22,
- COLOR_32_32_32_32_FLOAT = 0x23,
- CB_COLOR0_INFO__ARRAY_MODE_mask = 0x0f << 8,
- CB_COLOR0_INFO__ARRAY_MODE_shift = 8,
- ARRAY_LINEAR_GENERAL = 0x00,
- ARRAY_LINEAR_ALIGNED = 0x01,
-/* ARRAY_1D_TILED_THIN1 = 0x02, */
-/* ARRAY_2D_TILED_THIN1 = 0x04, */
- NUMBER_TYPE_mask = 0x07 << 12,
- NUMBER_TYPE_shift = 12,
- NUMBER_UNORM = 0x00,
- NUMBER_SNORM = 0x01,
- NUMBER_USCALED = 0x02,
- NUMBER_SSCALED = 0x03,
- NUMBER_UINT = 0x04,
- NUMBER_SINT = 0x05,
- NUMBER_SRGB = 0x06,
- NUMBER_FLOAT = 0x07,
- CB_COLOR0_INFO__READ_SIZE_bit = 1 << 15,
- COMP_SWAP_mask = 0x03 << 16,
- COMP_SWAP_shift = 16,
- SWAP_STD = 0x00,
- SWAP_ALT = 0x01,
- SWAP_STD_REV = 0x02,
- SWAP_ALT_REV = 0x03,
- CB_COLOR0_INFO__TILE_MODE_mask = 0x03 << 18,
- CB_COLOR0_INFO__TILE_MODE_shift = 18,
- TILE_DISABLE = 0x00,
- TILE_CLEAR_ENABLE = 0x01,
- TILE_FRAG_ENABLE = 0x02,
- BLEND_CLAMP_bit = 1 << 20,
- CLEAR_COLOR_bit = 1 << 21,
- BLEND_BYPASS_bit = 1 << 22,
- BLEND_FLOAT32_bit = 1 << 23,
- SIMPLE_FLOAT_bit = 1 << 24,
- CB_COLOR0_INFO__ROUND_MODE_bit = 1 << 25,
-/* TILE_COMPACT_bit = 1 << 26, */
- SOURCE_FORMAT_bit = 1 << 27,
- CB_COLOR0_TILE = 0x000280c0,
- CB_COLOR0_TILE_num = 8,
- CB_COLOR0_FRAG = 0x000280e0,
- CB_COLOR0_FRAG_num = 8,
- CB_COLOR0_MASK = 0x00028100,
- CB_COLOR0_MASK_num = 8,
- CMASK_BLOCK_MAX_mask = 0xfff << 0,
- CMASK_BLOCK_MAX_shift = 0,
- FMASK_TILE_MAX_mask = 0xfffff << 12,
- FMASK_TILE_MAX_shift = 12,
- CB_CLEAR_RED = 0x00028120,
- CB_CLEAR_GREEN = 0x00028124,
- CB_CLEAR_BLUE = 0x00028128,
- CB_CLEAR_ALPHA = 0x0002812c,
- SQ_ALU_CONST_BUFFER_SIZE_PS_0 = 0x00028140,
- SQ_ALU_CONST_BUFFER_SIZE_PS_0_num = 16,
- SQ_ALU_CONST_BUFFER_SIZE_PS_0__DATA_mask = 0x1ff << 0,
- SQ_ALU_CONST_BUFFER_SIZE_PS_0__DATA_shift = 0,
- SQ_ALU_CONST_BUFFER_SIZE_VS_0 = 0x00028180,
- SQ_ALU_CONST_BUFFER_SIZE_VS_0_num = 16,
- SQ_ALU_CONST_BUFFER_SIZE_VS_0__DATA_mask = 0x1ff << 0,
- SQ_ALU_CONST_BUFFER_SIZE_VS_0__DATA_shift = 0,
- SQ_ALU_CONST_BUFFER_SIZE_GS_0 = 0x000281c0,
- SQ_ALU_CONST_BUFFER_SIZE_GS_0_num = 16,
- SQ_ALU_CONST_BUFFER_SIZE_GS_0__DATA_mask = 0x1ff << 0,
- SQ_ALU_CONST_BUFFER_SIZE_GS_0__DATA_shift = 0,
- PA_SC_WINDOW_OFFSET = 0x00028200,
- WINDOW_X_OFFSET_mask = 0x7fff << 0,
- WINDOW_X_OFFSET_shift = 0,
- WINDOW_Y_OFFSET_mask = 0x7fff << 16,
- WINDOW_Y_OFFSET_shift = 16,
- PA_SC_WINDOW_SCISSOR_TL = 0x00028204,
- PA_SC_WINDOW_SCISSOR_TL__TL_X_mask = 0x3fff << 0,
- PA_SC_WINDOW_SCISSOR_TL__TL_X_shift = 0,
- PA_SC_WINDOW_SCISSOR_TL__TL_Y_mask = 0x3fff << 16,
- PA_SC_WINDOW_SCISSOR_TL__TL_Y_shift = 16,
- WINDOW_OFFSET_DISABLE_bit = 1 << 31,
- PA_SC_WINDOW_SCISSOR_BR = 0x00028208,
- PA_SC_WINDOW_SCISSOR_BR__BR_X_mask = 0x3fff << 0,
- PA_SC_WINDOW_SCISSOR_BR__BR_X_shift = 0,
- PA_SC_WINDOW_SCISSOR_BR__BR_Y_mask = 0x3fff << 16,
- PA_SC_WINDOW_SCISSOR_BR__BR_Y_shift = 16,
- PA_SC_CLIPRECT_RULE = 0x0002820c,
- CLIP_RULE_mask = 0xffff << 0,
- CLIP_RULE_shift = 0,
- PA_SC_CLIPRECT_0_TL = 0x00028210,
- PA_SC_CLIPRECT_0_TL_num = 4,
- PA_SC_CLIPRECT_0_TL_offset = 8,
- PA_SC_CLIPRECT_0_TL__TL_X_mask = 0x3fff << 0,
- PA_SC_CLIPRECT_0_TL__TL_X_shift = 0,
- PA_SC_CLIPRECT_0_TL__TL_Y_mask = 0x3fff << 16,
- PA_SC_CLIPRECT_0_TL__TL_Y_shift = 16,
- PA_SC_CLIPRECT_0_BR = 0x00028214,
- PA_SC_CLIPRECT_0_BR_num = 4,
- PA_SC_CLIPRECT_0_BR_offset = 8,
- PA_SC_CLIPRECT_0_BR__BR_X_mask = 0x3fff << 0,
- PA_SC_CLIPRECT_0_BR__BR_X_shift = 0,
- PA_SC_CLIPRECT_0_BR__BR_Y_mask = 0x3fff << 16,
- PA_SC_CLIPRECT_0_BR__BR_Y_shift = 16,
- CB_TARGET_MASK = 0x00028238,
- TARGET0_ENABLE_mask = 0x0f << 0,
- TARGET0_ENABLE_shift = 0,
- TARGET1_ENABLE_mask = 0x0f << 4,
- TARGET1_ENABLE_shift = 4,
- TARGET2_ENABLE_mask = 0x0f << 8,
- TARGET2_ENABLE_shift = 8,
- TARGET3_ENABLE_mask = 0x0f << 12,
- TARGET3_ENABLE_shift = 12,
- TARGET4_ENABLE_mask = 0x0f << 16,
- TARGET4_ENABLE_shift = 16,
- TARGET5_ENABLE_mask = 0x0f << 20,
- TARGET5_ENABLE_shift = 20,
- TARGET6_ENABLE_mask = 0x0f << 24,
- TARGET6_ENABLE_shift = 24,
- TARGET7_ENABLE_mask = 0x0f << 28,
- TARGET7_ENABLE_shift = 28,
- CB_SHADER_MASK = 0x0002823c,
- OUTPUT0_ENABLE_mask = 0x0f << 0,
- OUTPUT0_ENABLE_shift = 0,
- OUTPUT1_ENABLE_mask = 0x0f << 4,
- OUTPUT1_ENABLE_shift = 4,
- OUTPUT2_ENABLE_mask = 0x0f << 8,
- OUTPUT2_ENABLE_shift = 8,
- OUTPUT3_ENABLE_mask = 0x0f << 12,
- OUTPUT3_ENABLE_shift = 12,
- OUTPUT4_ENABLE_mask = 0x0f << 16,
- OUTPUT4_ENABLE_shift = 16,
- OUTPUT5_ENABLE_mask = 0x0f << 20,
- OUTPUT5_ENABLE_shift = 20,
- OUTPUT6_ENABLE_mask = 0x0f << 24,
- OUTPUT6_ENABLE_shift = 24,
- OUTPUT7_ENABLE_mask = 0x0f << 28,
- OUTPUT7_ENABLE_shift = 28,
- PA_SC_GENERIC_SCISSOR_TL = 0x00028240,
- PA_SC_GENERIC_SCISSOR_TL__TL_X_mask = 0x3fff << 0,
- PA_SC_GENERIC_SCISSOR_TL__TL_X_shift = 0,
- PA_SC_GENERIC_SCISSOR_TL__TL_Y_mask = 0x3fff << 16,
- PA_SC_GENERIC_SCISSOR_TL__TL_Y_shift = 16,
-/* WINDOW_OFFSET_DISABLE_bit = 1 << 31, */
- PA_SC_GENERIC_SCISSOR_BR = 0x00028244,
- PA_SC_GENERIC_SCISSOR_BR__BR_X_mask = 0x3fff << 0,
- PA_SC_GENERIC_SCISSOR_BR__BR_X_shift = 0,
- PA_SC_GENERIC_SCISSOR_BR__BR_Y_mask = 0x3fff << 16,
- PA_SC_GENERIC_SCISSOR_BR__BR_Y_shift = 16,
- PA_SC_VPORT_SCISSOR_0_TL = 0x00028250,
- PA_SC_VPORT_SCISSOR_0_TL_num = 16,
- PA_SC_VPORT_SCISSOR_0_TL_offset = 8,
- PA_SC_VPORT_SCISSOR_0_TL__TL_X_mask = 0x3fff << 0,
- PA_SC_VPORT_SCISSOR_0_TL__TL_X_shift = 0,
- PA_SC_VPORT_SCISSOR_0_TL__TL_Y_mask = 0x3fff << 16,
- PA_SC_VPORT_SCISSOR_0_TL__TL_Y_shift = 16,
-/* WINDOW_OFFSET_DISABLE_bit = 1 << 31, */
- PA_SC_VPORT_SCISSOR_0_BR = 0x00028254,
- PA_SC_VPORT_SCISSOR_0_BR_num = 16,
- PA_SC_VPORT_SCISSOR_0_BR_offset = 8,
- PA_SC_VPORT_SCISSOR_0_BR__BR_X_mask = 0x3fff << 0,
- PA_SC_VPORT_SCISSOR_0_BR__BR_X_shift = 0,
- PA_SC_VPORT_SCISSOR_0_BR__BR_Y_mask = 0x3fff << 16,
- PA_SC_VPORT_SCISSOR_0_BR__BR_Y_shift = 16,
- PA_SC_VPORT_ZMIN_0 = 0x000282d0,
- PA_SC_VPORT_ZMIN_0_num = 16,
- PA_SC_VPORT_ZMIN_0_offset = 8,
- PA_SC_VPORT_ZMAX_0 = 0x000282d4,
- PA_SC_VPORT_ZMAX_0_num = 16,
- PA_SC_VPORT_ZMAX_0_offset = 8,
- SX_MISC = 0x00028350,
- MULTIPASS_bit = 1 << 0,
- SQ_VTX_SEMANTIC_0 = 0x00028380,
- SQ_VTX_SEMANTIC_0_num = 32,
-/* SEMANTIC_ID_mask = 0xff << 0, */
-/* SEMANTIC_ID_shift = 0, */
- VGT_MAX_VTX_INDX = 0x00028400,
- VGT_MIN_VTX_INDX = 0x00028404,
- VGT_INDX_OFFSET = 0x00028408,
- VGT_MULTI_PRIM_IB_RESET_INDX = 0x0002840c,
- SX_ALPHA_TEST_CONTROL = 0x00028410,
- ALPHA_FUNC_mask = 0x07 << 0,
- ALPHA_FUNC_shift = 0,
- REF_NEVER = 0x00,
- REF_LESS = 0x01,
- REF_EQUAL = 0x02,
- REF_LEQUAL = 0x03,
- REF_GREATER = 0x04,
- REF_NOTEQUAL = 0x05,
- REF_GEQUAL = 0x06,
- REF_ALWAYS = 0x07,
- ALPHA_TEST_ENABLE_bit = 1 << 3,
- ALPHA_TEST_BYPASS_bit = 1 << 8,
- CB_BLEND_RED = 0x00028414,
- CB_BLEND_GREEN = 0x00028418,
- CB_BLEND_BLUE = 0x0002841c,
- CB_BLEND_ALPHA = 0x00028420,
- CB_FOG_RED = 0x00028424,
- CB_FOG_GREEN = 0x00028428,
- CB_FOG_BLUE = 0x0002842c,
- DB_STENCILREFMASK = 0x00028430,
- STENCILREF_mask = 0xff << 0,
- STENCILREF_shift = 0,
- STENCILMASK_mask = 0xff << 8,
- STENCILMASK_shift = 8,
- STENCILWRITEMASK_mask = 0xff << 16,
- STENCILWRITEMASK_shift = 16,
- DB_STENCILREFMASK_BF = 0x00028434,
- STENCILREF_BF_mask = 0xff << 0,
- STENCILREF_BF_shift = 0,
- STENCILMASK_BF_mask = 0xff << 8,
- STENCILMASK_BF_shift = 8,
- STENCILWRITEMASK_BF_mask = 0xff << 16,
- STENCILWRITEMASK_BF_shift = 16,
- SX_ALPHA_REF = 0x00028438,
- PA_CL_VPORT_XSCALE_0 = 0x0002843c,
- PA_CL_VPORT_XSCALE_0_num = 16,
- PA_CL_VPORT_XSCALE_0_offset = 24,
- PA_CL_VPORT_XOFFSET_0 = 0x00028440,
- PA_CL_VPORT_XOFFSET_0_num = 16,
- PA_CL_VPORT_XOFFSET_0_offset = 24,
- PA_CL_VPORT_YSCALE_0 = 0x00028444,
- PA_CL_VPORT_YSCALE_0_num = 16,
- PA_CL_VPORT_YSCALE_0_offset = 24,
- PA_CL_VPORT_YOFFSET_0 = 0x00028448,
- PA_CL_VPORT_YOFFSET_0_num = 16,
- PA_CL_VPORT_YOFFSET_0_offset = 24,
- PA_CL_VPORT_ZSCALE_0 = 0x0002844c,
- PA_CL_VPORT_ZSCALE_0_num = 16,
- PA_CL_VPORT_ZSCALE_0_offset = 24,
- PA_CL_VPORT_ZOFFSET_0 = 0x00028450,
- PA_CL_VPORT_ZOFFSET_0_num = 16,
- PA_CL_VPORT_ZOFFSET_0_offset = 24,
- SPI_VS_OUT_ID_0 = 0x00028614,
- SPI_VS_OUT_ID_0_num = 10,
- SEMANTIC_0_mask = 0xff << 0,
- SEMANTIC_0_shift = 0,
- SEMANTIC_1_mask = 0xff << 8,
- SEMANTIC_1_shift = 8,
- SEMANTIC_2_mask = 0xff << 16,
- SEMANTIC_2_shift = 16,
- SEMANTIC_3_mask = 0xff << 24,
- SEMANTIC_3_shift = 24,
- SPI_PS_INPUT_CNTL_0 = 0x00028644,
- SPI_PS_INPUT_CNTL_0_num = 32,
- SEMANTIC_mask = 0xff << 0,
- SEMANTIC_shift = 0,
- DEFAULT_VAL_mask = 0x03 << 8,
- DEFAULT_VAL_shift = 8,
- X_0_0F = 0x00,
- FLAT_SHADE_bit = 1 << 10,
- SEL_CENTROID_bit = 1 << 11,
- SEL_LINEAR_bit = 1 << 12,
- CYL_WRAP_mask = 0x0f << 13,
- CYL_WRAP_shift = 13,
- PT_SPRITE_TEX_bit = 1 << 17,
- SEL_SAMPLE_bit = 1 << 18,
- SPI_VS_OUT_CONFIG = 0x000286c4,
- VS_PER_COMPONENT_bit = 1 << 0,
- VS_EXPORT_COUNT_mask = 0x1f << 1,
- VS_EXPORT_COUNT_shift = 1,
- VS_EXPORTS_FOG_bit = 1 << 8,
- VS_OUT_FOG_VEC_ADDR_mask = 0x1f << 9,
- VS_OUT_FOG_VEC_ADDR_shift = 9,
- SPI_PS_IN_CONTROL_0 = 0x000286cc,
- NUM_INTERP_mask = 0x3f << 0,
- NUM_INTERP_shift = 0,
- POSITION_ENA_bit = 1 << 8,
- POSITION_CENTROID_bit = 1 << 9,
- POSITION_ADDR_mask = 0x1f << 10,
- POSITION_ADDR_shift = 10,
- PARAM_GEN_mask = 0x0f << 15,
- PARAM_GEN_shift = 15,
- PARAM_GEN_ADDR_mask = 0x7f << 19,
- PARAM_GEN_ADDR_shift = 19,
- BARYC_SAMPLE_CNTL_mask = 0x03 << 26,
- BARYC_SAMPLE_CNTL_shift = 26,
- CENTROIDS_ONLY = 0x00,
- CENTERS_ONLY = 0x01,
- CENTROIDS_AND_CENTERS = 0x02,
- UNDEF = 0x03,
- PERSP_GRADIENT_ENA_bit = 1 << 28,
- LINEAR_GRADIENT_ENA_bit = 1 << 29,
- POSITION_SAMPLE_bit = 1 << 30,
- BARYC_AT_SAMPLE_ENA_bit = 1 << 31,
- SPI_PS_IN_CONTROL_1 = 0x000286d0,
- GEN_INDEX_PIX_bit = 1 << 0,
- GEN_INDEX_PIX_ADDR_mask = 0x7f << 1,
- GEN_INDEX_PIX_ADDR_shift = 1,
- FRONT_FACE_ENA_bit = 1 << 8,
- FRONT_FACE_CHAN_mask = 0x03 << 9,
- FRONT_FACE_CHAN_shift = 9,
- FRONT_FACE_ALL_BITS_bit = 1 << 11,
- FRONT_FACE_ADDR_mask = 0x1f << 12,
- FRONT_FACE_ADDR_shift = 12,
- FOG_ADDR_mask = 0x7f << 17,
- FOG_ADDR_shift = 17,
- FIXED_PT_POSITION_ENA_bit = 1 << 24,
- FIXED_PT_POSITION_ADDR_mask = 0x1f << 25,
- FIXED_PT_POSITION_ADDR_shift = 25,
- SPI_INTERP_CONTROL_0 = 0x000286d4,
- FLAT_SHADE_ENA_bit = 1 << 0,
- PNT_SPRITE_ENA_bit = 1 << 1,
- PNT_SPRITE_OVRD_X_mask = 0x07 << 2,
- PNT_SPRITE_OVRD_X_shift = 2,
- SPI_PNT_SPRITE_SEL_0 = 0x00,
- SPI_PNT_SPRITE_SEL_1 = 0x01,
- SPI_PNT_SPRITE_SEL_S = 0x02,
- SPI_PNT_SPRITE_SEL_T = 0x03,
- SPI_PNT_SPRITE_SEL_NONE = 0x04,
- PNT_SPRITE_OVRD_Y_mask = 0x07 << 5,
- PNT_SPRITE_OVRD_Y_shift = 5,
-/* SPI_PNT_SPRITE_SEL_0 = 0x00, */
-/* SPI_PNT_SPRITE_SEL_1 = 0x01, */
-/* SPI_PNT_SPRITE_SEL_S = 0x02, */
-/* SPI_PNT_SPRITE_SEL_T = 0x03, */
-/* SPI_PNT_SPRITE_SEL_NONE = 0x04, */
- PNT_SPRITE_OVRD_Z_mask = 0x07 << 8,
- PNT_SPRITE_OVRD_Z_shift = 8,
-/* SPI_PNT_SPRITE_SEL_0 = 0x00, */
-/* SPI_PNT_SPRITE_SEL_1 = 0x01, */
-/* SPI_PNT_SPRITE_SEL_S = 0x02, */
-/* SPI_PNT_SPRITE_SEL_T = 0x03, */
-/* SPI_PNT_SPRITE_SEL_NONE = 0x04, */
- PNT_SPRITE_OVRD_W_mask = 0x07 << 11,
- PNT_SPRITE_OVRD_W_shift = 11,
-/* SPI_PNT_SPRITE_SEL_0 = 0x00, */
-/* SPI_PNT_SPRITE_SEL_1 = 0x01, */
-/* SPI_PNT_SPRITE_SEL_S = 0x02, */
-/* SPI_PNT_SPRITE_SEL_T = 0x03, */
-/* SPI_PNT_SPRITE_SEL_NONE = 0x04, */
- PNT_SPRITE_TOP_1_bit = 1 << 14,
- SPI_INPUT_Z = 0x000286d8,
- PROVIDE_Z_TO_SPI_bit = 1 << 0,
- SPI_FOG_CNTL = 0x000286dc,
- PASS_FOG_THROUGH_PS_bit = 1 << 0,
- PIXEL_FOG_FUNC_mask = 0x03 << 1,
- PIXEL_FOG_FUNC_shift = 1,
- SPI_FOG_NONE = 0x00,
- SPI_FOG_EXP = 0x01,
- SPI_FOG_EXP2 = 0x02,
- SPI_FOG_LINEAR = 0x03,
- PIXEL_FOG_SRC_SEL_bit = 1 << 3,
- VS_FOG_CLAMP_DISABLE_bit = 1 << 4,
- SPI_FOG_FUNC_SCALE = 0x000286e0,
- SPI_FOG_FUNC_BIAS = 0x000286e4,
- CB_BLEND0_CONTROL = 0x00028780,
- CB_BLEND0_CONTROL_num = 8,
- COLOR_SRCBLEND_mask = 0x1f << 0,
- COLOR_SRCBLEND_shift = 0,
- COLOR_COMB_FCN_mask = 0x07 << 5,
- COLOR_COMB_FCN_shift = 5,
- COLOR_DESTBLEND_mask = 0x1f << 8,
- COLOR_DESTBLEND_shift = 8,
- OPACITY_WEIGHT_bit = 1 << 13,
- ALPHA_SRCBLEND_mask = 0x1f << 16,
- ALPHA_SRCBLEND_shift = 16,
- ALPHA_COMB_FCN_mask = 0x07 << 21,
- ALPHA_COMB_FCN_shift = 21,
- ALPHA_DESTBLEND_mask = 0x1f << 24,
- ALPHA_DESTBLEND_shift = 24,
- SEPARATE_ALPHA_BLEND_bit = 1 << 29,
- VGT_DMA_BASE_HI = 0x000287e4,
- VGT_DMA_BASE_HI__BASE_ADDR_mask = 0xff << 0,
- VGT_DMA_BASE_HI__BASE_ADDR_shift = 0,
- VGT_DMA_BASE = 0x000287e8,
- VGT_DRAW_INITIATOR = 0x000287f0,
- SOURCE_SELECT_mask = 0x03 << 0,
- SOURCE_SELECT_shift = 0,
- DI_SRC_SEL_DMA = 0x00,
- DI_SRC_SEL_IMMEDIATE = 0x01,
- DI_SRC_SEL_AUTO_INDEX = 0x02,
- DI_SRC_SEL_RESERVED = 0x03,
- MAJOR_MODE_mask = 0x03 << 2,
- MAJOR_MODE_shift = 2,
- DI_MAJOR_MODE_0 = 0x00,
- DI_MAJOR_MODE_1 = 0x01,
- SPRITE_EN_bit = 1 << 4,
- NOT_EOP_bit = 1 << 5,
- USE_OPAQUE_bit = 1 << 6,
- VGT_IMMED_DATA = 0x000287f4,
- VGT_EVENT_ADDRESS_REG = 0x000287f8,
- ADDRESS_LOW_mask = 0xfffffff << 0,
- ADDRESS_LOW_shift = 0,
- DB_DEPTH_CONTROL = 0x00028800,
- STENCIL_ENABLE_bit = 1 << 0,
- Z_ENABLE_bit = 1 << 1,
- Z_WRITE_ENABLE_bit = 1 << 2,
- ZFUNC_mask = 0x07 << 4,
- ZFUNC_shift = 4,
- FRAG_NEVER = 0x00,
- FRAG_LESS = 0x01,
- FRAG_EQUAL = 0x02,
- FRAG_LEQUAL = 0x03,
- FRAG_GREATER = 0x04,
- FRAG_NOTEQUAL = 0x05,
- FRAG_GEQUAL = 0x06,
- FRAG_ALWAYS = 0x07,
- BACKFACE_ENABLE_bit = 1 << 7,
- STENCILFUNC_mask = 0x07 << 8,
- STENCILFUNC_shift = 8,
-/* REF_NEVER = 0x00, */
-/* REF_LESS = 0x01, */
-/* REF_EQUAL = 0x02, */
-/* REF_LEQUAL = 0x03, */
-/* REF_GREATER = 0x04, */
-/* REF_NOTEQUAL = 0x05, */
-/* REF_GEQUAL = 0x06, */
-/* REF_ALWAYS = 0x07, */
- STENCILFAIL_mask = 0x07 << 11,
- STENCILFAIL_shift = 11,
- STENCIL_KEEP = 0x00,
- STENCIL_ZERO = 0x01,
- STENCIL_REPLACE = 0x02,
- STENCIL_INCR_CLAMP = 0x03,
- STENCIL_DECR_CLAMP = 0x04,
- STENCIL_INVERT = 0x05,
- STENCIL_INCR_WRAP = 0x06,
- STENCIL_DECR_WRAP = 0x07,
- STENCILZPASS_mask = 0x07 << 14,
- STENCILZPASS_shift = 14,
-/* STENCIL_KEEP = 0x00, */
-/* STENCIL_ZERO = 0x01, */
-/* STENCIL_REPLACE = 0x02, */
-/* STENCIL_INCR_CLAMP = 0x03, */
-/* STENCIL_DECR_CLAMP = 0x04, */
-/* STENCIL_INVERT = 0x05, */
-/* STENCIL_INCR_WRAP = 0x06, */
-/* STENCIL_DECR_WRAP = 0x07, */
- STENCILZFAIL_mask = 0x07 << 17,
- STENCILZFAIL_shift = 17,
-/* STENCIL_KEEP = 0x00, */
-/* STENCIL_ZERO = 0x01, */
-/* STENCIL_REPLACE = 0x02, */
-/* STENCIL_INCR_CLAMP = 0x03, */
-/* STENCIL_DECR_CLAMP = 0x04, */
-/* STENCIL_INVERT = 0x05, */
-/* STENCIL_INCR_WRAP = 0x06, */
-/* STENCIL_DECR_WRAP = 0x07, */
- STENCILFUNC_BF_mask = 0x07 << 20,
- STENCILFUNC_BF_shift = 20,
-/* REF_NEVER = 0x00, */
-/* REF_LESS = 0x01, */
-/* REF_EQUAL = 0x02, */
-/* REF_LEQUAL = 0x03, */
-/* REF_GREATER = 0x04, */
-/* REF_NOTEQUAL = 0x05, */
-/* REF_GEQUAL = 0x06, */
-/* REF_ALWAYS = 0x07, */
- STENCILFAIL_BF_mask = 0x07 << 23,
- STENCILFAIL_BF_shift = 23,
-/* STENCIL_KEEP = 0x00, */
-/* STENCIL_ZERO = 0x01, */
-/* STENCIL_REPLACE = 0x02, */
-/* STENCIL_INCR_CLAMP = 0x03, */
-/* STENCIL_DECR_CLAMP = 0x04, */
-/* STENCIL_INVERT = 0x05, */
-/* STENCIL_INCR_WRAP = 0x06, */
-/* STENCIL_DECR_WRAP = 0x07, */
- STENCILZPASS_BF_mask = 0x07 << 26,
- STENCILZPASS_BF_shift = 26,
-/* STENCIL_KEEP = 0x00, */
-/* STENCIL_ZERO = 0x01, */
-/* STENCIL_REPLACE = 0x02, */
-/* STENCIL_INCR_CLAMP = 0x03, */
-/* STENCIL_DECR_CLAMP = 0x04, */
-/* STENCIL_INVERT = 0x05, */
-/* STENCIL_INCR_WRAP = 0x06, */
-/* STENCIL_DECR_WRAP = 0x07, */
- STENCILZFAIL_BF_mask = 0x07 << 29,
- STENCILZFAIL_BF_shift = 29,
-/* STENCIL_KEEP = 0x00, */
-/* STENCIL_ZERO = 0x01, */
-/* STENCIL_REPLACE = 0x02, */
-/* STENCIL_INCR_CLAMP = 0x03, */
-/* STENCIL_DECR_CLAMP = 0x04, */
-/* STENCIL_INVERT = 0x05, */
-/* STENCIL_INCR_WRAP = 0x06, */
-/* STENCIL_DECR_WRAP = 0x07, */
- CB_BLEND_CONTROL = 0x00028804,
-/* COLOR_SRCBLEND_mask = 0x1f << 0, */
-/* COLOR_SRCBLEND_shift = 0, */
- BLEND_ZERO = 0x00,
- BLEND_ONE = 0x01,
- BLEND_SRC_COLOR = 0x02,
- BLEND_ONE_MINUS_SRC_COLOR = 0x03,
- BLEND_SRC_ALPHA = 0x04,
- BLEND_ONE_MINUS_SRC_ALPHA = 0x05,
- BLEND_DST_ALPHA = 0x06,
- BLEND_ONE_MINUS_DST_ALPHA = 0x07,
- BLEND_DST_COLOR = 0x08,
- BLEND_ONE_MINUS_DST_COLOR = 0x09,
- BLEND_SRC_ALPHA_SATURATE = 0x0a,
- BLEND_BOTH_SRC_ALPHA = 0x0b,
- BLEND_BOTH_INV_SRC_ALPHA = 0x0c,
- BLEND_CONSTANT_COLOR = 0x0d,
- BLEND_ONE_MINUS_CONSTANT_COLOR = 0x0e,
- BLEND_SRC1_COLOR = 0x0f,
- BLEND_INV_SRC1_COLOR = 0x10,
- BLEND_SRC1_ALPHA = 0x11,
- BLEND_INV_SRC1_ALPHA = 0x12,
- BLEND_CONSTANT_ALPHA = 0x13,
- BLEND_ONE_MINUS_CONSTANT_ALPHA = 0x14,
-/* COLOR_COMB_FCN_mask = 0x07 << 5, */
-/* COLOR_COMB_FCN_shift = 5, */
- COMB_DST_PLUS_SRC = 0x00,
- COMB_SRC_MINUS_DST = 0x01,
- COMB_MIN_DST_SRC = 0x02,
- COMB_MAX_DST_SRC = 0x03,
- COMB_DST_MINUS_SRC = 0x04,
-/* COLOR_DESTBLEND_mask = 0x1f << 8, */
-/* COLOR_DESTBLEND_shift = 8, */
-/* BLEND_ZERO = 0x00, */
-/* BLEND_ONE = 0x01, */
-/* BLEND_SRC_COLOR = 0x02, */
-/* BLEND_ONE_MINUS_SRC_COLOR = 0x03, */
-/* BLEND_SRC_ALPHA = 0x04, */
-/* BLEND_ONE_MINUS_SRC_ALPHA = 0x05, */
-/* BLEND_DST_ALPHA = 0x06, */
-/* BLEND_ONE_MINUS_DST_ALPHA = 0x07, */
-/* BLEND_DST_COLOR = 0x08, */
-/* BLEND_ONE_MINUS_DST_COLOR = 0x09, */
-/* BLEND_SRC_ALPHA_SATURATE = 0x0a, */
-/* BLEND_BOTH_SRC_ALPHA = 0x0b, */
-/* BLEND_BOTH_INV_SRC_ALPHA = 0x0c, */
-/* BLEND_CONSTANT_COLOR = 0x0d, */
-/* BLEND_ONE_MINUS_CONSTANT_COLOR = 0x0e, */
-/* BLEND_SRC1_COLOR = 0x0f, */
-/* BLEND_INV_SRC1_COLOR = 0x10, */
-/* BLEND_SRC1_ALPHA = 0x11, */
-/* BLEND_INV_SRC1_ALPHA = 0x12, */
-/* BLEND_CONSTANT_ALPHA = 0x13, */
-/* BLEND_ONE_MINUS_CONSTANT_ALPHA = 0x14, */
-/* OPACITY_WEIGHT_bit = 1 << 13, */
-/* ALPHA_SRCBLEND_mask = 0x1f << 16, */
-/* ALPHA_SRCBLEND_shift = 16, */
-/* BLEND_ZERO = 0x00, */
-/* BLEND_ONE = 0x01, */
-/* BLEND_SRC_COLOR = 0x02, */
-/* BLEND_ONE_MINUS_SRC_COLOR = 0x03, */
-/* BLEND_SRC_ALPHA = 0x04, */
-/* BLEND_ONE_MINUS_SRC_ALPHA = 0x05, */
-/* BLEND_DST_ALPHA = 0x06, */
-/* BLEND_ONE_MINUS_DST_ALPHA = 0x07, */
-/* BLEND_DST_COLOR = 0x08, */
-/* BLEND_ONE_MINUS_DST_COLOR = 0x09, */
-/* BLEND_SRC_ALPHA_SATURATE = 0x0a, */
-/* BLEND_BOTH_SRC_ALPHA = 0x0b, */
-/* BLEND_BOTH_INV_SRC_ALPHA = 0x0c, */
-/* BLEND_CONSTANT_COLOR = 0x0d, */
-/* BLEND_ONE_MINUS_CONSTANT_COLOR = 0x0e, */
-/* BLEND_SRC1_COLOR = 0x0f, */
-/* BLEND_INV_SRC1_COLOR = 0x10, */
-/* BLEND_SRC1_ALPHA = 0x11, */
-/* BLEND_INV_SRC1_ALPHA = 0x12, */
-/* BLEND_CONSTANT_ALPHA = 0x13, */
-/* BLEND_ONE_MINUS_CONSTANT_ALPHA = 0x14, */
-/* ALPHA_COMB_FCN_mask = 0x07 << 21, */
-/* ALPHA_COMB_FCN_shift = 21, */
-/* COMB_DST_PLUS_SRC = 0x00, */
-/* COMB_SRC_MINUS_DST = 0x01, */
-/* COMB_MIN_DST_SRC = 0x02, */
-/* COMB_MAX_DST_SRC = 0x03, */
-/* COMB_DST_MINUS_SRC = 0x04, */
-/* ALPHA_DESTBLEND_mask = 0x1f << 24, */
-/* ALPHA_DESTBLEND_shift = 24, */
-/* BLEND_ZERO = 0x00, */
-/* BLEND_ONE = 0x01, */
-/* BLEND_SRC_COLOR = 0x02, */
-/* BLEND_ONE_MINUS_SRC_COLOR = 0x03, */
-/* BLEND_SRC_ALPHA = 0x04, */
-/* BLEND_ONE_MINUS_SRC_ALPHA = 0x05, */
-/* BLEND_DST_ALPHA = 0x06, */
-/* BLEND_ONE_MINUS_DST_ALPHA = 0x07, */
-/* BLEND_DST_COLOR = 0x08, */
-/* BLEND_ONE_MINUS_DST_COLOR = 0x09, */
-/* BLEND_SRC_ALPHA_SATURATE = 0x0a, */
-/* BLEND_BOTH_SRC_ALPHA = 0x0b, */
-/* BLEND_BOTH_INV_SRC_ALPHA = 0x0c, */
-/* BLEND_CONSTANT_COLOR = 0x0d, */
-/* BLEND_ONE_MINUS_CONSTANT_COLOR = 0x0e, */
-/* BLEND_SRC1_COLOR = 0x0f, */
-/* BLEND_INV_SRC1_COLOR = 0x10, */
-/* BLEND_SRC1_ALPHA = 0x11, */
-/* BLEND_INV_SRC1_ALPHA = 0x12, */
-/* BLEND_CONSTANT_ALPHA = 0x13, */
-/* BLEND_ONE_MINUS_CONSTANT_ALPHA = 0x14, */
-/* SEPARATE_ALPHA_BLEND_bit = 1 << 29, */
- CB_COLOR_CONTROL = 0x00028808,
- FOG_ENABLE_bit = 1 << 0,
- MULTIWRITE_ENABLE_bit = 1 << 1,
- DITHER_ENABLE_bit = 1 << 2,
- DEGAMMA_ENABLE_bit = 1 << 3,
- SPECIAL_OP_mask = 0x07 << 4,
- SPECIAL_OP_shift = 4,
- SPECIAL_NORMAL = 0x00,
- SPECIAL_DISABLE = 0x01,
- SPECIAL_FAST_CLEAR = 0x02,
- SPECIAL_FORCE_CLEAR = 0x03,
- SPECIAL_EXPAND_COLOR = 0x04,
- SPECIAL_EXPAND_TEXTURE = 0x05,
- SPECIAL_EXPAND_SAMPLES = 0x06,
- SPECIAL_RESOLVE_BOX = 0x07,
- PER_MRT_BLEND_bit = 1 << 7,
- TARGET_BLEND_ENABLE_mask = 0xff << 8,
- TARGET_BLEND_ENABLE_shift = 8,
- ROP3_mask = 0xff << 16,
- ROP3_shift = 16,
- DB_SHADER_CONTROL = 0x0002880c,
- Z_EXPORT_ENABLE_bit = 1 << 0,
- STENCIL_REF_EXPORT_ENABLE_bit = 1 << 1,
- Z_ORDER_mask = 0x03 << 4,
- Z_ORDER_shift = 4,
- LATE_Z = 0x00,
- EARLY_Z_THEN_LATE_Z = 0x01,
- RE_Z = 0x02,
- EARLY_Z_THEN_RE_Z = 0x03,
- KILL_ENABLE_bit = 1 << 6,
- COVERAGE_TO_MASK_ENABLE_bit = 1 << 7,
- MASK_EXPORT_ENABLE_bit = 1 << 8,
- DUAL_EXPORT_ENABLE_bit = 1 << 9,
- EXEC_ON_HIER_FAIL_bit = 1 << 10,
- EXEC_ON_NOOP_bit = 1 << 11,
- PA_CL_CLIP_CNTL = 0x00028810,
- UCP_ENA_0_bit = 1 << 0,
- UCP_ENA_1_bit = 1 << 1,
- UCP_ENA_2_bit = 1 << 2,
- UCP_ENA_3_bit = 1 << 3,
- UCP_ENA_4_bit = 1 << 4,
- UCP_ENA_5_bit = 1 << 5,
- PS_UCP_Y_SCALE_NEG_bit = 1 << 13,
- PS_UCP_MODE_mask = 0x03 << 14,
- PS_UCP_MODE_shift = 14,
- CLIP_DISABLE_bit = 1 << 16,
- UCP_CULL_ONLY_ENA_bit = 1 << 17,
- BOUNDARY_EDGE_FLAG_ENA_bit = 1 << 18,
- DX_CLIP_SPACE_DEF_bit = 1 << 19,
- DIS_CLIP_ERR_DETECT_bit = 1 << 20,
- VTX_KILL_OR_bit = 1 << 21,
- DX_LINEAR_ATTR_CLIP_ENA_bit = 1 << 24,
- VTE_VPORT_PROVOKE_DISABLE_bit = 1 << 25,
- ZCLIP_NEAR_DISABLE_bit = 1 << 26,
- ZCLIP_FAR_DISABLE_bit = 1 << 27,
- PA_SU_SC_MODE_CNTL = 0x00028814,
- CULL_FRONT_bit = 1 << 0,
- CULL_BACK_bit = 1 << 1,
- FACE_bit = 1 << 2,
- POLY_MODE_mask = 0x03 << 3,
- POLY_MODE_shift = 3,
- X_DISABLE_POLY_MODE = 0x00,
- X_DUAL_MODE = 0x01,
- POLYMODE_FRONT_PTYPE_mask = 0x07 << 5,
- POLYMODE_FRONT_PTYPE_shift = 5,
- X_DRAW_POINTS = 0x00,
- X_DRAW_LINES = 0x01,
- X_DRAW_TRIANGLES = 0x02,
- POLYMODE_BACK_PTYPE_mask = 0x07 << 8,
- POLYMODE_BACK_PTYPE_shift = 8,
-/* X_DRAW_POINTS = 0x00, */
-/* X_DRAW_LINES = 0x01, */
-/* X_DRAW_TRIANGLES = 0x02, */
- POLY_OFFSET_FRONT_ENABLE_bit = 1 << 11,
- POLY_OFFSET_BACK_ENABLE_bit = 1 << 12,
- POLY_OFFSET_PARA_ENABLE_bit = 1 << 13,
- VTX_WINDOW_OFFSET_ENABLE_bit = 1 << 16,
- PROVOKING_VTX_LAST_bit = 1 << 19,
- PERSP_CORR_DIS_bit = 1 << 20,
- MULTI_PRIM_IB_ENA_bit = 1 << 21,
- PA_CL_VTE_CNTL = 0x00028818,
- VPORT_X_SCALE_ENA_bit = 1 << 0,
- VPORT_X_OFFSET_ENA_bit = 1 << 1,
- VPORT_Y_SCALE_ENA_bit = 1 << 2,
- VPORT_Y_OFFSET_ENA_bit = 1 << 3,
- VPORT_Z_SCALE_ENA_bit = 1 << 4,
- VPORT_Z_OFFSET_ENA_bit = 1 << 5,
- VTX_XY_FMT_bit = 1 << 8,
- VTX_Z_FMT_bit = 1 << 9,
- VTX_W0_FMT_bit = 1 << 10,
- PERFCOUNTER_REF_bit = 1 << 11,
- PA_CL_VS_OUT_CNTL = 0x0002881c,
- CLIP_DIST_ENA_0_bit = 1 << 0,
- CLIP_DIST_ENA_1_bit = 1 << 1,
- CLIP_DIST_ENA_2_bit = 1 << 2,
- CLIP_DIST_ENA_3_bit = 1 << 3,
- CLIP_DIST_ENA_4_bit = 1 << 4,
- CLIP_DIST_ENA_5_bit = 1 << 5,
- CLIP_DIST_ENA_6_bit = 1 << 6,
- CLIP_DIST_ENA_7_bit = 1 << 7,
- CULL_DIST_ENA_0_bit = 1 << 8,
- CULL_DIST_ENA_1_bit = 1 << 9,
- CULL_DIST_ENA_2_bit = 1 << 10,
- CULL_DIST_ENA_3_bit = 1 << 11,
- CULL_DIST_ENA_4_bit = 1 << 12,
- CULL_DIST_ENA_5_bit = 1 << 13,
- CULL_DIST_ENA_6_bit = 1 << 14,
- CULL_DIST_ENA_7_bit = 1 << 15,
- USE_VTX_POINT_SIZE_bit = 1 << 16,
- USE_VTX_EDGE_FLAG_bit = 1 << 17,
- USE_VTX_RENDER_TARGET_INDX_bit = 1 << 18,
- USE_VTX_VIEWPORT_INDX_bit = 1 << 19,
- USE_VTX_KILL_FLAG_bit = 1 << 20,
- VS_OUT_MISC_VEC_ENA_bit = 1 << 21,
- VS_OUT_CCDIST0_VEC_ENA_bit = 1 << 22,
- VS_OUT_CCDIST1_VEC_ENA_bit = 1 << 23,
- PA_CL_NANINF_CNTL = 0x00028820,
- VTE_XY_INF_DISCARD_bit = 1 << 0,
- VTE_Z_INF_DISCARD_bit = 1 << 1,
- VTE_W_INF_DISCARD_bit = 1 << 2,
- VTE_0XNANINF_IS_0_bit = 1 << 3,
- VTE_XY_NAN_RETAIN_bit = 1 << 4,
- VTE_Z_NAN_RETAIN_bit = 1 << 5,
- VTE_W_NAN_RETAIN_bit = 1 << 6,
- VTE_W_RECIP_NAN_IS_0_bit = 1 << 7,
- VS_XY_NAN_TO_INF_bit = 1 << 8,
- VS_XY_INF_RETAIN_bit = 1 << 9,
- VS_Z_NAN_TO_INF_bit = 1 << 10,
- VS_Z_INF_RETAIN_bit = 1 << 11,
- VS_W_NAN_TO_INF_bit = 1 << 12,
- VS_W_INF_RETAIN_bit = 1 << 13,
- VS_CLIP_DIST_INF_DISCARD_bit = 1 << 14,
- VTE_NO_OUTPUT_NEG_0_bit = 1 << 20,
- SQ_PGM_START_PS = 0x00028840,
- SQ_PGM_RESOURCES_PS = 0x00028850,
- NUM_GPRS_mask = 0xff << 0,
- NUM_GPRS_shift = 0,
- STACK_SIZE_mask = 0xff << 8,
- STACK_SIZE_shift = 8,
- SQ_PGM_RESOURCES_PS__DX10_CLAMP_bit = 1 << 21,
- FETCH_CACHE_LINES_mask = 0x07 << 24,
- FETCH_CACHE_LINES_shift = 24,
- UNCACHED_FIRST_INST_bit = 1 << 28,
- CLAMP_CONSTS_bit = 1 << 31,
- SQ_PGM_EXPORTS_PS = 0x00028854,
- EXPORT_MODE_mask = 0x1f << 0,
- EXPORT_MODE_shift = 0,
- SQ_PGM_START_VS = 0x00028858,
- SQ_PGM_RESOURCES_VS = 0x00028868,
-/* NUM_GPRS_mask = 0xff << 0, */
-/* NUM_GPRS_shift = 0, */
-/* STACK_SIZE_mask = 0xff << 8, */
-/* STACK_SIZE_shift = 8, */
- SQ_PGM_RESOURCES_VS__DX10_CLAMP_bit = 1 << 21,
-/* FETCH_CACHE_LINES_mask = 0x07 << 24, */
-/* FETCH_CACHE_LINES_shift = 24, */
-/* UNCACHED_FIRST_INST_bit = 1 << 28, */
- SQ_PGM_START_GS = 0x0002886c,
- SQ_PGM_RESOURCES_GS = 0x0002887c,
-/* NUM_GPRS_mask = 0xff << 0, */
-/* NUM_GPRS_shift = 0, */
-/* STACK_SIZE_mask = 0xff << 8, */
-/* STACK_SIZE_shift = 8, */
- SQ_PGM_RESOURCES_GS__DX10_CLAMP_bit = 1 << 21,
-/* FETCH_CACHE_LINES_mask = 0x07 << 24, */
-/* FETCH_CACHE_LINES_shift = 24, */
-/* UNCACHED_FIRST_INST_bit = 1 << 28, */
- SQ_PGM_START_ES = 0x00028880,
- SQ_PGM_RESOURCES_ES = 0x00028890,
-/* NUM_GPRS_mask = 0xff << 0, */
-/* NUM_GPRS_shift = 0, */
-/* STACK_SIZE_mask = 0xff << 8, */
-/* STACK_SIZE_shift = 8, */
- SQ_PGM_RESOURCES_ES__DX10_CLAMP_bit = 1 << 21,
-/* FETCH_CACHE_LINES_mask = 0x07 << 24, */
-/* FETCH_CACHE_LINES_shift = 24, */
-/* UNCACHED_FIRST_INST_bit = 1 << 28, */
- SQ_PGM_START_FS = 0x00028894,
- SQ_PGM_RESOURCES_FS = 0x000288a4,
-/* NUM_GPRS_mask = 0xff << 0, */
-/* NUM_GPRS_shift = 0, */
-/* STACK_SIZE_mask = 0xff << 8, */
-/* STACK_SIZE_shift = 8, */
- SQ_PGM_RESOURCES_FS__DX10_CLAMP_bit = 1 << 21,
- SQ_ESGS_RING_ITEMSIZE = 0x000288a8,
- ITEMSIZE_mask = 0x7fff << 0,
- ITEMSIZE_shift = 0,
- SQ_GSVS_RING_ITEMSIZE = 0x000288ac,
-/* ITEMSIZE_mask = 0x7fff << 0, */
-/* ITEMSIZE_shift = 0, */
- SQ_ESTMP_RING_ITEMSIZE = 0x000288b0,
-/* ITEMSIZE_mask = 0x7fff << 0, */
-/* ITEMSIZE_shift = 0, */
- SQ_GSTMP_RING_ITEMSIZE = 0x000288b4,
-/* ITEMSIZE_mask = 0x7fff << 0, */
-/* ITEMSIZE_shift = 0, */
- SQ_VSTMP_RING_ITEMSIZE = 0x000288b8,
-/* ITEMSIZE_mask = 0x7fff << 0, */
-/* ITEMSIZE_shift = 0, */
- SQ_PSTMP_RING_ITEMSIZE = 0x000288bc,
-/* ITEMSIZE_mask = 0x7fff << 0, */
-/* ITEMSIZE_shift = 0, */
- SQ_FBUF_RING_ITEMSIZE = 0x000288c0,
-/* ITEMSIZE_mask = 0x7fff << 0, */
-/* ITEMSIZE_shift = 0, */
- SQ_REDUC_RING_ITEMSIZE = 0x000288c4,
-/* ITEMSIZE_mask = 0x7fff << 0, */
-/* ITEMSIZE_shift = 0, */
- SQ_GS_VERT_ITEMSIZE = 0x000288c8,
-/* ITEMSIZE_mask = 0x7fff << 0, */
-/* ITEMSIZE_shift = 0, */
- SQ_PGM_CF_OFFSET_PS = 0x000288cc,
- PGM_CF_OFFSET_mask = 0xfffff << 0,
- PGM_CF_OFFSET_shift = 0,
- SQ_PGM_CF_OFFSET_VS = 0x000288d0,
-/* PGM_CF_OFFSET_mask = 0xfffff << 0, */
-/* PGM_CF_OFFSET_shift = 0, */
- SQ_PGM_CF_OFFSET_GS = 0x000288d4,
-/* PGM_CF_OFFSET_mask = 0xfffff << 0, */
-/* PGM_CF_OFFSET_shift = 0, */
- SQ_PGM_CF_OFFSET_ES = 0x000288d8,
-/* PGM_CF_OFFSET_mask = 0xfffff << 0, */
-/* PGM_CF_OFFSET_shift = 0, */
- SQ_PGM_CF_OFFSET_FS = 0x000288dc,
-/* PGM_CF_OFFSET_mask = 0xfffff << 0, */
-/* PGM_CF_OFFSET_shift = 0, */
- SQ_VTX_SEMANTIC_CLEAR = 0x000288e0,
- SQ_ALU_CONST_CACHE_PS_0 = 0x00028940,
- SQ_ALU_CONST_CACHE_PS_0_num = 16,
- SQ_ALU_CONST_CACHE_VS_0 = 0x00028980,
- SQ_ALU_CONST_CACHE_VS_0_num = 16,
- SQ_ALU_CONST_CACHE_GS_0 = 0x000289c0,
- SQ_ALU_CONST_CACHE_GS_0_num = 16,
- PA_SU_POINT_SIZE = 0x00028a00,
- PA_SU_POINT_SIZE__HEIGHT_mask = 0xffff << 0,
- PA_SU_POINT_SIZE__HEIGHT_shift = 0,
- PA_SU_POINT_SIZE__WIDTH_mask = 0xffff << 16,
- PA_SU_POINT_SIZE__WIDTH_shift = 16,
- PA_SU_POINT_MINMAX = 0x00028a04,
- MIN_SIZE_mask = 0xffff << 0,
- MIN_SIZE_shift = 0,
- MAX_SIZE_mask = 0xffff << 16,
- MAX_SIZE_shift = 16,
- PA_SU_LINE_CNTL = 0x00028a08,
- PA_SU_LINE_CNTL__WIDTH_mask = 0xffff << 0,
- PA_SU_LINE_CNTL__WIDTH_shift = 0,
- PA_SC_LINE_STIPPLE = 0x00028a0c,
- LINE_PATTERN_mask = 0xffff << 0,
- LINE_PATTERN_shift = 0,
- REPEAT_COUNT_mask = 0xff << 16,
- REPEAT_COUNT_shift = 16,
- PATTERN_BIT_ORDER_bit = 1 << 28,
- AUTO_RESET_CNTL_mask = 0x03 << 29,
- AUTO_RESET_CNTL_shift = 29,
- VGT_OUTPUT_PATH_CNTL = 0x00028a10,
- PATH_SELECT_mask = 0x03 << 0,
- PATH_SELECT_shift = 0,
- VGT_OUTPATH_VTX_REUSE = 0x00,
- VGT_OUTPATH_TESS_EN = 0x01,
- VGT_OUTPATH_PASSTHRU = 0x02,
- VGT_OUTPATH_GS_BLOCK = 0x03,
- VGT_HOS_CNTL = 0x00028a14,
- TESS_MODE_mask = 0x03 << 0,
- TESS_MODE_shift = 0,
- VGT_HOS_MAX_TESS_LEVEL = 0x00028a18,
- VGT_HOS_MIN_TESS_LEVEL = 0x00028a1c,
- VGT_HOS_REUSE_DEPTH = 0x00028a20,
- REUSE_DEPTH_mask = 0xff << 0,
- REUSE_DEPTH_shift = 0,
- VGT_GROUP_PRIM_TYPE = 0x00028a24,
- VGT_GROUP_PRIM_TYPE__PRIM_TYPE_mask = 0x1f << 0,
- VGT_GROUP_PRIM_TYPE__PRIM_TYPE_shift = 0,
- VGT_GRP_3D_POINT = 0x00,
- VGT_GRP_3D_LINE = 0x01,
- VGT_GRP_3D_TRI = 0x02,
- VGT_GRP_3D_RECT = 0x03,
- VGT_GRP_3D_QUAD = 0x04,
- VGT_GRP_2D_COPY_RECT_V0 = 0x05,
- VGT_GRP_2D_COPY_RECT_V1 = 0x06,
- VGT_GRP_2D_COPY_RECT_V2 = 0x07,
- VGT_GRP_2D_COPY_RECT_V3 = 0x08,
- VGT_GRP_2D_FILL_RECT = 0x09,
- VGT_GRP_2D_LINE = 0x0a,
- VGT_GRP_2D_TRI = 0x0b,
- VGT_GRP_PRIM_INDEX_LINE = 0x0c,
- VGT_GRP_PRIM_INDEX_TRI = 0x0d,
- VGT_GRP_PRIM_INDEX_QUAD = 0x0e,
- VGT_GRP_3D_LINE_ADJ = 0x0f,
- VGT_GRP_3D_TRI_ADJ = 0x10,
- RETAIN_ORDER_bit = 1 << 14,
- RETAIN_QUADS_bit = 1 << 15,
- PRIM_ORDER_mask = 0x07 << 16,
- PRIM_ORDER_shift = 16,
- VGT_GRP_LIST = 0x00,
- VGT_GRP_STRIP = 0x01,
- VGT_GRP_FAN = 0x02,
- VGT_GRP_LOOP = 0x03,
- VGT_GRP_POLYGON = 0x04,
- VGT_GROUP_FIRST_DECR = 0x00028a28,
- FIRST_DECR_mask = 0x0f << 0,
- FIRST_DECR_shift = 0,
- VGT_GROUP_DECR = 0x00028a2c,
- DECR_mask = 0x0f << 0,
- DECR_shift = 0,
- VGT_GROUP_VECT_0_CNTL = 0x00028a30,
- COMP_X_EN_bit = 1 << 0,
- COMP_Y_EN_bit = 1 << 1,
- COMP_Z_EN_bit = 1 << 2,
- COMP_W_EN_bit = 1 << 3,
- VGT_GROUP_VECT_0_CNTL__STRIDE_mask = 0xff << 8,
- VGT_GROUP_VECT_0_CNTL__STRIDE_shift = 8,
- SHIFT_mask = 0xff << 16,
- SHIFT_shift = 16,
- VGT_GROUP_VECT_1_CNTL = 0x00028a34,
-/* COMP_X_EN_bit = 1 << 0, */
-/* COMP_Y_EN_bit = 1 << 1, */
-/* COMP_Z_EN_bit = 1 << 2, */
-/* COMP_W_EN_bit = 1 << 3, */
- VGT_GROUP_VECT_1_CNTL__STRIDE_mask = 0xff << 8,
- VGT_GROUP_VECT_1_CNTL__STRIDE_shift = 8,
-/* SHIFT_mask = 0xff << 16, */
-/* SHIFT_shift = 16, */
- VGT_GROUP_VECT_0_FMT_CNTL = 0x00028a38,
- X_CONV_mask = 0x0f << 0,
- X_CONV_shift = 0,
- VGT_GRP_INDEX_16 = 0x00,
- VGT_GRP_INDEX_32 = 0x01,
- VGT_GRP_UINT_16 = 0x02,
- VGT_GRP_UINT_32 = 0x03,
- VGT_GRP_SINT_16 = 0x04,
- VGT_GRP_SINT_32 = 0x05,
- VGT_GRP_FLOAT_32 = 0x06,
- VGT_GRP_AUTO_PRIM = 0x07,
- VGT_GRP_FIX_1_23_TO_FLOAT = 0x08,
- X_OFFSET_mask = 0x0f << 4,
- X_OFFSET_shift = 4,
- Y_CONV_mask = 0x0f << 8,
- Y_CONV_shift = 8,
-/* VGT_GRP_INDEX_16 = 0x00, */
-/* VGT_GRP_INDEX_32 = 0x01, */
-/* VGT_GRP_UINT_16 = 0x02, */
-/* VGT_GRP_UINT_32 = 0x03, */
-/* VGT_GRP_SINT_16 = 0x04, */
-/* VGT_GRP_SINT_32 = 0x05, */
-/* VGT_GRP_FLOAT_32 = 0x06, */
-/* VGT_GRP_AUTO_PRIM = 0x07, */
-/* VGT_GRP_FIX_1_23_TO_FLOAT = 0x08, */
- Y_OFFSET_mask = 0x0f << 12,
- Y_OFFSET_shift = 12,
- Z_CONV_mask = 0x0f << 16,
- Z_CONV_shift = 16,
-/* VGT_GRP_INDEX_16 = 0x00, */
-/* VGT_GRP_INDEX_32 = 0x01, */
-/* VGT_GRP_UINT_16 = 0x02, */
-/* VGT_GRP_UINT_32 = 0x03, */
-/* VGT_GRP_SINT_16 = 0x04, */
-/* VGT_GRP_SINT_32 = 0x05, */
-/* VGT_GRP_FLOAT_32 = 0x06, */
-/* VGT_GRP_AUTO_PRIM = 0x07, */
-/* VGT_GRP_FIX_1_23_TO_FLOAT = 0x08, */
- Z_OFFSET_mask = 0x0f << 20,
- Z_OFFSET_shift = 20,
- W_CONV_mask = 0x0f << 24,
- W_CONV_shift = 24,
-/* VGT_GRP_INDEX_16 = 0x00, */
-/* VGT_GRP_INDEX_32 = 0x01, */
-/* VGT_GRP_UINT_16 = 0x02, */
-/* VGT_GRP_UINT_32 = 0x03, */
-/* VGT_GRP_SINT_16 = 0x04, */
-/* VGT_GRP_SINT_32 = 0x05, */
-/* VGT_GRP_FLOAT_32 = 0x06, */
-/* VGT_GRP_AUTO_PRIM = 0x07, */
-/* VGT_GRP_FIX_1_23_TO_FLOAT = 0x08, */
- W_OFFSET_mask = 0x0f << 28,
- W_OFFSET_shift = 28,
- VGT_GROUP_VECT_1_FMT_CNTL = 0x00028a3c,
-/* X_CONV_mask = 0x0f << 0, */
-/* X_CONV_shift = 0, */
-/* VGT_GRP_INDEX_16 = 0x00, */
-/* VGT_GRP_INDEX_32 = 0x01, */
-/* VGT_GRP_UINT_16 = 0x02, */
-/* VGT_GRP_UINT_32 = 0x03, */
-/* VGT_GRP_SINT_16 = 0x04, */
-/* VGT_GRP_SINT_32 = 0x05, */
-/* VGT_GRP_FLOAT_32 = 0x06, */
-/* VGT_GRP_AUTO_PRIM = 0x07, */
-/* VGT_GRP_FIX_1_23_TO_FLOAT = 0x08, */
-/* X_OFFSET_mask = 0x0f << 4, */
-/* X_OFFSET_shift = 4, */
-/* Y_CONV_mask = 0x0f << 8, */
-/* Y_CONV_shift = 8, */
-/* VGT_GRP_INDEX_16 = 0x00, */
-/* VGT_GRP_INDEX_32 = 0x01, */
-/* VGT_GRP_UINT_16 = 0x02, */
-/* VGT_GRP_UINT_32 = 0x03, */
-/* VGT_GRP_SINT_16 = 0x04, */
-/* VGT_GRP_SINT_32 = 0x05, */
-/* VGT_GRP_FLOAT_32 = 0x06, */
-/* VGT_GRP_AUTO_PRIM = 0x07, */
-/* VGT_GRP_FIX_1_23_TO_FLOAT = 0x08, */
-/* Y_OFFSET_mask = 0x0f << 12, */
-/* Y_OFFSET_shift = 12, */
-/* Z_CONV_mask = 0x0f << 16, */
-/* Z_CONV_shift = 16, */
-/* VGT_GRP_INDEX_16 = 0x00, */
-/* VGT_GRP_INDEX_32 = 0x01, */
-/* VGT_GRP_UINT_16 = 0x02, */
-/* VGT_GRP_UINT_32 = 0x03, */
-/* VGT_GRP_SINT_16 = 0x04, */
-/* VGT_GRP_SINT_32 = 0x05, */
-/* VGT_GRP_FLOAT_32 = 0x06, */
-/* VGT_GRP_AUTO_PRIM = 0x07, */
-/* VGT_GRP_FIX_1_23_TO_FLOAT = 0x08, */
-/* Z_OFFSET_mask = 0x0f << 20, */
-/* Z_OFFSET_shift = 20, */
-/* W_CONV_mask = 0x0f << 24, */
-/* W_CONV_shift = 24, */
-/* VGT_GRP_INDEX_16 = 0x00, */
-/* VGT_GRP_INDEX_32 = 0x01, */
-/* VGT_GRP_UINT_16 = 0x02, */
-/* VGT_GRP_UINT_32 = 0x03, */
-/* VGT_GRP_SINT_16 = 0x04, */
-/* VGT_GRP_SINT_32 = 0x05, */
-/* VGT_GRP_FLOAT_32 = 0x06, */
-/* VGT_GRP_AUTO_PRIM = 0x07, */
-/* VGT_GRP_FIX_1_23_TO_FLOAT = 0x08, */
-/* W_OFFSET_mask = 0x0f << 28, */
-/* W_OFFSET_shift = 28, */
- VGT_GS_MODE = 0x00028a40,
- MODE_mask = 0x03 << 0,
- MODE_shift = 0,
- GS_OFF = 0x00,
- GS_SCENARIO_A = 0x01,
- GS_SCENARIO_B = 0x02,
- GS_SCENARIO_G = 0x03,
- ES_PASSTHRU_bit = 1 << 2,
- CUT_MODE_mask = 0x03 << 3,
- CUT_MODE_shift = 3,
- GS_CUT_1024 = 0x00,
- GS_CUT_512 = 0x01,
- GS_CUT_256 = 0x02,
- GS_CUT_128 = 0x03,
- PA_SC_MPASS_PS_CNTL = 0x00028a48,
- MPASS_PIX_VEC_PER_PASS_mask = 0xfffff << 0,
- MPASS_PIX_VEC_PER_PASS_shift = 0,
- MPASS_PS_ENA_bit = 1 << 31,
- PA_SC_MODE_CNTL = 0x00028a4c,
- MSAA_ENABLE_bit = 1 << 0,
- CLIPRECT_ENABLE_bit = 1 << 1,
- LINE_STIPPLE_ENABLE_bit = 1 << 2,
- MULTI_CHIP_PRIM_DISCARD_ENAB_bit = 1 << 3,
- WALK_ORDER_ENABLE_bit = 1 << 4,
- HALVE_DETAIL_SAMPLE_PERF_bit = 1 << 5,
- WALK_SIZE_bit = 1 << 6,
- WALK_ALIGNMENT_bit = 1 << 7,
- WALK_ALIGN8_PRIM_FITS_ST_bit = 1 << 8,
- TILE_COVER_NO_SCISSOR_bit = 1 << 9,
- KILL_PIX_POST_HI_Z_bit = 1 << 10,
- KILL_PIX_POST_DETAIL_MASK_bit = 1 << 11,
- MULTI_CHIP_SUPERTILE_ENABLE_bit = 1 << 12,
- TILE_COVER_DISABLE_bit = 1 << 13,
- FORCE_EOV_CNTDWN_ENABLE_bit = 1 << 14,
- FORCE_EOV_TILE_ENABLE_bit = 1 << 15,
- FORCE_EOV_REZ_ENABLE_bit = 1 << 16,
- PS_ITER_SAMPLE_bit = 1 << 17,
- VGT_ENHANCE = 0x00028a50,
- VGT_ENHANCE__MI_TIMESTAMP_RES_mask = 0x03 << 0,
- VGT_ENHANCE__MI_TIMESTAMP_RES_shift = 0,
- X_0_992_CLOCKS_LATENCY_RANGE_IN_STEPS_OF_32 = 0x00,
- X_0_496_CLOCKS_LATENCY_RANGE_IN_STEPS_OF_16 = 0x01,
- X_0_248_CLOCKS_LATENCY_RANGE_IN_STEPS_OF_8 = 0x02,
- X_0_124_CLOCKS_LATENCY_RANGE_IN_STEPS_OF_4 = 0x03,
- MISC_mask = 0x3fffffff << 2,
- MISC_shift = 2,
- VGT_GS_OUT_PRIM_TYPE = 0x00028a6c,
- OUTPRIM_TYPE_mask = 0x3f << 0,
- OUTPRIM_TYPE_shift = 0,
- POINTLIST = 0x00,
- LINESTRIP = 0x01,
- TRISTRIP = 0x02,
- VGT_DMA_SIZE = 0x00028a74,
- VGT_DMA_INDEX_TYPE = 0x00028a7c,
-/* INDEX_TYPE_mask = 0x03 << 0, */
-/* INDEX_TYPE_shift = 0, */
- VGT_INDEX_16 = 0x00,
- VGT_INDEX_32 = 0x01,
- SWAP_MODE_mask = 0x03 << 2,
- SWAP_MODE_shift = 2,
- VGT_DMA_SWAP_NONE = 0x00,
- VGT_DMA_SWAP_16_BIT = 0x01,
- VGT_DMA_SWAP_32_BIT = 0x02,
- VGT_DMA_SWAP_WORD = 0x03,
- VGT_PRIMITIVEID_EN = 0x00028a84,
- PRIMITIVEID_EN_bit = 1 << 0,
- VGT_DMA_NUM_INSTANCES = 0x00028a88,
- VGT_EVENT_INITIATOR = 0x00028a90,
- EVENT_TYPE_mask = 0x3f << 0,
- EVENT_TYPE_shift = 0,
- CACHE_FLUSH_TS = 0x04,
- CONTEXT_DONE = 0x05,
- CACHE_FLUSH = 0x06,
- VIZQUERY_START = 0x07,
- VIZQUERY_END = 0x08,
- SC_WAIT_WC = 0x09,
- MPASS_PS_CP_REFETCH = 0x0a,
- MPASS_PS_RST_START = 0x0b,
- MPASS_PS_INCR_START = 0x0c,
- RST_PIX_CNT = 0x0d,
- RST_VTX_CNT = 0x0e,
- VS_PARTIAL_FLUSH = 0x0f,
- PS_PARTIAL_FLUSH = 0x10,
- CACHE_FLUSH_AND_INV_TS_EVENT = 0x14,
- ZPASS_DONE = 0x15,
- CACHE_FLUSH_AND_INV_EVENT = 0x16,
- PERFCOUNTER_START = 0x17,
- PERFCOUNTER_STOP = 0x18,
- PIPELINESTAT_START = 0x19,
- PIPELINESTAT_STOP = 0x1a,
- PERFCOUNTER_SAMPLE = 0x1b,
- FLUSH_ES_OUTPUT = 0x1c,
- FLUSH_GS_OUTPUT = 0x1d,
- SAMPLE_PIPELINESTAT = 0x1e,
- SO_VGTSTREAMOUT_FLUSH = 0x1f,
- SAMPLE_STREAMOUTSTATS = 0x20,
- RESET_VTX_CNT = 0x21,
- BLOCK_CONTEXT_DONE = 0x22,
- CR_CONTEXT_DONE = 0x23,
- VGT_FLUSH = 0x24,
- CR_DONE_TS = 0x25,
- SQ_NON_EVENT = 0x26,
- SC_SEND_DB_VPZ = 0x27,
- BOTTOM_OF_PIPE_TS = 0x28,
- DB_CACHE_FLUSH_AND_INV = 0x2a,
- ADDRESS_HI_mask = 0xff << 19,
- ADDRESS_HI_shift = 19,
- EXTENDED_EVENT_bit = 1 << 27,
- VGT_MULTI_PRIM_IB_RESET_EN = 0x00028a94,
- RESET_EN_bit = 1 << 0,
- VGT_INSTANCE_STEP_RATE_0 = 0x00028aa0,
- VGT_INSTANCE_STEP_RATE_1 = 0x00028aa4,
- VGT_STRMOUT_EN = 0x00028ab0,
- STREAMOUT_bit = 1 << 0,
- VGT_REUSE_OFF = 0x00028ab4,
- REUSE_OFF_bit = 1 << 0,
- VGT_VTX_CNT_EN = 0x00028ab8,
- VTX_CNT_EN_bit = 1 << 0,
- VGT_STRMOUT_BUFFER_SIZE_0 = 0x00028ad0,
- VGT_STRMOUT_VTX_STRIDE_0 = 0x00028ad4,
- VGT_STRMOUT_VTX_STRIDE_0__STRIDE_mask = 0x3ff << 0,
- VGT_STRMOUT_VTX_STRIDE_0__STRIDE_shift = 0,
- VGT_STRMOUT_BUFFER_BASE_0 = 0x00028ad8,
- VGT_STRMOUT_BUFFER_OFFSET_0 = 0x00028adc,
- VGT_STRMOUT_BUFFER_SIZE_1 = 0x00028ae0,
- VGT_STRMOUT_VTX_STRIDE_1 = 0x00028ae4,
- VGT_STRMOUT_VTX_STRIDE_1__STRIDE_mask = 0x3ff << 0,
- VGT_STRMOUT_VTX_STRIDE_1__STRIDE_shift = 0,
- VGT_STRMOUT_BUFFER_BASE_1 = 0x00028ae8,
- VGT_STRMOUT_BUFFER_OFFSET_1 = 0x00028aec,
- VGT_STRMOUT_BUFFER_SIZE_2 = 0x00028af0,
- VGT_STRMOUT_VTX_STRIDE_2 = 0x00028af4,
- VGT_STRMOUT_VTX_STRIDE_2__STRIDE_mask = 0x3ff << 0,
- VGT_STRMOUT_VTX_STRIDE_2__STRIDE_shift = 0,
- VGT_STRMOUT_BUFFER_BASE_2 = 0x00028af8,
- VGT_STRMOUT_BUFFER_OFFSET_2 = 0x00028afc,
- VGT_STRMOUT_BUFFER_SIZE_3 = 0x00028b00,
- VGT_STRMOUT_VTX_STRIDE_3 = 0x00028b04,
- VGT_STRMOUT_VTX_STRIDE_3__STRIDE_mask = 0x3ff << 0,
- VGT_STRMOUT_VTX_STRIDE_3__STRIDE_shift = 0,
- VGT_STRMOUT_BUFFER_BASE_3 = 0x00028b08,
- VGT_STRMOUT_BUFFER_OFFSET_3 = 0x00028b0c,
- VGT_STRMOUT_BASE_OFFSET_0 = 0x00028b10,
- VGT_STRMOUT_BASE_OFFSET_1 = 0x00028b14,
- VGT_STRMOUT_BASE_OFFSET_2 = 0x00028b18,
- VGT_STRMOUT_BASE_OFFSET_3 = 0x00028b1c,
- VGT_STRMOUT_BUFFER_EN = 0x00028b20,
- BUFFER_0_EN_bit = 1 << 0,
- BUFFER_1_EN_bit = 1 << 1,
- BUFFER_2_EN_bit = 1 << 2,
- BUFFER_3_EN_bit = 1 << 3,
- VGT_STRMOUT_DRAW_OPAQUE_OFFSET = 0x00028b28,
- VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE = 0x00028b2c,
- VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE = 0x00028b30,
- VGT_STRMOUT_BASE_OFFSET_HI_0 = 0x00028b44,
- VGT_STRMOUT_BASE_OFFSET_HI_0__BASE_OFFSET_mask = 0x3f << 0,
- VGT_STRMOUT_BASE_OFFSET_HI_0__BASE_OFFSET_shift = 0,
- VGT_STRMOUT_BASE_OFFSET_HI_1 = 0x00028b48,
- VGT_STRMOUT_BASE_OFFSET_HI_1__BASE_OFFSET_mask = 0x3f << 0,
- VGT_STRMOUT_BASE_OFFSET_HI_1__BASE_OFFSET_shift = 0,
- VGT_STRMOUT_BASE_OFFSET_HI_2 = 0x00028b4c,
- VGT_STRMOUT_BASE_OFFSET_HI_2__BASE_OFFSET_mask = 0x3f << 0,
- VGT_STRMOUT_BASE_OFFSET_HI_2__BASE_OFFSET_shift = 0,
- VGT_STRMOUT_BASE_OFFSET_HI_3 = 0x00028b50,
- VGT_STRMOUT_BASE_OFFSET_HI_3__BASE_OFFSET_mask = 0x3f << 0,
- VGT_STRMOUT_BASE_OFFSET_HI_3__BASE_OFFSET_shift = 0,
- PA_SC_LINE_CNTL = 0x00028c00,
- BRES_CNTL_mask = 0xff << 0,
- BRES_CNTL_shift = 0,
- USE_BRES_CNTL_bit = 1 << 8,
- EXPAND_LINE_WIDTH_bit = 1 << 9,
- LAST_PIXEL_bit = 1 << 10,
- PA_SC_AA_CONFIG = 0x00028c04,
- MSAA_NUM_SAMPLES_mask = 0x03 << 0,
- MSAA_NUM_SAMPLES_shift = 0,
- AA_MASK_CENTROID_DTMN_bit = 1 << 4,
- MAX_SAMPLE_DIST_mask = 0x0f << 13,
- MAX_SAMPLE_DIST_shift = 13,
- PA_SU_VTX_CNTL = 0x00028c08,
- PIX_CENTER_bit = 1 << 0,
- PA_SU_VTX_CNTL__ROUND_MODE_mask = 0x03 << 1,
- PA_SU_VTX_CNTL__ROUND_MODE_shift = 1,
- X_TRUNCATE = 0x00,
- X_ROUND = 0x01,
- X_ROUND_TO_EVEN = 0x02,
- X_ROUND_TO_ODD = 0x03,
- QUANT_MODE_mask = 0x07 << 3,
- QUANT_MODE_shift = 3,
- X_1_16TH = 0x00,
- X_1_8TH = 0x01,
- X_1_4TH = 0x02,
- X_1_2 = 0x03,
- X_1 = 0x04,
- X_1_256TH = 0x05,
- PA_CL_GB_VERT_CLIP_ADJ = 0x00028c0c,
- PA_CL_GB_VERT_DISC_ADJ = 0x00028c10,
- PA_CL_GB_HORZ_CLIP_ADJ = 0x00028c14,
- PA_CL_GB_HORZ_DISC_ADJ = 0x00028c18,
- PA_SC_AA_SAMPLE_LOCS_MCTX = 0x00028c1c,
-/* S0_X_mask = 0x0f << 0, */
-/* S0_X_shift = 0, */
-/* S0_Y_mask = 0x0f << 4, */
-/* S0_Y_shift = 4, */
-/* S1_X_mask = 0x0f << 8, */
-/* S1_X_shift = 8, */
-/* S1_Y_mask = 0x0f << 12, */
-/* S1_Y_shift = 12, */
-/* S2_X_mask = 0x0f << 16, */
-/* S2_X_shift = 16, */
-/* S2_Y_mask = 0x0f << 20, */
-/* S2_Y_shift = 20, */
-/* S3_X_mask = 0x0f << 24, */
-/* S3_X_shift = 24, */
-/* S3_Y_mask = 0x0f << 28, */
-/* S3_Y_shift = 28, */
- PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX = 0x00028c20,
-/* S4_X_mask = 0x0f << 0, */
-/* S4_X_shift = 0, */
-/* S4_Y_mask = 0x0f << 4, */
-/* S4_Y_shift = 4, */
-/* S5_X_mask = 0x0f << 8, */
-/* S5_X_shift = 8, */
-/* S5_Y_mask = 0x0f << 12, */
-/* S5_Y_shift = 12, */
-/* S6_X_mask = 0x0f << 16, */
-/* S6_X_shift = 16, */
-/* S6_Y_mask = 0x0f << 20, */
-/* S6_Y_shift = 20, */
-/* S7_X_mask = 0x0f << 24, */
-/* S7_X_shift = 24, */
-/* S7_Y_mask = 0x0f << 28, */
-/* S7_Y_shift = 28, */
- CB_CLRCMP_CONTROL = 0x00028c30,
- CLRCMP_FCN_SRC_mask = 0x07 << 0,
- CLRCMP_FCN_SRC_shift = 0,
- CLRCMP_DRAW_ALWAYS = 0x00,
- CLRCMP_DRAW_NEVER = 0x01,
- CLRCMP_DRAW_ON_NEQ = 0x04,
- CLRCMP_DRAW_ON_EQ = 0x05,
- CLRCMP_FCN_DST_mask = 0x07 << 8,
- CLRCMP_FCN_DST_shift = 8,
-/* CLRCMP_DRAW_ALWAYS = 0x00, */
-/* CLRCMP_DRAW_NEVER = 0x01, */
-/* CLRCMP_DRAW_ON_NEQ = 0x04, */
-/* CLRCMP_DRAW_ON_EQ = 0x05, */
- CLRCMP_FCN_SEL_mask = 0x03 << 24,
- CLRCMP_FCN_SEL_shift = 24,
- CLRCMP_SEL_DST = 0x00,
- CLRCMP_SEL_SRC = 0x01,
- CLRCMP_SEL_AND = 0x02,
- CB_CLRCMP_SRC = 0x00028c34,
- CB_CLRCMP_DST = 0x00028c38,
- CB_CLRCMP_MSK = 0x00028c3c,
- PA_SC_AA_MASK = 0x00028c48,
- VGT_VERTEX_REUSE_BLOCK_CNTL = 0x00028c58,
- VTX_REUSE_DEPTH_mask = 0xff << 0,
- VTX_REUSE_DEPTH_shift = 0,
- VGT_OUT_DEALLOC_CNTL = 0x00028c5c,
- DEALLOC_DIST_mask = 0x7f << 0,
- DEALLOC_DIST_shift = 0,
- DB_RENDER_CONTROL = 0x00028d0c,
- DEPTH_CLEAR_ENABLE_bit = 1 << 0,
- STENCIL_CLEAR_ENABLE_bit = 1 << 1,
- DEPTH_COPY_bit = 1 << 2,
- STENCIL_COPY_bit = 1 << 3,
- RESUMMARIZE_ENABLE_bit = 1 << 4,
- STENCIL_COMPRESS_DISABLE_bit = 1 << 5,
- DEPTH_COMPRESS_DISABLE_bit = 1 << 6,
- COPY_CENTROID_bit = 1 << 7,
- COPY_SAMPLE_mask = 0x07 << 8,
- COPY_SAMPLE_shift = 8,
- ZPASS_INCREMENT_DISABLE_bit = 1 << 11,
- DB_RENDER_OVERRIDE = 0x00028d10,
- FORCE_HIZ_ENABLE_mask = 0x03 << 0,
- FORCE_HIZ_ENABLE_shift = 0,
- FORCE_OFF = 0x00,
- FORCE_ENABLE = 0x01,
- FORCE_DISABLE = 0x02,
- FORCE_RESERVED = 0x03,
- FORCE_HIS_ENABLE0_mask = 0x03 << 2,
- FORCE_HIS_ENABLE0_shift = 2,
-/* FORCE_OFF = 0x00, */
-/* FORCE_ENABLE = 0x01, */
-/* FORCE_DISABLE = 0x02, */
-/* FORCE_RESERVED = 0x03, */
- FORCE_HIS_ENABLE1_mask = 0x03 << 4,
- FORCE_HIS_ENABLE1_shift = 4,
-/* FORCE_OFF = 0x00, */
-/* FORCE_ENABLE = 0x01, */
-/* FORCE_DISABLE = 0x02, */
-/* FORCE_RESERVED = 0x03, */
- FORCE_SHADER_Z_ORDER_bit = 1 << 6,
- FAST_Z_DISABLE_bit = 1 << 7,
- FAST_STENCIL_DISABLE_bit = 1 << 8,
- NOOP_CULL_DISABLE_bit = 1 << 9,
- FORCE_COLOR_KILL_bit = 1 << 10,
- FORCE_Z_READ_bit = 1 << 11,
- FORCE_STENCIL_READ_bit = 1 << 12,
- FORCE_FULL_Z_RANGE_mask = 0x03 << 13,
- FORCE_FULL_Z_RANGE_shift = 13,
-/* FORCE_OFF = 0x00, */
-/* FORCE_ENABLE = 0x01, */
-/* FORCE_DISABLE = 0x02, */
-/* FORCE_RESERVED = 0x03, */
- FORCE_QC_SMASK_CONFLICT_bit = 1 << 15,
- DISABLE_VIEWPORT_CLAMP_bit = 1 << 16,
- IGNORE_SC_ZRANGE_bit = 1 << 17,
- DB_HTILE_SURFACE = 0x00028d24,
- HTILE_WIDTH_bit = 1 << 0,
- HTILE_HEIGHT_bit = 1 << 1,
- LINEAR_bit = 1 << 2,
- FULL_CACHE_bit = 1 << 3,
- HTILE_USES_PRELOAD_WIN_bit = 1 << 4,
- PRELOAD_bit = 1 << 5,
- PREFETCH_WIDTH_mask = 0x3f << 6,
- PREFETCH_WIDTH_shift = 6,
- PREFETCH_HEIGHT_mask = 0x3f << 12,
- PREFETCH_HEIGHT_shift = 12,
- DB_SRESULTS_COMPARE_STATE1 = 0x00028d2c,
- COMPAREFUNC1_mask = 0x07 << 0,
- COMPAREFUNC1_shift = 0,
-/* REF_NEVER = 0x00, */
-/* REF_LESS = 0x01, */
-/* REF_EQUAL = 0x02, */
-/* REF_LEQUAL = 0x03, */
-/* REF_GREATER = 0x04, */
-/* REF_NOTEQUAL = 0x05, */
-/* REF_GEQUAL = 0x06, */
-/* REF_ALWAYS = 0x07, */
- COMPAREVALUE1_mask = 0xff << 4,
- COMPAREVALUE1_shift = 4,
- COMPAREMASK1_mask = 0xff << 12,
- COMPAREMASK1_shift = 12,
- ENABLE1_bit = 1 << 24,
- DB_PRELOAD_CONTROL = 0x00028d30,
- START_X_mask = 0xff << 0,
- START_X_shift = 0,
- START_Y_mask = 0xff << 8,
- START_Y_shift = 8,
- MAX_X_mask = 0xff << 16,
- MAX_X_shift = 16,
- MAX_Y_mask = 0xff << 24,
- MAX_Y_shift = 24,
- DB_PREFETCH_LIMIT = 0x00028d34,
- DEPTH_HEIGHT_TILE_MAX_mask = 0x3ff << 0,
- DEPTH_HEIGHT_TILE_MAX_shift = 0,
- PA_SU_POLY_OFFSET_DB_FMT_CNTL = 0x00028df8,
- POLY_OFFSET_NEG_NUM_DB_BITS_mask = 0xff << 0,
- POLY_OFFSET_NEG_NUM_DB_BITS_shift = 0,
- POLY_OFFSET_DB_IS_FLOAT_FMT_bit = 1 << 8,
- PA_SU_POLY_OFFSET_CLAMP = 0x00028dfc,
- PA_SU_POLY_OFFSET_FRONT_SCALE = 0x00028e00,
- PA_SU_POLY_OFFSET_FRONT_OFFSET = 0x00028e04,
- PA_SU_POLY_OFFSET_BACK_SCALE = 0x00028e08,
- PA_SU_POLY_OFFSET_BACK_OFFSET = 0x00028e0c,
- PA_CL_POINT_X_RAD = 0x00028e10,
- PA_CL_POINT_Y_RAD = 0x00028e14,
- PA_CL_POINT_SIZE = 0x00028e18,
- PA_CL_POINT_CULL_RAD = 0x00028e1c,
- PA_CL_UCP_0_X = 0x00028e20,
- PA_CL_UCP_0_X_num = 6,
- PA_CL_UCP_0_X_offset = 16,
- PA_CL_UCP_0_Y = 0x00028e24,
- PA_CL_UCP_0_Y_num = 6,
- PA_CL_UCP_0_Y_offset = 16,
- PA_CL_UCP_0_Z = 0x00028e28,
- PA_CL_UCP_0_Z_num = 6,
- PA_CL_UCP_0_Z_offset = 16,
- SQ_ALU_CONSTANT0_0 = 0x00030000,
- SQ_ALU_CONSTANT1_0 = 0x00030004,
- SQ_ALU_CONSTANT2_0 = 0x00030008,
- SQ_ALU_CONSTANT3_0 = 0x0003000c,
- SQ_VTX_CONSTANT_WORD0_0 = 0x00038000,
- SQ_TEX_RESOURCE_WORD0_0 = 0x00038000,
- DIM_mask = 0x07 << 0,
- DIM_shift = 0,
- SQ_TEX_DIM_1D = 0x00,
- SQ_TEX_DIM_2D = 0x01,
- SQ_TEX_DIM_3D = 0x02,
- SQ_TEX_DIM_CUBEMAP = 0x03,
- SQ_TEX_DIM_1D_ARRAY = 0x04,
- SQ_TEX_DIM_2D_ARRAY = 0x05,
- SQ_TEX_DIM_2D_MSAA = 0x06,
- SQ_TEX_DIM_2D_ARRAY_MSAA = 0x07,
- SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask = 0x0f << 3,
- SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift = 3,
- TILE_TYPE_bit = 1 << 7,
- PITCH_mask = 0x7ff << 8,
- PITCH_shift = 8,
- TEX_WIDTH_mask = 0x1fff << 19,
- TEX_WIDTH_shift = 19,
- SQ_VTX_CONSTANT_WORD1_0 = 0x00038004,
- SQ_TEX_RESOURCE_WORD1_0 = 0x00038004,
- TEX_HEIGHT_mask = 0x1fff << 0,
- TEX_HEIGHT_shift = 0,
- TEX_DEPTH_mask = 0x1fff << 13,
- TEX_DEPTH_shift = 13,
- SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask = 0x3f << 26,
- SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift = 26,
- SQ_VTX_CONSTANT_WORD2_0 = 0x00038008,
- BASE_ADDRESS_HI_mask = 0xff << 0,
- BASE_ADDRESS_HI_shift = 0,
- SQ_VTX_CONSTANT_WORD2_0__STRIDE_mask = 0x7ff << 8,
- SQ_VTX_CONSTANT_WORD2_0__STRIDE_shift = 8,
- SQ_VTX_CONSTANT_WORD2_0__CLAMP_X_bit = 1 << 19,
- SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_mask = 0x3f << 20,
- SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_shift = 20,
- SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_mask = 0x03 << 26,
- SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_shift = 26,
-/* SQ_NUM_FORMAT_NORM = 0x00, */
-/* SQ_NUM_FORMAT_INT = 0x01, */
-/* SQ_NUM_FORMAT_SCALED = 0x02, */
- SQ_VTX_CONSTANT_WORD2_0__FORMAT_COMP_ALL_bit = 1 << 28,
- SQ_VTX_CONSTANT_WORD2_0__SRF_MODE_ALL_bit = 1 << 29,
- SQ_VTX_CONSTANT_WORD2_0__ENDIAN_SWAP_mask = 0x03 << 30,
- SQ_VTX_CONSTANT_WORD2_0__ENDIAN_SWAP_shift = 30,
-/* SQ_ENDIAN_NONE = 0x00, */
-/* SQ_ENDIAN_8IN16 = 0x01, */
-/* SQ_ENDIAN_8IN32 = 0x02, */
- SQ_TEX_RESOURCE_WORD2_0 = 0x00038008,
- SQ_VTX_CONSTANT_WORD3_0 = 0x0003800c,
- MEM_REQUEST_SIZE_mask = 0x03 << 0,
- MEM_REQUEST_SIZE_shift = 0,
- SQ_TEX_RESOURCE_WORD3_0 = 0x0003800c,
- SQ_TEX_RESOURCE_WORD4_0 = 0x00038010,
- FORMAT_COMP_X_mask = 0x03 << 0,
- FORMAT_COMP_X_shift = 0,
- SQ_FORMAT_COMP_UNSIGNED = 0x00,
- SQ_FORMAT_COMP_SIGNED = 0x01,
- SQ_FORMAT_COMP_UNSIGNED_BIASED = 0x02,
- FORMAT_COMP_Y_mask = 0x03 << 2,
- FORMAT_COMP_Y_shift = 2,
-/* SQ_FORMAT_COMP_UNSIGNED = 0x00, */
-/* SQ_FORMAT_COMP_SIGNED = 0x01, */
-/* SQ_FORMAT_COMP_UNSIGNED_BIASED = 0x02, */
- FORMAT_COMP_Z_mask = 0x03 << 4,
- FORMAT_COMP_Z_shift = 4,
-/* SQ_FORMAT_COMP_UNSIGNED = 0x00, */
-/* SQ_FORMAT_COMP_SIGNED = 0x01, */
-/* SQ_FORMAT_COMP_UNSIGNED_BIASED = 0x02, */
- FORMAT_COMP_W_mask = 0x03 << 6,
- FORMAT_COMP_W_shift = 6,
-/* SQ_FORMAT_COMP_UNSIGNED = 0x00, */
-/* SQ_FORMAT_COMP_SIGNED = 0x01, */
-/* SQ_FORMAT_COMP_UNSIGNED_BIASED = 0x02, */
- SQ_TEX_RESOURCE_WORD4_0__NUM_FORMAT_ALL_mask = 0x03 << 8,
- SQ_TEX_RESOURCE_WORD4_0__NUM_FORMAT_ALL_shift = 8,
-/* SQ_NUM_FORMAT_NORM = 0x00, */
-/* SQ_NUM_FORMAT_INT = 0x01, */
-/* SQ_NUM_FORMAT_SCALED = 0x02, */
- SQ_TEX_RESOURCE_WORD4_0__SRF_MODE_ALL_bit = 1 << 10,
- SQ_TEX_RESOURCE_WORD4_0__FORCE_DEGAMMA_bit = 1 << 11,
- SQ_TEX_RESOURCE_WORD4_0__ENDIAN_SWAP_mask = 0x03 << 12,
- SQ_TEX_RESOURCE_WORD4_0__ENDIAN_SWAP_shift = 12,
-/* SQ_ENDIAN_NONE = 0x00, */
-/* SQ_ENDIAN_8IN16 = 0x01, */
-/* SQ_ENDIAN_8IN32 = 0x02, */
- REQUEST_SIZE_mask = 0x03 << 14,
- REQUEST_SIZE_shift = 14,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask = 0x07 << 16,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift = 16,
-/* SQ_SEL_X = 0x00, */
-/* SQ_SEL_Y = 0x01, */
-/* SQ_SEL_Z = 0x02, */
-/* SQ_SEL_W = 0x03, */
-/* SQ_SEL_0 = 0x04, */
-/* SQ_SEL_1 = 0x05, */
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask = 0x07 << 19,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift = 19,
-/* SQ_SEL_X = 0x00, */
-/* SQ_SEL_Y = 0x01, */
-/* SQ_SEL_Z = 0x02, */
-/* SQ_SEL_W = 0x03, */
-/* SQ_SEL_0 = 0x04, */
-/* SQ_SEL_1 = 0x05, */
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask = 0x07 << 22,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift = 22,
-/* SQ_SEL_X = 0x00, */
-/* SQ_SEL_Y = 0x01, */
-/* SQ_SEL_Z = 0x02, */
-/* SQ_SEL_W = 0x03, */
-/* SQ_SEL_0 = 0x04, */
-/* SQ_SEL_1 = 0x05, */
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask = 0x07 << 25,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift = 25,
-/* SQ_SEL_X = 0x00, */
-/* SQ_SEL_Y = 0x01, */
-/* SQ_SEL_Z = 0x02, */
-/* SQ_SEL_W = 0x03, */
-/* SQ_SEL_0 = 0x04, */
-/* SQ_SEL_1 = 0x05, */
- BASE_LEVEL_mask = 0x0f << 28,
- BASE_LEVEL_shift = 28,
- SQ_TEX_RESOURCE_WORD5_0 = 0x00038014,
- LAST_LEVEL_mask = 0x0f << 0,
- LAST_LEVEL_shift = 0,
- BASE_ARRAY_mask = 0x1fff << 4,
- BASE_ARRAY_shift = 4,
- LAST_ARRAY_mask = 0x1fff << 17,
- LAST_ARRAY_shift = 17,
- SQ_TEX_RESOURCE_WORD6_0 = 0x00038018,
- MPEG_CLAMP_mask = 0x03 << 0,
- MPEG_CLAMP_shift = 0,
- SQ_TEX_MPEG_CLAMP_OFF = 0x00,
- SQ_TEX_MPEG_9 = 0x01,
- SQ_TEX_MPEG_10 = 0x02,
- PERF_MODULATION_mask = 0x07 << 5,
- PERF_MODULATION_shift = 5,
- INTERLACED_bit = 1 << 8,
- SQ_TEX_RESOURCE_WORD6_0__TYPE_mask = 0x03 << 30,
- SQ_TEX_RESOURCE_WORD6_0__TYPE_shift = 30,
- SQ_TEX_VTX_INVALID_TEXTURE = 0x00,
- SQ_TEX_VTX_INVALID_BUFFER = 0x01,
- SQ_TEX_VTX_VALID_TEXTURE = 0x02,
- SQ_TEX_VTX_VALID_BUFFER = 0x03,
- SQ_VTX_CONSTANT_WORD6_0 = 0x00038018,
- SQ_VTX_CONSTANT_WORD6_0__TYPE_mask = 0x03 << 30,
- SQ_VTX_CONSTANT_WORD6_0__TYPE_shift = 30,
-/* SQ_TEX_VTX_INVALID_TEXTURE = 0x00, */
-/* SQ_TEX_VTX_INVALID_BUFFER = 0x01, */
-/* SQ_TEX_VTX_VALID_TEXTURE = 0x02, */
-/* SQ_TEX_VTX_VALID_BUFFER = 0x03, */
- SQ_TEX_SAMPLER_WORD0_0 = 0x0003c000,
- SQ_TEX_SAMPLER_WORD0_0__CLAMP_X_mask = 0x07 << 0,
- SQ_TEX_SAMPLER_WORD0_0__CLAMP_X_shift = 0,
- SQ_TEX_WRAP = 0x00,
- SQ_TEX_MIRROR = 0x01,
- SQ_TEX_CLAMP_LAST_TEXEL = 0x02,
- SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 0x03,
- SQ_TEX_CLAMP_HALF_BORDER = 0x04,
- SQ_TEX_MIRROR_ONCE_HALF_BORDER = 0x05,
- SQ_TEX_CLAMP_BORDER = 0x06,
- SQ_TEX_MIRROR_ONCE_BORDER = 0x07,
- CLAMP_Y_mask = 0x07 << 3,
- CLAMP_Y_shift = 3,
-/* SQ_TEX_WRAP = 0x00, */
-/* SQ_TEX_MIRROR = 0x01, */
-/* SQ_TEX_CLAMP_LAST_TEXEL = 0x02, */
-/* SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 0x03, */
-/* SQ_TEX_CLAMP_HALF_BORDER = 0x04, */
-/* SQ_TEX_MIRROR_ONCE_HALF_BORDER = 0x05, */
-/* SQ_TEX_CLAMP_BORDER = 0x06, */
-/* SQ_TEX_MIRROR_ONCE_BORDER = 0x07, */
- CLAMP_Z_mask = 0x07 << 6,
- CLAMP_Z_shift = 6,
-/* SQ_TEX_WRAP = 0x00, */
-/* SQ_TEX_MIRROR = 0x01, */
-/* SQ_TEX_CLAMP_LAST_TEXEL = 0x02, */
-/* SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 0x03, */
-/* SQ_TEX_CLAMP_HALF_BORDER = 0x04, */
-/* SQ_TEX_MIRROR_ONCE_HALF_BORDER = 0x05, */
-/* SQ_TEX_CLAMP_BORDER = 0x06, */
-/* SQ_TEX_MIRROR_ONCE_BORDER = 0x07, */
- XY_MAG_FILTER_mask = 0x07 << 9,
- XY_MAG_FILTER_shift = 9,
- SQ_TEX_XY_FILTER_POINT = 0x00,
- SQ_TEX_XY_FILTER_BILINEAR = 0x01,
- SQ_TEX_XY_FILTER_BICUBIC = 0x02,
- XY_MIN_FILTER_mask = 0x07 << 12,
- XY_MIN_FILTER_shift = 12,
-/* SQ_TEX_XY_FILTER_POINT = 0x00, */
-/* SQ_TEX_XY_FILTER_BILINEAR = 0x01, */
-/* SQ_TEX_XY_FILTER_BICUBIC = 0x02, */
- Z_FILTER_mask = 0x03 << 15,
- Z_FILTER_shift = 15,
- SQ_TEX_Z_FILTER_NONE = 0x00,
- SQ_TEX_Z_FILTER_POINT = 0x01,
- SQ_TEX_Z_FILTER_LINEAR = 0x02,
- MIP_FILTER_mask = 0x03 << 17,
- MIP_FILTER_shift = 17,
-/* SQ_TEX_Z_FILTER_NONE = 0x00, */
-/* SQ_TEX_Z_FILTER_POINT = 0x01, */
-/* SQ_TEX_Z_FILTER_LINEAR = 0x02, */
- BORDER_COLOR_TYPE_mask = 0x03 << 22,
- BORDER_COLOR_TYPE_shift = 22,
- SQ_TEX_BORDER_COLOR_TRANS_BLACK = 0x00,
- SQ_TEX_BORDER_COLOR_OPAQUE_BLACK = 0x01,
- SQ_TEX_BORDER_COLOR_OPAQUE_WHITE = 0x02,
- SQ_TEX_BORDER_COLOR_REGISTER = 0x03,
- POINT_SAMPLING_CLAMP_bit = 1 << 24,
- TEX_ARRAY_OVERRIDE_bit = 1 << 25,
- DEPTH_COMPARE_FUNCTION_mask = 0x07 << 26,
- DEPTH_COMPARE_FUNCTION_shift = 26,
- SQ_TEX_DEPTH_COMPARE_NEVER = 0x00,
- SQ_TEX_DEPTH_COMPARE_LESS = 0x01,
- SQ_TEX_DEPTH_COMPARE_EQUAL = 0x02,
- SQ_TEX_DEPTH_COMPARE_LESSEQUAL = 0x03,
- SQ_TEX_DEPTH_COMPARE_GREATER = 0x04,
- SQ_TEX_DEPTH_COMPARE_NOTEQUAL = 0x05,
- SQ_TEX_DEPTH_COMPARE_GREATEREQUAL = 0x06,
- SQ_TEX_DEPTH_COMPARE_ALWAYS = 0x07,
- CHROMA_KEY_mask = 0x03 << 29,
- CHROMA_KEY_shift = 29,
- SQ_TEX_CHROMA_KEY_DISABLED = 0x00,
- SQ_TEX_CHROMA_KEY_KILL = 0x01,
- SQ_TEX_CHROMA_KEY_BLEND = 0x02,
- LOD_USES_MINOR_AXIS_bit = 1 << 31,
- SQ_TEX_SAMPLER_WORD1_0 = 0x0003c004,
- MIN_LOD_mask = 0x3ff << 0,
- MIN_LOD_shift = 0,
- MAX_LOD_mask = 0x3ff << 10,
- MAX_LOD_shift = 10,
- SQ_TEX_SAMPLER_WORD1_0__LOD_BIAS_mask = 0xfff << 20,
- SQ_TEX_SAMPLER_WORD1_0__LOD_BIAS_shift = 20,
- SQ_TEX_SAMPLER_WORD2_0 = 0x0003c008,
- LOD_BIAS_SEC_mask = 0xfff << 0,
- LOD_BIAS_SEC_shift = 0,
- MC_COORD_TRUNCATE_bit = 1 << 12,
- SQ_TEX_SAMPLER_WORD2_0__FORCE_DEGAMMA_bit = 1 << 13,
- HIGH_PRECISION_FILTER_bit = 1 << 14,
- PERF_MIP_mask = 0x07 << 15,
- PERF_MIP_shift = 15,
- PERF_Z_mask = 0x03 << 18,
- PERF_Z_shift = 18,
- FETCH_4_bit = 1 << 26,
- SAMPLE_IS_PCF_bit = 1 << 27,
- SQ_TEX_SAMPLER_WORD2_0__TYPE_bit = 1 << 31,
- SQ_VTX_BASE_VTX_LOC = 0x0003cff0,
- SQ_VTX_START_INST_LOC = 0x0003cff4,
- SQ_LOOP_CONST_DX10_0 = 0x0003e200,
- SQ_LOOP_CONST_0 = 0x0003e200,
- SQ_LOOP_CONST_0__COUNT_mask = 0xfff << 0,
- SQ_LOOP_CONST_0__COUNT_shift = 0,
- INIT_mask = 0xfff << 12,
- INIT_shift = 12,
- INC_mask = 0xff << 24,
- INC_shift = 24,
- SQ_BOOL_CONST_0 = 0x0003e380,
- SQ_BOOL_CONST_0_num = 3,
-
-} ;
-
-#endif /* _AUTOREGS */
-
+++ /dev/null
-/*
- * RadeonHD R6xx, R7xx Register documentation
- *
- * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
- * Copyright (C) 2008-2009 Matthias Hopf
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef _R600_REG_R6xx_H_
-#define _R600_REG_R6xx_H_
-
-/*
- * Registers for R6xx chips that are not documented yet
- */
-
-enum {
-
- MM_INDEX = 0x0000,
- MM_DATA = 0x0004,
-
- SRBM_STATUS = 0x0e50,
- RLC_RQ_PENDING_bit = 1 << 3,
- RCU_RQ_PENDING_bit = 1 << 4,
- GRBM_RQ_PENDING_bit = 1 << 5,
- HI_RQ_PENDING_bit = 1 << 6,
- IO_EXTERN_SIGNAL_bit = 1 << 7,
- VMC_BUSY_bit = 1 << 8,
- MCB_BUSY_bit = 1 << 9,
- MCDZ_BUSY_bit = 1 << 10,
- MCDY_BUSY_bit = 1 << 11,
- MCDX_BUSY_bit = 1 << 12,
- MCDW_BUSY_bit = 1 << 13,
- SEM_BUSY_bit = 1 << 14,
- SRBM_STATUS__RLC_BUSY_bit = 1 << 15,
- PDMA_BUSY_bit = 1 << 16,
- IH_BUSY_bit = 1 << 17,
- CSC_BUSY_bit = 1 << 20,
- CMC7_BUSY_bit = 1 << 21,
- CMC6_BUSY_bit = 1 << 22,
- CMC5_BUSY_bit = 1 << 23,
- CMC4_BUSY_bit = 1 << 24,
- CMC3_BUSY_bit = 1 << 25,
- CMC2_BUSY_bit = 1 << 26,
- CMC1_BUSY_bit = 1 << 27,
- CMC0_BUSY_bit = 1 << 28,
- BIF_BUSY_bit = 1 << 29,
- IDCT_BUSY_bit = 1 << 30,
-
- SRBM_READ_ERROR = 0x0e98,
- READ_ADDRESS_mask = 0xffff << 2,
- READ_ADDRESS_shift = 2,
- READ_REQUESTER_HI_bit = 1 << 24,
- READ_REQUESTER_GRBM_bit = 1 << 25,
- READ_REQUESTER_RCU_bit = 1 << 26,
- READ_REQUESTER_RLC_bit = 1 << 27,
- READ_ERROR_bit = 1 << 31,
-
- SRBM_INT_STATUS = 0x0ea4,
- RDERR_INT_STAT_bit = 1 << 0,
- GFX_CNTX_SWITCH_INT_STAT_bit = 1 << 1,
- SRBM_INT_ACK = 0x0ea8,
- RDERR_INT_ACK_bit = 1 << 0,
- GFX_CNTX_SWITCH_INT_ACK_bit = 1 << 1,
-
- R6XX_MC_VM_FB_LOCATION = 0x2180,
-
- VENDOR_DEVICE_ID = 0x4000,
-
- D1GRPH_PRIMARY_SURFACE_ADDRESS = 0x6110,
- D1GRPH_PITCH = 0x6120,
- D1GRPH_Y_END = 0x6138,
-
- GRBM_STATUS = 0x8010,
- CMDFIFO_AVAIL_mask = 0x1f << 0,
- CMDFIFO_AVAIL_shift = 0,
- SRBM_RQ_PENDING_bit = 1 << 5,
- CP_RQ_PENDING_bit = 1 << 6,
- CF_RQ_PENDING_bit = 1 << 7,
- PF_RQ_PENDING_bit = 1 << 8,
- GRBM_EE_BUSY_bit = 1 << 10,
- GRBM_STATUS__VC_BUSY_bit = 1 << 11,
- DB03_CLEAN_bit = 1 << 12,
- CB03_CLEAN_bit = 1 << 13,
- VGT_BUSY_NO_DMA_bit = 1 << 16,
- GRBM_STATUS__VGT_BUSY_bit = 1 << 17,
- TA03_BUSY_bit = 1 << 18,
- GRBM_STATUS__TC_BUSY_bit = 1 << 19,
- SX_BUSY_bit = 1 << 20,
- SH_BUSY_bit = 1 << 21,
- SPI03_BUSY_bit = 1 << 22,
- SMX_BUSY_bit = 1 << 23,
- SC_BUSY_bit = 1 << 24,
- PA_BUSY_bit = 1 << 25,
- DB03_BUSY_bit = 1 << 26,
- CR_BUSY_bit = 1 << 27,
- CP_COHERENCY_BUSY_bit = 1 << 28,
- GRBM_STATUS__CP_BUSY_bit = 1 << 29,
- CB03_BUSY_bit = 1 << 30,
- GUI_ACTIVE_bit = 1 << 31,
- GRBM_STATUS2 = 0x8014,
- CR_CLEAN_bit = 1 << 0,
- SMX_CLEAN_bit = 1 << 1,
- SPI0_BUSY_bit = 1 << 8,
- SPI1_BUSY_bit = 1 << 9,
- SPI2_BUSY_bit = 1 << 10,
- SPI3_BUSY_bit = 1 << 11,
- TA0_BUSY_bit = 1 << 12,
- TA1_BUSY_bit = 1 << 13,
- TA2_BUSY_bit = 1 << 14,
- TA3_BUSY_bit = 1 << 15,
- DB0_BUSY_bit = 1 << 16,
- DB1_BUSY_bit = 1 << 17,
- DB2_BUSY_bit = 1 << 18,
- DB3_BUSY_bit = 1 << 19,
- CB0_BUSY_bit = 1 << 20,
- CB1_BUSY_bit = 1 << 21,
- CB2_BUSY_bit = 1 << 22,
- CB3_BUSY_bit = 1 << 23,
- GRBM_SOFT_RESET = 0x8020,
- SOFT_RESET_CP_bit = 1 << 0,
- SOFT_RESET_CB_bit = 1 << 1,
- SOFT_RESET_CR_bit = 1 << 2,
- SOFT_RESET_DB_bit = 1 << 3,
- SOFT_RESET_PA_bit = 1 << 5,
- SOFT_RESET_SC_bit = 1 << 6,
- SOFT_RESET_SMX_bit = 1 << 7,
- SOFT_RESET_SPI_bit = 1 << 8,
- SOFT_RESET_SH_bit = 1 << 9,
- SOFT_RESET_SX_bit = 1 << 10,
- SOFT_RESET_TC_bit = 1 << 11,
- SOFT_RESET_TA_bit = 1 << 12,
- SOFT_RESET_VC_bit = 1 << 13,
- SOFT_RESET_VGT_bit = 1 << 14,
- SOFT_RESET_GRBM_GCA_bit = 1 << 15,
-
- WAIT_UNTIL = 0x8040,
- WAIT_CP_DMA_IDLE_bit = 1 << 8,
- WAIT_CMDFIFO_bit = 1 << 10,
- WAIT_2D_IDLE_bit = 1 << 14,
- WAIT_3D_IDLE_bit = 1 << 15,
- WAIT_2D_IDLECLEAN_bit = 1 << 16,
- WAIT_3D_IDLECLEAN_bit = 1 << 17,
- WAIT_EXTERN_SIG_bit = 1 << 19,
- CMDFIFO_ENTRIES_mask = 0x1f << 20,
- CMDFIFO_ENTRIES_shift = 20,
-
- GRBM_READ_ERROR = 0x8058,
-/* READ_ADDRESS_mask = 0xffff << 2, */
-/* READ_ADDRESS_shift = 2, */
- READ_REQUESTER_SRBM_bit = 1 << 28,
- READ_REQUESTER_CP_bit = 1 << 29,
- READ_REQUESTER_WU_POLL_bit = 1 << 30,
-/* READ_ERROR_bit = 1 << 31, */
-
- SCRATCH_REG0 = 0x8500,
- SCRATCH_REG1 = 0x8504,
- SCRATCH_REG2 = 0x8508,
- SCRATCH_REG3 = 0x850c,
- SCRATCH_REG4 = 0x8510,
- SCRATCH_REG5 = 0x8514,
- SCRATCH_REG6 = 0x8518,
- SCRATCH_REG7 = 0x851c,
- SCRATCH_UMSK = 0x8540,
- SCRATCH_ADDR = 0x8544,
-
- CP_COHER_CNTL = 0x85f0,
- DEST_BASE_0_ENA_bit = 1 << 0,
- DEST_BASE_1_ENA_bit = 1 << 1,
- SO0_DEST_BASE_ENA_bit = 1 << 2,
- SO1_DEST_BASE_ENA_bit = 1 << 3,
- SO2_DEST_BASE_ENA_bit = 1 << 4,
- SO3_DEST_BASE_ENA_bit = 1 << 5,
- CB0_DEST_BASE_ENA_bit = 1 << 6,
- CB1_DEST_BASE_ENA_bit = 1 << 7,
- CB2_DEST_BASE_ENA_bit = 1 << 8,
- CB3_DEST_BASE_ENA_bit = 1 << 9,
- CB4_DEST_BASE_ENA_bit = 1 << 10,
- CB5_DEST_BASE_ENA_bit = 1 << 11,
- CB6_DEST_BASE_ENA_bit = 1 << 12,
- CB7_DEST_BASE_ENA_bit = 1 << 13,
- DB_DEST_BASE_ENA_bit = 1 << 14,
- CR_DEST_BASE_ENA_bit = 1 << 15,
- TC_ACTION_ENA_bit = 1 << 23,
- VC_ACTION_ENA_bit = 1 << 24,
- CB_ACTION_ENA_bit = 1 << 25,
- DB_ACTION_ENA_bit = 1 << 26,
- SH_ACTION_ENA_bit = 1 << 27,
- SMX_ACTION_ENA_bit = 1 << 28,
- CR0_ACTION_ENA_bit = 1 << 29,
- CR1_ACTION_ENA_bit = 1 << 30,
- CR2_ACTION_ENA_bit = 1 << 31,
- CP_COHER_SIZE = 0x85f4,
- CP_COHER_BASE = 0x85f8,
- CP_COHER_STATUS = 0x85fc,
- MATCHING_GFX_CNTX_mask = 0xff << 0,
- MATCHING_GFX_CNTX_shift = 0,
- MATCHING_CR_CNTX_mask = 0xffff << 8,
- MATCHING_CR_CNTX_shift = 8,
- STATUS_bit = 1 << 31,
-
- CP_STALLED_STAT1 = 0x8674,
- RBIU_TO_DMA_NOT_RDY_TO_RCV_bit = 1 << 0,
- RBIU_TO_IBS_NOT_RDY_TO_RCV_bit = 1 << 1,
- RBIU_TO_SEM_NOT_RDY_TO_RCV_bit = 1 << 2,
- RBIU_TO_2DREGS_NOT_RDY_TO_RCV_bit = 1 << 3,
- RBIU_TO_MEMWR_NOT_RDY_TO_RCV_bit = 1 << 4,
- RBIU_TO_MEMRD_NOT_RDY_TO_RCV_bit = 1 << 5,
- RBIU_TO_EOPD_NOT_RDY_TO_RCV_bit = 1 << 6,
- RBIU_TO_RECT_NOT_RDY_TO_RCV_bit = 1 << 7,
- RBIU_TO_STRMO_NOT_RDY_TO_RCV_bit = 1 << 8,
- RBIU_TO_PSTAT_NOT_RDY_TO_RCV_bit = 1 << 9,
- MIU_WAITING_ON_RDREQ_FREE_bit = 1 << 16,
- MIU_WAITING_ON_WRREQ_FREE_bit = 1 << 17,
- MIU_NEEDS_AVAIL_WRREQ_PHASE_bit = 1 << 18,
- RCIU_WAITING_ON_GRBM_FREE_bit = 1 << 24,
- RCIU_WAITING_ON_VGT_FREE_bit = 1 << 25,
- RCIU_STALLED_ON_ME_READ_bit = 1 << 26,
- RCIU_STALLED_ON_DMA_READ_bit = 1 << 27,
- RCIU_HALTED_BY_REG_VIOLATION_bit = 1 << 28,
- CP_STALLED_STAT2 = 0x8678,
- PFP_TO_CSF_NOT_RDY_TO_RCV_bit = 1 << 0,
- PFP_TO_MEQ_NOT_RDY_TO_RCV_bit = 1 << 1,
- PFP_TO_VGT_NOT_RDY_TO_RCV_bit = 1 << 2,
- PFP_HALTED_BY_INSTR_VIOLATION_bit = 1 << 3,
- MULTIPASS_IB_PENDING_IN_PFP_bit = 1 << 4,
- ME_BRUSH_WC_NOT_RDY_TO_RCV_bit = 1 << 8,
- ME_STALLED_ON_BRUSH_LOGIC_bit = 1 << 9,
- CR_CNTX_NOT_AVAIL_TO_ME_bit = 1 << 10,
- GFX_CNTX_NOT_AVAIL_TO_ME_bit = 1 << 11,
- ME_RCIU_NOT_RDY_TO_RCV_bit = 1 << 12,
- ME_TO_CONST_NOT_RDY_TO_RCV_bit = 1 << 13,
- ME_WAITING_DATA_FROM_PFP_bit = 1 << 14,
- ME_WAITING_ON_PARTIAL_FLUSH_bit = 1 << 15,
- RECT_FIFO_NEEDS_CR_RECT_DONE_bit = 1 << 16,
- RECT_FIFO_NEEDS_WR_CONFIRM_bit = 1 << 17,
- EOPD_FIFO_NEEDS_SC_EOP_DONE_bit = 1 << 18,
- EOPD_FIFO_NEEDS_SMX_EOP_DONE_bit = 1 << 19,
- EOPD_FIFO_NEEDS_WR_CONFIRM_bit = 1 << 20,
- EOPD_FIFO_NEEDS_SIGNAL_SEM_bit = 1 << 21,
- SO_NUMPRIM_FIFO_NEEDS_SOADDR_bit = 1 << 22,
- SO_NUMPRIM_FIFO_NEEDS_NUMPRIM_bit = 1 << 23,
- PIPE_STATS_FIFO_NEEDS_SAMPLE_bit = 1 << 24,
- SURF_SYNC_NEEDS_IDLE_CNTXS_bit = 1 << 30,
- SURF_SYNC_NEEDS_ALL_CLEAN_bit = 1 << 31,
- CP_BUSY_STAT = 0x867c,
- REG_BUS_FIFO_BUSY_bit = 1 << 0,
- RING_FETCHING_DATA_bit = 1 << 1,
- INDR1_FETCHING_DATA_bit = 1 << 2,
- INDR2_FETCHING_DATA_bit = 1 << 3,
- STATE_FETCHING_DATA_bit = 1 << 4,
- PRED_FETCHING_DATA_bit = 1 << 5,
- COHER_CNTR_NEQ_ZERO_bit = 1 << 6,
- PFP_PARSING_PACKETS_bit = 1 << 7,
- ME_PARSING_PACKETS_bit = 1 << 8,
- RCIU_PFP_BUSY_bit = 1 << 9,
- RCIU_ME_BUSY_bit = 1 << 10,
- OUTSTANDING_READ_TAGS_bit = 1 << 11,
- SEM_CMDFIFO_NOT_EMPTY_bit = 1 << 12,
- SEM_FAILED_AND_HOLDING_bit = 1 << 13,
- SEM_POLLING_FOR_PASS_bit = 1 << 14,
- _3D_BUSY_bit = 1 << 15,
- _2D_BUSY_bit = 1 << 16,
- CP_STAT = 0x8680,
- CSF_RING_BUSY_bit = 1 << 0,
- CSF_WPTR_POLL_BUSY_bit = 1 << 1,
- CSF_INDIRECT1_BUSY_bit = 1 << 2,
- CSF_INDIRECT2_BUSY_bit = 1 << 3,
- CSF_STATE_BUSY_bit = 1 << 4,
- CSF_PREDICATE_BUSY_bit = 1 << 5,
- CSF_BUSY_bit = 1 << 6,
- MIU_RDREQ_BUSY_bit = 1 << 7,
- MIU_WRREQ_BUSY_bit = 1 << 8,
- ROQ_RING_BUSY_bit = 1 << 9,
- ROQ_INDIRECT1_BUSY_bit = 1 << 10,
- ROQ_INDIRECT2_BUSY_bit = 1 << 11,
- ROQ_STATE_BUSY_bit = 1 << 12,
- ROQ_PREDICATE_BUSY_bit = 1 << 13,
- ROQ_ALIGN_BUSY_bit = 1 << 14,
- PFP_BUSY_bit = 1 << 15,
- MEQ_BUSY_bit = 1 << 16,
- ME_BUSY_bit = 1 << 17,
- QUERY_BUSY_bit = 1 << 18,
- SEMAPHORE_BUSY_bit = 1 << 19,
- INTERRUPT_BUSY_bit = 1 << 20,
- SURFACE_SYNC_BUSY_bit = 1 << 21,
- DMA_BUSY_bit = 1 << 22,
- RCIU_BUSY_bit = 1 << 23,
- CP_STAT__CP_BUSY_bit = 1 << 31,
-
- CP_ME_CNTL = 0x86d8,
- ME_STATMUX_mask = 0xff << 0,
- ME_STATMUX_shift = 0,
- ME_HALT_bit = 1 << 28,
- CP_ME_STATUS = 0x86dc,
-
- CP_RB_RPTR = 0x8700,
- RB_RPTR_mask = 0xfffff << 0,
- RB_RPTR_shift = 0,
- CP_RB_WPTR_DELAY = 0x8704,
- PRE_WRITE_TIMER_mask = 0xfffffff << 0,
- PRE_WRITE_TIMER_shift = 0,
- PRE_WRITE_LIMIT_mask = 0x0f << 28,
- PRE_WRITE_LIMIT_shift = 28,
-
- CP_ROQ_RB_STAT = 0x8780,
- ROQ_RPTR_PRIMARY_mask = 0x3ff << 0,
- ROQ_RPTR_PRIMARY_shift = 0,
- ROQ_WPTR_PRIMARY_mask = 0x3ff << 16,
- ROQ_WPTR_PRIMARY_shift = 16,
- CP_ROQ_IB1_STAT = 0x8784,
- ROQ_RPTR_INDIRECT1_mask = 0x3ff << 0,
- ROQ_RPTR_INDIRECT1_shift = 0,
- ROQ_WPTR_INDIRECT1_mask = 0x3ff << 16,
- ROQ_WPTR_INDIRECT1_shift = 16,
- CP_ROQ_IB2_STAT = 0x8788,
- ROQ_RPTR_INDIRECT2_mask = 0x3ff << 0,
- ROQ_RPTR_INDIRECT2_shift = 0,
- ROQ_WPTR_INDIRECT2_mask = 0x3ff << 16,
- ROQ_WPTR_INDIRECT2_shift = 16,
-
- CP_MEQ_STAT = 0x8794,
- MEQ_RPTR_mask = 0x3ff << 0,
- MEQ_RPTR_shift = 0,
- MEQ_WPTR_mask = 0x3ff << 16,
- MEQ_WPTR_shift = 16,
-
- CC_GC_SHADER_PIPE_CONFIG = 0x8950,
- INACTIVE_QD_PIPES_mask = 0xff << 8,
- INACTIVE_QD_PIPES_shift = 8,
- R6XX_MAX_QD_PIPES = 8,
- INACTIVE_SIMDS_mask = 0xff << 16,
- INACTIVE_SIMDS_shift = 16,
- R6XX_MAX_SIMDS = 8,
- GC_USER_SHADER_PIPE_CONFIG = 0x8954,
-
- VC_ENHANCE = 0x9714,
- DB_DEBUG = 0x9830,
- PREZ_MUST_WAIT_FOR_POSTZ_DONE = 1 << 31,
-
- DB_WATERMARKS = 0x00009838,
- DEPTH_FREE_mask = 0x1f << 0,
- DEPTH_FREE_shift = 0,
- DEPTH_FLUSH_mask = 0x3f << 5,
- DEPTH_FLUSH_shift = 5,
- FORCE_SUMMARIZE_mask = 0x0f << 11,
- FORCE_SUMMARIZE_shift = 11,
- DEPTH_PENDING_FREE_mask = 0x1f << 15,
- DEPTH_PENDING_FREE_shift = 15,
- DEPTH_CACHELINE_FREE_mask = 0x1f << 20,
- DEPTH_CACHELINE_FREE_shift = 20,
- EARLY_Z_PANIC_DISABLE_bit = 1 << 25,
- LATE_Z_PANIC_DISABLE_bit = 1 << 26,
- RE_Z_PANIC_DISABLE_bit = 1 << 27,
- DB_EXTRA_DEBUG_mask = 0x0f << 28,
- DB_EXTRA_DEBUG_shift = 28,
-
- CP_RB_BASE = 0xc100,
- CP_RB_CNTL = 0xc104,
- RB_BUFSZ_mask = 0x3f << 0,
- CP_RB_WPTR = 0xc114,
- RB_WPTR_mask = 0xfffff << 0,
- RB_WPTR_shift = 0,
- CP_RB_RPTR_WR = 0xc108,
- RB_RPTR_WR_mask = 0xfffff << 0,
- RB_RPTR_WR_shift = 0,
-
- CP_INT_STATUS = 0xc128,
- DISABLE_CNTX_SWITCH_INT_STAT_bit = 1 << 0,
- ENABLE_CNTX_SWITCH_INT_STAT_bit = 1 << 1,
- SEM_SIGNAL_INT_STAT_bit = 1 << 18,
- CNTX_BUSY_INT_STAT_bit = 1 << 19,
- CNTX_EMPTY_INT_STAT_bit = 1 << 20,
- WAITMEM_SEM_INT_STAT_bit = 1 << 21,
- PRIV_INSTR_INT_STAT_bit = 1 << 22,
- PRIV_REG_INT_STAT_bit = 1 << 23,
- OPCODE_ERROR_INT_STAT_bit = 1 << 24,
- SCRATCH_INT_STAT_bit = 1 << 25,
- TIME_STAMP_INT_STAT_bit = 1 << 26,
- RESERVED_BIT_ERROR_INT_STAT_bit = 1 << 27,
- DMA_INT_STAT_bit = 1 << 28,
- IB2_INT_STAT_bit = 1 << 29,
- IB1_INT_STAT_bit = 1 << 30,
- RB_INT_STAT_bit = 1 << 31,
-
-// SX_ALPHA_TEST_CONTROL = 0x00028410,
- ALPHA_FUNC__REF_NEVER = 0,
- ALPHA_FUNC__REF_ALWAYS = 7,
-// DB_SHADER_CONTROL = 0x0002880c,
- Z_ORDER__EARLY_Z_THEN_LATE_Z = 2,
-// PA_SU_SC_MODE_CNTL = 0x00028814,
-// POLY_MODE_mask = 0x03 << 3,
- POLY_MODE__TRIANGLES = 0, POLY_MODE__DUAL_MODE,
-// POLYMODE_FRONT_PTYPE_mask = 0x07 << 5,
- POLYMODE_PTYPE__POINTS = 0, POLYMODE_PTYPE__LINES, POLYMODE_PTYPE__TRIANGLES,
- PA_SC_AA_SAMPLE_LOCS_8S_WD1_M = 0x00028c20,
- DB_SRESULTS_COMPARE_STATE0 = 0x00028d28, /* See autoregs: DB_SRESULTS_COMPARE_STATE1 */
-// DB_SRESULTS_COMPARE_STATE1 = 0x00028d2c,
- DB_ALPHA_TO_MASK = 0x00028d44,
- ALPHA_TO_MASK_ENABLE = 1 << 0,
- ALPHA_TO_MASK_OFFSET0_mask = 0x03 << 8,
- ALPHA_TO_MASK_OFFSET0_shift = 8,
- ALPHA_TO_MASK_OFFSET1_mask = 0x03 << 10,
- ALPHA_TO_MASK_OFFSET1_shift = 10,
- ALPHA_TO_MASK_OFFSET2_mask = 0x03 << 12,
- ALPHA_TO_MASK_OFFSET2_shift = 12,
- ALPHA_TO_MASK_OFFSET3_mask = 0x03 << 14,
- ALPHA_TO_MASK_OFFSET3_shift = 14,
-
-// SQ_VTX_CONSTANT_WORD2_0 = 0x00038008,
-// SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_mask = 0x3f << 20,
- FMT_INVALID=0, FMT_8, FMT_4_4, FMT_3_3_2,
- FMT_16=5, FMT_16_FLOAT, FMT_8_8,
- FMT_5_6_5, FMT_6_5_5, FMT_1_5_5_5, FMT_4_4_4_4,
- FMT_5_5_5_1, FMT_32, FMT_32_FLOAT, FMT_16_16,
- FMT_16_16_FLOAT=16, FMT_8_24, FMT_8_24_FLOAT, FMT_24_8,
- FMT_24_8_FLOAT, FMT_10_11_11, FMT_10_11_11_FLOAT, FMT_11_11_10,
- FMT_11_11_10_FLOAT, FMT_2_10_10_10, FMT_8_8_8_8, FMT_10_10_10_2,
- FMT_X24_8_32_FLOAT, FMT_32_32, FMT_32_32_FLOAT, FMT_16_16_16_16,
- FMT_16_16_16_16_FLOAT=32, FMT_32_32_32_32=34, FMT_32_32_32_32_FLOAT,
- FMT_1 = 37, FMT_GB_GR=39,
- FMT_BG_RG, FMT_32_AS_8, FMT_32_AS_8_8, FMT_5_9_9_9_SHAREDEXP,
- FMT_8_8_8, FMT_16_16_16, FMT_16_16_16_FLOAT, FMT_32_32_32,
- FMT_32_32_32_FLOAT=48,
-
-// High level register file lengths
- SQ_ALU_CONSTANT = SQ_ALU_CONSTANT0_0, /* 256 PS, 256 VS */
- SQ_ALU_CONSTANT_ps_num = 256,
- SQ_ALU_CONSTANT_vs_num = 256,
- SQ_ALU_CONSTANT_all_num = 512,
- SQ_ALU_CONSTANT_offset = 16,
- SQ_ALU_CONSTANT_ps = 0,
- SQ_ALU_CONSTANT_vs = SQ_ALU_CONSTANT_ps + SQ_ALU_CONSTANT_ps_num,
- SQ_TEX_RESOURCE = SQ_TEX_RESOURCE_WORD0_0, /* 160 PS, 160 VS, 16 FS, 160 GS */
- SQ_TEX_RESOURCE_ps_num = 160,
- SQ_TEX_RESOURCE_vs_num = 160,
- SQ_TEX_RESOURCE_fs_num = 16,
- SQ_TEX_RESOURCE_gs_num = 160,
- SQ_TEX_RESOURCE_all_num = 496,
- SQ_TEX_RESOURCE_offset = 28,
- SQ_TEX_RESOURCE_ps = 0,
- SQ_TEX_RESOURCE_vs = SQ_TEX_RESOURCE_ps + SQ_TEX_RESOURCE_ps_num,
- SQ_TEX_RESOURCE_fs = SQ_TEX_RESOURCE_vs + SQ_TEX_RESOURCE_vs_num,
- SQ_TEX_RESOURCE_gs = SQ_TEX_RESOURCE_fs + SQ_TEX_RESOURCE_fs_num,
- SQ_VTX_RESOURCE = SQ_VTX_CONSTANT_WORD0_0, /* 160 PS, 160 VS, 16 FS, 160 GS */
- SQ_VTX_RESOURCE_ps_num = 160,
- SQ_VTX_RESOURCE_vs_num = 160,
- SQ_VTX_RESOURCE_fs_num = 16,
- SQ_VTX_RESOURCE_gs_num = 160,
- SQ_VTX_RESOURCE_all_num = 496,
- SQ_VTX_RESOURCE_offset = 28,
- SQ_VTX_RESOURCE_ps = 0,
- SQ_VTX_RESOURCE_vs = SQ_VTX_RESOURCE_ps + SQ_VTX_RESOURCE_ps_num,
- SQ_VTX_RESOURCE_fs = SQ_VTX_RESOURCE_vs + SQ_VTX_RESOURCE_vs_num,
- SQ_VTX_RESOURCE_gs = SQ_VTX_RESOURCE_fs + SQ_VTX_RESOURCE_fs_num,
- SQ_TEX_SAMPLER_WORD = SQ_TEX_SAMPLER_WORD0_0, /* 18 per PS, VS, GS */
- SQ_TEX_SAMPLER_WORD_ps_num = 18,
- SQ_TEX_SAMPLER_WORD_vs_num = 18,
- SQ_TEX_SAMPLER_WORD_gs_num = 18,
- SQ_TEX_SAMPLER_WORD_all_num = 54,
- SQ_TEX_SAMPLER_WORD_offset = 12,
- SQ_TEX_SAMPLER_WORD_ps = 0,
- SQ_TEX_SAMPLER_WORD_vs = SQ_TEX_SAMPLER_WORD_ps + SQ_TEX_SAMPLER_WORD_ps_num,
- SQ_TEX_SAMPLER_WORD_gs = SQ_TEX_SAMPLER_WORD_vs + SQ_TEX_SAMPLER_WORD_vs_num,
- SQ_LOOP_CONST = SQ_LOOP_CONST_0, /* 32 per PS, VS, GS */
- SQ_LOOP_CONST_ps_num = 32,
- SQ_LOOP_CONST_vs_num = 32,
- SQ_LOOP_CONST_gs_num = 32,
- SQ_LOOP_CONST_all_num = 96,
- SQ_LOOP_CONST_offset = 4,
- SQ_LOOP_CONST_ps = 0,
- SQ_LOOP_CONST_vs = SQ_LOOP_CONST_ps + SQ_LOOP_CONST_ps_num,
- SQ_LOOP_CONST_gs = SQ_LOOP_CONST_vs + SQ_LOOP_CONST_vs_num,
-} ;
-
-
-#endif
+++ /dev/null
-/*
- * RadeonHD R6xx, R7xx Register documentation
- *
- * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
- * Copyright (C) 2008-2009 Matthias Hopf
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef _R600_REG_R7xx_H_
-#define _R600_REG_R7xx_H_
-
-/*
- * Register update for R7xx chips
- */
-
-enum {
-
- R7XX_MC_VM_FB_LOCATION = 0x00002024,
-
-// GRBM_STATUS = 0x00008010,
- R7XX_TA_BUSY_bit = 1 << 14,
-
- R7xx_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ = 0x00008d8c,
- RING0_OFFSET_mask = 0xff << 0,
- RING0_OFFSET_shift = 0,
- ISOLATE_ES_ENABLE_bit = 1 << 12,
- ISOLATE_GS_ENABLE_bit = 1 << 13,
- VS_PC_LIMIT_ENABLE_bit = 1 << 14,
-
-// SQ_ALU_WORD0 = 0x00008dfc,
-// SRC0_SEL_mask = 0x1ff << 0,
-// SRC1_SEL_mask = 0x1ff << 13,
- R7xx_SQ_ALU_SRC_1_DBL_L = 0xf4,
- R7xx_SQ_ALU_SRC_1_DBL_M = 0xf5,
- R7xx_SQ_ALU_SRC_0_5_DBL_L = 0xf6,
- R7xx_SQ_ALU_SRC_0_5_DBL_M = 0xf7,
-// INDEX_MODE_mask = 0x07 << 26,
- R7xx_SQ_INDEX_GLOBAL = 0x05,
- R7xx_SQ_INDEX_GLOBAL_AR_X = 0x06,
- R6xx_SQ_ALU_WORD1_OP2 = 0x00008dfc,
- R7xx_SQ_ALU_WORD1_OP2_V2 = 0x00008dfc,
- R6xx_FOG_MERGE_bit = 1 << 5,
- R6xx_OMOD_mask = 0x03 << 6,
- R7xx_OMOD_mask = 0x03 << 5,
- R6xx_OMOD_shift = 6,
- R7xx_OMOD_shift = 5,
- R6xx_SQ_ALU_WORD1_OP2__ALU_INST_mask = 0x3ff << 8,
- R7xx_SQ_ALU_WORD1_OP2_V2__ALU_INST_mask = 0x7ff << 7,
- R6xx_SQ_ALU_WORD1_OP2__ALU_INST_shift = 8,
- R7xx_SQ_ALU_WORD1_OP2_V2__ALU_INST_shift = 7,
- R7xx_SQ_OP2_INST_FREXP_64 = 0x07,
- R7xx_SQ_OP2_INST_ADD_64 = 0x17,
- R7xx_SQ_OP2_INST_MUL_64 = 0x1b,
- R7xx_SQ_OP2_INST_FLT64_TO_FLT32 = 0x1c,
- R7xx_SQ_OP2_INST_FLT32_TO_FLT64 = 0x1d,
- R7xx_SQ_OP2_INST_LDEXP_64 = 0x7a,
- R7xx_SQ_OP2_INST_FRACT_64 = 0x7b,
- R7xx_SQ_OP2_INST_PRED_SETGT_64 = 0x7c,
- R7xx_SQ_OP2_INST_PRED_SETE_64 = 0x7d,
- R7xx_SQ_OP2_INST_PRED_SETGE_64 = 0x7e,
-// SQ_ALU_WORD1_OP3 = 0x00008dfc,
-// SRC2_SEL_mask = 0x1ff << 0,
-// R7xx_SQ_ALU_SRC_1_DBL_L = 0xf4,
-// R7xx_SQ_ALU_SRC_1_DBL_M = 0xf5,
-// R7xx_SQ_ALU_SRC_0_5_DBL_L = 0xf6,
-// R7xx_SQ_ALU_SRC_0_5_DBL_M = 0xf7,
-// SQ_ALU_WORD1_OP3__ALU_INST_mask = 0x1f << 13,
- R7xx_SQ_OP3_INST_MULADD_64 = 0x08,
- R7xx_SQ_OP3_INST_MULADD_64_M2 = 0x09,
- R7xx_SQ_OP3_INST_MULADD_64_M4 = 0x0a,
- R7xx_SQ_OP3_INST_MULADD_64_D2 = 0x0b,
-// SQ_CF_ALU_WORD1 = 0x00008dfc,
- R6xx_USES_WATERFALL_bit = 1 << 25,
- R7xx_SQ_CF_ALU_WORD1__ALT_CONST_bit = 1 << 25,
-// SQ_CF_ALLOC_EXPORT_WORD0 = 0x00008dfc,
-// ARRAY_BASE_mask = 0x1fff << 0,
-// TYPE_mask = 0x03 << 13,
-// SQ_EXPORT_PARAM = 0x02,
-// X_UNUSED_FOR_SX_EXPORTS = 0x03,
-// ELEM_SIZE_mask = 0x03 << 30,
-// SQ_CF_ALLOC_EXPORT_WORD1 = 0x00008dfc,
-// SQ_CF_ALLOC_EXPORT_WORD1__CF_INST_mask = 0x7f << 23,
- R7xx_SQ_CF_INST_MEM_EXPORT = 0x3a,
-// SQ_CF_WORD1 = 0x00008dfc,
-// SQ_CF_WORD1__COUNT_mask = 0x07 << 10,
- R7xx_COUNT_3_bit = 1 << 19,
-// SQ_CF_WORD1__CF_INST_mask = 0x7f << 23,
- R7xx_SQ_CF_INST_END_PROGRAM = 0x19,
- R7xx_SQ_CF_INST_WAIT_ACK = 0x1a,
- R7xx_SQ_CF_INST_TEX_ACK = 0x1b,
- R7xx_SQ_CF_INST_VTX_ACK = 0x1c,
- R7xx_SQ_CF_INST_VTX_TC_ACK = 0x1d,
-// SQ_VTX_WORD0 = 0x00008dfc,
-// VTX_INST_mask = 0x1f << 0,
- R7xx_SQ_VTX_INST_MEM = 0x02,
-// SQ_VTX_WORD2 = 0x00008dfc,
- R7xx_SQ_VTX_WORD2__ALT_CONST_bit = 1 << 20,
-
-// SQ_TEX_WORD0 = 0x00008dfc,
-// TEX_INST_mask = 0x1f << 0,
- R7xx_X_MEMORY_READ = 0x02,
- R7xx_SQ_TEX_INST_KEEP_GRADIENTS = 0x0a,
- R7xx_X_FETCH4_LOAD4_INSTRUCTION_FOR_DX10_1 = 0x0f,
- R7xx_SQ_TEX_WORD0__ALT_CONST_bit = 1 << 24,
-
- R7xx_PA_SC_EDGERULE = 0x00028230,
- R7xx_SPI_THREAD_GROUPING = 0x000286c8,
- PS_GROUPING_mask = 0x1f << 0,
- PS_GROUPING_shift = 0,
- VS_GROUPING_mask = 0x1f << 8,
- VS_GROUPING_shift = 8,
- GS_GROUPING_mask = 0x1f << 16,
- GS_GROUPING_shift = 16,
- ES_GROUPING_mask = 0x1f << 24,
- ES_GROUPING_shift = 24,
- R7xx_CB_SHADER_CONTROL = 0x000287a0,
- RT0_ENABLE_bit = 1 << 0,
- RT1_ENABLE_bit = 1 << 1,
- RT2_ENABLE_bit = 1 << 2,
- RT3_ENABLE_bit = 1 << 3,
- RT4_ENABLE_bit = 1 << 4,
- RT5_ENABLE_bit = 1 << 5,
- RT6_ENABLE_bit = 1 << 6,
- RT7_ENABLE_bit = 1 << 7,
-// DB_ALPHA_TO_MASK = 0x00028d44,
- R7xx_OFFSET_ROUND_bit = 1 << 16,
-// SQ_TEX_SAMPLER_MISC_0 = 0x0003d03c,
- R7xx_TRUNCATE_COORD_bit = 1 << 9,
- R7xx_DISABLE_CUBE_WRAP_bit = 1 << 10,
-// DB_RENDER_CONTROL = 0x00028d0c,
- PERFECT_ZPASS_COUNTS_bit = 1 << 15,
-
-} ;
-
-#endif /* _R600_REG_R7xx_H_ */
+++ /dev/null
-/*
-Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
-
-The Weather Channel (TM) funded Tungsten Graphics to develop the
-initial release of the Radeon 8500 driver under the XFree86 license.
-This notice must be preserved.
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-*/
-
-/**
- * \file
- *
- * \author Keith Whitwell <keith@tungstengraphics.com>
- */
-
-#include "main/glheader.h"
-#include "main/imports.h"
-#include "main/colormac.h"
-#include "main/context.h"
-#include "main/enums.h"
-#include "main/image.h"
-#include "main/mfeatures.h"
-#include "main/mipmap.h"
-#include "main/simple_list.h"
-#include "main/texobj.h"
-
-#include "texmem.h"
-
-#include "r600_context.h"
-#include "radeon_mipmap_tree.h"
-#include "r600_tex.h"
-
-
-static unsigned int translate_wrap_mode(GLenum wrapmode)
-{
- switch(wrapmode) {
- case GL_REPEAT: return SQ_TEX_WRAP;
- case GL_CLAMP: return SQ_TEX_CLAMP_HALF_BORDER;
- case GL_CLAMP_TO_EDGE: return SQ_TEX_CLAMP_LAST_TEXEL;
- case GL_CLAMP_TO_BORDER: return SQ_TEX_CLAMP_BORDER;
- case GL_MIRRORED_REPEAT: return SQ_TEX_MIRROR;
- case GL_MIRROR_CLAMP_EXT: return SQ_TEX_MIRROR_ONCE_HALF_BORDER;
- case GL_MIRROR_CLAMP_TO_EDGE_EXT: return SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
- case GL_MIRROR_CLAMP_TO_BORDER_EXT: return SQ_TEX_MIRROR_ONCE_BORDER;
- default:
- radeon_error("bad wrap mode in %s", __FUNCTION__);
- return 0;
- }
-}
-
-
-/**
- * Update the cached hardware registers based on the current texture wrap modes.
- *
- * \param t Texture object whose wrap modes are to be set
- */
-static void r600UpdateTexWrap(radeonTexObjPtr t)
-{
- struct gl_texture_object *tObj = &t->base;
-
- SETfield(t->SQ_TEX_SAMPLER0, translate_wrap_mode(tObj->Sampler.WrapS),
- SQ_TEX_SAMPLER_WORD0_0__CLAMP_X_shift, SQ_TEX_SAMPLER_WORD0_0__CLAMP_X_mask);
-
- if (tObj->Target != GL_TEXTURE_1D) {
- SETfield(t->SQ_TEX_SAMPLER0, translate_wrap_mode(tObj->Sampler.WrapT),
- CLAMP_Y_shift, CLAMP_Y_mask);
-
- if (tObj->Target == GL_TEXTURE_3D)
- SETfield(t->SQ_TEX_SAMPLER0, translate_wrap_mode(tObj->Sampler.WrapR),
- CLAMP_Z_shift, CLAMP_Z_mask);
- }
-}
-
-static void r600SetTexDefaultState(radeonTexObjPtr t)
-{
- /* Init text object to default states. */
- t->SQ_TEX_RESOURCE0 = 0;
- SETfield(t->SQ_TEX_RESOURCE0, SQ_TEX_DIM_2D, DIM_shift, DIM_mask);
- SETfield(t->SQ_TEX_RESOURCE0, ARRAY_LINEAR_GENERAL,
- SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift, SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask);
- CLEARbit(t->SQ_TEX_RESOURCE0, TILE_TYPE_bit);
-
- t->SQ_TEX_RESOURCE1 = 0;
- SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8_8_8,
- SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
-
- t->SQ_TEX_RESOURCE2 = 0;
- t->SQ_TEX_RESOURCE3 = 0;
-
- t->SQ_TEX_RESOURCE4 = 0;
- SETfield(t->SQ_TEX_RESOURCE4, SQ_FORMAT_COMP_UNSIGNED,
- FORMAT_COMP_X_shift, FORMAT_COMP_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_FORMAT_COMP_UNSIGNED,
- FORMAT_COMP_Y_shift, FORMAT_COMP_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_FORMAT_COMP_UNSIGNED,
- FORMAT_COMP_Z_shift, FORMAT_COMP_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_FORMAT_COMP_UNSIGNED,
- FORMAT_COMP_W_shift, FORMAT_COMP_W_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_NUM_FORMAT_NORM,
- SQ_TEX_RESOURCE_WORD4_0__NUM_FORMAT_ALL_shift, SQ_TEX_RESOURCE_WORD4_0__NUM_FORMAT_ALL_mask);
- CLEARbit(t->SQ_TEX_RESOURCE4, SQ_TEX_RESOURCE_WORD4_0__SRF_MODE_ALL_bit);
- CLEARbit(t->SQ_TEX_RESOURCE4, SQ_TEX_RESOURCE_WORD4_0__FORCE_DEGAMMA_bit);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_ENDIAN_NONE,
- SQ_TEX_RESOURCE_WORD4_0__ENDIAN_SWAP_shift, SQ_TEX_RESOURCE_WORD4_0__ENDIAN_SWAP_mask);
- SETfield(t->SQ_TEX_RESOURCE4, 1, REQUEST_SIZE_shift, REQUEST_SIZE_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- SETfield(t->SQ_TEX_RESOURCE4, 0, BASE_LEVEL_shift, BASE_LEVEL_mask); /* mip-maps */
-
- t->SQ_TEX_RESOURCE5 = 0;
- t->SQ_TEX_RESOURCE6 = 0;
-
- SETfield(t->SQ_TEX_RESOURCE6, SQ_TEX_VTX_VALID_TEXTURE,
- SQ_TEX_RESOURCE_WORD6_0__TYPE_shift, SQ_TEX_RESOURCE_WORD6_0__TYPE_mask);
-
- /* Initialize sampler registers */
- t->SQ_TEX_SAMPLER0 = 0;
- SETfield(t->SQ_TEX_SAMPLER0, SQ_TEX_WRAP, SQ_TEX_SAMPLER_WORD0_0__CLAMP_X_shift,
- SQ_TEX_SAMPLER_WORD0_0__CLAMP_X_mask);
- SETfield(t->SQ_TEX_SAMPLER0, SQ_TEX_WRAP, CLAMP_Y_shift, CLAMP_Y_mask);
- SETfield(t->SQ_TEX_SAMPLER0, SQ_TEX_WRAP, CLAMP_Z_shift, CLAMP_Z_mask);
- SETfield(t->SQ_TEX_SAMPLER0, SQ_TEX_XY_FILTER_POINT, XY_MAG_FILTER_shift, XY_MAG_FILTER_mask);
- SETfield(t->SQ_TEX_SAMPLER0, SQ_TEX_XY_FILTER_POINT, XY_MIN_FILTER_shift, XY_MIN_FILTER_mask);
- SETfield(t->SQ_TEX_SAMPLER0, SQ_TEX_Z_FILTER_NONE, Z_FILTER_shift, Z_FILTER_mask);
- SETfield(t->SQ_TEX_SAMPLER0, SQ_TEX_Z_FILTER_NONE, MIP_FILTER_shift, MIP_FILTER_mask);
- SETfield(t->SQ_TEX_SAMPLER0, SQ_TEX_BORDER_COLOR_TRANS_BLACK, BORDER_COLOR_TYPE_shift, BORDER_COLOR_TYPE_mask);
-
- t->SQ_TEX_SAMPLER1 = 0;
- SETfield(t->SQ_TEX_SAMPLER1, 0x3ff, MAX_LOD_shift, MAX_LOD_mask);
-
- t->SQ_TEX_SAMPLER2 = 0;
- SETbit(t->SQ_TEX_SAMPLER2, SQ_TEX_SAMPLER_WORD2_0__TYPE_bit);
-}
-
-
-#if 0
-static GLuint aniso_filter(GLfloat anisotropy)
-{
- if (anisotropy >= 16.0) {
- return R300_TX_MAX_ANISO_16_TO_1;
- } else if (anisotropy >= 8.0) {
- return R300_TX_MAX_ANISO_8_TO_1;
- } else if (anisotropy >= 4.0) {
- return R300_TX_MAX_ANISO_4_TO_1;
- } else if (anisotropy >= 2.0) {
- return R300_TX_MAX_ANISO_2_TO_1;
- } else {
- return R300_TX_MAX_ANISO_1_TO_1;
- }
- return 0;
-}
-#endif
-
-/**
- * Set the texture magnification and minification modes.
- *
- * \param t Texture whose filter modes are to be set
- * \param minf Texture minification mode
- * \param magf Texture magnification mode
- * \param anisotropy Maximum anisotropy level
- */
-static void r600SetTexFilter(radeonTexObjPtr t, GLenum minf, GLenum magf, GLfloat anisotropy)
-{
- /* Force revalidation to account for switches from/to mipmapping. */
- t->validated = GL_FALSE;
-
- /* Note that EXT_texture_filter_anisotropic is extremely vague about
- * how anisotropic filtering interacts with the "normal" filter modes.
- * When anisotropic filtering is enabled, we override min and mag
- * filter settings completely. This includes driconf's settings.
- */
- if (anisotropy >= 2.0 && (minf != GL_NEAREST) && (magf != GL_NEAREST)) {
- /*t->pp_txfilter |= R300_TX_MAG_FILTER_ANISO
- | R300_TX_MIN_FILTER_ANISO
- | R300_TX_MIN_FILTER_MIP_LINEAR
- | aniso_filter(anisotropy);*/
- radeon_print(RADEON_TEXTURE, RADEON_NORMAL, "Using maximum anisotropy of %f\n", anisotropy);
- return;
- }
-
- switch (minf) {
- case GL_NEAREST:
- SETfield(t->SQ_TEX_SAMPLER0, TEX_XYFilter_Point,
- XY_MIN_FILTER_shift, XY_MIN_FILTER_mask);
- SETfield(t->SQ_TEX_SAMPLER0, TEX_MipFilter_None,
- MIP_FILTER_shift, MIP_FILTER_mask);
- break;
- case GL_LINEAR:
- SETfield(t->SQ_TEX_SAMPLER0, TEX_XYFilter_Linear,
- XY_MIN_FILTER_shift, XY_MIN_FILTER_mask);
- SETfield(t->SQ_TEX_SAMPLER0, TEX_MipFilter_None,
- MIP_FILTER_shift, MIP_FILTER_mask);
- break;
- case GL_NEAREST_MIPMAP_NEAREST:
- SETfield(t->SQ_TEX_SAMPLER0, TEX_XYFilter_Point,
- XY_MIN_FILTER_shift, XY_MIN_FILTER_mask);
- SETfield(t->SQ_TEX_SAMPLER0, TEX_MipFilter_Point,
- MIP_FILTER_shift, MIP_FILTER_mask);
- break;
- case GL_NEAREST_MIPMAP_LINEAR:
- SETfield(t->SQ_TEX_SAMPLER0, TEX_XYFilter_Point,
- XY_MIN_FILTER_shift, XY_MIN_FILTER_mask);
- SETfield(t->SQ_TEX_SAMPLER0, TEX_MipFilter_Linear,
- MIP_FILTER_shift, MIP_FILTER_mask);
- break;
- case GL_LINEAR_MIPMAP_NEAREST:
- SETfield(t->SQ_TEX_SAMPLER0, TEX_XYFilter_Linear,
- XY_MIN_FILTER_shift, XY_MIN_FILTER_mask);
- SETfield(t->SQ_TEX_SAMPLER0, TEX_MipFilter_Point,
- MIP_FILTER_shift, MIP_FILTER_mask);
- break;
- case GL_LINEAR_MIPMAP_LINEAR:
- SETfield(t->SQ_TEX_SAMPLER0, TEX_XYFilter_Linear,
- XY_MIN_FILTER_shift, XY_MIN_FILTER_mask);
- SETfield(t->SQ_TEX_SAMPLER0, TEX_MipFilter_Linear,
- MIP_FILTER_shift, MIP_FILTER_mask);
- break;
- }
-
- /* Note we don't have 3D mipmaps so only use the mag filter setting
- * to set the 3D texture filter mode.
- */
- switch (magf) {
- case GL_NEAREST:
- SETfield(t->SQ_TEX_SAMPLER0, TEX_XYFilter_Point,
- XY_MAG_FILTER_shift, XY_MAG_FILTER_mask);
- break;
- case GL_LINEAR:
- SETfield(t->SQ_TEX_SAMPLER0, TEX_XYFilter_Linear,
- XY_MAG_FILTER_shift, XY_MAG_FILTER_mask);
- break;
- }
-}
-
-static void r600SetTexBorderColor(radeonTexObjPtr t, const GLfloat color[4])
-{
- t->TD_PS_SAMPLER0_BORDER_ALPHA = *((uint32_t*)&(color[3]));
- t->TD_PS_SAMPLER0_BORDER_BLUE = *((uint32_t*)&(color[2]));
- t->TD_PS_SAMPLER0_BORDER_GREEN = *((uint32_t*)&(color[1]));
- t->TD_PS_SAMPLER0_BORDER_RED = *((uint32_t*)&(color[0]));
- SETfield(t->SQ_TEX_SAMPLER0, SQ_TEX_BORDER_COLOR_REGISTER,
- BORDER_COLOR_TYPE_shift, BORDER_COLOR_TYPE_mask);
-}
-
-/**
- * Changes variables and flags for a state update, which will happen at the
- * next UpdateTextureState
- */
-
-static void r600TexParameter(struct gl_context * ctx, GLenum target,
- struct gl_texture_object *texObj,
- GLenum pname, const GLfloat * params)
-{
- radeonTexObj* t = radeon_tex_obj(texObj);
- GLenum baseFormat;
-
- radeon_print(RADEON_STATE | RADEON_TEXTURE, RADEON_VERBOSE,
- "%s( %s )\n", __FUNCTION__,
- _mesa_lookup_enum_by_nr(pname));
-
- switch (pname) {
- case GL_TEXTURE_MIN_FILTER:
- case GL_TEXTURE_MAG_FILTER:
- case GL_TEXTURE_MAX_ANISOTROPY_EXT:
- r600SetTexFilter(t, texObj->Sampler.MinFilter, texObj->Sampler.MagFilter, texObj->Sampler.MaxAnisotropy);
- break;
-
- case GL_TEXTURE_WRAP_S:
- case GL_TEXTURE_WRAP_T:
- case GL_TEXTURE_WRAP_R:
- r600UpdateTexWrap(t);
- break;
-
- case GL_TEXTURE_BORDER_COLOR:
- r600SetTexBorderColor(t, texObj->Sampler.BorderColor.f);
- break;
-
- case GL_TEXTURE_BASE_LEVEL:
- case GL_TEXTURE_MAX_LEVEL:
- case GL_TEXTURE_MIN_LOD:
- case GL_TEXTURE_MAX_LOD:
- t->validated = GL_FALSE;
- break;
-
- case GL_DEPTH_TEXTURE_MODE:
- if (!texObj->Image[0][texObj->BaseLevel])
- return;
- baseFormat = texObj->Image[0][texObj->BaseLevel]->_BaseFormat;
- if (baseFormat == GL_DEPTH_COMPONENT ||
- baseFormat == GL_DEPTH_STENCIL) {
- r600SetDepthTexMode(texObj);
- break;
- } else {
- /* If the texture isn't a depth texture, changing this
- * state won't cause any changes to the hardware.
- * Don't force a flush of texture state.
- */
- return;
- }
-
- default:
- return;
- }
-}
-
-static void r600DeleteTexture(struct gl_context * ctx, struct gl_texture_object *texObj)
-{
- context_t* rmesa = R700_CONTEXT(ctx);
- radeonTexObj* t = radeon_tex_obj(texObj);
-
- radeon_print(RADEON_STATE | RADEON_TEXTURE, RADEON_NORMAL,
- "%s( %p (target = %s) )\n", __FUNCTION__,
- (void *)texObj,
- _mesa_lookup_enum_by_nr(texObj->Target));
-
- if (rmesa) {
- int i;
- radeon_firevertices(&rmesa->radeon);
-
- for(i = 0; i < R700_MAX_TEXTURE_UNITS; ++i)
- if (rmesa->hw.textures[i] == t)
- rmesa->hw.textures[i] = 0;
- }
-
- if (t->bo) {
- radeon_bo_unref(t->bo);
- t->bo = NULL;
- }
-
- radeon_miptree_unreference(&t->mt);
-
- _mesa_delete_texture_object(ctx, texObj);
-}
-
-/**
- * Allocate a new texture object.
- * Called via ctx->Driver.NewTextureObject.
- * Note: this function will be called during context creation to
- * allocate the default texture objects.
- * Fixup MaxAnisotropy according to user preference.
- */
-static struct gl_texture_object *r600NewTextureObject(struct gl_context * ctx,
- GLuint name,
- GLenum target)
-{
- context_t* rmesa = R700_CONTEXT(ctx);
- radeonTexObj* t = CALLOC_STRUCT(radeon_tex_obj);
-
-
- radeon_print(RADEON_STATE | RADEON_TEXTURE, RADEON_NORMAL,
- "%s( %p (target = %s) )\n", __FUNCTION__,
- t, _mesa_lookup_enum_by_nr(target));
-
- _mesa_initialize_texture_object(&t->base, name, target);
- t->base.Sampler.MaxAnisotropy = rmesa->radeon.initialMaxAnisotropy;
-
- /* Initialize hardware state */
- r600SetTexDefaultState(t);
- r600UpdateTexWrap(t);
- r600SetTexFilter(t, t->base.Sampler.MinFilter, t->base.Sampler.MagFilter, t->base.Sampler.MaxAnisotropy);
- r600SetTexBorderColor(t, t->base.Sampler.BorderColor.f);
-
- return &t->base;
-}
-
-unsigned r600IsFormatRenderable(gl_format mesa_format)
-{
- switch (mesa_format) {
- case MESA_FORMAT_RGBA8888:
- case MESA_FORMAT_SIGNED_RGBA8888:
- case MESA_FORMAT_RGBA8888_REV:
- case MESA_FORMAT_SIGNED_RGBA8888_REV:
- case MESA_FORMAT_ARGB8888:
- case MESA_FORMAT_XRGB8888:
- case MESA_FORMAT_ARGB8888_REV:
- case MESA_FORMAT_XRGB8888_REV:
- case MESA_FORMAT_RGB565:
- case MESA_FORMAT_RGB565_REV:
- case MESA_FORMAT_ARGB4444:
- case MESA_FORMAT_ARGB4444_REV:
- case MESA_FORMAT_ARGB1555:
- case MESA_FORMAT_ARGB1555_REV:
- case MESA_FORMAT_AL88:
- case MESA_FORMAT_AL88_REV:
- case MESA_FORMAT_RGB332:
- case MESA_FORMAT_A8:
- case MESA_FORMAT_I8:
- case MESA_FORMAT_L8:
- case MESA_FORMAT_RGBA_FLOAT32:
- case MESA_FORMAT_RGBA_FLOAT16:
- case MESA_FORMAT_ALPHA_FLOAT32:
- case MESA_FORMAT_ALPHA_FLOAT16:
- case MESA_FORMAT_LUMINANCE_FLOAT32:
- case MESA_FORMAT_LUMINANCE_FLOAT16:
- case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32:
- case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16:
- case MESA_FORMAT_INTENSITY_FLOAT32: /* X, X, X, X */
- case MESA_FORMAT_INTENSITY_FLOAT16: /* X, X, X, X */
- case MESA_FORMAT_X8_Z24:
- case MESA_FORMAT_S8_Z24:
- case MESA_FORMAT_Z24_S8:
- case MESA_FORMAT_Z16:
- case MESA_FORMAT_Z32:
- case MESA_FORMAT_SARGB8:
- case MESA_FORMAT_SLA8:
- case MESA_FORMAT_SL8:
- return 1;
- default:
- return 0;
- }
-}
-
-void r600InitTextureFuncs(radeonContextPtr radeon, struct dd_function_table *functions)
-{
- /* Note: we only plug in the functions we implement in the driver
- * since _mesa_init_driver_functions() was already called.
- */
-
- radeon_init_common_texture_funcs(radeon, functions);
-
- functions->NewTextureObject = r600NewTextureObject;
- functions->DeleteTexture = r600DeleteTexture;
- functions->IsTextureResident = driIsTextureResident;
-
- functions->TexParameter = r600TexParameter;
-}
+++ /dev/null
-/*
-Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
-
-The Weather Channel (TM) funded Tungsten Graphics to develop the
-initial release of the Radeon 8500 driver under the XFree86 license.
-This notice must be preserved.
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-**************************************************************************/
-
-/*
- * Authors:
- * Keith Whitwell <keith@tungstengraphics.com>
- */
-
-#ifndef __r600_TEX_H__
-#define __r600_TEX_H__
-
-/* TODO : review this after texture load code. */
-#define R700_BLIT_WIDTH_BYTES 1024
-/* The BASE_ADDRESS and MIP_ADDRESS fields are 256-byte-aligned */
-#define R700_TEXTURE_ALIGNMENT_MASK 0x255
-/* Texel pitch is 8 alignment. */
-#define R700_TEXEL_PITCH_ALIGNMENT_MASK 0x7
-
-#define R700_MAX_TEXTURE_UNITS 16
-
-extern void r600SetDepthTexMode(struct gl_texture_object *tObj);
-
-extern void r600SetTexBuffer(__DRIcontext *pDRICtx, GLint target,
- __DRIdrawable *dPriv);
-
-extern void r600SetTexBuffer2(__DRIcontext *pDRICtx, GLint target,
- GLint format, __DRIdrawable *dPriv);
-
-extern void r600SetTexOffset(__DRIcontext *pDRICtx, GLint texname,
- unsigned long long offset, GLint depth,
- GLuint pitch);
-
-extern GLboolean r600ValidateBuffers(struct gl_context * ctx);
-
-extern void r600InitTextureFuncs(radeonContextPtr radeon, struct dd_function_table *functions);
-
-unsigned r600IsFormatRenderable(gl_format mesa_format);
-
-#endif /* __r600_TEX_H__ */
+++ /dev/null
-/*
-Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
-
-The Weather Channel (TM) funded Tungsten Graphics to develop the
-initial release of the Radeon 8500 driver under the XFree86 license.
-This notice must be preserved.
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-**************************************************************************/
-
-/**
- * \file
- *
- * \author Keith Whitwell <keith@tungstengraphics.com>
- *
- * \todo Enable R300 texture tiling code?
- */
-
-#include "main/glheader.h"
-#include "main/imports.h"
-#include "main/context.h"
-#include "main/macros.h"
-#include "main/teximage.h"
-#include "main/texobj.h"
-#include "main/enums.h"
-#include "main/simple_list.h"
-
-#include "r600_context.h"
-#include "radeon_mipmap_tree.h"
-#include "r600_tex.h"
-#include "r700_fragprog.h"
-#include "r700_vertprog.h"
-
-#include "evergreen_tex.h"
-
-void r600UpdateTextureState(struct gl_context * ctx);
-
-void r600UpdateTextureState(struct gl_context * ctx)
-{
- context_t *context = R700_CONTEXT(ctx);
- R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
- struct gl_texture_unit *texUnit;
- struct radeon_tex_obj *t;
- GLuint unit;
-
- R600_STATECHANGE(context, tx);
- R600_STATECHANGE(context, tx_smplr);
- R600_STATECHANGE(context, tx_brdr_clr);
-
- for (unit = 0; unit < R700_MAX_TEXTURE_UNITS; unit++) {
- texUnit = &ctx->Texture.Unit[unit];
- t = radeon_tex_obj(ctx->Texture.Unit[unit]._Current);
- r700->textures[unit] = NULL;
- if (texUnit->_ReallyEnabled) {
- if (!t)
- continue;
- r700->textures[unit] = t;
- }
- }
-}
-
-static GLboolean r600GetTexFormat(struct gl_texture_object *tObj, gl_format mesa_format)
-{
- radeonTexObj *t = radeon_tex_obj(tObj);
-
- CLEARfield(t->SQ_TEX_RESOURCE4, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- CLEARfield(t->SQ_TEX_RESOURCE4, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- CLEARfield(t->SQ_TEX_RESOURCE4, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- CLEARfield(t->SQ_TEX_RESOURCE4, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- CLEARbit(t->SQ_TEX_RESOURCE4, SQ_TEX_RESOURCE_WORD4_0__FORCE_DEGAMMA_bit);
-
- SETfield(t->SQ_TEX_RESOURCE4, SQ_FORMAT_COMP_UNSIGNED,
- FORMAT_COMP_X_shift, FORMAT_COMP_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_FORMAT_COMP_UNSIGNED,
- FORMAT_COMP_Y_shift, FORMAT_COMP_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_FORMAT_COMP_UNSIGNED,
- FORMAT_COMP_Z_shift, FORMAT_COMP_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_FORMAT_COMP_UNSIGNED,
- FORMAT_COMP_W_shift, FORMAT_COMP_W_mask);
-
- CLEARbit(t->SQ_TEX_RESOURCE0, TILE_TYPE_bit);
- SETfield(t->SQ_TEX_RESOURCE0, ARRAY_LINEAR_GENERAL,
- SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift,
- SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask);
-
- switch (mesa_format) /* This is mesa format. */
- {
- case MESA_FORMAT_RGBA8888:
- case MESA_FORMAT_SIGNED_RGBA8888:
- SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8_8_8,
- SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
-
-#ifdef MESA_BIG_ENDIAN
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
-#else
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
-#endif
- if (mesa_format == MESA_FORMAT_SIGNED_RGBA8888) {
- SETfield(t->SQ_TEX_RESOURCE4, SQ_FORMAT_COMP_SIGNED,
- FORMAT_COMP_X_shift, FORMAT_COMP_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_FORMAT_COMP_SIGNED,
- FORMAT_COMP_Y_shift, FORMAT_COMP_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_FORMAT_COMP_SIGNED,
- FORMAT_COMP_Z_shift, FORMAT_COMP_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_FORMAT_COMP_SIGNED,
- FORMAT_COMP_W_shift, FORMAT_COMP_W_mask);
- }
- break;
- case MESA_FORMAT_RGBA8888_REV:
- case MESA_FORMAT_SIGNED_RGBA8888_REV:
- SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8_8_8,
- SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
-
-#ifdef MESA_BIG_ENDIAN
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
-#else
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
-#endif
- if (mesa_format == MESA_FORMAT_SIGNED_RGBA8888_REV) {
- SETfield(t->SQ_TEX_RESOURCE4, SQ_FORMAT_COMP_SIGNED,
- FORMAT_COMP_X_shift, FORMAT_COMP_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_FORMAT_COMP_SIGNED,
- FORMAT_COMP_Y_shift, FORMAT_COMP_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_FORMAT_COMP_SIGNED,
- FORMAT_COMP_Z_shift, FORMAT_COMP_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_FORMAT_COMP_SIGNED,
- FORMAT_COMP_W_shift, FORMAT_COMP_W_mask);
- }
- break;
- case MESA_FORMAT_ARGB8888:
- SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8_8_8,
- SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
-
-#ifdef MESA_BIG_ENDIAN
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
-#else
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
-#endif
- break;
- case MESA_FORMAT_XRGB8888:
- SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8_8_8,
- SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
-
-#ifdef MESA_BIG_ENDIAN
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
-#else
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
-#endif
- break;
- case MESA_FORMAT_XRGB8888_REV:
- SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8_8_8,
- SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
-
-#ifdef MESA_BIG_ENDIAN
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
-#else
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
-#endif
- break;
- case MESA_FORMAT_ARGB8888_REV:
- SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8_8_8,
- SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
-
-#ifdef MESA_BIG_ENDIAN
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
-#else
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
-#endif
- break;
- case MESA_FORMAT_RGB888:
- SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8_8,
- SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
-
-#ifdef MESA_BIG_ENDIAN
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
-#else
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
-#endif
- break;
- case MESA_FORMAT_RGB565:
- SETfield(t->SQ_TEX_RESOURCE1, FMT_5_6_5,
- SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
-
-#ifdef MESA_BIG_ENDIAN
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
-#else
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
-#endif
-
- break;
- case MESA_FORMAT_RGB565_REV:
- SETfield(t->SQ_TEX_RESOURCE1, FMT_5_6_5,
- SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
-
-#ifdef MESA_BIG_ENDIAN
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
-#else
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
-#endif
- break;
- case MESA_FORMAT_ARGB4444:
- SETfield(t->SQ_TEX_RESOURCE1, FMT_4_4_4_4,
- SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
-
-#ifdef MESA_BIG_ENDIAN
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
-#else
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
-#endif
- break;
- case MESA_FORMAT_ARGB4444_REV:
- SETfield(t->SQ_TEX_RESOURCE1, FMT_4_4_4_4,
- SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
-#ifdef MESA_BIG_ENDIAN
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
-#else
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
-#endif
- break;
- case MESA_FORMAT_ARGB1555:
- SETfield(t->SQ_TEX_RESOURCE1, FMT_1_5_5_5,
- SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
-#ifdef MESA_BIG_ENDIAN
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
-#else
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
-#endif
- break;
- case MESA_FORMAT_ARGB1555_REV:
- SETfield(t->SQ_TEX_RESOURCE1, FMT_1_5_5_5,
- SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
-#ifdef MESA_BIG_ENDIAN
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
-#else
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
-#endif
- break;
- case MESA_FORMAT_AL88:
- case MESA_FORMAT_AL88_REV: /* TODO : Check this. */
- SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8,
- SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
-
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_RGB332:
- SETfield(t->SQ_TEX_RESOURCE1, FMT_3_3_2,
- SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
-
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_A8: /* ZERO, ZERO, ZERO, X */
- SETfield(t->SQ_TEX_RESOURCE1, FMT_8,
- SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
-
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_0,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_0,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_0,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_L8: /* X, X, X, ONE */
- SETfield(t->SQ_TEX_RESOURCE1, FMT_8,
- SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
-
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_I8: /* X, X, X, X */
- SETfield(t->SQ_TEX_RESOURCE1, FMT_8,
- SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
-
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- /* YUV422 TODO conversion */ /* X, Y, Z, ONE, G8R8_G8B8 */
- /*
- case MESA_FORMAT_YCBCR:
- t->SQ_TEX_RESOURCE1.bitfields.DATA_FORMAT = ;
- break;
- */
- /* VUY422 TODO conversion */ /* X, Y, Z, ONE, G8R8_G8B8 */
- /*
- case MESA_FORMAT_YCBCR_REV:
- t->SQ_TEX_RESOURCE1.bitfields.DATA_FORMAT = ;
- break;
- */
- case MESA_FORMAT_RGB_DXT1: /* not supported yet */
- case MESA_FORMAT_RGBA_DXT1: /* not supported yet */
- case MESA_FORMAT_RGBA_DXT3: /* not supported yet */
- case MESA_FORMAT_RGBA_DXT5: /* not supported yet */
- return GL_FALSE;
-
- case MESA_FORMAT_RGBA_FLOAT32:
- SETfield(t->SQ_TEX_RESOURCE1, FMT_32_32_32_32_FLOAT,
- SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
-
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_RGBA_FLOAT16:
- SETfield(t->SQ_TEX_RESOURCE1, FMT_16_16_16_16_FLOAT,
- SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
-
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_RGB_FLOAT32: /* X, Y, Z, ONE */
- SETfield(t->SQ_TEX_RESOURCE1, FMT_32_32_32_FLOAT,
- SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
-
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_RGB_FLOAT16:
- SETfield(t->SQ_TEX_RESOURCE1, FMT_16_16_16_FLOAT,
- SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
-
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_ALPHA_FLOAT32: /* ZERO, ZERO, ZERO, X */
- SETfield(t->SQ_TEX_RESOURCE1, FMT_32_FLOAT,
- SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
-
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_0,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_0,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_0,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_ALPHA_FLOAT16: /* ZERO, ZERO, ZERO, X */
- SETfield(t->SQ_TEX_RESOURCE1, FMT_16_FLOAT,
- SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
-
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_0,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_0,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_0,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_LUMINANCE_FLOAT32: /* X, X, X, ONE */
- SETfield(t->SQ_TEX_RESOURCE1, FMT_32_FLOAT,
- SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
-
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_LUMINANCE_FLOAT16: /* X, X, X, ONE */
- SETfield(t->SQ_TEX_RESOURCE1, FMT_16_FLOAT,
- SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
-
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32:
- SETfield(t->SQ_TEX_RESOURCE1, FMT_32_32_FLOAT,
- SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
-
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16:
- SETfield(t->SQ_TEX_RESOURCE1, FMT_16_16_FLOAT,
- SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
-
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_INTENSITY_FLOAT32: /* X, X, X, X */
- SETfield(t->SQ_TEX_RESOURCE1, FMT_32_FLOAT,
- SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
-
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_INTENSITY_FLOAT16: /* X, X, X, X */
- SETfield(t->SQ_TEX_RESOURCE1, FMT_16_FLOAT,
- SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
-
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case MESA_FORMAT_Z16:
- case MESA_FORMAT_X8_Z24:
- case MESA_FORMAT_S8_Z24:
- case MESA_FORMAT_Z24_S8:
- case MESA_FORMAT_Z32:
- case MESA_FORMAT_S8:
- SETbit(t->SQ_TEX_RESOURCE0, TILE_TYPE_bit);
- SETfield(t->SQ_TEX_RESOURCE0, ARRAY_1D_TILED_THIN1,
- SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift,
- SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask);
- switch (mesa_format) {
- case MESA_FORMAT_Z16:
- SETfield(t->SQ_TEX_RESOURCE1, FMT_16,
- SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
- break;
- case MESA_FORMAT_X8_Z24:
- case MESA_FORMAT_S8_Z24:
- SETfield(t->SQ_TEX_RESOURCE1, FMT_8_24,
- SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
- break;
- case MESA_FORMAT_Z24_S8:
- SETfield(t->SQ_TEX_RESOURCE1, FMT_24_8,
- SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
- break;
- case MESA_FORMAT_Z32:
- SETfield(t->SQ_TEX_RESOURCE1, FMT_32,
- SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
- break;
- case MESA_FORMAT_S8:
- SETfield(t->SQ_TEX_RESOURCE1, FMT_8,
- SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
- break;
- default:
- break;
- };
- switch (tObj->Sampler.DepthMode) {
- case GL_LUMINANCE: /* X, X, X, ONE */
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case GL_INTENSITY: /* X, X, X, X */
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- case GL_ALPHA: /* ZERO, ZERO, ZERO, X */
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_0,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_0,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_0,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- break;
- default:
- return GL_FALSE;
- }
- break;
- /* EXT_texture_sRGB */
- case MESA_FORMAT_SARGB8:
- SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8_8_8,
- SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
-
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- SETbit(t->SQ_TEX_RESOURCE4, SQ_TEX_RESOURCE_WORD4_0__FORCE_DEGAMMA_bit);
- break;
- case MESA_FORMAT_SLA8:
- SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8,
- SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
-
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- SETbit(t->SQ_TEX_RESOURCE4, SQ_TEX_RESOURCE_WORD4_0__FORCE_DEGAMMA_bit);
- break;
- case MESA_FORMAT_SL8: /* X, X, X, ONE */
- SETfield(t->SQ_TEX_RESOURCE1, FMT_8,
- SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
-
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- SETbit(t->SQ_TEX_RESOURCE4, SQ_TEX_RESOURCE_WORD4_0__FORCE_DEGAMMA_bit);
- break;
- default:
- /* Not supported format */
- return GL_FALSE;
- };
-
- return GL_TRUE;
-}
-
-static GLuint r600_translate_shadow_func(GLenum func)
-{
- switch (func) {
- case GL_NEVER:
- return SQ_TEX_DEPTH_COMPARE_NEVER;
- case GL_LESS:
- return SQ_TEX_DEPTH_COMPARE_LESS;
- case GL_LEQUAL:
- return SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
- case GL_GREATER:
- return SQ_TEX_DEPTH_COMPARE_GREATER;
- case GL_GEQUAL:
- return SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
- case GL_NOTEQUAL:
- return SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
- case GL_EQUAL:
- return SQ_TEX_DEPTH_COMPARE_EQUAL;
- case GL_ALWAYS:
- return SQ_TEX_DEPTH_COMPARE_ALWAYS;
- default:
- WARN_ONCE("Unknown shadow compare function! %d", func);
- return 0;
- }
-}
-
-static INLINE uint32_t
-S_FIXED(float value, uint32_t frac_bits)
-{
- return value * (1 << frac_bits);
-}
-
-void r600SetDepthTexMode(struct gl_texture_object *tObj)
-{
- radeonTexObjPtr t;
-
- if (!tObj)
- return;
-
- t = radeon_tex_obj(tObj);
-
- if(!r600GetTexFormat(tObj, tObj->Image[0][tObj->BaseLevel]->TexFormat))
- t->validated = GL_FALSE;
-}
-
-/**
- * Compute the cached hardware register values for the given texture object.
- *
- * \param rmesa Context pointer
- * \param t the r300 texture object
- */
-static GLboolean setup_hardware_state(struct gl_context * ctx, struct gl_texture_object *texObj, int unit)
-{
- context_t *rmesa = R700_CONTEXT(ctx);
- radeonTexObj *t = radeon_tex_obj(texObj);
- const struct gl_texture_image *firstImage;
- GLuint uTexelPitch, row_align;
-
- if (rmesa->radeon.radeonScreen->driScreen->dri2.enabled &&
- t->image_override &&
- t->bo)
- return GL_TRUE;
-
- firstImage = t->base.Image[0][t->minLod];
-
- if (!t->image_override) {
- if (!r600GetTexFormat(texObj, firstImage->TexFormat)) {
- radeon_warning("unsupported texture format in %s\n",
- __FUNCTION__);
- return GL_FALSE;
- }
- }
-
- switch (texObj->Target) {
- case GL_TEXTURE_1D:
- SETfield(t->SQ_TEX_RESOURCE0, SQ_TEX_DIM_1D, DIM_shift, DIM_mask);
- SETfield(t->SQ_TEX_RESOURCE1, 0, TEX_DEPTH_shift, TEX_DEPTH_mask);
- break;
- case GL_TEXTURE_2D:
- case GL_TEXTURE_RECTANGLE_NV:
- SETfield(t->SQ_TEX_RESOURCE0, SQ_TEX_DIM_2D, DIM_shift, DIM_mask);
- SETfield(t->SQ_TEX_RESOURCE1, 0, TEX_DEPTH_shift, TEX_DEPTH_mask);
- break;
- case GL_TEXTURE_3D:
- SETfield(t->SQ_TEX_RESOURCE0, SQ_TEX_DIM_3D, DIM_shift, DIM_mask);
- SETfield(t->SQ_TEX_RESOURCE1, firstImage->Depth - 1, // ???
- TEX_DEPTH_shift, TEX_DEPTH_mask);
- break;
- case GL_TEXTURE_CUBE_MAP:
- SETfield(t->SQ_TEX_RESOURCE0, SQ_TEX_DIM_CUBEMAP, DIM_shift, DIM_mask);
- SETfield(t->SQ_TEX_RESOURCE1, 0, TEX_DEPTH_shift, TEX_DEPTH_mask);
- break;
- default:
- radeon_error("unexpected texture target type in %s\n", __FUNCTION__);
- return GL_FALSE;
- }
-
- row_align = rmesa->radeon.texture_row_align - 1;
- uTexelPitch = (_mesa_format_row_stride(firstImage->TexFormat, firstImage->Width) + row_align) & ~row_align;
- uTexelPitch = uTexelPitch / _mesa_get_format_bytes(firstImage->TexFormat);
- uTexelPitch = (uTexelPitch + R700_TEXEL_PITCH_ALIGNMENT_MASK)
- & ~R700_TEXEL_PITCH_ALIGNMENT_MASK;
-
- /* min pitch is 8 */
- if (uTexelPitch < 8)
- uTexelPitch = 8;
-
- SETfield(t->SQ_TEX_RESOURCE0, (uTexelPitch/8)-1, PITCH_shift, PITCH_mask);
- SETfield(t->SQ_TEX_RESOURCE0, firstImage->Width - 1,
- TEX_WIDTH_shift, TEX_WIDTH_mask);
- SETfield(t->SQ_TEX_RESOURCE1, firstImage->Height - 1,
- TEX_HEIGHT_shift, TEX_HEIGHT_mask);
-
- t->SQ_TEX_RESOURCE2 = get_base_teximage_offset(t) / 256;
-
- t->SQ_TEX_RESOURCE3 = radeon_miptree_image_offset(t->mt, 0, t->minLod + 1) / 256;
-
- SETfield(t->SQ_TEX_RESOURCE4, 0, BASE_LEVEL_shift, BASE_LEVEL_mask);
- SETfield(t->SQ_TEX_RESOURCE5, t->maxLod - t->minLod, LAST_LEVEL_shift, LAST_LEVEL_mask);
-
- SETfield(t->SQ_TEX_SAMPLER1,
- S_FIXED(CLAMP(t->base.Sampler.MinLod - t->minLod, 0, 15), 6),
- MIN_LOD_shift, MIN_LOD_mask);
- SETfield(t->SQ_TEX_SAMPLER1,
- S_FIXED(CLAMP(t->base.Sampler.MaxLod - t->minLod, 0, 15), 6),
- MAX_LOD_shift, MAX_LOD_mask);
- SETfield(t->SQ_TEX_SAMPLER1,
- S_FIXED(CLAMP(ctx->Texture.Unit[unit].LodBias + t->base.Sampler.LodBias, -16, 16), 6),
- SQ_TEX_SAMPLER_WORD1_0__LOD_BIAS_shift, SQ_TEX_SAMPLER_WORD1_0__LOD_BIAS_mask);
-
- if(texObj->Sampler.CompareMode == GL_COMPARE_R_TO_TEXTURE_ARB)
- {
- SETfield(t->SQ_TEX_SAMPLER0, r600_translate_shadow_func(texObj->Sampler.CompareFunc), DEPTH_COMPARE_FUNCTION_shift, DEPTH_COMPARE_FUNCTION_mask);
- }
- else
- {
- CLEARfield(t->SQ_TEX_SAMPLER0, DEPTH_COMPARE_FUNCTION_mask);
- }
-
- return GL_TRUE;
-}
-
-/**
- * Ensure the given texture is ready for rendering.
- *
- * Mostly this means populating the texture object's mipmap tree.
- */
-static GLboolean r600_validate_texture(struct gl_context * ctx, struct gl_texture_object *texObj, int unit)
-{
- radeonTexObj *t = radeon_tex_obj(texObj);
-
- if (!radeon_validate_texture_miptree(ctx, texObj))
- return GL_FALSE;
-
- /* Configure the hardware registers (more precisely, the cached version
- * of the hardware registers). */
- if (!setup_hardware_state(ctx, texObj, unit))
- return GL_FALSE;
-
- t->validated = GL_TRUE;
- return GL_TRUE;
-}
-
-/**
- * Ensure all enabled and complete textures are uploaded along with any buffers being used.
- */
-GLboolean r600ValidateBuffers(struct gl_context * ctx)
-{
- context_t *rmesa = R700_CONTEXT(ctx);
- struct radeon_renderbuffer *rrb;
- struct radeon_bo *pbo;
- int i;
- int ret;
-
- radeon_cs_space_reset_bos(rmesa->radeon.cmdbuf.cs);
-
- rrb = radeon_get_colorbuffer(&rmesa->radeon);
- /* color buffer */
- if (rrb && rrb->bo) {
- radeon_cs_space_add_persistent_bo(rmesa->radeon.cmdbuf.cs,
- rrb->bo, 0,
- RADEON_GEM_DOMAIN_VRAM);
- }
-
- /* depth buffer */
- rrb = radeon_get_depthbuffer(&rmesa->radeon);
- if (rrb && rrb->bo) {
- radeon_cs_space_add_persistent_bo(rmesa->radeon.cmdbuf.cs,
- rrb->bo, 0,
- RADEON_GEM_DOMAIN_VRAM);
- }
-
- for (i = 0; i < ctx->Const.MaxTextureImageUnits; ++i) {
- radeonTexObj *t;
-
- if (!ctx->Texture.Unit[i]._ReallyEnabled)
- continue;
-
- if (!r600_validate_texture(ctx, ctx->Texture.Unit[i]._Current, i)) {
- radeon_warning("failed to validate texture for unit %d.\n", i);
- }
- t = radeon_tex_obj(ctx->Texture.Unit[i]._Current);
- if (t->image_override && t->bo)
- radeon_cs_space_add_persistent_bo(rmesa->radeon.cmdbuf.cs,
- t->bo,
- RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
- else if (t->mt->bo)
- radeon_cs_space_add_persistent_bo(rmesa->radeon.cmdbuf.cs,
- t->mt->bo,
- RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
- }
-
- pbo = (struct radeon_bo *)r700GetActiveFpShaderBo(ctx);
- if (pbo) {
- radeon_cs_space_add_persistent_bo(rmesa->radeon.cmdbuf.cs, pbo,
- RADEON_GEM_DOMAIN_GTT, 0);
- }
-
- pbo = (struct radeon_bo *)r700GetActiveVpShaderBo(ctx);
- if (pbo) {
- radeon_cs_space_add_persistent_bo(rmesa->radeon.cmdbuf.cs, pbo,
- RADEON_GEM_DOMAIN_GTT, 0);
- }
-
- pbo = (struct radeon_bo *)r700GetActiveFpShaderConstBo(ctx);
- if (pbo) {
- radeon_cs_space_add_persistent_bo(rmesa->radeon.cmdbuf.cs, pbo,
- RADEON_GEM_DOMAIN_GTT, 0);
- }
-
- pbo = (struct radeon_bo *)r700GetActiveVpShaderConstBo(ctx);
- if (pbo) {
- radeon_cs_space_add_persistent_bo(rmesa->radeon.cmdbuf.cs, pbo,
- RADEON_GEM_DOMAIN_GTT, 0);
- }
-
- ret = radeon_cs_space_check_with_bo(rmesa->radeon.cmdbuf.cs, first_elem(&rmesa->radeon.dma.reserved)->bo, RADEON_GEM_DOMAIN_GTT, 0);
- if (ret)
- return GL_FALSE;
- return GL_TRUE;
-}
-
-void r600SetTexOffset(__DRIcontext * pDRICtx, GLint texname,
- unsigned long long offset, GLint depth, GLuint pitch)
-{
- context_t *rmesa = pDRICtx->driverPrivate;
- struct gl_texture_object *tObj =
- _mesa_lookup_texture(rmesa->radeon.glCtx, texname);
- radeonTexObjPtr t = radeon_tex_obj(tObj);
- const struct gl_texture_image *firstImage;
- uint32_t pitch_val, size, row_align;
-
- if (!tObj)
- return;
-
- if(rmesa->radeon.radeonScreen->chip_family >= CHIP_FAMILY_CEDAR)
- {
- evergreenSetTexOffset(pDRICtx, texname, offset, depth, pitch);
- return;
- }
-
- t->image_override = GL_TRUE;
-
- if (!offset)
- return;
-
- firstImage = t->base.Image[0][t->minLod];
- row_align = rmesa->radeon.texture_row_align - 1;
- size = ((_mesa_format_row_stride(firstImage->TexFormat, firstImage->Width) + row_align) & ~row_align) * firstImage->Height;
- if (t->bo) {
- radeon_bo_unref(t->bo);
- t->bo = NULL;
- }
- t->bo = radeon_legacy_bo_alloc_fake(rmesa->radeon.radeonScreen->bom, size, offset);
- t->override_offset = offset;
- pitch_val = pitch;
- switch (depth) {
- case 32:
- SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8_8_8,
- SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
-
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- pitch_val /= 4;
- break;
- case 24:
- default:
- SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8_8_8,
- SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
-
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- pitch_val /= 4;
- break;
- case 16:
- SETfield(t->SQ_TEX_RESOURCE1, FMT_5_6_5,
- SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
-
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- pitch_val /= 2;
- break;
- }
-
- pitch_val = (pitch_val + R700_TEXEL_PITCH_ALIGNMENT_MASK)
- & ~R700_TEXEL_PITCH_ALIGNMENT_MASK;
-
- /* min pitch is 8 */
- if (pitch_val < 8)
- pitch_val = 8;
-
- SETfield(t->SQ_TEX_RESOURCE0, (pitch_val/8)-1, PITCH_shift, PITCH_mask);
-}
-
-void r600SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_format, __DRIdrawable *dPriv)
-{
- struct gl_texture_unit *texUnit;
- struct gl_texture_object *texObj;
- struct gl_texture_image *texImage;
- struct radeon_renderbuffer *rb;
- radeon_texture_image *rImage;
- radeonContextPtr radeon;
- context_t *rmesa;
- struct radeon_framebuffer *rfb;
- radeonTexObjPtr t;
- uint32_t pitch_val;
- gl_format texFormat;
-
- radeon = pDRICtx->driverPrivate;
- rmesa = pDRICtx->driverPrivate;
-
- if(rmesa->radeon.radeonScreen->chip_family >= CHIP_FAMILY_CEDAR)
- {
- evergreenSetTexBuffer(pDRICtx, target, glx_texture_format, dPriv);
- return;
- }
-
- rfb = dPriv->driverPrivate;
- texUnit = &radeon->glCtx->Texture.Unit[radeon->glCtx->Texture.CurrentUnit];
- texObj = _mesa_select_tex_object(radeon->glCtx, texUnit, target);
- texImage = _mesa_get_tex_image(radeon->glCtx, texObj, target, 0);
-
- rImage = get_radeon_texture_image(texImage);
- t = radeon_tex_obj(texObj);
- if (t == NULL) {
- return;
- }
-
- radeon_update_renderbuffers(pDRICtx, dPriv, GL_TRUE);
- rb = rfb->color_rb[0];
- if (rb->bo == NULL) {
- /* Failed to BO for the buffer */
- return;
- }
-
- _mesa_lock_texture(radeon->glCtx, texObj);
- if (t->bo) {
- radeon_bo_unref(t->bo);
- t->bo = NULL;
- }
- if (rImage->bo) {
- radeon_bo_unref(rImage->bo);
- rImage->bo = NULL;
- }
-
- radeon_miptree_unreference(&t->mt);
- radeon_miptree_unreference(&rImage->mt);
-
- rImage->bo = rb->bo;
- radeon_bo_ref(rImage->bo);
- t->bo = rb->bo;
- radeon_bo_ref(t->bo);
- t->image_override = GL_TRUE;
- t->override_offset = 0;
- pitch_val = rb->pitch;
- switch (rb->cpp) {
- case 4:
- if (glx_texture_format == __DRI_TEXTURE_FORMAT_RGB) {
- texFormat = MESA_FORMAT_RGB888;
- SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8_8_8,
- SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
-
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- } else {
- texFormat = MESA_FORMAT_ARGB8888;
- SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8_8_8,
- SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
-
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- }
- pitch_val /= 4;
- break;
- case 3:
- default:
- // FMT_8_8_8 ???
- texFormat = MESA_FORMAT_RGB888;
- SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8_8_8,
- SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
-
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- pitch_val /= 4;
- break;
- case 2:
- texFormat = MESA_FORMAT_RGB565;
- SETfield(t->SQ_TEX_RESOURCE1, FMT_5_6_5,
- SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
-
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
- SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
- pitch_val /= 2;
- break;
- }
-
- _mesa_init_teximage_fields(radeon->glCtx, target, texImage,
- rb->base.Width, rb->base.Height, 1, 0,
- rb->cpp, texFormat);
- rImage->base.RowStride = rb->pitch / rb->cpp;
-
- pitch_val = (pitch_val + R700_TEXEL_PITCH_ALIGNMENT_MASK)
- & ~R700_TEXEL_PITCH_ALIGNMENT_MASK;
-
- /* min pitch is 8 */
- if (pitch_val < 8)
- pitch_val = 8;
-
- SETfield(t->SQ_TEX_RESOURCE0, (pitch_val/8)-1, PITCH_shift, PITCH_mask);
- SETfield(t->SQ_TEX_RESOURCE0, rb->base.Width - 1,
- TEX_WIDTH_shift, TEX_WIDTH_mask);
- SETfield(t->SQ_TEX_RESOURCE1, rb->base.Height - 1,
- TEX_HEIGHT_shift, TEX_HEIGHT_mask);
-
- t->validated = GL_TRUE;
- _mesa_unlock_texture(radeon->glCtx, texObj);
- return;
-}
-
-void r600SetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPriv)
-{
- r600SetTexBuffer2(pDRICtx, target, __DRI_TEXTURE_FORMAT_RGBA, dPriv);
-}
+++ /dev/null
-/*
- * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Authors:
- * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
- */
-
-#include <stdio.h>
-#include <stdarg.h>
-#include <stdlib.h>
-#include <string.h>
-#include <math.h>
-
-#include "main/mtypes.h"
-#include "main/imports.h"
-#include "program/prog_parameter.h"
-
-#include "radeon_debug.h"
-#include "r600_context.h"
-
-#include "r700_assembler.h"
-#include "evergreen_sq.h"
-
-#define USE_CF_FOR_CONTINUE_BREAK 1
-#define USE_CF_FOR_POP_AFTER 1
-
-struct prog_instruction noise1_insts[12] = {
- {OPCODE_BGNSUB , {{13, 0, 1672, 0, 0, 0}, {13, 0, 1672, 0, 0, 0}, {13, 0, 1672, 0, 0, 0}}, {13, 0, 15, 0, 8, 1672, 0}, 0, 0, 0, 1, 0, 0, 0, -1, 0, 0, 0},
- {OPCODE_MOV , {{0, 0, 0, 0, 0, 0}, {13, 0, 1672, 0, 0, 0}, {13, 0, 1672, 0, 0, 0}}, {0, 0, 2, 0, 8, 1672, 0}, 0, 0, 0, 1, 0, 0, 0, -1, 0, 0, 0},
- {OPCODE_MOV , {{8, 0, 0, 0, 0, 0}, {13, 0, 1672, 0, 0, 0}, {13, 0, 1672, 0, 0, 0}}, {0, 0, 4, 0, 8, 1672, 0}, 0, 0, 0, 1, 0, 0, 0, -1, 0, 0, 0},
- {OPCODE_MOV , {{8, 0, 585, 0, 0, 0}, {13, 0, 1672, 0, 0, 0}, {13, 0, 1672, 0, 0, 0}}, {0, 0, 8, 0, 8, 1672, 0}, 0, 0, 0, 1, 0, 0, 0, -1, 0, 0, 0},
- {OPCODE_SGT , {{0, 0, 585, 0, 0, 0}, {8, 0, 1170, 0, 0, 0}, {13, 0, 1672, 0, 0, 0}}, {0, 1, 1, 0, 8, 1672, 0}, 1, 0, 0, 1, 0, 0, 0, -1, 0, 0, 0},
- {OPCODE_IF , {{13, 0, 1672, 0, 0, 0}, {13, 0, 1672, 0, 0, 0}, {13, 0, 1672, 0, 0, 0}}, {13, 0, 15, 0, 7, 0, 0}, 0, 0, 0, 1, 0, 0, 0, 15, 0, 0, 0},
- {OPCODE_MOV , {{0, 0, 1755, 0, 0, 0}, {13, 0, 1672, 0, 0, 0}, {13, 0, 1672, 0, 0, 0}}, {0, 0, 1, 0, 8, 1672, 0}, 0, 0, 0, 1, 0, 0, 0, -1, 0, 0, 0},
- {OPCODE_RET , {{13, 0, 1672, 0, 0, 0}, {13, 0, 1672, 0, 0, 0}, {13, 0, 1672, 0, 0, 0}}, {13, 0, 15, 0, 8, 1672, 0}, 0, 0, 0, 1, 0, 0, 0, -1, 0, 0, 0},
- {OPCODE_ENDIF , {{13, 0, 1672, 0, 0, 0}, {13, 0, 1672, 0, 0, 0}, {13, 0, 1672, 0, 0, 0}}, {13, 0, 15, 0, 8, 1672, 0}, 0, 0, 0, 1, 0, 0, 0, -1, 0, 0, 0},
- {OPCODE_MOV , {{0, 0, 1170, 0, 0, 0}, {13, 0, 1672, 0, 0, 0}, {13, 0, 1672, 0, 0, 0}}, {0, 0, 1, 0, 8, 1672, 0}, 0, 0, 0, 1, 0, 0, 0, -1, 0, 0, 0},
- {OPCODE_RET , {{13, 0, 1672, 0, 0, 0}, {13, 0, 1672, 0, 0, 0}, {13, 0, 1672, 0, 0, 0}}, {13, 0, 15, 0, 8, 1672, 0}, 0, 0, 0, 1, 0, 0, 0, -1, 0, 0, 0},
- {OPCODE_ENDSUB , {{13, 0, 1672, 0, 0, 0}, {13, 0, 1672, 0, 0, 0}, {13, 0, 1672, 0, 0, 0}}, {13, 0, 15, 0, 8, 1672, 0}, 0, 0, 0, 1, 0, 0, 0, -1, 0, 0, 0}
-};
-float noise1_const[2][4] = {
- {0.300000f, 0.900000f, 0.500000f, 0.300000f}
-};
-
-COMPILED_SUB noise1_presub = {
- &(noise1_insts[0]),
- 12,
- 2,
- 1,
- 0,
- &(noise1_const[0]),
- SWIZZLE_X,
- SWIZZLE_X,
- SWIZZLE_X,
- SWIZZLE_X,
- {0,0,0},
- 0
-};
-
-BITS addrmode_PVSDST(PVSDST * pPVSDST)
-{
- return pPVSDST->addrmode0 | ((BITS)pPVSDST->addrmode1 << 1);
-}
-
-void setaddrmode_PVSDST(PVSDST * pPVSDST, BITS addrmode)
-{
- pPVSDST->addrmode0 = addrmode & 1;
- pPVSDST->addrmode1 = (addrmode >> 1) & 1;
-}
-
-void nomask_PVSDST(PVSDST * pPVSDST)
-{
- pPVSDST->writex = pPVSDST->writey = pPVSDST->writez = pPVSDST->writew = 1;
-}
-
-BITS addrmode_PVSSRC(PVSSRC* pPVSSRC)
-{
- return pPVSSRC->addrmode0 | ((BITS)pPVSSRC->addrmode1 << 1);
-}
-
-void setaddrmode_PVSSRC(PVSSRC* pPVSSRC, BITS addrmode)
-{
- pPVSSRC->addrmode0 = addrmode & 1;
- pPVSSRC->addrmode1 = (addrmode >> 1) & 1;
-}
-
-
-void setswizzle_PVSSRC(PVSSRC* pPVSSRC, BITS swz)
-{
- pPVSSRC->swizzlex =
- pPVSSRC->swizzley =
- pPVSSRC->swizzlez =
- pPVSSRC->swizzlew = swz;
-}
-
-void noswizzle_PVSSRC(PVSSRC* pPVSSRC)
-{
- pPVSSRC->swizzlex = SQ_SEL_X;
- pPVSSRC->swizzley = SQ_SEL_Y;
- pPVSSRC->swizzlez = SQ_SEL_Z;
- pPVSSRC->swizzlew = SQ_SEL_W;
-}
-
-void
-swizzleagain_PVSSRC(PVSSRC * pPVSSRC, BITS x, BITS y, BITS z, BITS w)
-{
- switch (x)
- {
- case SQ_SEL_X: x = pPVSSRC->swizzlex;
- break;
- case SQ_SEL_Y: x = pPVSSRC->swizzley;
- break;
- case SQ_SEL_Z: x = pPVSSRC->swizzlez;
- break;
- case SQ_SEL_W: x = pPVSSRC->swizzlew;
- break;
- default:;
- }
-
- switch (y)
- {
- case SQ_SEL_X: y = pPVSSRC->swizzlex;
- break;
- case SQ_SEL_Y: y = pPVSSRC->swizzley;
- break;
- case SQ_SEL_Z: y = pPVSSRC->swizzlez;
- break;
- case SQ_SEL_W: y = pPVSSRC->swizzlew;
- break;
- default:;
- }
-
- switch (z)
- {
- case SQ_SEL_X: z = pPVSSRC->swizzlex;
- break;
- case SQ_SEL_Y: z = pPVSSRC->swizzley;
- break;
- case SQ_SEL_Z: z = pPVSSRC->swizzlez;
- break;
- case SQ_SEL_W: z = pPVSSRC->swizzlew;
- break;
- default:;
- }
-
- switch (w)
- {
- case SQ_SEL_X: w = pPVSSRC->swizzlex;
- break;
- case SQ_SEL_Y: w = pPVSSRC->swizzley;
- break;
- case SQ_SEL_Z: w = pPVSSRC->swizzlez;
- break;
- case SQ_SEL_W: w = pPVSSRC->swizzlew;
- break;
- default:;
- }
-
- pPVSSRC->swizzlex = x;
- pPVSSRC->swizzley = y;
- pPVSSRC->swizzlez = z;
- pPVSSRC->swizzlew = w;
-}
-
-void neg_PVSSRC(PVSSRC* pPVSSRC)
-{
- pPVSSRC->negx = 1;
- pPVSSRC->negy = 1;
- pPVSSRC->negz = 1;
- pPVSSRC->negw = 1;
-}
-
-void noneg_PVSSRC(PVSSRC* pPVSSRC)
-{
- pPVSSRC->negx = 0;
- pPVSSRC->negy = 0;
- pPVSSRC->negz = 0;
- pPVSSRC->negw = 0;
-}
-
-// negate argument (for SUB instead of ADD and alike)
-void flipneg_PVSSRC(PVSSRC* pPVSSRC)
-{
- pPVSSRC->negx = !pPVSSRC->negx;
- pPVSSRC->negy = !pPVSSRC->negy;
- pPVSSRC->negz = !pPVSSRC->negz;
- pPVSSRC->negw = !pPVSSRC->negw;
-}
-
-void zerocomp_PVSSRC(PVSSRC* pPVSSRC, int c)
-{
- switch (c)
- {
- case 0: pPVSSRC->swizzlex = SQ_SEL_0; pPVSSRC->negx = 0; break;
- case 1: pPVSSRC->swizzley = SQ_SEL_0; pPVSSRC->negy = 0; break;
- case 2: pPVSSRC->swizzlez = SQ_SEL_0; pPVSSRC->negz = 0; break;
- case 3: pPVSSRC->swizzlew = SQ_SEL_0; pPVSSRC->negw = 0; break;
- default:;
- }
-}
-
-void onecomp_PVSSRC(PVSSRC* pPVSSRC, int c)
-{
- switch (c)
- {
- case 0: pPVSSRC->swizzlex = SQ_SEL_1; pPVSSRC->negx = 0; break;
- case 1: pPVSSRC->swizzley = SQ_SEL_1; pPVSSRC->negy = 0; break;
- case 2: pPVSSRC->swizzlez = SQ_SEL_1; pPVSSRC->negz = 0; break;
- case 3: pPVSSRC->swizzlew = SQ_SEL_1; pPVSSRC->negw = 0; break;
- default:;
- }
-}
-
-BITS is_misc_component_exported(VAP_OUT_VTX_FMT_0* pOutVTXFmt0)
-{
- return (pOutVTXFmt0->point_size |
- pOutVTXFmt0->edge_flag |
- pOutVTXFmt0->rta_index |
- pOutVTXFmt0->kill_flag |
- pOutVTXFmt0->viewport_index);
-}
-
-BITS is_depth_component_exported(OUT_FRAGMENT_FMT_0* pFPOutFmt)
-{
- return (pFPOutFmt->depth |
- pFPOutFmt->stencil_ref |
- pFPOutFmt->mask |
- pFPOutFmt->coverage_to_mask);
-}
-
-GLboolean is_reduction_opcode(PVSDWORD* dest)
-{
- if (dest->dst.op3 == 0)
- {
- if ( (dest->dst.opcode == SQ_OP2_INST_DOT4 || dest->dst.opcode == SQ_OP2_INST_DOT4_IEEE || dest->dst.opcode == SQ_OP2_INST_CUBE) )
- {
- return GL_TRUE;
- }
- }
- return GL_FALSE;
-}
-
-#if 0 /* unused */
-GLboolean EG_is_reduction_opcode(PVSDWORD* dest)
-{
- if (dest->dst.op3 == 0)
- {
- if ( (dest->dst.opcode == EG_OP2_INST_DOT4 || dest->dst.opcode == EG_OP2_INST_DOT4_IEEE || dest->dst.opcode == EG_OP2_INST_CUBE) )
- {
- return GL_TRUE;
- }
- }
- return GL_FALSE;
-}
-#endif
-
-GLuint GetSurfaceFormat(GLenum eType, GLuint nChannels, GLuint * pClient_size)
-{
- GLuint format = FMT_INVALID;
- GLuint uiElemSize = 0;
-
- switch (eType)
- {
- case GL_BYTE:
- case GL_UNSIGNED_BYTE:
- uiElemSize = 1;
- switch(nChannels)
- {
- case 1:
- format = FMT_8; break;
- case 2:
- format = FMT_8_8; break;
- case 3:
- /* for some (small/unaligned) strides using 4 comps works
- * better, probably same as GL_SHORT below
- * test piglit/draw-vertices */
- format = FMT_8_8_8_8; break;
- case 4:
- format = FMT_8_8_8_8; break;
- default:
- break;
- }
- break;
-
- case GL_UNSIGNED_SHORT:
- case GL_SHORT:
- uiElemSize = 2;
- switch(nChannels)
- {
- case 1:
- format = FMT_16; break;
- case 2:
- format = FMT_16_16; break;
- case 3:
- /* 3 comp GL_SHORT vertex format doesnt work on r700
- 4 somehow works, test - sauerbraten */
- format = FMT_16_16_16_16; break;
- case 4:
- format = FMT_16_16_16_16; break;
- default:
- break;
- }
- break;
-
- case GL_UNSIGNED_INT:
- case GL_INT:
- uiElemSize = 4;
- switch(nChannels)
- {
- case 1:
- format = FMT_32; break;
- case 2:
- format = FMT_32_32; break;
- case 3:
- format = FMT_32_32_32; break;
- case 4:
- format = FMT_32_32_32_32; break;
- default:
- break;
- }
- break;
-
- case GL_FLOAT:
- uiElemSize = 4;
- switch(nChannels)
- {
- case 1:
- format = FMT_32_FLOAT; break;
- case 2:
- format = FMT_32_32_FLOAT; break;
- case 3:
- format = FMT_32_32_32_FLOAT; break;
- case 4:
- format = FMT_32_32_32_32_FLOAT; break;
- default:
- break;
- }
- break;
- case GL_DOUBLE:
- uiElemSize = 8;
- switch(nChannels)
- {
- case 1:
- format = FMT_32_FLOAT; break;
- case 2:
- format = FMT_32_32_FLOAT; break;
- case 3:
- format = FMT_32_32_32_FLOAT; break;
- case 4:
- format = FMT_32_32_32_32_FLOAT; break;
- default:
- break;
- }
- break;
- default:
- ;
- //GL_ASSERT_NO_CASE();
- }
-
- if(NULL != pClient_size)
- {
- *pClient_size = uiElemSize * nChannels;
- }
-
- return(format);
-}
-
-unsigned int r700GetNumOperands(GLuint opcode, GLuint nIsOp3)
-{
- if(nIsOp3 > 0)
- {
- return 3;
- }
-
- switch (opcode)
- {
- case SQ_OP2_INST_ADD:
- case SQ_OP2_INST_KILLE:
- case SQ_OP2_INST_KILLGT:
- case SQ_OP2_INST_KILLGE:
- case SQ_OP2_INST_KILLNE:
- case SQ_OP2_INST_MUL:
- case SQ_OP2_INST_MAX:
- case SQ_OP2_INST_MIN:
- //case SQ_OP2_INST_MAX_DX10:
- //case SQ_OP2_INST_MIN_DX10:
- case SQ_OP2_INST_SETE:
- case SQ_OP2_INST_SETNE:
- case SQ_OP2_INST_SETGT:
- case SQ_OP2_INST_SETGE:
- case SQ_OP2_INST_PRED_SETE:
- case SQ_OP2_INST_PRED_SETGT:
- case SQ_OP2_INST_PRED_SETGE:
- case SQ_OP2_INST_PRED_SETNE:
- case SQ_OP2_INST_DOT4:
- case SQ_OP2_INST_DOT4_IEEE:
- case SQ_OP2_INST_CUBE:
- return 2;
-
- case SQ_OP2_INST_MOV:
- case SQ_OP2_INST_MOVA_FLOOR:
- case SQ_OP2_INST_FRACT:
- case SQ_OP2_INST_FLOOR:
- case SQ_OP2_INST_TRUNC:
- case SQ_OP2_INST_EXP_IEEE:
- case SQ_OP2_INST_LOG_CLAMPED:
- case SQ_OP2_INST_LOG_IEEE:
- case SQ_OP2_INST_RECIP_IEEE:
- case SQ_OP2_INST_RECIPSQRT_IEEE:
- case SQ_OP2_INST_FLT_TO_INT:
- case SQ_OP2_INST_SIN:
- case SQ_OP2_INST_COS:
- return 1;
-
- default: radeon_error(
- "Need instruction operand number for %x.\n", opcode);
- };
-
- return 3;
-}
-
-unsigned int EG_GetNumOperands(GLuint opcode, GLuint nIsOp3)
-{
- if(nIsOp3 > 0)
- {
- return 3;
- }
-
- switch (opcode)
- {
- case EG_OP2_INST_ADD:
- case EG_OP2_INST_KILLE:
- case EG_OP2_INST_KILLGT:
- case EG_OP2_INST_KILLGE:
- case EG_OP2_INST_KILLNE:
- case EG_OP2_INST_MUL:
- case EG_OP2_INST_MAX:
- case EG_OP2_INST_MIN:
- //case EG_OP2_INST_MAX_DX10:
- //case EG_OP2_INST_MIN_DX10:
- case EG_OP2_INST_SETE:
- case EG_OP2_INST_SETNE:
- case EG_OP2_INST_SETGT:
- case EG_OP2_INST_SETGE:
- case EG_OP2_INST_PRED_SETE:
- case EG_OP2_INST_PRED_SETGT:
- case EG_OP2_INST_PRED_SETGE:
- case EG_OP2_INST_PRED_SETNE:
- case EG_OP2_INST_DOT4:
- case EG_OP2_INST_DOT4_IEEE:
- case EG_OP2_INST_CUBE:
- return 2;
-
- case EG_OP2_INST_MOV:
- //case SQ_OP2_INST_MOVA_FLOOR:
- case EG_OP2_INST_FRACT:
- case EG_OP2_INST_FLOOR:
- case EG_OP2_INST_TRUNC:
- case EG_OP2_INST_EXP_IEEE:
- case EG_OP2_INST_LOG_CLAMPED:
- case EG_OP2_INST_LOG_IEEE:
- case EG_OP2_INST_RECIP_IEEE:
- case EG_OP2_INST_RECIPSQRT_IEEE:
- case EG_OP2_INST_FLT_TO_INT:
- case EG_OP2_INST_SIN:
- case EG_OP2_INST_COS:
- case EG_OP2_INST_FLT_TO_INT_FLOOR:
- case EG_OP2_INST_MOVA_INT:
- return 1;
-
- default: radeon_error(
- "Need instruction operand number for %x.\n", opcode);
- };
-
- return 3;
-}
-
-int Init_r700_AssemblerBase(SHADER_PIPE_TYPE spt, r700_AssemblerBase* pAsm, R700_Shader* pShader)
-{
- GLuint i;
-
- Init_R700_Shader(pShader);
- pAsm->pR700Shader = pShader;
- pAsm->currentShaderType = spt;
-
- pAsm->cf_last_export_ptr = NULL;
-
- pAsm->cf_current_export_clause_ptr = NULL;
- pAsm->cf_current_alu_clause_ptr = NULL;
- pAsm->cf_current_tex_clause_ptr = NULL;
- pAsm->cf_current_vtx_clause_ptr = NULL;
- pAsm->cf_current_cf_clause_ptr = NULL;
-
- // No clause has been created yet
- pAsm->cf_current_clause_type = CF_EMPTY_CLAUSE;
-
- pAsm->number_of_colorandz_exports = 0;
- pAsm->number_of_exports = 0;
- pAsm->number_of_export_opcodes = 0;
-
- pAsm->alu_x_opcode = 0;
-
- pAsm->D2.bits = 0;
-
- pAsm->D.bits = 0;
- pAsm->S[0].bits = 0;
- pAsm->S[1].bits = 0;
- pAsm->S[2].bits = 0;
-
- pAsm->uLastPosUpdate = 0;
-
- *(BITS *) &pAsm->fp_stOutFmt0 = 0;
-
- pAsm->uIIns = 0;
- pAsm->uOIns = 0;
- pAsm->number_used_registers = 0;
- pAsm->uUsedConsts = 256;
-
-
- // Fragment programs
- pAsm->uBoolConsts = 0;
- pAsm->uIntConsts = 0;
- pAsm->uInsts = 0;
- pAsm->uConsts = 0;
-
- pAsm->FCSP = 0;
- pAsm->fc_stack[0].type = FC_NONE;
-
- pAsm->aArgSubst[0] =
- pAsm->aArgSubst[1] =
- pAsm->aArgSubst[2] =
- pAsm->aArgSubst[3] = (-1);
-
- pAsm->uOutputs = 0;
-
- for (i=0; i<NUMBER_OF_OUTPUT_COLORS; i++)
- {
- pAsm->color_export_register_number[i] = (-1);
- }
-
-
- pAsm->depth_export_register_number = (-1);
- pAsm->stencil_export_register_number = (-1);
- pAsm->coverage_to_mask_export_register_number = (-1);
- pAsm->mask_export_register_number = (-1);
-
- pAsm->starting_export_register_number = 0;
- pAsm->starting_vfetch_register_number = 0;
- pAsm->starting_temp_register_number = 0;
- pAsm->uFirstHelpReg = 0;
-
- pAsm->input_position_is_used = GL_FALSE;
- pAsm->input_normal_is_used = GL_FALSE;
-
- for (i=0; i<NUMBER_OF_INPUT_COLORS; i++)
- {
- pAsm->input_color_is_used[ i ] = GL_FALSE;
- }
-
- for (i=0; i<NUMBER_OF_TEXTURE_UNITS; i++)
- {
- pAsm->input_texture_unit_is_used[ i ] = GL_FALSE;
- }
-
- for (i=0; i<VERT_ATTRIB_MAX; i++)
- {
- pAsm->vfetch_instruction_ptr_array[ i ] = NULL;
- }
-
- pAsm->number_of_inputs = 0;
-
- pAsm->is_tex = GL_FALSE;
- pAsm->need_tex_barrier = GL_FALSE;
-
- pAsm->subs = NULL;
- pAsm->unSubArraySize = 0;
- pAsm->unSubArrayPointer = 0;
- pAsm->callers = NULL;
- pAsm->unCallerArraySize = 0;
- pAsm->unCallerArrayPointer = 0;
-
- pAsm->CALLSP = 0;
- pAsm->CALLSTACK[0].FCSP_BeforeEntry = 0;
- pAsm->CALLSTACK[0].plstCFInstructions_local
- = &(pAsm->pR700Shader->lstCFInstructions);
-
- pAsm->CALLSTACK[0].max = 0;
- pAsm->CALLSTACK[0].current = 0;
-
- SetActiveCFlist(pAsm->pR700Shader, pAsm->CALLSTACK[0].plstCFInstructions_local);
-
- pAsm->unCFflags = 0;
-
- pAsm->presubs = NULL;
- pAsm->unPresubArraySize = 0;
- pAsm->unNumPresub = 0;
- pAsm->unCurNumILInsts = 0;
-
- pAsm->unVetTexBits = 0;
-
- return 0;
-}
-
-GLboolean IsTex(gl_inst_opcode Opcode)
-{
- if( (OPCODE_TEX==Opcode) || (OPCODE_TXP==Opcode) || (OPCODE_TXB==Opcode) ||
- (OPCODE_DDX==Opcode) || (OPCODE_DDY==Opcode) || (OPCODE_TXL==Opcode) )
- {
- return GL_TRUE;
- }
- return GL_FALSE;
-}
-
-GLboolean IsAlu(gl_inst_opcode Opcode)
-{
- //TODO : more for fc and ex for higher spec.
- if( IsTex(Opcode) )
- {
- return GL_FALSE;
- }
- return GL_TRUE;
-}
-
-int check_current_clause(r700_AssemblerBase* pAsm,
- CF_CLAUSE_TYPE new_clause_type)
-{
- if (pAsm->cf_current_clause_type != new_clause_type)
- { //Close last open clause
- switch (pAsm->cf_current_clause_type)
- {
- case CF_ALU_CLAUSE:
- if ( pAsm->cf_current_alu_clause_ptr != NULL)
- {
- pAsm->cf_current_alu_clause_ptr = NULL;
- }
- break;
- case CF_VTX_CLAUSE:
- if ( pAsm->cf_current_vtx_clause_ptr != NULL)
- {
- pAsm->cf_current_vtx_clause_ptr = NULL;
- }
- break;
- case CF_TEX_CLAUSE:
- if ( pAsm->cf_current_tex_clause_ptr != NULL)
- {
- pAsm->cf_current_tex_clause_ptr = NULL;
- }
- break;
- case CF_EXPORT_CLAUSE:
- if ( pAsm->cf_current_export_clause_ptr != NULL)
- {
- pAsm->cf_current_export_clause_ptr = NULL;
- }
- break;
- case CF_OTHER_CLAUSE:
- if ( pAsm->cf_current_cf_clause_ptr != NULL)
- {
- pAsm->cf_current_cf_clause_ptr = NULL;
- }
- break;
- case CF_EMPTY_CLAUSE:
- break;
- default:
- radeon_error(
- "Unknown CF_CLAUSE_TYPE (%d) in check_current_clause. \n", (int) new_clause_type);
- return GL_FALSE;
- }
-
- pAsm->cf_current_clause_type = CF_EMPTY_CLAUSE;
-
- // Create new clause
- switch (new_clause_type)
- {
- case CF_ALU_CLAUSE:
- pAsm->cf_current_clause_type = CF_ALU_CLAUSE;
- break;
- case CF_VTX_CLAUSE:
- pAsm->cf_current_clause_type = CF_VTX_CLAUSE;
- break;
- case CF_TEX_CLAUSE:
- pAsm->cf_current_clause_type = CF_TEX_CLAUSE;
- break;
- case CF_EXPORT_CLAUSE:
- {
- R700ControlFlowSXClause* pR700ControlFlowSXClause
- = (R700ControlFlowSXClause*) CALLOC_STRUCT(R700ControlFlowSXClause);
-
- // Add new export instruction to control flow program
- if (pR700ControlFlowSXClause != 0)
- {
- pAsm->cf_current_export_clause_ptr = pR700ControlFlowSXClause;
- Init_R700ControlFlowSXClause(pR700ControlFlowSXClause);
- AddCFInstruction( pAsm->pR700Shader,
- (R700ControlFlowInstruction *)pR700ControlFlowSXClause );
- }
- else
- {
- radeon_error(
- "Error allocating new EXPORT CF instruction in check_current_clause. \n");
- return GL_FALSE;
- }
- pAsm->cf_current_clause_type = CF_EXPORT_CLAUSE;
- }
- break;
- case CF_EMPTY_CLAUSE:
- break;
- case CF_OTHER_CLAUSE:
- pAsm->cf_current_clause_type = CF_OTHER_CLAUSE;
- break;
- default:
- radeon_error(
- "Unknown CF_CLAUSE_TYPE (%d) in check_current_clause. \n", (int) new_clause_type);
- return GL_FALSE;
- }
- }
-
- return GL_TRUE;
-}
-
-GLboolean add_cf_instruction(r700_AssemblerBase* pAsm)
-{
- if(GL_FALSE == check_current_clause(pAsm, CF_OTHER_CLAUSE))
- {
- return GL_FALSE;
- }
-
- pAsm->cf_current_cf_clause_ptr =
- (R700ControlFlowGenericClause*) CALLOC_STRUCT(R700ControlFlowGenericClause);
-
- if (pAsm->cf_current_cf_clause_ptr != NULL)
- {
- Init_R700ControlFlowGenericClause(pAsm->cf_current_cf_clause_ptr);
- AddCFInstruction( pAsm->pR700Shader,
- (R700ControlFlowInstruction *)pAsm->cf_current_cf_clause_ptr );
- }
- else
- {
- radeon_error("Could not allocate a new VFetch CF instruction.\n");
- return GL_FALSE;
- }
-
- return GL_TRUE;
-}
-
-GLboolean add_vfetch_instruction(r700_AssemblerBase* pAsm,
- R700VertexInstruction* vertex_instruction_ptr)
-{
- if( GL_FALSE == check_current_clause(pAsm, CF_VTX_CLAUSE) )
- {
- return GL_FALSE;
- }
-
- if( pAsm->cf_current_vtx_clause_ptr == NULL ||
- ( (pAsm->cf_current_vtx_clause_ptr != NULL) &&
- (pAsm->cf_current_vtx_clause_ptr->m_Word1.f.count >= GetCFMaxInstructions(pAsm->cf_current_vtx_clause_ptr->m_ShaderInstType)-1)
- ) )
- {
- // Create new Vfetch control flow instruction for this new clause
- pAsm->cf_current_vtx_clause_ptr = (R700ControlFlowGenericClause*) CALLOC_STRUCT(R700ControlFlowGenericClause);
-
- if (pAsm->cf_current_vtx_clause_ptr != NULL)
- {
- Init_R700ControlFlowGenericClause(pAsm->cf_current_vtx_clause_ptr);
- AddCFInstruction( pAsm->pR700Shader,
- (R700ControlFlowInstruction *)pAsm->cf_current_vtx_clause_ptr );
- }
- else
- {
- radeon_error("Could not allocate a new VFetch CF instruction.\n");
- return GL_FALSE;
- }
-
- if(8 == pAsm->unAsic)
- {
- SETfield(pAsm->cf_current_vtx_clause_ptr->m_Word1.val, EG_CF_INST_VC,
- EG_CF_WORD1__CF_INST_shift, EG_CF_WORD1__CF_INST_mask);
- SETfield(pAsm->cf_current_vtx_clause_ptr->m_Word1.val, 0,
- EG_CF_WORD1__POP_COUNT_shift, EG_CF_WORD1__POP_COUNT_mask);
- SETfield(pAsm->cf_current_vtx_clause_ptr->m_Word1.val, 0,
- EG_CF_WORD1__CF_CONST_shift, EG_CF_WORD1__CF_CONST_mask);
- SETfield(pAsm->cf_current_vtx_clause_ptr->m_Word1.val, SQ_CF_COND_ACTIVE,
- EG_CF_WORD1__COND_shift, EG_CF_WORD1__COND_mask);
- SETfield(pAsm->cf_current_vtx_clause_ptr->m_Word1.val, 0,
- EG_CF_WORD1__COUNT_shift, EG_CF_WORD1__COUNT_mask);
- SETfield(pAsm->cf_current_vtx_clause_ptr->m_Word1.val, 0,
- EG_CF_WORD1__VPM_shift, EG_CF_WORD1__VPM_bit);
- SETfield(pAsm->cf_current_vtx_clause_ptr->m_Word1.val, 0,
- EG_CF_WORD1__EOP_shift, EG_CF_WORD1__EOP_bit);
- SETfield(pAsm->cf_current_vtx_clause_ptr->m_Word1.val, 0,
- EG_CF_WORD1__WQM_shift, EG_CF_WORD1__WQM_bit);
- SETfield(pAsm->cf_current_vtx_clause_ptr->m_Word1.val, 1,
- EG_CF_WORD1__BARRIER_shift, EG_CF_WORD1__BARRIER_bit);
- }
- else
- {
- pAsm->cf_current_vtx_clause_ptr->m_Word1.f.pop_count = 0x0;
- pAsm->cf_current_vtx_clause_ptr->m_Word1.f.cf_const = 0x0;
- pAsm->cf_current_vtx_clause_ptr->m_Word1.f.cond = SQ_CF_COND_ACTIVE;
- pAsm->cf_current_vtx_clause_ptr->m_Word1.f.count = 0x0;
- pAsm->cf_current_vtx_clause_ptr->m_Word1.f.end_of_program = 0x0;
- pAsm->cf_current_vtx_clause_ptr->m_Word1.f.valid_pixel_mode = 0x0;
- pAsm->cf_current_vtx_clause_ptr->m_Word1.f.cf_inst = SQ_CF_INST_VTX;
- pAsm->cf_current_vtx_clause_ptr->m_Word1.f.whole_quad_mode = 0x0;
- pAsm->cf_current_vtx_clause_ptr->m_Word1.f.barrier = 0x1;
- }
-
- LinkVertexInstruction(pAsm->cf_current_vtx_clause_ptr, vertex_instruction_ptr );
- }
- else
- {
- if(8 == pAsm->unAsic)
- {
- unsigned int count = GETbits(pAsm->cf_current_vtx_clause_ptr->m_Word1.val,
- EG_CF_WORD1__COUNT_shift, EG_CF_WORD1__COUNT_mask) + 1;
- SETfield(pAsm->cf_current_vtx_clause_ptr->m_Word1.val, count,
- EG_CF_WORD1__COUNT_shift, EG_CF_WORD1__COUNT_mask);
- }
- else
- {
- pAsm->cf_current_vtx_clause_ptr->m_Word1.f.count++;
- }
- }
-
- AddVTXInstruction(pAsm->pR700Shader, vertex_instruction_ptr);
-
- return GL_TRUE;
-}
-
-GLboolean add_tex_instruction(r700_AssemblerBase* pAsm,
- R700TextureInstruction* tex_instruction_ptr)
-{
- if ( GL_FALSE == check_current_clause(pAsm, CF_TEX_CLAUSE) )
- {
- return GL_FALSE;
- }
-
- if ( pAsm->cf_current_tex_clause_ptr == NULL ||
- ( (pAsm->cf_current_tex_clause_ptr != NULL) &&
- (pAsm->cf_current_tex_clause_ptr->m_Word1.f.count >= GetCFMaxInstructions(pAsm->cf_current_tex_clause_ptr->m_ShaderInstType)-1)
- ) )
- {
- // new tex cf instruction for this new clause
- pAsm->cf_current_tex_clause_ptr = (R700ControlFlowGenericClause*) CALLOC_STRUCT(R700ControlFlowGenericClause);
-
- if (pAsm->cf_current_tex_clause_ptr != NULL)
- {
- Init_R700ControlFlowGenericClause(pAsm->cf_current_tex_clause_ptr);
- AddCFInstruction( pAsm->pR700Shader,
- (R700ControlFlowInstruction *)pAsm->cf_current_tex_clause_ptr );
- }
- else
- {
- radeon_error("Could not allocate a new TEX CF instruction.\n");
- return GL_FALSE;
- }
-
- if(8 == pAsm->unAsic)
- {
- SETfield(pAsm->cf_current_tex_clause_ptr->m_Word1.val, EG_CF_INST_TC,
- EG_CF_WORD1__CF_INST_shift, EG_CF_WORD1__CF_INST_mask);
- SETfield(pAsm->cf_current_tex_clause_ptr->m_Word1.val, 0,
- EG_CF_WORD1__POP_COUNT_shift, EG_CF_WORD1__POP_COUNT_mask);
- SETfield(pAsm->cf_current_tex_clause_ptr->m_Word1.val, 0,
- EG_CF_WORD1__CF_CONST_shift, EG_CF_WORD1__CF_CONST_mask);
- SETfield(pAsm->cf_current_tex_clause_ptr->m_Word1.val, SQ_CF_COND_ACTIVE,
- EG_CF_WORD1__COND_shift, EG_CF_WORD1__COND_mask);
- SETfield(pAsm->cf_current_tex_clause_ptr->m_Word1.val, 0,
- EG_CF_WORD1__COUNT_shift, EG_CF_WORD1__COUNT_mask);
- SETfield(pAsm->cf_current_tex_clause_ptr->m_Word1.val, 0,
- EG_CF_WORD1__VPM_shift, EG_CF_WORD1__VPM_bit);
- SETfield(pAsm->cf_current_tex_clause_ptr->m_Word1.val, 0,
- EG_CF_WORD1__EOP_shift, EG_CF_WORD1__EOP_bit);
- SETfield(pAsm->cf_current_tex_clause_ptr->m_Word1.val, 0,
- EG_CF_WORD1__WQM_shift, EG_CF_WORD1__WQM_bit);
-#ifdef FORCE_CF_TEX_BARRIER
- SETfield(pAsm->cf_current_tex_clause_ptr->m_Word1.val, 1,
- EG_CF_WORD1__BARRIER_shift, EG_CF_WORD1__BARRIER_bit);
-#else
- SETfield(pAsm->cf_current_tex_clause_ptr->m_Word1.val, 0,
- EG_CF_WORD1__BARRIER_shift, EG_CF_WORD1__BARRIER_bit);
-#endif
- }
- else
- {
- pAsm->cf_current_tex_clause_ptr->m_Word1.f.pop_count = 0x0;
- pAsm->cf_current_tex_clause_ptr->m_Word1.f.cf_const = 0x0;
- pAsm->cf_current_tex_clause_ptr->m_Word1.f.cond = SQ_CF_COND_ACTIVE;
-
- pAsm->cf_current_tex_clause_ptr->m_Word1.f.end_of_program = 0x0;
- pAsm->cf_current_tex_clause_ptr->m_Word1.f.valid_pixel_mode = 0x0;
- pAsm->cf_current_tex_clause_ptr->m_Word1.f.cf_inst = SQ_CF_INST_TEX;
- pAsm->cf_current_tex_clause_ptr->m_Word1.f.whole_quad_mode = 0x0;
- pAsm->cf_current_tex_clause_ptr->m_Word1.f.barrier = 0x0; //0x1;
- }
- }
- else
- {
- if(8 == pAsm->unAsic)
- {
- unsigned int count = GETbits(pAsm->cf_current_tex_clause_ptr->m_Word1.val,
- EG_CF_WORD1__COUNT_shift, EG_CF_WORD1__COUNT_mask) + 1;
- SETfield(pAsm->cf_current_tex_clause_ptr->m_Word1.val, count,
- EG_CF_WORD1__COUNT_shift, EG_CF_WORD1__COUNT_mask);
- }
- else
- {
- pAsm->cf_current_tex_clause_ptr->m_Word1.f.count++;
- }
- }
-
- // If this clause constains any TEX instruction that is dependent on a
- // previous instruction, set the barrier bit, also always set for vert
- // programs as tex deps are not(yet) computed for them
- if( pAsm->currentShaderType == SPT_VP || pAsm->pInstDeps[pAsm->uiCurInst].nDstDep > (-1) || pAsm->need_tex_barrier == GL_TRUE )
- {
- pAsm->cf_current_tex_clause_ptr->m_Word1.f.barrier = 0x1;
- }
-
- if(NULL == pAsm->cf_current_tex_clause_ptr->m_pLinkedTEXInstruction)
- {
- pAsm->cf_current_tex_clause_ptr->m_pLinkedTEXInstruction = tex_instruction_ptr;
- tex_instruction_ptr->m_pLinkedGenericClause = pAsm->cf_current_tex_clause_ptr;
- }
-
- AddTEXInstruction(pAsm->pR700Shader, tex_instruction_ptr);
-
- return GL_TRUE;
-}
-
-GLboolean assemble_vfetch_instruction(r700_AssemblerBase* pAsm,
- GLuint gl_client_id,
- GLuint destination_register,
- GLuint number_of_elements,
- GLenum dataElementType,
- VTX_FETCH_METHOD* pFetchMethod)
-{
- GLuint client_size_inbyte;
- GLuint data_format;
- GLuint mega_fetch_count;
- GLuint is_mega_fetch_flag;
-
- R700VertexGenericFetch* vfetch_instruction_ptr;
- R700VertexGenericFetch* assembled_vfetch_instruction_ptr = pAsm->vfetch_instruction_ptr_array[ gl_client_id ];
-
- if (assembled_vfetch_instruction_ptr == NULL)
- {
- vfetch_instruction_ptr = (R700VertexGenericFetch*) CALLOC_STRUCT(R700VertexGenericFetch);
- if (vfetch_instruction_ptr == NULL)
- {
- return GL_FALSE;
- }
- Init_R700VertexGenericFetch(vfetch_instruction_ptr);
- }
- else
- {
- vfetch_instruction_ptr = assembled_vfetch_instruction_ptr;
- }
-
- data_format = GetSurfaceFormat(dataElementType, number_of_elements, &client_size_inbyte);
-
- if(GL_TRUE == pFetchMethod->bEnableMini) //More conditions here
- {
- //TODO : mini fetch
- mega_fetch_count = 0;
- is_mega_fetch_flag = 0;
- }
- else
- {
- mega_fetch_count = MEGA_FETCH_BYTES - 1;
- is_mega_fetch_flag = 0x1;
- pFetchMethod->mega_fetch_remainder = MEGA_FETCH_BYTES - client_size_inbyte;
- }
-
- vfetch_instruction_ptr->m_Word0.f.vtx_inst = SQ_VTX_INST_FETCH;
- vfetch_instruction_ptr->m_Word0.f.fetch_type = SQ_VTX_FETCH_VERTEX_DATA;
- vfetch_instruction_ptr->m_Word0.f.fetch_whole_quad = 0x0;
-
- vfetch_instruction_ptr->m_Word0.f.buffer_id = gl_client_id;
- vfetch_instruction_ptr->m_Word0.f.src_gpr = 0x0;
- vfetch_instruction_ptr->m_Word0.f.src_rel = SQ_ABSOLUTE;
- vfetch_instruction_ptr->m_Word0.f.src_sel_x = SQ_SEL_X;
- vfetch_instruction_ptr->m_Word0.f.mega_fetch_count = mega_fetch_count;
-
- vfetch_instruction_ptr->m_Word1.f.dst_sel_x = (number_of_elements < 1) ? SQ_SEL_0 : SQ_SEL_X;
- vfetch_instruction_ptr->m_Word1.f.dst_sel_y = (number_of_elements < 2) ? SQ_SEL_0 : SQ_SEL_Y;
- vfetch_instruction_ptr->m_Word1.f.dst_sel_z = (number_of_elements < 3) ? SQ_SEL_0 : SQ_SEL_Z;
- vfetch_instruction_ptr->m_Word1.f.dst_sel_w = (number_of_elements < 4) ? SQ_SEL_1 : SQ_SEL_W;
-
- vfetch_instruction_ptr->m_Word1.f.use_const_fields = 1;
-
- // Destination register
- vfetch_instruction_ptr->m_Word1_GPR.f.dst_gpr = destination_register;
- vfetch_instruction_ptr->m_Word1_GPR.f.dst_rel = SQ_ABSOLUTE;
-
- vfetch_instruction_ptr->m_Word2.f.offset = 0;
- vfetch_instruction_ptr->m_Word2.f.const_buf_no_stride = 0x0;
-
- vfetch_instruction_ptr->m_Word2.f.mega_fetch = is_mega_fetch_flag;
-
- if (assembled_vfetch_instruction_ptr == NULL)
- {
- if ( GL_FALSE == add_vfetch_instruction(pAsm, (R700VertexInstruction *)vfetch_instruction_ptr) )
- {
- return GL_FALSE;
- }
-
- if (pAsm->vfetch_instruction_ptr_array[ gl_client_id ] != NULL)
- {
- return GL_FALSE;
- }
- else
- {
- pAsm->vfetch_instruction_ptr_array[ gl_client_id ] = vfetch_instruction_ptr;
- }
- }
-
- return GL_TRUE;
-}
-
-GLboolean EG_assemble_vfetch_instruction(r700_AssemblerBase* pAsm,
- GLuint destination_register,
- GLenum type,
- GLint size,
- GLubyte element,
- GLuint _signed,
- GLboolean normalize,
- GLenum format,
- VTX_FETCH_METHOD * pFetchMethod)
-{
- GLuint client_size_inbyte;
- GLuint data_format;
- GLuint mega_fetch_count;
- GLuint is_mega_fetch_flag;
-
- GLuint dst_sel_x, dst_sel_y, dst_sel_z, dst_sel_w;
-
- R700VertexGenericFetch* vfetch_instruction_ptr;
- R700VertexGenericFetch* assembled_vfetch_instruction_ptr
- = pAsm->vfetch_instruction_ptr_array[element];
-
- if (assembled_vfetch_instruction_ptr == NULL)
- {
- vfetch_instruction_ptr = (R700VertexGenericFetch*) CALLOC_STRUCT(R700VertexGenericFetch);
- if (vfetch_instruction_ptr == NULL)
- {
- return GL_FALSE;
- }
- Init_R700VertexGenericFetch(vfetch_instruction_ptr);
- }
- else
- {
- vfetch_instruction_ptr = assembled_vfetch_instruction_ptr;
- }
-
- data_format = GetSurfaceFormat(type, size, &client_size_inbyte);
-
- if(GL_TRUE == pFetchMethod->bEnableMini) //More conditions here
- {
- //TODO : mini fetch
- mega_fetch_count = 0;
- is_mega_fetch_flag = 0;
- }
- else
- {
- mega_fetch_count = MEGA_FETCH_BYTES - 1;
- is_mega_fetch_flag = 0x1;
- pFetchMethod->mega_fetch_remainder = MEGA_FETCH_BYTES - client_size_inbyte;
- }
-
- SETfield(vfetch_instruction_ptr->m_Word0.val, EG_VC_INST_FETCH,
- EG_VTX_WORD0__VC_INST_shift,
- EG_VTX_WORD0__VC_INST_mask);
- SETfield(vfetch_instruction_ptr->m_Word0.val, EG_VTX_FETCH_VERTEX_DATA,
- EG_VTX_WORD0__FETCH_TYPE_shift,
- EG_VTX_WORD0__FETCH_TYPE_mask);
- CLEARbit(vfetch_instruction_ptr->m_Word0.val,
- EG_VTX_WORD0__FWQ_bit);
- SETfield(vfetch_instruction_ptr->m_Word0.val, element,
- EG_VTX_WORD0__BUFFER_ID_shift,
- EG_VTX_WORD0__BUFFER_ID_mask);
- SETfield(vfetch_instruction_ptr->m_Word0.val, 0x0,
- EG_VTX_WORD0__SRC_GPR_shift,
- EG_VTX_WORD0__SRC_GPR_mask);
- SETfield(vfetch_instruction_ptr->m_Word0.val, SQ_ABSOLUTE,
- EG_VTX_WORD0__SRC_REL_shift,
- EG_VTX_WORD0__SRC_REL_bit);
- SETfield(vfetch_instruction_ptr->m_Word0.val, SQ_SEL_X,
- EG_VTX_WORD0__SRC_SEL_X_shift,
- EG_VTX_WORD0__SRC_SEL_X_mask);
- SETfield(vfetch_instruction_ptr->m_Word0.val, mega_fetch_count,
- EG_VTX_WORD0__MFC_shift,
- EG_VTX_WORD0__MFC_mask);
-
- if(format == GL_BGRA)
- {
- dst_sel_x = (size < 1) ? SQ_SEL_0 : SQ_SEL_Z;
- dst_sel_y = (size < 2) ? SQ_SEL_0 : SQ_SEL_Y;
- dst_sel_z = (size < 3) ? SQ_SEL_0 : SQ_SEL_X;
- dst_sel_w = (size < 4) ? SQ_SEL_1 : SQ_SEL_W;
- }
- else
- {
- dst_sel_x = (size < 1) ? SQ_SEL_0 : SQ_SEL_X;
- dst_sel_y = (size < 2) ? SQ_SEL_0 : SQ_SEL_Y;
- dst_sel_z = (size < 3) ? SQ_SEL_0 : SQ_SEL_Z;
- dst_sel_w = (size < 4) ? SQ_SEL_1 : SQ_SEL_W;
-
- }
- SETfield(vfetch_instruction_ptr->m_Word1.val, dst_sel_x,
- EG_VTX_WORD1__DST_SEL_X_shift,
- EG_VTX_WORD1__DST_SEL_X_mask);
- SETfield(vfetch_instruction_ptr->m_Word1.val, dst_sel_y,
- EG_VTX_WORD1__DST_SEL_Y_shift,
- EG_VTX_WORD1__DST_SEL_Y_mask);
- SETfield(vfetch_instruction_ptr->m_Word1.val, dst_sel_z,
- EG_VTX_WORD1__DST_SEL_Z_shift,
- EG_VTX_WORD1__DST_SEL_Z_mask);
- SETfield(vfetch_instruction_ptr->m_Word1.val, dst_sel_w,
- EG_VTX_WORD1__DST_SEL_W_shift,
- EG_VTX_WORD1__DST_SEL_W_mask);
-
- SETfield(vfetch_instruction_ptr->m_Word1.val, 1,
- EG_VTX_WORD1__UCF_shift,
- EG_VTX_WORD1__UCF_bit);
- SETfield(vfetch_instruction_ptr->m_Word1.val, data_format,
- EG_VTX_WORD1__DATA_FORMAT_shift,
- EG_VTX_WORD1__DATA_FORMAT_mask);
-#ifdef TEST_VFETCH
- SETfield(vfetch_instruction_ptr->m_Word1.val, SQ_FORMAT_COMP_SIGNED,
- EG_VTX_WORD1__FCA_shift,
- EG_VTX_WORD1__FCA_bit);
-#else
- if(1 == _signed)
- {
- SETfield(vfetch_instruction_ptr->m_Word1.val, SQ_FORMAT_COMP_SIGNED,
- EG_VTX_WORD1__FCA_shift,
- EG_VTX_WORD1__FCA_bit);
- }
- else
- {
- SETfield(vfetch_instruction_ptr->m_Word1.val, SQ_FORMAT_COMP_UNSIGNED,
- EG_VTX_WORD1__FCA_shift,
- EG_VTX_WORD1__FCA_bit);
- }
-#endif /* TEST_VFETCH */
-
- if(GL_TRUE == normalize)
- {
- SETfield(vfetch_instruction_ptr->m_Word1.val, SQ_NUM_FORMAT_NORM,
- EG_VTX_WORD1__NFA_shift,
- EG_VTX_WORD1__NFA_mask);
- }
- else
- {
- SETfield(vfetch_instruction_ptr->m_Word1.val, SQ_NUM_FORMAT_SCALED,
- EG_VTX_WORD1__NFA_shift,
- EG_VTX_WORD1__NFA_mask);
- }
-
- /* Destination register */
- SETfield(vfetch_instruction_ptr->m_Word1.val, destination_register,
- EG_VTX_WORD1_GPR__DST_GPR_shift,
- EG_VTX_WORD1_GPR__DST_GPR_mask);
- SETfield(vfetch_instruction_ptr->m_Word1.val, SQ_ABSOLUTE,
- EG_VTX_WORD1_GPR__DST_REL_shift,
- EG_VTX_WORD1_GPR__DST_REL_bit);
-
-
- SETfield(vfetch_instruction_ptr->m_Word2.val, 0,
- EG_VTX_WORD2__OFFSET_shift,
- EG_VTX_WORD2__OFFSET_mask);
- SETfield(vfetch_instruction_ptr->m_Word2.val,
-#ifdef MESA_BIG_ENDIAN
- SQ_ENDIAN_8IN32,
-#else
- SQ_ENDIAN_NONE,
-#endif
- EG_VTX_WORD2__ENDIAN_SWAP_shift,
- EG_VTX_WORD2__ENDIAN_SWAP_mask);
- SETfield(vfetch_instruction_ptr->m_Word2.val, 0,
- EG_VTX_WORD2__CBNS_shift,
- EG_VTX_WORD2__CBNS_bit);
- SETfield(vfetch_instruction_ptr->m_Word2.val, is_mega_fetch_flag,
- EG_VTX_WORD2__MEGA_FETCH_shift,
- EG_VTX_WORD2__MEGA_FETCH_mask);
-
- if (assembled_vfetch_instruction_ptr == NULL)
- {
- if ( GL_FALSE == add_vfetch_instruction(pAsm, (R700VertexInstruction *)vfetch_instruction_ptr) )
- {
- return GL_FALSE;
- }
-
- if (pAsm->vfetch_instruction_ptr_array[element] != NULL)
- {
- return GL_FALSE;
- }
- else
- {
- pAsm->vfetch_instruction_ptr_array[element] = vfetch_instruction_ptr;
- }
- }
-
- return GL_TRUE;
-}
-
-GLboolean assemble_vfetch_instruction2(r700_AssemblerBase* pAsm,
- GLuint destination_register,
- GLenum type,
- GLint size,
- GLubyte element,
- GLuint _signed,
- GLboolean normalize,
- GLenum format,
- VTX_FETCH_METHOD * pFetchMethod)
-{
- GLuint client_size_inbyte;
- GLuint data_format;
- GLuint mega_fetch_count;
- GLuint is_mega_fetch_flag;
-
- R700VertexGenericFetch* vfetch_instruction_ptr;
- R700VertexGenericFetch* assembled_vfetch_instruction_ptr
- = pAsm->vfetch_instruction_ptr_array[element];
-
- if (assembled_vfetch_instruction_ptr == NULL)
- {
- vfetch_instruction_ptr = (R700VertexGenericFetch*) CALLOC_STRUCT(R700VertexGenericFetch);
- if (vfetch_instruction_ptr == NULL)
- {
- return GL_FALSE;
- }
- Init_R700VertexGenericFetch(vfetch_instruction_ptr);
- }
- else
- {
- vfetch_instruction_ptr = assembled_vfetch_instruction_ptr;
- }
-
- data_format = GetSurfaceFormat(type, size, &client_size_inbyte);
-
- if(GL_TRUE == pFetchMethod->bEnableMini) //More conditions here
- {
- //TODO : mini fetch
- mega_fetch_count = 0;
- is_mega_fetch_flag = 0;
- }
- else
- {
- mega_fetch_count = MEGA_FETCH_BYTES - 1;
- is_mega_fetch_flag = 0x1;
- pFetchMethod->mega_fetch_remainder = MEGA_FETCH_BYTES - client_size_inbyte;
- }
-
- vfetch_instruction_ptr->m_Word0.f.vtx_inst = SQ_VTX_INST_FETCH;
- vfetch_instruction_ptr->m_Word0.f.fetch_type = SQ_VTX_FETCH_VERTEX_DATA;
- vfetch_instruction_ptr->m_Word0.f.fetch_whole_quad = 0x0;
-
- vfetch_instruction_ptr->m_Word0.f.buffer_id = element;
- vfetch_instruction_ptr->m_Word0.f.src_gpr = 0x0;
- vfetch_instruction_ptr->m_Word0.f.src_rel = SQ_ABSOLUTE;
- vfetch_instruction_ptr->m_Word0.f.src_sel_x = SQ_SEL_X;
- vfetch_instruction_ptr->m_Word0.f.mega_fetch_count = mega_fetch_count;
-
- if(format == GL_BGRA)
- {
- vfetch_instruction_ptr->m_Word1.f.dst_sel_x = (size < 1) ? SQ_SEL_0 : SQ_SEL_Z;
- vfetch_instruction_ptr->m_Word1.f.dst_sel_y = (size < 2) ? SQ_SEL_0 : SQ_SEL_Y;
- vfetch_instruction_ptr->m_Word1.f.dst_sel_z = (size < 3) ? SQ_SEL_0 : SQ_SEL_X;
- vfetch_instruction_ptr->m_Word1.f.dst_sel_w = (size < 4) ? SQ_SEL_1 : SQ_SEL_W;
- }
- else
- {
- vfetch_instruction_ptr->m_Word1.f.dst_sel_x = (size < 1) ? SQ_SEL_0 : SQ_SEL_X;
- vfetch_instruction_ptr->m_Word1.f.dst_sel_y = (size < 2) ? SQ_SEL_0 : SQ_SEL_Y;
- vfetch_instruction_ptr->m_Word1.f.dst_sel_z = (size < 3) ? SQ_SEL_0 : SQ_SEL_Z;
- vfetch_instruction_ptr->m_Word1.f.dst_sel_w = (size < 4) ? SQ_SEL_1 : SQ_SEL_W;
-
- }
-
- vfetch_instruction_ptr->m_Word1.f.use_const_fields = 1;
- vfetch_instruction_ptr->m_Word1.f.data_format = data_format;
-#ifdef MESA_BIG_ENDIAN
- vfetch_instruction_ptr->m_Word2.f.endian_swap = SQ_ENDIAN_8IN32;
-#else
- vfetch_instruction_ptr->m_Word2.f.endian_swap = SQ_ENDIAN_NONE;
-#endif
-
- if(1 == _signed)
- {
- vfetch_instruction_ptr->m_Word1.f.format_comp_all = SQ_FORMAT_COMP_SIGNED;
- }
- else
- {
- vfetch_instruction_ptr->m_Word1.f.format_comp_all = SQ_FORMAT_COMP_UNSIGNED;
- }
-
- if(GL_TRUE == normalize)
- {
- vfetch_instruction_ptr->m_Word1.f.num_format_all = SQ_NUM_FORMAT_NORM;
- }
- else
- {
- vfetch_instruction_ptr->m_Word1.f.num_format_all = SQ_NUM_FORMAT_INT;
- }
-
- // Destination register
- vfetch_instruction_ptr->m_Word1_GPR.f.dst_gpr = destination_register;
- vfetch_instruction_ptr->m_Word1_GPR.f.dst_rel = SQ_ABSOLUTE;
-
- vfetch_instruction_ptr->m_Word2.f.offset = 0;
- vfetch_instruction_ptr->m_Word2.f.const_buf_no_stride = 0x0;
-
- vfetch_instruction_ptr->m_Word2.f.mega_fetch = is_mega_fetch_flag;
-
- if (assembled_vfetch_instruction_ptr == NULL)
- {
- if ( GL_FALSE == add_vfetch_instruction(pAsm, (R700VertexInstruction *)vfetch_instruction_ptr) )
- {
- return GL_FALSE;
- }
-
- if (pAsm->vfetch_instruction_ptr_array[element] != NULL)
- {
- return GL_FALSE;
- }
- else
- {
- pAsm->vfetch_instruction_ptr_array[element] = vfetch_instruction_ptr;
- }
- }
-
- return GL_TRUE;
-}
-
-GLboolean cleanup_vfetch_instructions(r700_AssemblerBase* pAsm)
-{
- GLint i;
- pAsm->cf_current_clause_type = CF_EMPTY_CLAUSE;
- pAsm->cf_current_vtx_clause_ptr = NULL;
-
- for (i=0; i<VERT_ATTRIB_MAX; i++)
- {
- pAsm->vfetch_instruction_ptr_array[ i ] = NULL;
- }
-
- cleanup_vfetch_shaderinst(pAsm->pR700Shader);
-
- return GL_TRUE;
-}
-
-GLuint gethelpr(r700_AssemblerBase* pAsm)
-{
- GLuint r = pAsm->uHelpReg;
- pAsm->uHelpReg++;
- if (pAsm->uHelpReg > pAsm->number_used_registers)
- {
- pAsm->number_used_registers = pAsm->uHelpReg;
- }
- return r;
-}
-void resethelpr(r700_AssemblerBase* pAsm)
-{
- pAsm->uHelpReg = pAsm->uFirstHelpReg;
-}
-
-void checkop_init(r700_AssemblerBase* pAsm)
-{
- resethelpr(pAsm);
- pAsm->aArgSubst[0] =
- pAsm->aArgSubst[1] =
- pAsm->aArgSubst[2] =
- pAsm->aArgSubst[3] = -1;
-}
-
-static GLboolean next_ins(r700_AssemblerBase *pAsm)
-{
- struct prog_instruction *pILInst = &(pAsm->pILInst[pAsm->uiCurInst]);
-
- if (GL_TRUE == pAsm->is_tex)
- {
- if (pILInst->TexSrcTarget == TEXTURE_RECT_INDEX)
- {
- if (GL_FALSE == assemble_tex_instruction(pAsm, GL_FALSE))
- {
- radeon_error("Error assembling TEX instruction\n");
- return GL_FALSE;
- }
- }
- else
- {
- if (GL_FALSE == assemble_tex_instruction(pAsm, GL_TRUE))
- {
- radeon_error("Error assembling TEX instruction\n");
- return GL_FALSE;
- }
- }
- }
- else
- { //ALU
- if (GL_FALSE == assemble_alu_instruction(pAsm))
- {
- radeon_error("Error assembling ALU instruction\n");
- return GL_FALSE;
- }
- }
-
- if (pAsm->D.dst.rtype == DST_REG_OUT)
- {
- assert(pAsm->D.dst.reg >= pAsm->starting_export_register_number);
- }
-
- //reset for next inst.
- pAsm->D.bits = 0;
- pAsm->D2.bits = 0;
- pAsm->S[0].bits = 0;
- pAsm->S[1].bits = 0;
- pAsm->S[2].bits = 0;
- pAsm->is_tex = GL_FALSE;
- pAsm->need_tex_barrier = GL_FALSE;
- pAsm->D2.bits = 0;
- pAsm->C[0].bits = pAsm->C[1].bits = pAsm->C[2].bits = pAsm->C[3].bits = 0;
- return GL_TRUE;
-}
-
-GLboolean mov_temp(r700_AssemblerBase* pAsm, int src)
-{
- GLuint tmp = gethelpr(pAsm);
-
- //mov src to temp helper gpr.
- pAsm->D.dst.opcode = SQ_OP2_INST_MOV;
-
- setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE);
-
- pAsm->D.dst.rtype = DST_REG_TEMPORARY;
- pAsm->D.dst.reg = tmp;
-
- nomask_PVSDST(&(pAsm->D.dst));
-
- if( GL_FALSE == assemble_src(pAsm, src, 0) )
- {
- return GL_FALSE;
- }
-
- noswizzle_PVSSRC(&(pAsm->S[0].src));
- noneg_PVSSRC(&(pAsm->S[0].src));
-
- if( GL_FALSE == next_ins(pAsm) )
- {
- return GL_FALSE;
- }
-
- pAsm->aArgSubst[1 + src] = tmp;
-
- return GL_TRUE;
-}
-
-GLboolean checkop1(r700_AssemblerBase* pAsm)
-{
- checkop_init(pAsm);
- return GL_TRUE;
-}
-
-GLboolean checkop2(r700_AssemblerBase* pAsm)
-{
- GLboolean bSrcConst[2];
- struct prog_instruction *pILInst = &(pAsm->pILInst[pAsm->uiCurInst]);
-
- checkop_init(pAsm);
-
- if( (pILInst->SrcReg[0].File == PROGRAM_UNIFORM) ||
- (pILInst->SrcReg[0].File == PROGRAM_CONSTANT) ||
- (pILInst->SrcReg[0].File == PROGRAM_LOCAL_PARAM) ||
- (pILInst->SrcReg[0].File == PROGRAM_ENV_PARAM) ||
- (pILInst->SrcReg[0].File == PROGRAM_STATE_VAR) )
- {
- bSrcConst[0] = GL_TRUE;
- }
- else
- {
- bSrcConst[0] = GL_FALSE;
- }
- if( (pILInst->SrcReg[1].File == PROGRAM_UNIFORM) ||
- (pILInst->SrcReg[1].File == PROGRAM_CONSTANT) ||
- (pILInst->SrcReg[1].File == PROGRAM_LOCAL_PARAM) ||
- (pILInst->SrcReg[1].File == PROGRAM_ENV_PARAM) ||
- (pILInst->SrcReg[1].File == PROGRAM_STATE_VAR) )
- {
- bSrcConst[1] = GL_TRUE;
- }
- else
- {
- bSrcConst[1] = GL_FALSE;
- }
-
- if( (bSrcConst[0] == GL_TRUE) && (bSrcConst[1] == GL_TRUE) )
- {
- if(pILInst->SrcReg[0].Index != pILInst->SrcReg[1].Index)
- {
- if( GL_FALSE == mov_temp(pAsm, 1) )
- {
- return GL_FALSE;
- }
- }
- }
-
- return GL_TRUE;
-}
-
-GLboolean checkop3(r700_AssemblerBase* pAsm)
-{
- GLboolean bSrcConst[3];
- struct prog_instruction *pILInst = &(pAsm->pILInst[pAsm->uiCurInst]);
-
- checkop_init(pAsm);
-
- if( (pILInst->SrcReg[0].File == PROGRAM_UNIFORM) ||
- (pILInst->SrcReg[0].File == PROGRAM_CONSTANT) ||
- (pILInst->SrcReg[0].File == PROGRAM_LOCAL_PARAM) ||
- (pILInst->SrcReg[0].File == PROGRAM_ENV_PARAM) ||
- (pILInst->SrcReg[0].File == PROGRAM_STATE_VAR) )
- {
- bSrcConst[0] = GL_TRUE;
- }
- else
- {
- bSrcConst[0] = GL_FALSE;
- }
- if( (pILInst->SrcReg[1].File == PROGRAM_UNIFORM) ||
- (pILInst->SrcReg[1].File == PROGRAM_CONSTANT) ||
- (pILInst->SrcReg[1].File == PROGRAM_LOCAL_PARAM) ||
- (pILInst->SrcReg[1].File == PROGRAM_ENV_PARAM) ||
- (pILInst->SrcReg[1].File == PROGRAM_STATE_VAR) )
- {
- bSrcConst[1] = GL_TRUE;
- }
- else
- {
- bSrcConst[1] = GL_FALSE;
- }
- if( (pILInst->SrcReg[2].File == PROGRAM_UNIFORM) ||
- (pILInst->SrcReg[2].File == PROGRAM_CONSTANT) ||
- (pILInst->SrcReg[2].File == PROGRAM_LOCAL_PARAM) ||
- (pILInst->SrcReg[2].File == PROGRAM_ENV_PARAM) ||
- (pILInst->SrcReg[2].File == PROGRAM_STATE_VAR) )
- {
- bSrcConst[2] = GL_TRUE;
- }
- else
- {
- bSrcConst[2] = GL_FALSE;
- }
-
- if( (GL_TRUE == bSrcConst[0]) &&
- (GL_TRUE == bSrcConst[1]) &&
- (GL_TRUE == bSrcConst[2]) )
- {
- if( GL_FALSE == mov_temp(pAsm, 1) )
- {
- return GL_FALSE;
- }
- if( GL_FALSE == mov_temp(pAsm, 2) )
- {
- return GL_FALSE;
- }
-
- return GL_TRUE;
- }
- else if( (GL_TRUE == bSrcConst[0]) &&
- (GL_TRUE == bSrcConst[1]) )
- {
- if(pILInst->SrcReg[0].Index != pILInst->SrcReg[1].Index)
- {
- if( GL_FALSE == mov_temp(pAsm, 1) )
- {
- return GL_FALSE;
- }
- }
-
- return GL_TRUE;
- }
- else if ( (GL_TRUE == bSrcConst[0]) &&
- (GL_TRUE == bSrcConst[2]) )
- {
- if(pILInst->SrcReg[0].Index != pILInst->SrcReg[2].Index)
- {
- if( GL_FALSE == mov_temp(pAsm, 2) )
- {
- return GL_FALSE;
- }
- }
-
- return GL_TRUE;
- }
- else if( (GL_TRUE == bSrcConst[1]) &&
- (GL_TRUE == bSrcConst[2]) )
- {
- if(pILInst->SrcReg[1].Index != pILInst->SrcReg[2].Index)
- {
- if( GL_FALSE == mov_temp(pAsm, 2) )
- {
- return GL_FALSE;
- }
- }
-
- return GL_TRUE;
- }
-
- return GL_TRUE;
-}
-
-GLboolean assemble_src(r700_AssemblerBase *pAsm,
- int src,
- int fld)
-{
- struct prog_instruction *pILInst = &(pAsm->pILInst[pAsm->uiCurInst]);
-
- if (fld == -1)
- {
- fld = src;
- }
-
- if(pAsm->aArgSubst[1+src] >= 0)
- {
- assert(fld >= 0);
- setaddrmode_PVSSRC(&(pAsm->S[fld].src), ADDR_ABSOLUTE);
- pAsm->S[fld].src.rtype = SRC_REG_TEMPORARY;
- pAsm->S[fld].src.reg = pAsm->aArgSubst[1+src];
- }
- else
- {
- if (1 == pILInst->SrcReg[src].RelAddr)
- {
- setaddrmode_PVSSRC(&(pAsm->S[fld].src), ADDR_RELATIVE_A0);
- }
- else
- {
- setaddrmode_PVSSRC(&(pAsm->S[fld].src), ADDR_ABSOLUTE);
- }
- switch (pILInst->SrcReg[src].File)
- {
- case PROGRAM_TEMPORARY:
- pAsm->S[fld].src.rtype = SRC_REG_TEMPORARY;
- pAsm->S[fld].src.reg = pILInst->SrcReg[src].Index + pAsm->starting_temp_register_number;
- break;
- case PROGRAM_CONSTANT:
- case PROGRAM_LOCAL_PARAM:
- case PROGRAM_ENV_PARAM:
- case PROGRAM_STATE_VAR:
- case PROGRAM_UNIFORM:
- pAsm->S[fld].src.rtype = SRC_REG_CONSTANT;
- if(pILInst->SrcReg[src].Index < 0)
- {
- WARN_ONCE("Negative register offsets not supported yet!\n");
- pAsm->S[fld].src.reg = 0;
- }
- else
- {
- pAsm->S[fld].src.reg = pILInst->SrcReg[src].Index;
- }
- break;
- case PROGRAM_INPUT:
- pAsm->S[fld].src.rtype = SRC_REG_GPR;
- switch (pAsm->currentShaderType)
- {
- case SPT_FP:
- pAsm->S[fld].src.reg = pAsm->uiFP_AttributeMap[pILInst->SrcReg[src].Index];
- break;
- case SPT_VP:
- pAsm->S[fld].src.reg = pAsm->ucVP_AttributeMap[pILInst->SrcReg[src].Index];
- break;
- }
- break;
- case PROGRAM_OUTPUT:
- pAsm->S[fld].src.rtype = SRC_REG_GPR;
- switch (pAsm->currentShaderType)
- {
- case SPT_FP:
- pAsm->S[fld].src.reg = pAsm->uiFP_OutputMap[pILInst->SrcReg[src].Index];
- break;
- case SPT_VP:
- pAsm->S[fld].src.reg = pAsm->ucVP_OutputMap[pILInst->SrcReg[src].Index];
- break;
- }
- break;
- default:
- radeon_error("Invalid source argument type : %d \n", pILInst->SrcReg[src].File);
- return GL_FALSE;
- }
- }
-
- pAsm->S[fld].src.swizzlex = pILInst->SrcReg[src].Swizzle & 0x7;
- pAsm->S[fld].src.swizzley = (pILInst->SrcReg[src].Swizzle >> 3) & 0x7;
- pAsm->S[fld].src.swizzlez = (pILInst->SrcReg[src].Swizzle >> 6) & 0x7;
- pAsm->S[fld].src.swizzlew = (pILInst->SrcReg[src].Swizzle >> 9) & 0x7;
-
- pAsm->S[fld].src.negx = pILInst->SrcReg[src].Negate & 0x1;
- pAsm->S[fld].src.negy = (pILInst->SrcReg[src].Negate >> 1) & 0x1;
- pAsm->S[fld].src.negz = (pILInst->SrcReg[src].Negate >> 2) & 0x1;
- pAsm->S[fld].src.negw = (pILInst->SrcReg[src].Negate >> 3) & 0x1;
-
- return GL_TRUE;
-}
-
-GLboolean assemble_dst(r700_AssemblerBase *pAsm)
-{
- struct prog_instruction *pILInst = &(pAsm->pILInst[pAsm->uiCurInst]);
- switch (pILInst->DstReg.File)
- {
- case PROGRAM_TEMPORARY:
- if (1 == pILInst->DstReg.RelAddr)
- {
- setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_RELATIVE_A0);
- }
- else
- {
- setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE);
- }
- pAsm->D.dst.rtype = DST_REG_TEMPORARY;
- pAsm->D.dst.reg = pILInst->DstReg.Index + pAsm->starting_temp_register_number;
- break;
- case PROGRAM_ADDRESS:
- setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE);
- pAsm->D.dst.rtype = DST_REG_A0;
- pAsm->D.dst.reg = 0;
- break;
- case PROGRAM_OUTPUT:
- if (1 == pILInst->DstReg.RelAddr)
- {
- setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_RELATIVE_A0);
- }
- else
- {
- setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE);
- }
- pAsm->D.dst.rtype = DST_REG_OUT;
- switch (pAsm->currentShaderType)
- {
- case SPT_FP:
- pAsm->D.dst.reg = pAsm->uiFP_OutputMap[pILInst->DstReg.Index];
- break;
- case SPT_VP:
- pAsm->D.dst.reg = pAsm->ucVP_OutputMap[pILInst->DstReg.Index];
- break;
- }
- break;
- default:
- radeon_error("Invalid destination output argument type\n");
- return GL_FALSE;
- }
-
- pAsm->D.dst.writex = pILInst->DstReg.WriteMask & 0x1;
- pAsm->D.dst.writey = (pILInst->DstReg.WriteMask >> 1) & 0x1;
- pAsm->D.dst.writez = (pILInst->DstReg.WriteMask >> 2) & 0x1;
- pAsm->D.dst.writew = (pILInst->DstReg.WriteMask >> 3) & 0x1;
-
- if(pILInst->SaturateMode == SATURATE_ZERO_ONE)
- {
- pAsm->D2.dst2.SaturateMode = 1;
- }
- else
- {
- pAsm->D2.dst2.SaturateMode = 0;
- }
-
- return GL_TRUE;
-}
-
-GLboolean tex_dst(r700_AssemblerBase *pAsm)
-{
- struct prog_instruction *pILInst = &(pAsm->pILInst[pAsm->uiCurInst]);
-
- if(PROGRAM_TEMPORARY == pILInst->DstReg.File)
- {
- pAsm->D.dst.rtype = DST_REG_TEMPORARY;
- pAsm->D.dst.reg = pAsm->pILInst[pAsm->uiCurInst].DstReg.Index + pAsm->starting_temp_register_number;
-
- setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE);
- }
- else if(PROGRAM_OUTPUT == pILInst->DstReg.File)
- {
- pAsm->D.dst.rtype = DST_REG_OUT;
- switch (pAsm->currentShaderType)
- {
- case SPT_FP:
- pAsm->D.dst.reg = pAsm->uiFP_OutputMap[pILInst->DstReg.Index];
- break;
- case SPT_VP:
- pAsm->D.dst.reg = pAsm->ucVP_OutputMap[pILInst->DstReg.Index];
- break;
- }
-
- setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE);
- }
- else
- {
- radeon_error("Invalid destination output argument type\n");
- return GL_FALSE;
- }
-
- pAsm->D.dst.writex = pILInst->DstReg.WriteMask & 0x1;
- pAsm->D.dst.writey = (pILInst->DstReg.WriteMask >> 1) & 0x1;
- pAsm->D.dst.writez = (pILInst->DstReg.WriteMask >> 2) & 0x1;
- pAsm->D.dst.writew = (pILInst->DstReg.WriteMask >> 3) & 0x1;
-
- return GL_TRUE;
-}
-
-GLboolean tex_src(r700_AssemblerBase *pAsm)
-{
- struct prog_instruction *pILInst = &(pAsm->pILInst[pAsm->uiCurInst]);
-
- GLboolean bValidTexCoord = GL_FALSE;
-
- if(pAsm->aArgSubst[1] >= 0)
- {
- bValidTexCoord = GL_TRUE;
- setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE);
- pAsm->S[0].src.rtype = SRC_REG_TEMPORARY;
- pAsm->S[0].src.reg = pAsm->aArgSubst[1];
- }
- else
- {
- switch (pILInst->SrcReg[0].File) {
- case PROGRAM_UNIFORM:
- case PROGRAM_CONSTANT:
- case PROGRAM_LOCAL_PARAM:
- case PROGRAM_ENV_PARAM:
- case PROGRAM_STATE_VAR:
- break;
- case PROGRAM_TEMPORARY:
- bValidTexCoord = GL_TRUE;
- pAsm->S[0].src.reg = pILInst->SrcReg[0].Index +
- pAsm->starting_temp_register_number;
- pAsm->S[0].src.rtype = SRC_REG_TEMPORARY;
- break;
- case PROGRAM_INPUT:
- if(SPT_VP == pAsm->currentShaderType)
- {
- switch (pILInst->SrcReg[0].Index)
- {
- case VERT_ATTRIB_TEX0:
- case VERT_ATTRIB_TEX1:
- case VERT_ATTRIB_TEX2:
- case VERT_ATTRIB_TEX3:
- case VERT_ATTRIB_TEX4:
- case VERT_ATTRIB_TEX5:
- case VERT_ATTRIB_TEX6:
- case VERT_ATTRIB_TEX7:
- bValidTexCoord = GL_TRUE;
- pAsm->S[0].src.reg =
- pAsm->ucVP_AttributeMap[pILInst->SrcReg[0].Index];
- pAsm->S[0].src.rtype = SRC_REG_GPR;
- break;
- }
- }
- else
- {
- switch (pILInst->SrcReg[0].Index)
- {
- case FRAG_ATTRIB_WPOS:
- case FRAG_ATTRIB_COL0:
- case FRAG_ATTRIB_COL1:
- case FRAG_ATTRIB_FOGC:
- case FRAG_ATTRIB_TEX0:
- case FRAG_ATTRIB_TEX1:
- case FRAG_ATTRIB_TEX2:
- case FRAG_ATTRIB_TEX3:
- case FRAG_ATTRIB_TEX4:
- case FRAG_ATTRIB_TEX5:
- case FRAG_ATTRIB_TEX6:
- case FRAG_ATTRIB_TEX7:
- bValidTexCoord = GL_TRUE;
- pAsm->S[0].src.reg =
- pAsm->uiFP_AttributeMap[pILInst->SrcReg[0].Index];
- pAsm->S[0].src.rtype = SRC_REG_GPR;
- break;
- case FRAG_ATTRIB_FACE:
- fprintf(stderr, "FRAG_ATTRIB_FACE unsupported\n");
- break;
- case FRAG_ATTRIB_PNTC:
- fprintf(stderr, "FRAG_ATTRIB_PNTC unsupported\n");
- break;
- }
-
- if( (pILInst->SrcReg[0].Index >= FRAG_ATTRIB_VAR0) ||
- (pILInst->SrcReg[0].Index < FRAG_ATTRIB_MAX) )
- {
- bValidTexCoord = GL_TRUE;
- pAsm->S[0].src.reg =
- pAsm->uiFP_AttributeMap[pILInst->SrcReg[0].Index];
- pAsm->S[0].src.rtype = SRC_REG_GPR;
- }
- }
-
- break;
- }
- }
-
- if(GL_TRUE == bValidTexCoord)
- {
- setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE);
- }
- else
- {
- radeon_error("Invalid source texcoord for TEX instruction\n");
- return GL_FALSE;
- }
-
- pAsm->S[0].src.swizzlex = pILInst->SrcReg[0].Swizzle & 0x7;
- pAsm->S[0].src.swizzley = (pILInst->SrcReg[0].Swizzle >> 3) & 0x7;
- pAsm->S[0].src.swizzlez = (pILInst->SrcReg[0].Swizzle >> 6) & 0x7;
- pAsm->S[0].src.swizzlew = (pILInst->SrcReg[0].Swizzle >> 9) & 0x7;
-
- pAsm->S[0].src.negx = pILInst->SrcReg[0].Negate & 0x1;
- pAsm->S[0].src.negy = (pILInst->SrcReg[0].Negate >> 1) & 0x1;
- pAsm->S[0].src.negz = (pILInst->SrcReg[0].Negate >> 2) & 0x1;
- pAsm->S[0].src.negw = (pILInst->SrcReg[0].Negate >> 3) & 0x1;
-
- return GL_TRUE;
-}
-
-GLboolean assemble_tex_instruction(r700_AssemblerBase *pAsm, GLboolean normalized)
-{
- PVSSRC * texture_coordinate_source;
- PVSSRC * texture_unit_source;
-
- R700TextureInstruction* tex_instruction_ptr = (R700TextureInstruction*) CALLOC_STRUCT(R700TextureInstruction);
- if (tex_instruction_ptr == NULL)
- {
- return GL_FALSE;
- }
- Init_R700TextureInstruction(tex_instruction_ptr);
-
- texture_coordinate_source = &(pAsm->S[0].src);
- texture_unit_source = &(pAsm->S[1].src);
-
- if(8 == pAsm->unAsic) /* evergreen */
- {
-
- SETfield(tex_instruction_ptr->m_Word0.val, pAsm->D.dst.opcode,
- EG_TEX_WORD0__TEX_INST_shift,
- EG_TEX_WORD0__TEX_INST_mask);
-
- if( (SQ_TEX_INST_GET_GRADIENTS_H == pAsm->D.dst.opcode)
- ||(SQ_TEX_INST_GET_GRADIENTS_V == pAsm->D.dst.opcode) )
- {
- /* Use fine texel derivative calculation rather than use quad derivative */
- SETfield(tex_instruction_ptr->m_Word0.val, 1,
- EG_TEX_WORD0__INST_MOD_shift,
- EG_TEX_WORD0__INST_MOD_mask);
- }
- else
- {
- SETfield(tex_instruction_ptr->m_Word0.val, 0,
- EG_TEX_WORD0__INST_MOD_shift,
- EG_TEX_WORD0__INST_MOD_mask);
- }
-
- CLEARbit(tex_instruction_ptr->m_Word0.val, EG_TEX_WORD0__FWQ_bit);
-
- if(SPT_VP == pAsm->currentShaderType)
- {
- SETfield(tex_instruction_ptr->m_Word0.val, (texture_unit_source->reg + VERT_ATTRIB_MAX),
- EG_TEX_WORD0__RESOURCE_ID_shift,
- EG_TEX_WORD0__RESOURCE_ID_mask);
- pAsm->unVetTexBits |= 1 << texture_unit_source->reg;
- }
- else
- {
- SETfield(tex_instruction_ptr->m_Word0.val, texture_unit_source->reg,
- EG_TEX_WORD0__RESOURCE_ID_shift,
- EG_TEX_WORD0__RESOURCE_ID_mask);
- }
-
- CLEARbit(tex_instruction_ptr->m_Word0.val, EG_TEX_WORD0__ALT_CONST_bit);
- SETfield(tex_instruction_ptr->m_Word0.val, 0,
- EG_TEX_WORD0__RIM_shift,
- EG_TEX_WORD0__RIM_mask);
- SETfield(tex_instruction_ptr->m_Word0.val, 0,
- EG_TEX_WORD0__SIM_shift,
- EG_TEX_WORD0__SIM_mask);
- }
- else
- {
- tex_instruction_ptr->m_Word0.f.tex_inst = pAsm->D.dst.opcode;
- tex_instruction_ptr->m_Word0.f.bc_frac_mode = 0x0;
- tex_instruction_ptr->m_Word0.f.fetch_whole_quad = 0x0;
- tex_instruction_ptr->m_Word0.f.alt_const = 0;
-
- if(SPT_VP == pAsm->currentShaderType)
- {
- tex_instruction_ptr->m_Word0.f.resource_id = texture_unit_source->reg + VERT_ATTRIB_MAX;
- pAsm->unVetTexBits |= 1 << texture_unit_source->reg;
- }
- else
- {
- tex_instruction_ptr->m_Word0.f.resource_id = texture_unit_source->reg;
- }
- }
-
- tex_instruction_ptr->m_Word1.f.lod_bias = 0x0;
- if (normalized) {
- tex_instruction_ptr->m_Word1.f.coord_type_x = SQ_TEX_NORMALIZED;
- tex_instruction_ptr->m_Word1.f.coord_type_y = SQ_TEX_NORMALIZED;
- tex_instruction_ptr->m_Word1.f.coord_type_z = SQ_TEX_NORMALIZED;
- tex_instruction_ptr->m_Word1.f.coord_type_w = SQ_TEX_NORMALIZED;
- } else {
- /* XXX: UNNORMALIZED tex coords have limited wrap modes */
- tex_instruction_ptr->m_Word1.f.coord_type_x = SQ_TEX_UNNORMALIZED;
- tex_instruction_ptr->m_Word1.f.coord_type_y = SQ_TEX_UNNORMALIZED;
- tex_instruction_ptr->m_Word1.f.coord_type_z = SQ_TEX_UNNORMALIZED;
- tex_instruction_ptr->m_Word1.f.coord_type_w = SQ_TEX_UNNORMALIZED;
- }
-
- tex_instruction_ptr->m_Word2.f.offset_x = 0x0;
- tex_instruction_ptr->m_Word2.f.offset_y = 0x0;
- tex_instruction_ptr->m_Word2.f.offset_z = 0x0;
- tex_instruction_ptr->m_Word2.f.sampler_id = texture_unit_source->reg;
-
- // dst
- if ( (pAsm->D.dst.rtype == DST_REG_TEMPORARY) ||
- (pAsm->D.dst.rtype == DST_REG_OUT) )
- {
- if(8 == pAsm->unAsic) /* evergreen */
- {
- SETfield(tex_instruction_ptr->m_Word0.val, texture_coordinate_source->reg,
- EG_TEX_WORD0__SRC_GPR_shift,
- EG_TEX_WORD0__SRC_GPR_mask);
- SETfield(tex_instruction_ptr->m_Word0.val, SQ_ABSOLUTE,
- EG_TEX_WORD0__SRC_REL_shift,
- EG_TEX_WORD0__SRC_REL_bit);
- }
- else
- {
- tex_instruction_ptr->m_Word0.f.src_gpr = texture_coordinate_source->reg;
- tex_instruction_ptr->m_Word0.f.src_rel = SQ_ABSOLUTE;
- }
-
- tex_instruction_ptr->m_Word1.f.dst_gpr = pAsm->D.dst.reg;
- tex_instruction_ptr->m_Word1.f.dst_rel = SQ_ABSOLUTE;
-
- tex_instruction_ptr->m_Word1.f.dst_sel_x = (pAsm->D.dst.writex ? texture_unit_source->swizzlex : SQ_SEL_MASK);
- tex_instruction_ptr->m_Word1.f.dst_sel_y = (pAsm->D.dst.writey ? texture_unit_source->swizzley : SQ_SEL_MASK);
- tex_instruction_ptr->m_Word1.f.dst_sel_z = (pAsm->D.dst.writez ? texture_unit_source->swizzlez : SQ_SEL_MASK);
- tex_instruction_ptr->m_Word1.f.dst_sel_w = (pAsm->D.dst.writew ? texture_unit_source->swizzlew : SQ_SEL_MASK);
-
-
- tex_instruction_ptr->m_Word2.f.src_sel_x = texture_coordinate_source->swizzlex;
- tex_instruction_ptr->m_Word2.f.src_sel_y = texture_coordinate_source->swizzley;
- tex_instruction_ptr->m_Word2.f.src_sel_z = texture_coordinate_source->swizzlez;
- tex_instruction_ptr->m_Word2.f.src_sel_w = texture_coordinate_source->swizzlew;
- }
- else
- {
- radeon_error("Only temp destination registers supported for TEX dest regs.\n");
- return GL_FALSE;
- }
-
- if( GL_FALSE == add_tex_instruction(pAsm, tex_instruction_ptr) )
- {
- return GL_FALSE;
- }
-
- return GL_TRUE;
-}
-
-void initialize(r700_AssemblerBase *pAsm)
-{
- GLuint cycle, component;
-
- for (cycle=0; cycle<NUMBER_OF_CYCLES; cycle++)
- {
- for (component=0; component<NUMBER_OF_COMPONENTS; component++)
- {
- pAsm->hw_gpr[cycle][component] = (-1);
- }
- }
- for (component=0; component<NUMBER_OF_COMPONENTS; component++)
- {
- pAsm->hw_cfile_addr[component] = (-1);
- pAsm->hw_cfile_chan[component] = (-1);
- }
-}
-
-GLboolean assemble_alu_src(R700ALUInstruction* alu_instruction_ptr,
- int source_index,
- PVSSRC* pSource,
- BITS scalar_channel_index,
- r700_AssemblerBase *pAsm)
-{
- BITS src_sel;
- BITS src_rel;
- BITS src_chan;
- BITS src_neg;
-
- //--------------------------------------------------------------------------
- // Source for operands src0, src1.
- // Values [0,127] correspond to GPR[0..127].
- // Values [256,511] correspond to cfile constants c[0..255].
-
- //--------------------------------------------------------------------------
- // Other special values are shown in the list below.
-
- // 248 SQ_ALU_SRC_0: special constant 0.0.
- // 249 SQ_ALU_SRC_1: special constant 1.0 float.
-
- // 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
- // 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
-
- // 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
- // 253 SQ_ALU_SRC_LITERAL: literal constant.
-
- // 254 SQ_ALU_SRC_PV: previous vector result.
- // 255 SQ_ALU_SRC_PS: previous scalar result.
- //--------------------------------------------------------------------------
-
- BITS channel_swizzle;
- switch (scalar_channel_index)
- {
- case 0: channel_swizzle = pSource->swizzlex; break;
- case 1: channel_swizzle = pSource->swizzley; break;
- case 2: channel_swizzle = pSource->swizzlez; break;
- case 3: channel_swizzle = pSource->swizzlew; break;
- default: channel_swizzle = SQ_SEL_MASK; break;
- }
-
- if(channel_swizzle == SQ_SEL_0)
- {
- src_sel = SQ_ALU_SRC_0;
- }
- else if (channel_swizzle == SQ_SEL_1)
- {
- src_sel = SQ_ALU_SRC_1;
- }
- else
- {
- if ( (pSource->rtype == SRC_REG_TEMPORARY) ||
- (pSource->rtype == SRC_REG_GPR)
- )
- {
- src_sel = pSource->reg;
- }
- else if (pSource->rtype == SRC_REG_CONSTANT)
- {
- /* TODO : 4 const buffers */
- if(GL_TRUE == pAsm->bUseMemConstant)
- {
- src_sel = pSource->reg + SQ_ALU_SRC_KCACHE0_BASE;
- pAsm->kcacheUsed = SQ_ALU_SRC_KCACHE0_BASE;
- }
- else
- {
- src_sel = pSource->reg + CFILE_REGISTER_OFFSET;
- }
- }
- else if (pSource->rtype == SRC_REC_LITERAL)
- {
- src_sel = SQ_ALU_SRC_LITERAL;
- }
- else
- {
- radeon_error("Source (%d) register type (%d) not one of TEMP, INPUT, or CONSTANT.\n",
- source_index, pSource->rtype);
- return GL_FALSE;
- }
- }
-
- if( ADDR_ABSOLUTE == addrmode_PVSSRC(pSource) )
- {
- src_rel = SQ_ABSOLUTE;
- }
- else
- {
- src_rel = SQ_RELATIVE;
- }
-
- switch (channel_swizzle)
- {
- case SQ_SEL_X:
- src_chan = SQ_CHAN_X;
- break;
- case SQ_SEL_Y:
- src_chan = SQ_CHAN_Y;
- break;
- case SQ_SEL_Z:
- src_chan = SQ_CHAN_Z;
- break;
- case SQ_SEL_W:
- src_chan = SQ_CHAN_W;
- break;
- case SQ_SEL_0:
- case SQ_SEL_1:
- // Does not matter since src_sel controls
- src_chan = SQ_CHAN_X;
- break;
- default:
- radeon_error("Unknown source select value (%d) in assemble_alu_src().\n", channel_swizzle);
- return GL_FALSE;
- break;
- }
-
- switch (scalar_channel_index)
- {
- case 0: src_neg = pSource->negx; break;
- case 1: src_neg = pSource->negy; break;
- case 2: src_neg = pSource->negz; break;
- case 3: src_neg = pSource->negw; break;
- default: src_neg = 0; break;
- }
-
- switch (source_index)
- {
- case 0:
- assert(alu_instruction_ptr);
- alu_instruction_ptr->m_Word0.f.src0_sel = src_sel;
- alu_instruction_ptr->m_Word0.f.src0_rel = src_rel;
- alu_instruction_ptr->m_Word0.f.src0_chan = src_chan;
- alu_instruction_ptr->m_Word0.f.src0_neg = src_neg;
- break;
- case 1:
- assert(alu_instruction_ptr);
- alu_instruction_ptr->m_Word0.f.src1_sel = src_sel;
- alu_instruction_ptr->m_Word0.f.src1_rel = src_rel;
- alu_instruction_ptr->m_Word0.f.src1_chan = src_chan;
- alu_instruction_ptr->m_Word0.f.src1_neg = src_neg;
- break;
- case 2:
- assert(alu_instruction_ptr);
- alu_instruction_ptr->m_Word1_OP3.f.src2_sel = src_sel;
- alu_instruction_ptr->m_Word1_OP3.f.src2_rel = src_rel;
- alu_instruction_ptr->m_Word1_OP3.f.src2_chan = src_chan;
- alu_instruction_ptr->m_Word1_OP3.f.src2_neg = src_neg;
- break;
- default:
- radeon_error("Only three sources allowed in ALU opcodes.\n");
- return GL_FALSE;
- break;
- }
-
- return GL_TRUE;
-}
-
-GLboolean add_alu_instruction(r700_AssemblerBase* pAsm,
- R700ALUInstruction* alu_instruction_ptr,
- GLuint contiguous_slots_needed)
-{
- if( GL_FALSE == check_current_clause(pAsm, CF_ALU_CLAUSE) )
- {
- return GL_FALSE;
- }
-
- if ( pAsm->alu_x_opcode != 0 ||
- pAsm->cf_current_alu_clause_ptr == NULL ||
- ( (pAsm->cf_current_alu_clause_ptr != NULL) &&
- (pAsm->cf_current_alu_clause_ptr->m_Word1.f.count >= (GetCFMaxInstructions(pAsm->cf_current_alu_clause_ptr->m_ShaderInstType)-contiguous_slots_needed-1) )
- ) )
- {
-
- //new cf inst for this clause
- pAsm->cf_current_alu_clause_ptr = (R700ControlFlowALUClause*) CALLOC_STRUCT(R700ControlFlowALUClause);
-
- // link the new cf to cf segment
- if(NULL != pAsm->cf_current_alu_clause_ptr)
- {
- Init_R700ControlFlowALUClause(pAsm->cf_current_alu_clause_ptr);
- AddCFInstruction( pAsm->pR700Shader,
- (R700ControlFlowInstruction *)pAsm->cf_current_alu_clause_ptr );
- }
- else
- {
- radeon_error("Could not allocate a new ALU CF instruction.\n");
- return GL_FALSE;
- }
-
- pAsm->cf_current_alu_clause_ptr->m_Word0.f.kcache_bank0 = 0x0;
- pAsm->cf_current_alu_clause_ptr->m_Word0.f.kcache_bank1 = 0x0;
- pAsm->cf_current_alu_clause_ptr->m_Word0.f.kcache_mode0 = SQ_CF_KCACHE_NOP;
-
- pAsm->cf_current_alu_clause_ptr->m_Word1.f.kcache_mode1 = SQ_CF_KCACHE_NOP;
- pAsm->cf_current_alu_clause_ptr->m_Word1.f.kcache_addr0 = 0x0;
- pAsm->cf_current_alu_clause_ptr->m_Word1.f.kcache_addr1 = 0x0;
-
- pAsm->cf_current_alu_clause_ptr->m_Word1.f.count = 0x0;
-
- if(pAsm->alu_x_opcode != 0)
- {
- pAsm->cf_current_alu_clause_ptr->m_Word1.f.cf_inst = pAsm->alu_x_opcode;
- pAsm->alu_x_opcode = 0;
- }
- else
- {
- pAsm->cf_current_alu_clause_ptr->m_Word1.f.cf_inst = SQ_CF_INST_ALU;
- }
-
- pAsm->cf_current_alu_clause_ptr->m_Word1.f.whole_quad_mode = 0x0;
-
- pAsm->cf_current_alu_clause_ptr->m_Word1.f.barrier = 0x1;
- }
- else
- {
- pAsm->cf_current_alu_clause_ptr->m_Word1.f.count += (GetInstructionSize(alu_instruction_ptr->m_ShaderInstType) / 2);
- }
-
- /* TODO : handle 4 bufs */
- if( (pAsm->kcacheUsed > 0) && (GL_TRUE == pAsm->bUseMemConstant) )
- {
- pAsm->cf_current_alu_clause_ptr->m_Word0.f.kcache_bank0 = 0x0;
- pAsm->cf_current_alu_clause_ptr->m_Word0.f.kcache_bank1 = 0x0;
- pAsm->cf_current_alu_clause_ptr->m_Word0.f.kcache_mode0 = SQ_CF_KCACHE_LOCK_2;
- pAsm->cf_current_alu_clause_ptr->m_Word1.f.kcache_mode1 = SQ_CF_KCACHE_NOP;
- pAsm->cf_current_alu_clause_ptr->m_Word1.f.kcache_addr0 = 0x0;
- pAsm->cf_current_alu_clause_ptr->m_Word1.f.kcache_addr1 = 0x0;
- }
-
- // If this clause constains any instruction that is forward dependent on a TEX instruction,
- // set the whole_quad_mode for this clause
- if ( pAsm->pInstDeps[pAsm->uiCurInst].nDstDep > (-1) )
- {
- pAsm->cf_current_alu_clause_ptr->m_Word1.f.whole_quad_mode = 0x1;
- }
-
- if (pAsm->cf_current_alu_clause_ptr->m_Word1.f.count >= (GetCFMaxInstructions(pAsm->cf_current_alu_clause_ptr->m_ShaderInstType)-1) )
- {
- alu_instruction_ptr->m_Word0.f.last = 1;
- }
-
- if(NULL == pAsm->cf_current_alu_clause_ptr->m_pLinkedALUInstruction)
- {
- pAsm->cf_current_alu_clause_ptr->m_pLinkedALUInstruction = alu_instruction_ptr;
- alu_instruction_ptr->m_pLinkedALUClause = pAsm->cf_current_alu_clause_ptr;
- }
-
- AddALUInstruction(pAsm->pR700Shader, alu_instruction_ptr);
-
- return GL_TRUE;
-}
-
-GLboolean EG_add_ps_interp(r700_AssemblerBase* pAsm)
-{
- R700ALUInstruction * alu_instruction_ptr = NULL;
-
- int ui;
- unsigned int uj;
- unsigned int unWord0Temp = 0x380C00;
- unsigned int unWord1Temp = 0x146B10; //SQ_SEL_X
-
- if(pAsm->uIIns > 0)
- {
- for(ui=(pAsm->uIIns-1); ui>=0; ui--)
- {
- for(uj=0; uj<8; uj++)
- {
- alu_instruction_ptr = (R700ALUInstruction*) CALLOC_STRUCT(R700ALUInstruction);
- Init_R700ALUInstruction(alu_instruction_ptr);
- alu_instruction_ptr->m_Word0.val = unWord0Temp;
- alu_instruction_ptr->m_Word1.val = unWord1Temp;
-
- if(uj < 4)
- {
- SETfield(alu_instruction_ptr->m_Word1.val, EG_OP2_INST_INTERP_ZW,
- EG_ALU_WORD1_OP2__ALU_INST_shift, EG_ALU_WORD1_OP2__ALU_INST_mask);
- }
- else
- {
- SETfield(alu_instruction_ptr->m_Word1.val, EG_OP2_INST_INTERP_XY,
- EG_ALU_WORD1_OP2__ALU_INST_shift, EG_ALU_WORD1_OP2__ALU_INST_mask);
- }
- if( (uj > 1) && (uj < 6) )
- {
- SETfield(alu_instruction_ptr->m_Word1.val, 1,
- EG_ALU_WORD1_OP2__WRITE_MASK_shift, EG_ALU_WORD1_OP2__WRITE_MASK_bit);
- }
- else
- {
- SETfield(alu_instruction_ptr->m_Word1.val, 0,
- EG_ALU_WORD1_OP2__WRITE_MASK_shift, EG_ALU_WORD1_OP2__WRITE_MASK_bit);
- }
- if( (uj > 1) && (uj < 6) )
- {
- SETfield(alu_instruction_ptr->m_Word1.val, ui,
- EG_ALU_WORD1__DST_GPR_shift, EG_ALU_WORD1__DST_GPR_mask);
- }
- else
- {
- SETfield(alu_instruction_ptr->m_Word1.val, 111,
- EG_ALU_WORD1__DST_GPR_shift, EG_ALU_WORD1__DST_GPR_mask);
- }
-
- SETfield(alu_instruction_ptr->m_Word1.val, (uj % 4),
- EG_ALU_WORD1__DST_CHAN_shift, EG_ALU_WORD1__DST_CHAN_mask);
- SETfield(alu_instruction_ptr->m_Word0.val, (1 - (uj % 2)),
- EG_ALU_WORD0__SRC0_CHAN_shift, EG_ALU_WORD0__SRC0_CHAN_mask);
- SETfield(alu_instruction_ptr->m_Word0.val, (EG_ALU_SRC_PARAM_BASE + ui),
- EG_ALU_WORD0__SRC1_SEL_shift, EG_ALU_WORD0__SRC1_SEL_mask);
- if(3 == (uj % 4))
- {
- SETfield(alu_instruction_ptr->m_Word0.val, 1,
- EG_ALU_WORD0__LAST_shift, EG_ALU_WORD0__LAST_bit);
- }
-
- if(GL_FALSE == add_alu_instruction(pAsm, alu_instruction_ptr, 4) )
- {
- return GL_FALSE;
- }
- }
- }
- }
-
- return GL_TRUE;
-}
-
-void get_src_properties(R700ALUInstruction* alu_instruction_ptr,
- int source_index,
- BITS* psrc_sel,
- BITS* psrc_rel,
- BITS* psrc_chan,
- BITS* psrc_neg)
-{
- switch (source_index)
- {
- case 0:
- *psrc_sel = alu_instruction_ptr->m_Word0.f.src0_sel ;
- *psrc_rel = alu_instruction_ptr->m_Word0.f.src0_rel ;
- *psrc_chan = alu_instruction_ptr->m_Word0.f.src0_chan;
- *psrc_neg = alu_instruction_ptr->m_Word0.f.src0_neg ;
- break;
-
- case 1:
- *psrc_sel = alu_instruction_ptr->m_Word0.f.src1_sel ;
- *psrc_rel = alu_instruction_ptr->m_Word0.f.src1_rel ;
- *psrc_chan = alu_instruction_ptr->m_Word0.f.src1_chan;
- *psrc_neg = alu_instruction_ptr->m_Word0.f.src1_neg ;
- break;
-
- case 2:
- *psrc_sel = alu_instruction_ptr->m_Word1_OP3.f.src2_sel;
- *psrc_rel = alu_instruction_ptr->m_Word1_OP3.f.src2_rel;
- *psrc_chan = alu_instruction_ptr->m_Word1_OP3.f.src2_chan;
- *psrc_neg = alu_instruction_ptr->m_Word1_OP3.f.src2_neg;
- break;
- }
-}
-
-int is_cfile(BITS sel)
-{
- if (sel > 255 && sel < 512)
- {
- return 1;
- }
- return 0;
-}
-
-int is_const(BITS sel)
-{
- if (is_cfile(sel))
- {
- return 1;
- }
- else if(sel >= SQ_ALU_SRC_0 && sel <= SQ_ALU_SRC_LITERAL)
- {
- return 1;
- }
- return 0;
-}
-
-int is_gpr(BITS sel)
-{
- if (sel >= 0 && sel < 128)
- {
- return 1;
- }
- return 0;
-}
-
-const GLuint BANK_SWIZZLE_VEC[8] = {SQ_ALU_VEC_210, //000
- SQ_ALU_VEC_120, //001
- SQ_ALU_VEC_102, //010
-
- SQ_ALU_VEC_201, //011
- SQ_ALU_VEC_012, //100
- SQ_ALU_VEC_021, //101
-
- SQ_ALU_VEC_012, //110
- SQ_ALU_VEC_012}; //111
-
-const GLuint BANK_SWIZZLE_SCL[8] = {SQ_ALU_SCL_210, //000
- SQ_ALU_SCL_122, //001
- SQ_ALU_SCL_122, //010
-
- SQ_ALU_SCL_221, //011
- SQ_ALU_SCL_212, //100
- SQ_ALU_SCL_122, //101
-
- SQ_ALU_SCL_122, //110
- SQ_ALU_SCL_122}; //111
-
-GLboolean reserve_cfile(r700_AssemblerBase* pAsm,
- GLuint sel,
- GLuint chan)
-{
- int res_match = (-1);
- int res_empty = (-1);
-
- GLint res;
-
- for (res=3; res>=0; res--)
- {
- if(pAsm->hw_cfile_addr[ res] < 0)
- {
- res_empty = res;
- }
- else if( (pAsm->hw_cfile_addr[res] == (int)sel)
- &&
- (pAsm->hw_cfile_chan[ res ] == (int) chan) )
- {
- res_match = res;
- }
- }
-
- if(res_match >= 0)
- {
- // Read for this scalar component already reserved, nothing to do here.
- ;
- }
- else if(res_empty >= 0)
- {
- pAsm->hw_cfile_addr[ res_empty ] = sel;
- pAsm->hw_cfile_chan[ res_empty ] = chan;
- }
- else
- {
- radeon_error("All cfile read ports are used, cannot reference C$sel, channel $chan.\n");
- return GL_FALSE;
- }
- return GL_TRUE;
-}
-
-GLboolean reserve_gpr(r700_AssemblerBase* pAsm, GLuint sel, GLuint chan, GLuint cycle)
-{
- if(pAsm->hw_gpr[cycle][chan] < 0)
- {
- pAsm->hw_gpr[cycle][chan] = sel;
- }
- else if(pAsm->hw_gpr[cycle][chan] != (int)sel)
- {
- radeon_error("Another scalar operation has already used GPR read port for given channel\n");
- return GL_FALSE;
- }
-
- return GL_TRUE;
-}
-
-GLboolean cycle_for_scalar_bank_swizzle(const int swiz, const int sel, GLuint* pCycle)
-{
- switch (swiz)
- {
- case SQ_ALU_SCL_210:
- {
- int table[3] = {2, 1, 0};
- *pCycle = table[sel];
- return GL_TRUE;
- }
- break;
- case SQ_ALU_SCL_122:
- {
- int table[3] = {1, 2, 2};
- *pCycle = table[sel];
- return GL_TRUE;
- }
- break;
- case SQ_ALU_SCL_212:
- {
- int table[3] = {2, 1, 2};
- *pCycle = table[sel];
- return GL_TRUE;
- }
- break;
- case SQ_ALU_SCL_221:
- {
- int table[3] = {2, 2, 1};
- *pCycle = table[sel];
- return GL_TRUE;
- }
- break;
- default:
- radeon_error("Bad Scalar bank swizzle value\n");
- break;
- }
-
- return GL_FALSE;
-}
-
-GLboolean cycle_for_vector_bank_swizzle(const int swiz, const int sel, GLuint* pCycle)
-{
- switch (swiz)
- {
- case SQ_ALU_VEC_012:
- {
- int table[3] = {0, 1, 2};
- *pCycle = table[sel];
- }
- break;
- case SQ_ALU_VEC_021:
- {
- int table[3] = {0, 2, 1};
- *pCycle = table[sel];
- }
- break;
- case SQ_ALU_VEC_120:
- {
- int table[3] = {1, 2, 0};
- *pCycle = table[sel];
- }
- break;
- case SQ_ALU_VEC_102:
- {
- int table[3] = {1, 0, 2};
- *pCycle = table[sel];
- }
- break;
- case SQ_ALU_VEC_201:
- {
- int table[3] = {2, 0, 1};
- *pCycle = table[sel];
- }
- break;
- case SQ_ALU_VEC_210:
- {
- int table[3] = {2, 1, 0};
- *pCycle = table[sel];
- }
- break;
- default:
- radeon_error("Bad Vec bank swizzle value\n");
- return GL_FALSE;
- break;
- }
-
- return GL_TRUE;
-}
-
-GLboolean check_scalar(r700_AssemblerBase* pAsm,
- R700ALUInstruction* alu_instruction_ptr)
-{
- GLuint cycle;
- GLuint bank_swizzle;
- GLuint const_count = 0;
-
- BITS sel;
- BITS chan;
- BITS rel;
- BITS neg;
-
- GLuint src;
-
- BITS src_sel [3] = {0,0,0};
- BITS src_chan[3] = {0,0,0};
- BITS src_rel [3] = {0,0,0};
- BITS src_neg [3] = {0,0,0};
-
- GLuint swizzle_key;
- GLuint number_of_operands;
-
- if(8 == pAsm->unAsic)
- {
- number_of_operands = EG_GetNumOperands(pAsm->D.dst.opcode, pAsm->D.dst.op3);
- }
- else
- {
- number_of_operands = r700GetNumOperands(pAsm->D.dst.opcode, pAsm->D.dst.op3);
- }
-
- for (src=0; src<number_of_operands; src++)
- {
- get_src_properties(alu_instruction_ptr,
- src,
- &(src_sel[src]),
- &(src_rel[src]),
- &(src_chan[src]),
- &(src_neg[src]) );
- }
-
-
- swizzle_key = ( (is_const( src_sel[0] ) ? 4 : 0) +
- (is_const( src_sel[1] ) ? 2 : 0) +
- (is_const( src_sel[2] ) ? 1 : 0) );
-
- alu_instruction_ptr->m_Word1.f.bank_swizzle = BANK_SWIZZLE_SCL[ swizzle_key ];
-
- for (src=0; src<number_of_operands; src++)
- {
- sel = src_sel [src];
- chan = src_chan[src];
- rel = src_rel [src];
- neg = src_neg [src];
-
- if (is_const( sel ))
- {
- // Any constant, including literal and inline constants
- const_count++;
-
- if (is_cfile( sel ))
- {
- reserve_cfile(pAsm, sel, chan);
- }
-
- }
- }
-
- for (src=0; src<number_of_operands; src++)
- {
- sel = src_sel [src];
- chan = src_chan[src];
- rel = src_rel [src];
- neg = src_neg [src];
-
- if( is_gpr(sel) )
- {
- bank_swizzle = alu_instruction_ptr->m_Word1.f.bank_swizzle;
-
- if( GL_FALSE == cycle_for_scalar_bank_swizzle(bank_swizzle, src, &cycle) )
- {
- return GL_FALSE;
- }
-
- if(cycle < const_count)
- {
- if( GL_FALSE == reserve_gpr(pAsm, sel, chan, cycle) )
- {
- return GL_FALSE;
- }
- }
- }
- }
-
- return GL_TRUE;
-}
-
-GLboolean check_vector(r700_AssemblerBase* pAsm,
- R700ALUInstruction* alu_instruction_ptr)
-{
- GLuint cycle;
- GLuint bank_swizzle;
- GLuint const_count = 0;
-
- GLuint src;
-
- BITS sel;
- BITS chan;
- BITS rel;
- BITS neg;
-
- BITS src_sel [3] = {0,0,0};
- BITS src_chan[3] = {0,0,0};
- BITS src_rel [3] = {0,0,0};
- BITS src_neg [3] = {0,0,0};
-
- GLuint swizzle_key;
- GLuint number_of_operands;
-
- if(8 == pAsm->unAsic)
- {
- number_of_operands = EG_GetNumOperands(pAsm->D.dst.opcode, pAsm->D.dst.op3);
- }
- else
- {
- number_of_operands = r700GetNumOperands(pAsm->D.dst.opcode, pAsm->D.dst.op3);
- }
-
- for (src=0; src<number_of_operands; src++)
- {
- get_src_properties(alu_instruction_ptr,
- src,
- &(src_sel[src]),
- &(src_rel[src]),
- &(src_chan[src]),
- &(src_neg[src]) );
- }
-
-
- swizzle_key = ( (is_const( src_sel[0] ) ? 4 : 0) +
- (is_const( src_sel[1] ) ? 2 : 0) +
- (is_const( src_sel[2] ) ? 1 : 0)
- );
-
- alu_instruction_ptr->m_Word1.f.bank_swizzle = BANK_SWIZZLE_VEC[swizzle_key];
-
- for (src=0; src<number_of_operands; src++)
- {
- sel = src_sel [src];
- chan = src_chan[src];
- rel = src_rel [src];
- neg = src_neg [src];
-
-
- bank_swizzle = alu_instruction_ptr->m_Word1.f.bank_swizzle;
-
- if( is_gpr(sel) )
- {
- if( GL_FALSE == cycle_for_vector_bank_swizzle(bank_swizzle, src, &cycle) )
- {
- return GL_FALSE;
- }
-
- if ( (src == 1) &&
- (sel == src_sel[0]) &&
- (chan == src_chan[0]) )
- {
- }
- else
- {
- if( GL_FALSE == reserve_gpr(pAsm, sel, chan, cycle) )
- {
- return GL_FALSE;
- }
- }
- }
- else if( is_const(sel) )
- {
- const_count++;
-
- if( is_cfile(sel) )
- {
- if( GL_FALSE == reserve_cfile(pAsm, sel, chan) )
- {
- return GL_FALSE;
- }
- }
- }
- }
-
- return GL_TRUE;
-}
-
-GLboolean assemble_alu_instruction(r700_AssemblerBase *pAsm)
-{
- R700ALUInstruction * alu_instruction_ptr = NULL;
- R700ALUInstructionHalfLiteral * alu_instruction_ptr_hl;
- R700ALUInstructionFullLiteral * alu_instruction_ptr_fl;
-
- GLuint number_of_scalar_operations;
- GLboolean is_single_scalar_operation;
- GLuint scalar_channel_index;
-
- PVSSRC * pcurrent_source;
- int current_source_index;
- GLuint contiguous_slots_needed;
- GLuint uNumSrc;
- GLboolean bSplitInst;
-
- if(8 == pAsm->unAsic)
- {
- uNumSrc = EG_GetNumOperands(pAsm->D.dst.opcode, pAsm->D.dst.op3);
- }
- else
- {
- uNumSrc = r700GetNumOperands(pAsm->D.dst.opcode, pAsm->D.dst.op3);
- }
-
- //GLuint channel_swizzle, j;
- //GLuint chan_counter[4] = {0, 0, 0, 0};
- //PVSSRC * pSource[3];
- bSplitInst = GL_FALSE;
- pAsm->kcacheUsed = 0;
-
- if (1 == pAsm->D.dst.math)
- {
- is_single_scalar_operation = GL_TRUE;
- number_of_scalar_operations = 1;
- }
- else
- {
- is_single_scalar_operation = GL_FALSE;
- number_of_scalar_operations = 4;
-
-/* current assembler doesn't do more than 1 register per source */
-#if 0
- /* check read port, only very preliminary algorithm, not count in
- src0/1 same comp case and prev slot repeat case; also not count relative
- addressing. TODO: improve performance. */
- for(j=0; j<uNumSrc; j++)
- {
- pSource[j] = &(pAsm->S[j].src);
- }
- for(scalar_channel_index=0; scalar_channel_index<4; scalar_channel_index++)
- {
- for(j=0; j<uNumSrc; j++)
- {
- switch (scalar_channel_index)
- {
- case 0: channel_swizzle = pSource[j]->swizzlex; break;
- case 1: channel_swizzle = pSource[j]->swizzley; break;
- case 2: channel_swizzle = pSource[j]->swizzlez; break;
- case 3: channel_swizzle = pSource[j]->swizzlew; break;
- default: channel_swizzle = SQ_SEL_MASK; break;
- }
- if ( ((pSource[j]->rtype == SRC_REG_TEMPORARY) ||
- (pSource[j]->rtype == SRC_REG_GPR))
- && (channel_swizzle <= SQ_SEL_W) )
- {
- chan_counter[channel_swizzle]++;
- }
- }
- }
- if( (chan_counter[SQ_SEL_X] > 3)
- || (chan_counter[SQ_SEL_Y] > 3)
- || (chan_counter[SQ_SEL_Z] > 3)
- || (chan_counter[SQ_SEL_W] > 3) ) /* each chan bank has only 3 ports. */
- {
- bSplitInst = GL_TRUE;
- }
-#endif
- }
-
- contiguous_slots_needed = 0;
-
- if(!is_single_scalar_operation)
- {
- contiguous_slots_needed = 4;
- }
-
- contiguous_slots_needed += pAsm->D2.dst2.literal_slots;
-
- initialize(pAsm);
-
- for (scalar_channel_index=0;
- scalar_channel_index < number_of_scalar_operations;
- scalar_channel_index++)
- {
- if(scalar_channel_index == (number_of_scalar_operations-1))
- {
- switch(pAsm->D2.dst2.literal_slots)
- {
- case 0:
- alu_instruction_ptr = (R700ALUInstruction*) CALLOC_STRUCT(R700ALUInstruction);
- Init_R700ALUInstruction(alu_instruction_ptr);
- break;
- case 1:
- alu_instruction_ptr_hl = (R700ALUInstructionHalfLiteral*) CALLOC_STRUCT(R700ALUInstructionHalfLiteral);
- Init_R700ALUInstructionHalfLiteral(alu_instruction_ptr_hl, pAsm->C[0].f, pAsm->C[1].f);
- alu_instruction_ptr = (R700ALUInstruction*)alu_instruction_ptr_hl;
- break;
- case 2:
- alu_instruction_ptr_fl = (R700ALUInstructionFullLiteral*) CALLOC_STRUCT(R700ALUInstructionFullLiteral);
- Init_R700ALUInstructionFullLiteral(alu_instruction_ptr_fl,pAsm->C[0].f, pAsm->C[1].f, pAsm->C[2].f, pAsm->C[3].f);
- alu_instruction_ptr = (R700ALUInstruction*)alu_instruction_ptr_fl;
- break;
- };
- }
- else
- {
- alu_instruction_ptr = (R700ALUInstruction*) CALLOC_STRUCT(R700ALUInstruction);
- Init_R700ALUInstruction(alu_instruction_ptr);
- }
-
- //src 0
- current_source_index = 0;
- pcurrent_source = &(pAsm->S[0].src);
-
- if (GL_FALSE == assemble_alu_src(alu_instruction_ptr,
- current_source_index,
- pcurrent_source,
- scalar_channel_index,
- pAsm) )
- {
- return GL_FALSE;
- }
-
- if (uNumSrc > 1)
- {
- // Process source 1
- current_source_index = 1;
- pcurrent_source = &(pAsm->S[current_source_index].src);
-
- if (GL_FALSE == assemble_alu_src(alu_instruction_ptr,
- current_source_index,
- pcurrent_source,
- scalar_channel_index,
- pAsm) )
- {
- return GL_FALSE;
- }
- }
-
- //other bits
- alu_instruction_ptr->m_Word0.f.index_mode = pAsm->D2.dst2.index_mode;
-
- if( (is_single_scalar_operation == GL_TRUE)
- || (GL_TRUE == bSplitInst) )
- {
- alu_instruction_ptr->m_Word0.f.last = 1;
- }
- else
- {
- alu_instruction_ptr->m_Word0.f.last = (scalar_channel_index == 3) ? 1 : 0;
- }
-
- alu_instruction_ptr->m_Word0.f.pred_sel = (pAsm->D.dst.pred_inv > 0) ? 1 : 0;
- if(1 == pAsm->D.dst.predicated)
- {
- alu_instruction_ptr->m_Word1_OP2.f.update_pred = 0x1;
- alu_instruction_ptr->m_Word1_OP2.f.update_execute_mask = 0x1;
- }
- else
- {
- alu_instruction_ptr->m_Word1_OP2.f.update_pred = 0x0;
- alu_instruction_ptr->m_Word1_OP2.f.update_execute_mask = 0x0;
- }
-
- // dst
- if( (pAsm->D.dst.rtype == DST_REG_TEMPORARY) ||
- (pAsm->D.dst.rtype == DST_REG_OUT) )
- {
- alu_instruction_ptr->m_Word1.f.dst_gpr = pAsm->D.dst.reg;
- }
- else
- {
- radeon_error("Only temp destination registers supported for ALU dest regs.\n");
- return GL_FALSE;
- }
-
- if ( ADDR_RELATIVE_A0 == addrmode_PVSDST(&(pAsm->D.dst)) )
- {
- alu_instruction_ptr->m_Word1.f.dst_rel = SQ_RELATIVE;
- }
- else
- {
- alu_instruction_ptr->m_Word1.f.dst_rel = SQ_ABSOLUTE;
- }
-
- if ( is_single_scalar_operation == GL_TRUE )
- {
- // Override scalar_channel_index since only one scalar value will be written
- if(pAsm->D.dst.writex)
- {
- scalar_channel_index = 0;
- }
- else if(pAsm->D.dst.writey)
- {
- scalar_channel_index = 1;
- }
- else if(pAsm->D.dst.writez)
- {
- scalar_channel_index = 2;
- }
- else if(pAsm->D.dst.writew)
- {
- scalar_channel_index = 3;
- }
- }
-
- alu_instruction_ptr->m_Word1.f.dst_chan = scalar_channel_index;
-
- alu_instruction_ptr->m_Word1.f.clamp = pAsm->D2.dst2.SaturateMode;
-
- if (pAsm->D.dst.op3)
- {
- //op3
-
- alu_instruction_ptr->m_Word1_OP3.f.alu_inst = pAsm->D.dst.opcode;
-
- //There's 3rd src for op3
- current_source_index = 2;
- pcurrent_source = &(pAsm->S[current_source_index].src);
-
- if ( GL_FALSE == assemble_alu_src(alu_instruction_ptr,
- current_source_index,
- pcurrent_source,
- scalar_channel_index,
- pAsm) )
- {
- return GL_FALSE;
- }
- }
- else
- {
- //op2
- if (pAsm->bR6xx)
- {
- alu_instruction_ptr->m_Word1_OP2.f6.alu_inst = pAsm->D.dst.opcode;
-
- alu_instruction_ptr->m_Word1_OP2.f6.src0_abs = pAsm->S[0].src.abs;
- alu_instruction_ptr->m_Word1_OP2.f6.src1_abs = pAsm->S[1].src.abs;
-
- //alu_instruction_ptr->m_Word1_OP2.f6.update_execute_mask = 0x0;
- //alu_instruction_ptr->m_Word1_OP2.f6.update_pred = 0x0;
- switch (scalar_channel_index)
- {
- case 0:
- alu_instruction_ptr->m_Word1_OP2.f6.write_mask = pAsm->D.dst.writex;
- break;
- case 1:
- alu_instruction_ptr->m_Word1_OP2.f6.write_mask = pAsm->D.dst.writey;
- break;
- case 2:
- alu_instruction_ptr->m_Word1_OP2.f6.write_mask = pAsm->D.dst.writez;
- break;
- case 3:
- alu_instruction_ptr->m_Word1_OP2.f6.write_mask = pAsm->D.dst.writew;
- break;
- default:
- alu_instruction_ptr->m_Word1_OP2.f6.write_mask = 1; //SQ_SEL_MASK;
- break;
- }
- alu_instruction_ptr->m_Word1_OP2.f6.omod = SQ_ALU_OMOD_OFF;
- }
- else
- {
- alu_instruction_ptr->m_Word1_OP2.f.alu_inst = pAsm->D.dst.opcode;
-
- alu_instruction_ptr->m_Word1_OP2.f.src0_abs = pAsm->S[0].src.abs;
- alu_instruction_ptr->m_Word1_OP2.f.src1_abs = pAsm->S[1].src.abs;
-
- //alu_instruction_ptr->m_Word1_OP2.f.update_execute_mask = 0x0;
- //alu_instruction_ptr->m_Word1_OP2.f.update_pred = 0x0;
- switch (scalar_channel_index)
- {
- case 0:
- alu_instruction_ptr->m_Word1_OP2.f.write_mask = pAsm->D.dst.writex;
- break;
- case 1:
- alu_instruction_ptr->m_Word1_OP2.f.write_mask = pAsm->D.dst.writey;
- break;
- case 2:
- alu_instruction_ptr->m_Word1_OP2.f.write_mask = pAsm->D.dst.writez;
- break;
- case 3:
- alu_instruction_ptr->m_Word1_OP2.f.write_mask = pAsm->D.dst.writew;
- break;
- default:
- alu_instruction_ptr->m_Word1_OP2.f.write_mask = 1; //SQ_SEL_MASK;
- break;
- }
- alu_instruction_ptr->m_Word1_OP2.f.omod = SQ_ALU_OMOD_OFF;
- }
- }
-
- if(GL_FALSE == add_alu_instruction(pAsm, alu_instruction_ptr, contiguous_slots_needed) )
- {
- return GL_FALSE;
- }
-
- /*
- * Judge the type of current instruction, is it vector or scalar
- * instruction.
- */
- if (is_single_scalar_operation)
- {
- if(GL_FALSE == check_scalar(pAsm, alu_instruction_ptr) )
- {
- return GL_FALSE;
- }
- }
- else
- {
- if(GL_FALSE == check_vector(pAsm, alu_instruction_ptr) )
- {
- return GL_FALSE;
- }
- }
-
- contiguous_slots_needed -= 1;
- }
-
- return GL_TRUE;
-}
-
-GLboolean assemble_math_function(r700_AssemblerBase* pAsm, BITS opcode)
-{
- BITS tmp;
-
- checkop1(pAsm);
-
- tmp = gethelpr(pAsm);
-
- // opcode tmp.x, a.x
- // MOV dst, tmp.x
-
- pAsm->D.dst.opcode = opcode;
- pAsm->D.dst.math = 1;
-
- setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE);
- pAsm->D.dst.rtype = DST_REG_TEMPORARY;
- pAsm->D.dst.reg = tmp;
- pAsm->D.dst.writex = 1;
-
- if( GL_FALSE == assemble_src(pAsm, 0, -1) )
- {
- return GL_FALSE;
- }
-
- if( pAsm->pILInst[pAsm->uiCurInst].Opcode == OPCODE_RSQ )
- pAsm->S[0].src.abs = 1;
-
- if ( GL_FALSE == next_ins(pAsm) )
- {
- return GL_FALSE;
- }
-
- // Now replicate result to all necessary channels in destination
- pAsm->D.dst.opcode = SQ_OP2_INST_MOV;
-
- if( GL_FALSE == assemble_dst(pAsm) )
- {
- return GL_FALSE;
- }
-
- setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE);
- pAsm->S[0].src.rtype = DST_REG_TEMPORARY;
- pAsm->S[0].src.reg = tmp;
-
- setswizzle_PVSSRC(&(pAsm->S[0].src), SQ_SEL_X);
- noneg_PVSSRC(&(pAsm->S[0].src));
-
- if( GL_FALSE == next_ins(pAsm) )
- {
- return GL_FALSE;
- }
-
- return GL_TRUE;
-}
-
-GLboolean assemble_ABS(r700_AssemblerBase *pAsm)
-{
- checkop1(pAsm);
-
- pAsm->D.dst.opcode = SQ_OP2_INST_MAX;
-
- if( GL_FALSE == assemble_dst(pAsm) )
- {
- return GL_FALSE;
- }
- if( GL_FALSE == assemble_src(pAsm, 0, -1) )
- {
- return GL_FALSE;
- }
-
- pAsm->S[1].bits = pAsm->S[0].bits;
- flipneg_PVSSRC(&(pAsm->S[1].src));
-
- if ( GL_FALSE == next_ins(pAsm) )
- {
- return GL_FALSE;
- }
-
- return GL_TRUE;
-}
-
-GLboolean assemble_ADD(r700_AssemblerBase *pAsm)
-{
- if( GL_FALSE == checkop2(pAsm) )
- {
- return GL_FALSE;
- }
-
- pAsm->D.dst.opcode = SQ_OP2_INST_ADD;
-
- if( GL_FALSE == assemble_dst(pAsm) )
- {
- return GL_FALSE;
- }
-
- if( GL_FALSE == assemble_src(pAsm, 0, -1) )
- {
- return GL_FALSE;
- }
-
- if( GL_FALSE == assemble_src(pAsm, 1, -1) )
- {
- return GL_FALSE;
- }
-
- if(pAsm->pILInst[pAsm->uiCurInst].Opcode == OPCODE_SUB)
- {
- flipneg_PVSSRC(&(pAsm->S[1].src));
- }
-
- if( GL_FALSE == next_ins(pAsm) )
- {
- return GL_FALSE;
- }
-
- return GL_TRUE;
-}
-
-GLboolean assemble_ARL(r700_AssemblerBase *pAsm)
-{ /* TODO: ar values dont' persist between clauses */
- if( GL_FALSE == checkop1(pAsm) )
- {
- return GL_FALSE;
- }
-
- if(8 == pAsm->unAsic)
- {
- /* Evergreen */
-
- /* Float to Signed Integer Using FLOOR */
- pAsm->D.dst.opcode = EG_OP2_INST_FLT_TO_INT_FLOOR;
- setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE);
- pAsm->D.dst.rtype = DST_REG_TEMPORARY;
- pAsm->D.dst.reg = 0;
- pAsm->D.dst.writex = 0;
- pAsm->D.dst.writey = 0;
- pAsm->D.dst.writez = 0;
- pAsm->D.dst.writew = 0;
-
- if( GL_FALSE == assemble_src(pAsm, 0, -1) )
- {
- return GL_FALSE;
- }
-
- if( GL_FALSE == next_ins(pAsm) )
- {
- return GL_FALSE;
- }
-
- /* Copy Signed Integer To Integer in AR and GPR */
- pAsm->D.dst.opcode = EG_OP2_INST_MOVA_INT;
- setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE);
- pAsm->D.dst.rtype = DST_REG_TEMPORARY;
- pAsm->D.dst.reg = 0;
- pAsm->D.dst.writex = 0;
- pAsm->D.dst.writey = 0;
- pAsm->D.dst.writez = 0;
- pAsm->D.dst.writew = 0;
-
- if( GL_FALSE == assemble_src(pAsm, 0, -1) )
- {
- return GL_FALSE;
- }
-
- if( GL_FALSE == next_ins(pAsm) )
- {
- return GL_FALSE;
- }
- }
- else
- {
- /* r6xx/r7xx */
-
- /* Truncate floating-point to the nearest integer
- in the range [-256, +255], and copy to AR and
- to a GPR.
- */
- pAsm->D.dst.opcode = SQ_OP2_INST_MOVA_FLOOR;
- setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE);
- pAsm->D.dst.rtype = DST_REG_TEMPORARY;
- pAsm->D.dst.reg = 0;
- pAsm->D.dst.writex = 0;
- pAsm->D.dst.writey = 0;
- pAsm->D.dst.writez = 0;
- pAsm->D.dst.writew = 0;
-
- if( GL_FALSE == assemble_src(pAsm, 0, -1) )
- {
- return GL_FALSE;
- }
-
- if( GL_FALSE == next_ins(pAsm) )
- {
- return GL_FALSE;
- }
- }
-
- return GL_TRUE;
-}
-
-GLboolean assemble_BAD(char *opcode_str)
-{
- radeon_error("Not yet implemented instruction (%s)\n", opcode_str);
- return GL_FALSE;
-}
-
-GLboolean assemble_CMP(r700_AssemblerBase *pAsm)
-{
- int tmp;
-
- if( GL_FALSE == checkop3(pAsm) )
- {
- return GL_FALSE;
- }
-
- if(8 == pAsm->unAsic)
- {
- pAsm->D.dst.opcode = EG_OP3_INST_CNDGE;
- }
- else
- {
- pAsm->D.dst.opcode = SQ_OP3_INST_CNDGE;
- }
- pAsm->D.dst.op3 = 1;
-
- tmp = (-1);
-
- if(0xF != pAsm->pILInst[pAsm->uiCurInst].DstReg.WriteMask)
- {
- //OP3 has no support for write mask
- tmp = gethelpr(pAsm);
-
- setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE);
- pAsm->D.dst.rtype = DST_REG_TEMPORARY;
- pAsm->D.dst.reg = tmp;
-
- nomask_PVSDST(&(pAsm->D.dst));
- }
- else
- {
- if( GL_FALSE == assemble_dst(pAsm) )
- {
- return GL_FALSE;
- }
- }
-
- if( GL_FALSE == assemble_src(pAsm, 0, -1) )
- {
- return GL_FALSE;
- }
-
- if( GL_FALSE == assemble_src(pAsm, 2, 1) )
- {
- return GL_FALSE;
- }
-
- if( GL_FALSE == assemble_src(pAsm, 1, 2) )
- {
- return GL_FALSE;
- }
-
- if ( GL_FALSE == next_ins(pAsm) )
- {
- return GL_FALSE;
- }
-
- if (0xF != pAsm->pILInst[pAsm->uiCurInst].DstReg.WriteMask)
- {
- if( GL_FALSE == assemble_dst(pAsm) )
- {
- return GL_FALSE;
- }
-
- pAsm->D.dst.opcode = SQ_OP2_INST_MOV;
-
- //tmp for source
- setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE);
- pAsm->S[0].src.rtype = SRC_REG_TEMPORARY;
- pAsm->S[0].src.reg = tmp;
-
- noneg_PVSSRC(&(pAsm->S[0].src));
- noswizzle_PVSSRC(&(pAsm->S[0].src));
-
- if( GL_FALSE == next_ins(pAsm) )
- {
- return GL_FALSE;
- }
- }
-
- return GL_TRUE;
-}
-
-GLboolean assemble_TRIG(r700_AssemblerBase *pAsm, BITS opcode)
-{
- /*
- * r600 - trunc to -PI..PI range
- * r700 - normalize by dividing by 2PI
- * see fdo bug 27901
- */
-
- int tmp;
- checkop1(pAsm);
-
- tmp = gethelpr(pAsm);
- if(8 == pAsm->unAsic)
- {
- pAsm->D.dst.opcode = EG_OP3_INST_MULADD;
- }
- else
- {
- pAsm->D.dst.opcode = SQ_OP3_INST_MULADD;
- }
- pAsm->D.dst.op3 = 1;
-
- setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE);
- pAsm->D.dst.rtype = DST_REG_TEMPORARY;
- pAsm->D.dst.reg = tmp;
-
- assemble_src(pAsm, 0, -1);
-
- pAsm->S[1].src.rtype = SRC_REC_LITERAL;
- setswizzle_PVSSRC(&(pAsm->S[1].src), SQ_SEL_X);
-
- pAsm->S[2].src.rtype = SRC_REC_LITERAL;
- setswizzle_PVSSRC(&(pAsm->S[2].src), SQ_SEL_Y);
-
- pAsm->D2.dst2.literal_slots = 1;
- pAsm->C[0].f = 1/(3.1415926535 * 2);
- pAsm->C[1].f = 0.5f;
-
- if ( GL_FALSE == next_ins(pAsm) )
- {
- return GL_FALSE;
- }
-
- pAsm->D.dst.opcode = SQ_OP2_INST_FRACT;
-
- setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE);
- pAsm->D.dst.rtype = DST_REG_TEMPORARY;
- pAsm->D.dst.reg = tmp;
- pAsm->D.dst.writex = 1;
-
- setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE);
- pAsm->S[0].src.rtype = SRC_REG_TEMPORARY;
- pAsm->S[0].src.reg = tmp;
- setswizzle_PVSSRC(&(pAsm->S[0].src), SQ_SEL_X);
-
- if(( GL_FALSE == next_ins(pAsm) ))
- {
- return GL_FALSE;
- }
- if(8 == pAsm->unAsic)
- {
- pAsm->D.dst.opcode = EG_OP3_INST_MULADD;
- }
- else
- {
- pAsm->D.dst.opcode = SQ_OP3_INST_MULADD;
- }
- pAsm->D.dst.op3 = 1;
-
- setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE);
- pAsm->D.dst.rtype = DST_REG_TEMPORARY;
- pAsm->D.dst.reg = tmp;
-
- setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE);
- pAsm->S[0].src.rtype = SRC_REG_TEMPORARY;
- pAsm->S[0].src.reg = tmp;
- setswizzle_PVSSRC(&(pAsm->S[0].src), SQ_SEL_X);
-
- pAsm->S[1].src.rtype = SRC_REC_LITERAL;
- setswizzle_PVSSRC(&(pAsm->S[1].src), SQ_SEL_X);
-
- pAsm->S[2].src.rtype = SRC_REC_LITERAL;
- setswizzle_PVSSRC(&(pAsm->S[2].src), SQ_SEL_Y);
-
- pAsm->D2.dst2.literal_slots = 1;
-
- if (pAsm->bR6xx)
- {
- pAsm->C[0].f = 3.1415926535897f * 2.0f;
- pAsm->C[1].f = -3.1415926535897f;
- }
- else
- {
- pAsm->C[0].f = 1.0f;
- pAsm->C[1].f = -0.5f;
- }
-
- if(( GL_FALSE == next_ins(pAsm) ))
- {
- return GL_FALSE;
- }
-
- pAsm->D.dst.opcode = opcode;
- pAsm->D.dst.math = 1;
-
- assemble_dst(pAsm);
-
- setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE);
- pAsm->S[0].src.rtype = SRC_REG_TEMPORARY;
- pAsm->S[0].src.reg = tmp;
- setswizzle_PVSSRC(&(pAsm->S[0].src), SQ_SEL_X);
- noneg_PVSSRC(&(pAsm->S[0].src));
-
- next_ins(pAsm);
-
- //TODO - replicate if more channels set in WriteMask
- return GL_TRUE;
-
-}
-
-GLboolean assemble_DOT(r700_AssemblerBase *pAsm)
-{
- if( GL_FALSE == checkop2(pAsm) )
- {
- return GL_FALSE;
- }
-
- if(8 == pAsm->unAsic)
- {
- pAsm->D.dst.opcode = EG_OP2_INST_DOT4;
- }
- else
- {
- pAsm->D.dst.opcode = SQ_OP2_INST_DOT4;
- }
-
- if( GL_FALSE == assemble_dst(pAsm) )
- {
- return GL_FALSE;
- }
-
- if( GL_FALSE == assemble_src(pAsm, 0, -1) )
- {
- return GL_FALSE;
- }
-
- if( GL_FALSE == assemble_src(pAsm, 1, -1) )
- {
- return GL_FALSE;
- }
-
- if(OPCODE_DP2 == pAsm->pILInst[pAsm->uiCurInst].Opcode)
- {
- zerocomp_PVSSRC(&(pAsm->S[0].src),2);
- zerocomp_PVSSRC(&(pAsm->S[0].src),3);
- zerocomp_PVSSRC(&(pAsm->S[1].src),2);
- zerocomp_PVSSRC(&(pAsm->S[1].src),3);
- }
- else if(OPCODE_DP3 == pAsm->pILInst[pAsm->uiCurInst].Opcode)
- {
- zerocomp_PVSSRC(&(pAsm->S[0].src), 3);
- zerocomp_PVSSRC(&(pAsm->S[1].src), 3);
- }
- else if(pAsm->pILInst[pAsm->uiCurInst].Opcode == OPCODE_DPH)
- {
- onecomp_PVSSRC(&(pAsm->S[0].src), 3);
- }
-
- if ( GL_FALSE == next_ins(pAsm) )
- {
- return GL_FALSE;
- }
-
- return GL_TRUE;
-}
-
-GLboolean assemble_DST(r700_AssemblerBase *pAsm)
-{
- if( GL_FALSE == checkop2(pAsm) )
- {
- return GL_FALSE;
- }
-
- pAsm->D.dst.opcode = SQ_OP2_INST_MUL;
-
- if( GL_FALSE == assemble_dst(pAsm) )
- {
- return GL_FALSE;
- }
-
- if( GL_FALSE == assemble_src(pAsm, 0, -1) )
- {
- return GL_FALSE;
- }
-
- if( GL_FALSE == assemble_src(pAsm, 1, -1) )
- {
- return GL_FALSE;
- }
-
- onecomp_PVSSRC(&(pAsm->S[0].src), 0);
- onecomp_PVSSRC(&(pAsm->S[0].src), 3);
-
- onecomp_PVSSRC(&(pAsm->S[1].src), 0);
- onecomp_PVSSRC(&(pAsm->S[1].src), 2);
-
- if ( GL_FALSE == next_ins(pAsm) )
- {
- return GL_FALSE;
- }
-
- return GL_TRUE;
-}
-
-GLboolean assemble_EX2(r700_AssemblerBase *pAsm)
-{
- if(8 == pAsm->unAsic)
- {
- return assemble_math_function(pAsm, EG_OP2_INST_EXP_IEEE);
- }
-
- return assemble_math_function(pAsm, SQ_OP2_INST_EXP_IEEE);
-}
-
-GLboolean assemble_EXP(r700_AssemblerBase *pAsm)
-{
- BITS tmp;
-
- checkop1(pAsm);
-
- tmp = gethelpr(pAsm);
-
- // FLOOR tmp.x, a.x
- // EX2 dst.x tmp.x
-
- if (pAsm->pILInst->DstReg.WriteMask & 0x1) {
- pAsm->D.dst.opcode = SQ_OP2_INST_FLOOR;
-
- setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE);
- pAsm->D.dst.rtype = DST_REG_TEMPORARY;
- pAsm->D.dst.reg = tmp;
- pAsm->D.dst.writex = 1;
-
- if( GL_FALSE == assemble_src(pAsm, 0, -1) )
- {
- return GL_FALSE;
- }
-
- if( GL_FALSE == next_ins(pAsm) )
- {
- return GL_FALSE;
- }
-
- if(8 == pAsm->unAsic)
- {
- pAsm->D.dst.opcode = EG_OP2_INST_EXP_IEEE;
- }
- else
- {
- pAsm->D.dst.opcode = SQ_OP2_INST_EXP_IEEE;
- }
- pAsm->D.dst.math = 1;
-
- if( GL_FALSE == assemble_dst(pAsm) )
- {
- return GL_FALSE;
- }
-
- pAsm->D.dst.writey = pAsm->D.dst.writez = pAsm->D.dst.writew = 0;
-
- setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE);
- pAsm->S[0].src.rtype = DST_REG_TEMPORARY;
- pAsm->S[0].src.reg = tmp;
-
- setswizzle_PVSSRC(&(pAsm->S[0].src), SQ_SEL_X);
- noneg_PVSSRC(&(pAsm->S[0].src));
-
- if( GL_FALSE == next_ins(pAsm) )
- {
- return GL_FALSE;
- }
- }
-
- // FRACT dst.y a.x
-
- if ((pAsm->pILInst->DstReg.WriteMask >> 1) & 0x1) {
- pAsm->D.dst.opcode = SQ_OP2_INST_FRACT;
-
- if( GL_FALSE == assemble_dst(pAsm) )
- {
- return GL_FALSE;
- }
-
- if( GL_FALSE == assemble_src(pAsm, 0, -1) )
- {
- return GL_FALSE;
- }
-
- pAsm->D.dst.writex = pAsm->D.dst.writez = pAsm->D.dst.writew = 0;
-
- if( GL_FALSE == next_ins(pAsm) )
- {
- return GL_FALSE;
- }
- }
-
- // EX2 dst.z, a.x
-
- if ((pAsm->pILInst->DstReg.WriteMask >> 2) & 0x1) {
- if(8 == pAsm->unAsic)
- {
- pAsm->D.dst.opcode = EG_OP2_INST_EXP_IEEE;
- }
- else
- {
- pAsm->D.dst.opcode = SQ_OP2_INST_EXP_IEEE;
- }
- pAsm->D.dst.math = 1;
-
- if( GL_FALSE == assemble_dst(pAsm) )
- {
- return GL_FALSE;
- }
-
- if( GL_FALSE == assemble_src(pAsm, 0, -1) )
- {
- return GL_FALSE;
- }
-
- pAsm->D.dst.writex = pAsm->D.dst.writey = pAsm->D.dst.writew = 0;
-
- if( GL_FALSE == next_ins(pAsm) )
- {
- return GL_FALSE;
- }
- }
-
- // MOV dst.w 1.0
-
- if ((pAsm->pILInst->DstReg.WriteMask >> 3) & 0x1) {
- pAsm->D.dst.opcode = SQ_OP2_INST_MOV;
-
- if( GL_FALSE == assemble_dst(pAsm) )
- {
- return GL_FALSE;
- }
-
- pAsm->D.dst.writex = pAsm->D.dst.writey = pAsm->D.dst.writez = 0;
-
- setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE);
- pAsm->S[0].src.rtype = SRC_REG_TEMPORARY;
- pAsm->S[0].src.reg = tmp;
-
- setswizzle_PVSSRC(&(pAsm->S[0].src), SQ_SEL_1);
- noneg_PVSSRC(&(pAsm->S[0].src));
-
- if( GL_FALSE == next_ins(pAsm) )
- {
- return GL_FALSE;
- }
- }
-
- return GL_TRUE;
-}
-
-GLboolean assemble_FLR(r700_AssemblerBase *pAsm)
-{
- checkop1(pAsm);
-
- pAsm->D.dst.opcode = SQ_OP2_INST_FLOOR;
-
- if ( GL_FALSE == assemble_dst(pAsm) )
- {
- return GL_FALSE;
- }
-
- if ( GL_FALSE == assemble_src(pAsm, 0, -1) )
- {
- return GL_FALSE;
- }
-
- if ( GL_FALSE == next_ins(pAsm) )
- {
- return GL_FALSE;
- }
-
- return GL_TRUE;
-}
-
-GLboolean assemble_FLR_INT(r700_AssemblerBase *pAsm)
-{
- if(8 == pAsm->unAsic)
- {
- return assemble_math_function(pAsm, EG_OP2_INST_FLT_TO_INT);
- }
-
- return assemble_math_function(pAsm, SQ_OP2_INST_FLT_TO_INT);
-}
-
-GLboolean assemble_FRC(r700_AssemblerBase *pAsm)
-{
- checkop1(pAsm);
-
- pAsm->D.dst.opcode = SQ_OP2_INST_FRACT;
-
- if ( GL_FALSE == assemble_dst(pAsm) )
- {
- return GL_FALSE;
- }
-
- if ( GL_FALSE == assemble_src(pAsm, 0, -1) )
- {
- return GL_FALSE;
- }
-
- if ( GL_FALSE == next_ins(pAsm) )
- {
- return GL_FALSE;
- }
-
- return GL_TRUE;
-}
-
-GLboolean assemble_KIL(r700_AssemblerBase *pAsm, GLuint opcode)
-{
- struct prog_instruction *pILInst = &(pAsm->pILInst[pAsm->uiCurInst]);
-
- if(pILInst->Opcode == OPCODE_KIL)
- checkop1(pAsm);
-
- pAsm->D.dst.opcode = opcode;
- //pAsm->D.dst.math = 1;
-
- setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE);
- pAsm->D.dst.rtype = DST_REG_TEMPORARY;
- pAsm->D.dst.reg = 0;
- pAsm->D.dst.writex = 0;
- pAsm->D.dst.writey = 0;
- pAsm->D.dst.writez = 0;
- pAsm->D.dst.writew = 0;
-
- setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE);
- pAsm->S[0].src.rtype = SRC_REG_TEMPORARY;
- pAsm->S[0].src.reg = 0;
- setswizzle_PVSSRC(&(pAsm->S[0].src), SQ_SEL_0);
- noneg_PVSSRC(&(pAsm->S[0].src));
-
- if(pILInst->Opcode == OPCODE_KIL_NV)
- {
- setaddrmode_PVSSRC(&(pAsm->S[1].src), ADDR_ABSOLUTE);
- pAsm->S[1].src.rtype = SRC_REG_TEMPORARY;
- pAsm->S[1].src.reg = 0;
- setswizzle_PVSSRC(&(pAsm->S[1].src), SQ_SEL_1);
- neg_PVSSRC(&(pAsm->S[1].src));
- }
- else
- {
- if( GL_FALSE == assemble_src(pAsm, 0, 1) )
- {
- return GL_FALSE;
- }
-
- }
-
- if ( GL_FALSE == next_ins(pAsm) )
- {
- return GL_FALSE;
- }
-
- /* Doc says KILL has to be last(end) ALU clause */
- pAsm->pR700Shader->killIsUsed = GL_TRUE;
- pAsm->alu_x_opcode = SQ_CF_INST_ALU;
-
- return GL_TRUE;
-}
-
-GLboolean assemble_LG2(r700_AssemblerBase *pAsm)
-{
- if(8 == pAsm->unAsic)
- {
- return assemble_math_function(pAsm, EG_OP2_INST_LOG_IEEE);
- }
-
- return assemble_math_function(pAsm, SQ_OP2_INST_LOG_IEEE);
-}
-
-GLboolean assemble_LRP(r700_AssemblerBase *pAsm)
-{
- BITS tmp;
-
- if( GL_FALSE == checkop3(pAsm) )
- {
- return GL_FALSE;
- }
-
- tmp = gethelpr(pAsm);
-
- pAsm->D.dst.opcode = SQ_OP2_INST_ADD;
-
- pAsm->D.dst.rtype = DST_REG_TEMPORARY;
- pAsm->D.dst.reg = tmp;
- setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE);
- nomask_PVSDST(&(pAsm->D.dst));
-
-
- if( GL_FALSE == assemble_src(pAsm, 1, 0) )
- {
- return GL_FALSE;
- }
-
- if ( GL_FALSE == assemble_src(pAsm, 2, 1) )
- {
- return GL_FALSE;
- }
-
- neg_PVSSRC(&(pAsm->S[1].src));
-
- if( GL_FALSE == next_ins(pAsm) )
- {
- return GL_FALSE;
- }
-
- if(8 == pAsm->unAsic)
- {
- pAsm->D.dst.opcode = EG_OP3_INST_MULADD;
- }
- else
- {
- pAsm->D.dst.opcode = SQ_OP3_INST_MULADD;
- }
- pAsm->D.dst.op3 = 1;
-
- pAsm->D.dst.rtype = DST_REG_TEMPORARY;
- pAsm->D.dst.reg = tmp;
- nomask_PVSDST(&(pAsm->D.dst));
- setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE);
-
- setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE);
- pAsm->S[0].src.rtype = SRC_REG_TEMPORARY;
- pAsm->S[0].src.reg = tmp;
- noswizzle_PVSSRC(&(pAsm->S[0].src));
-
-
- if( GL_FALSE == assemble_src(pAsm, 0, 1) )
- {
- return GL_FALSE;
- }
-
- if( GL_FALSE == assemble_src(pAsm, 2, -1) )
- {
- return GL_FALSE;
- }
-
- if( GL_FALSE == next_ins(pAsm) )
- {
- return GL_FALSE;
- }
-
- pAsm->D.dst.opcode = SQ_OP2_INST_MOV;
-
- if( GL_FALSE == assemble_dst(pAsm) )
- {
- return GL_FALSE;
- }
-
- setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE);
- pAsm->S[0].src.rtype = SRC_REG_TEMPORARY;
- pAsm->S[0].src.reg = tmp;
- noswizzle_PVSSRC(&(pAsm->S[0].src));
-
- if( GL_FALSE == next_ins(pAsm) )
- {
- return GL_FALSE;
- }
-
- return GL_TRUE;
-}
-
-GLboolean assemble_LOG(r700_AssemblerBase *pAsm)
-{
- BITS tmp1, tmp2, tmp3;
-
- checkop1(pAsm);
-
- tmp1 = gethelpr(pAsm);
- tmp2 = gethelpr(pAsm);
- tmp3 = gethelpr(pAsm);
-
- // FIXME: The hardware can do fabs() directly on input
- // elements, but the compiler doesn't have the
- // capability to use that.
-
- // MAX tmp1.x, a.x, -a.x (fabs(a.x))
-
- pAsm->D.dst.opcode = SQ_OP2_INST_MAX;
-
- setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE);
- pAsm->D.dst.rtype = DST_REG_TEMPORARY;
- pAsm->D.dst.reg = tmp1;
- pAsm->D.dst.writex = 1;
-
- if( GL_FALSE == assemble_src(pAsm, 0, -1) )
- {
- return GL_FALSE;
- }
-
- pAsm->S[1].bits = pAsm->S[0].bits;
- flipneg_PVSSRC(&(pAsm->S[1].src));
-
- if ( GL_FALSE == next_ins(pAsm) )
- {
- return GL_FALSE;
- }
-
- // Entire algo:
- //
- // LG2 tmp2.x, tmp1.x
- // FLOOR tmp3.x, tmp2.x
- // MOV dst.x, tmp3.x
- // ADD tmp3.x, tmp2.x, -tmp3.x
- // EX2 dst.y, tmp3.x
- // MOV dst.z, tmp2.x
- // MOV dst.w, 1.0
-
- // LG2 tmp2.x, tmp1.x
- // FLOOR tmp3.x, tmp2.x
-
- if(8 == pAsm->unAsic)
- {
- pAsm->D.dst.opcode = EG_OP2_INST_LOG_IEEE;
- }
- else
- {
- pAsm->D.dst.opcode = SQ_OP2_INST_LOG_IEEE;
- }
- pAsm->D.dst.math = 1;
-
- setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE);
- pAsm->D.dst.rtype = DST_REG_TEMPORARY;
- pAsm->D.dst.reg = tmp2;
- pAsm->D.dst.writex = 1;
-
- setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE);
- pAsm->S[0].src.rtype = DST_REG_TEMPORARY;
- pAsm->S[0].src.reg = tmp1;
-
- setswizzle_PVSSRC(&(pAsm->S[0].src), SQ_SEL_X);
- noneg_PVSSRC(&(pAsm->S[0].src));
-
- if( GL_FALSE == next_ins(pAsm) )
- {
- return GL_FALSE;
- }
-
- pAsm->D.dst.opcode = SQ_OP2_INST_FLOOR;
-
- setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE);
- pAsm->D.dst.rtype = DST_REG_TEMPORARY;
- pAsm->D.dst.reg = tmp3;
- pAsm->D.dst.writex = 1;
-
- setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE);
- pAsm->S[0].src.rtype = DST_REG_TEMPORARY;
- pAsm->S[0].src.reg = tmp2;
-
- setswizzle_PVSSRC(&(pAsm->S[0].src), SQ_SEL_X);
- noneg_PVSSRC(&(pAsm->S[0].src));
-
- if( GL_FALSE == next_ins(pAsm) )
- {
- return GL_FALSE;
- }
-
- // MOV dst.x, tmp3.x
-
- pAsm->D.dst.opcode = SQ_OP2_INST_MOV;
-
- if( GL_FALSE == assemble_dst(pAsm) )
- {
- return GL_FALSE;
- }
-
- pAsm->D.dst.writey = pAsm->D.dst.writez = pAsm->D.dst.writew = 0;
-
- setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE);
- pAsm->S[0].src.rtype = DST_REG_TEMPORARY;
- pAsm->S[0].src.reg = tmp3;
-
- setswizzle_PVSSRC(&(pAsm->S[0].src), SQ_SEL_X);
- noneg_PVSSRC(&(pAsm->S[0].src));
-
- if( GL_FALSE == next_ins(pAsm) )
- {
- return GL_FALSE;
- }
-
- // ADD tmp3.x, tmp2.x, -tmp3.x
- // EX2 dst.y, tmp3.x
-
- pAsm->D.dst.opcode = SQ_OP2_INST_ADD;
-
- setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE);
- pAsm->D.dst.rtype = DST_REG_TEMPORARY;
- pAsm->D.dst.reg = tmp3;
- pAsm->D.dst.writex = 1;
-
- setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE);
- pAsm->S[0].src.rtype = DST_REG_TEMPORARY;
- pAsm->S[0].src.reg = tmp2;
-
- setswizzle_PVSSRC(&(pAsm->S[0].src), SQ_SEL_X);
- noneg_PVSSRC(&(pAsm->S[0].src));
-
- setaddrmode_PVSSRC(&(pAsm->S[1].src), ADDR_ABSOLUTE);
- pAsm->S[1].src.rtype = DST_REG_TEMPORARY;
- pAsm->S[1].src.reg = tmp3;
-
- setswizzle_PVSSRC(&(pAsm->S[1].src), SQ_SEL_X);
- neg_PVSSRC(&(pAsm->S[1].src));
-
- if( GL_FALSE == next_ins(pAsm) )
- {
- return GL_FALSE;
- }
-
- if(8 == pAsm->unAsic)
- {
- pAsm->D.dst.opcode = EG_OP2_INST_EXP_IEEE;
- }
- else
- {
- pAsm->D.dst.opcode = SQ_OP2_INST_EXP_IEEE;
- }
- pAsm->D.dst.math = 1;
-
- if( GL_FALSE == assemble_dst(pAsm) )
- {
- return GL_FALSE;
- }
-
- pAsm->D.dst.writex = pAsm->D.dst.writez = pAsm->D.dst.writew = 0;
-
- setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE);
- pAsm->S[0].src.rtype = DST_REG_TEMPORARY;
- pAsm->S[0].src.reg = tmp3;
-
- setswizzle_PVSSRC(&(pAsm->S[0].src), SQ_SEL_X);
- noneg_PVSSRC(&(pAsm->S[0].src));
-
- if( GL_FALSE == next_ins(pAsm) )
- {
- return GL_FALSE;
- }
-
- // MOV dst.z, tmp2.x
-
- pAsm->D.dst.opcode = SQ_OP2_INST_MOV;
-
- if( GL_FALSE == assemble_dst(pAsm) )
- {
- return GL_FALSE;
- }
-
- pAsm->D.dst.writex = pAsm->D.dst.writey = pAsm->D.dst.writew = 0;
-
- setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE);
- pAsm->S[0].src.rtype = DST_REG_TEMPORARY;
- pAsm->S[0].src.reg = tmp2;
-
- setswizzle_PVSSRC(&(pAsm->S[0].src), SQ_SEL_X);
- noneg_PVSSRC(&(pAsm->S[0].src));
-
- if( GL_FALSE == next_ins(pAsm) )
- {
- return GL_FALSE;
- }
-
- // MOV dst.w 1.0
-
- pAsm->D.dst.opcode = SQ_OP2_INST_MOV;
-
- if( GL_FALSE == assemble_dst(pAsm) )
- {
- return GL_FALSE;
- }
-
- pAsm->D.dst.writex = pAsm->D.dst.writey = pAsm->D.dst.writez = 0;
-
- setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE);
- pAsm->S[0].src.rtype = SRC_REG_TEMPORARY;
- pAsm->S[0].src.reg = tmp1;
-
- setswizzle_PVSSRC(&(pAsm->S[0].src), SQ_SEL_1);
- noneg_PVSSRC(&(pAsm->S[0].src));
-
- if( GL_FALSE == next_ins(pAsm) )
- {
- return GL_FALSE;
- }
-
- return GL_TRUE;
-}
-
-GLboolean assemble_MAD(struct r700_AssemblerBase *pAsm)
-{
- int tmp, ii;
- GLboolean bReplaceDst = GL_FALSE;
- struct prog_instruction *pILInst = &(pAsm->pILInst[pAsm->uiCurInst]);
-
- if( GL_FALSE == checkop3(pAsm) )
- {
- return GL_FALSE;
- }
-
- if(8 == pAsm->unAsic)
- {
- pAsm->D.dst.opcode = EG_OP3_INST_MULADD;
- }
- else
- {
- pAsm->D.dst.opcode = SQ_OP3_INST_MULADD;
- }
- pAsm->D.dst.op3 = 1;
-
- tmp = (-1);
-
- if(PROGRAM_TEMPORARY == pILInst->DstReg.File)
- { /* TODO : more investigation on MAD src and dst using same register */
- for(ii=0; ii<3; ii++)
- {
- if( (PROGRAM_TEMPORARY == pILInst->SrcReg[ii].File)
- && (pILInst->DstReg.Index == pILInst->SrcReg[ii].Index) )
- {
- bReplaceDst = GL_TRUE;
- break;
- }
- }
- }
- if(0xF != pILInst->DstReg.WriteMask)
- { /* OP3 has no support for write mask */
- bReplaceDst = GL_TRUE;
- }
-
- if(GL_TRUE == bReplaceDst)
- {
- tmp = gethelpr(pAsm);
-
- setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE);
- pAsm->D.dst.rtype = DST_REG_TEMPORARY;
- pAsm->D.dst.reg = tmp;
-
- nomask_PVSDST(&(pAsm->D.dst));
- }
- else
- {
- if( GL_FALSE == assemble_dst(pAsm) )
- {
- return GL_FALSE;
- }
- }
-
- if( GL_FALSE == assemble_src(pAsm, 0, -1) )
- {
- return GL_FALSE;
- }
-
- if( GL_FALSE == assemble_src(pAsm, 1, -1) )
- {
- return GL_FALSE;
- }
-
- if( GL_FALSE == assemble_src(pAsm, 2, -1) )
- {
- return GL_FALSE;
- }
-
- if ( GL_FALSE == next_ins(pAsm) )
- {
- return GL_FALSE;
- }
-
- if (GL_TRUE == bReplaceDst)
- {
- if( GL_FALSE == assemble_dst(pAsm) )
- {
- return GL_FALSE;
- }
-
- pAsm->D.dst.opcode = SQ_OP2_INST_MOV;
-
- //tmp for source
- setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE);
- pAsm->S[0].src.rtype = SRC_REG_TEMPORARY;
- pAsm->S[0].src.reg = tmp;
-
- noneg_PVSSRC(&(pAsm->S[0].src));
- noswizzle_PVSSRC(&(pAsm->S[0].src));
-
- if( GL_FALSE == next_ins(pAsm) )
- {
- return GL_FALSE;
- }
- }
-
- return GL_TRUE;
-}
-
-/* LIT dst, src */
-GLboolean assemble_LIT(r700_AssemblerBase *pAsm)
-{
- unsigned int dstReg;
- unsigned int dstType;
- checkop1(pAsm);
- int tmp = gethelpr(pAsm);
-
- if( GL_FALSE == assemble_dst(pAsm) )
- {
- return GL_FALSE;
- }
- dstReg = pAsm->D.dst.reg;
- dstType = pAsm->D.dst.rtype;
-
- /* dst.xw, <- 1.0 */
- if( pAsm->D.dst.writex || pAsm->D.dst.writew )
- {
- if( GL_FALSE == assemble_src(pAsm, 0, -1) )
- {
- return GL_FALSE;
- }
-
- pAsm->D.dst.opcode = SQ_OP2_INST_MOV;
- pAsm->D.dst.writey = 0;
- pAsm->D.dst.writez = 0;
- pAsm->S[0].src.rtype = SRC_REG_TEMPORARY;
- pAsm->S[0].src.reg = tmp;
- setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE);
- noneg_PVSSRC(&(pAsm->S[0].src));
- pAsm->S[0].src.swizzlex = SQ_SEL_1;
- pAsm->S[0].src.swizzley = SQ_SEL_1;
- pAsm->S[0].src.swizzlez = SQ_SEL_1;
- pAsm->S[0].src.swizzlew = SQ_SEL_1;
- if( GL_FALSE == next_ins(pAsm) )
- {
- return GL_FALSE;
- }
- }
-
- if( GL_FALSE == assemble_dst(pAsm) )
- {
- return GL_FALSE;
- }
-
- if( pAsm->D.dst.writey ) {
-
- if( GL_FALSE == assemble_src(pAsm, 0, -1) )
- {
- return GL_FALSE;
- }
-
- /* dst.y = max(src.x, 0.0) */
- pAsm->D.dst.opcode = SQ_OP2_INST_MAX;
- pAsm->D.dst.writex = 0;
- pAsm->D.dst.writey = 1;
- pAsm->D.dst.writez = 0;
- pAsm->D.dst.writew = 0;
- swizzleagain_PVSSRC(&(pAsm->S[0].src), SQ_SEL_X, SQ_SEL_X, SQ_SEL_X, SQ_SEL_X);
- pAsm->S[1].src.rtype = SRC_REG_TEMPORARY;
- pAsm->S[1].src.reg = tmp;
- setaddrmode_PVSSRC(&(pAsm->S[1].src), ADDR_ABSOLUTE);
- noneg_PVSSRC(&(pAsm->S[1].src));
- pAsm->S[1].src.swizzlex = SQ_SEL_0;
- pAsm->S[1].src.swizzley = SQ_SEL_0;
- pAsm->S[1].src.swizzlez = SQ_SEL_0;
- pAsm->S[1].src.swizzlew = SQ_SEL_0;
- if( GL_FALSE == next_ins(pAsm) )
- {
- return GL_FALSE;
- }
- }
-
- if( GL_FALSE == assemble_dst(pAsm) )
- {
- return GL_FALSE;
- }
- if ( pAsm->D.dst.writez) {
-
- if( GL_FALSE == assemble_src(pAsm, 0, -1) )
- {
- return GL_FALSE;
- }
-
- /* dst.z = log(src.y) */
- if(8 == pAsm->unAsic)
- {
- pAsm->D.dst.opcode = EG_OP2_INST_LOG_CLAMPED;
- }
- else
- {
- pAsm->D.dst.opcode = SQ_OP2_INST_LOG_CLAMPED;
- }
- pAsm->D.dst.math = 1;
- pAsm->D.dst.writex = 0;
- pAsm->D.dst.writey = 0;
- pAsm->D.dst.writez = 1;
- pAsm->D.dst.writew = 0;
- swizzleagain_PVSSRC(&(pAsm->S[0].src), SQ_SEL_Y, SQ_SEL_Y, SQ_SEL_Y, SQ_SEL_Y);
- if( GL_FALSE == next_ins(pAsm) )
- {
- return GL_FALSE;
- }
-
- if( GL_FALSE == assemble_src(pAsm, 0, -1) )
- {
- return GL_FALSE;
- }
-
- if( GL_FALSE == assemble_src(pAsm, 0, 2) )
- {
- return GL_FALSE;
- }
-
- swizzleagain_PVSSRC(&(pAsm->S[0].src), SQ_SEL_W, SQ_SEL_W, SQ_SEL_W, SQ_SEL_W);
-
- swizzleagain_PVSSRC(&(pAsm->S[2].src), SQ_SEL_X, SQ_SEL_X, SQ_SEL_X, SQ_SEL_X);
-
- /* tmp.x = amd MUL_LIT(src.w, dst.z, src.x ) */
- if(8 == pAsm->unAsic)
- {
- pAsm->D.dst.opcode = EG_OP3_INST_MUL_LIT;
- }
- else
- {
- pAsm->D.dst.opcode = SQ_OP3_INST_MUL_LIT;
- }
- pAsm->D.dst.math = 1;
- pAsm->D.dst.op3 = 1;
- pAsm->D.dst.rtype = DST_REG_TEMPORARY;
- pAsm->D.dst.reg = tmp;
- pAsm->D.dst.writex = 1;
- pAsm->D.dst.writey = 0;
- pAsm->D.dst.writez = 0;
- pAsm->D.dst.writew = 0;
-
-
- pAsm->S[1].src.rtype = SRC_REG_TEMPORARY;
- pAsm->S[1].src.reg = dstReg;
- setaddrmode_PVSSRC(&(pAsm->S[1].src), ADDR_ABSOLUTE);
- noneg_PVSSRC(&(pAsm->S[1].src));
- pAsm->S[1].src.swizzlex = SQ_SEL_Z;
- pAsm->S[1].src.swizzley = SQ_SEL_Z;
- pAsm->S[1].src.swizzlez = SQ_SEL_Z;
- pAsm->S[1].src.swizzlew = SQ_SEL_Z;
-
- if( GL_FALSE == next_ins(pAsm) )
- {
- return GL_FALSE;
- }
-
- /* dst.z = exp(tmp.x) */
- if( GL_FALSE == assemble_dst(pAsm) )
- {
- return GL_FALSE;
- }
- if(8 == pAsm->unAsic)
- {
- pAsm->D.dst.opcode = EG_OP2_INST_EXP_IEEE;
- }
- else
- {
- pAsm->D.dst.opcode = SQ_OP2_INST_EXP_IEEE;
- }
- pAsm->D.dst.math = 1;
- pAsm->D.dst.writex = 0;
- pAsm->D.dst.writey = 0;
- pAsm->D.dst.writez = 1;
- pAsm->D.dst.writew = 0;
-
- pAsm->S[0].src.rtype = SRC_REG_TEMPORARY;
- pAsm->S[0].src.reg = tmp;
- setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE);
- noneg_PVSSRC(&(pAsm->S[0].src));
- pAsm->S[0].src.swizzlex = SQ_SEL_X;
- pAsm->S[0].src.swizzley = SQ_SEL_X;
- pAsm->S[0].src.swizzlez = SQ_SEL_X;
- pAsm->S[0].src.swizzlew = SQ_SEL_X;
-
- if( GL_FALSE == next_ins(pAsm) )
- {
- return GL_FALSE;
- }
- }
- return GL_TRUE;
-}
-
-GLboolean assemble_MAX(r700_AssemblerBase *pAsm)
-{
- if( GL_FALSE == checkop2(pAsm) )
- {
- return GL_FALSE;
- }
-
- pAsm->D.dst.opcode = SQ_OP2_INST_MAX;
-
- if( GL_FALSE == assemble_dst(pAsm) )
- {
- return GL_FALSE;
- }
-
- if( GL_FALSE == assemble_src(pAsm, 0, -1) )
- {
- return GL_FALSE;
- }
-
- if( GL_FALSE == assemble_src(pAsm, 1, -1) )
- {
- return GL_FALSE;
- }
-
- if( GL_FALSE == next_ins(pAsm) )
- {
- return GL_FALSE;
- }
-
- return GL_TRUE;
-}
-
-GLboolean assemble_MIN(r700_AssemblerBase *pAsm)
-{
- if( GL_FALSE == checkop2(pAsm) )
- {
- return GL_FALSE;
- }
-
- pAsm->D.dst.opcode = SQ_OP2_INST_MIN;
-
- if( GL_FALSE == assemble_dst(pAsm) )
- {
- return GL_FALSE;
- }
-
- if( GL_FALSE == assemble_src(pAsm, 0, -1) )
- {
- return GL_FALSE;
- }
-
- if( GL_FALSE == assemble_src(pAsm, 1, -1) )
- {
- return GL_FALSE;
- }
-
- if( GL_FALSE == next_ins(pAsm) )
- {
- return GL_FALSE;
- }
-
- return GL_TRUE;
-}
-
-GLboolean assemble_MOV(r700_AssemblerBase *pAsm)
-{
- checkop1(pAsm);
-
- pAsm->D.dst.opcode = SQ_OP2_INST_MOV;
-
- if (GL_FALSE == assemble_dst(pAsm))
- {
- return GL_FALSE;
- }
-
- if (GL_FALSE == assemble_src(pAsm, 0, -1))
- {
- return GL_FALSE;
- }
-
- if ( GL_FALSE == next_ins(pAsm) )
- {
- return GL_FALSE;
- }
-
- return GL_TRUE;
-}
-
-GLboolean assemble_MUL(r700_AssemblerBase *pAsm)
-{
- if( GL_FALSE == checkop2(pAsm) )
- {
- return GL_FALSE;
- }
-
- pAsm->D.dst.opcode = SQ_OP2_INST_MUL;
-
- if( GL_FALSE == assemble_dst(pAsm) )
- {
- return GL_FALSE;
- }
-
- if( GL_FALSE == assemble_src(pAsm, 0, -1) )
- {
- return GL_FALSE;
- }
-
- if( GL_FALSE == assemble_src(pAsm, 1, -1) )
- {
- return GL_FALSE;
- }
-
- if( GL_FALSE == next_ins(pAsm) )
- {
- return GL_FALSE;
- }
-
- return GL_TRUE;
-}
-
-GLboolean assemble_POW(r700_AssemblerBase *pAsm)
-{
- BITS tmp;
-
- checkop1(pAsm);
-
- tmp = gethelpr(pAsm);
-
- // LG2 tmp.x, a.swizzle
- if(8 == pAsm->unAsic)
- {
- pAsm->D.dst.opcode = EG_OP2_INST_LOG_IEEE;
- }
- else
- {
- pAsm->D.dst.opcode = SQ_OP2_INST_LOG_IEEE;
- }
- pAsm->D.dst.math = 1;
-
- setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE);
- pAsm->D.dst.rtype = DST_REG_TEMPORARY;
- pAsm->D.dst.reg = tmp;
- nomask_PVSDST(&(pAsm->D.dst));
-
- if( GL_FALSE == assemble_src(pAsm, 0, -1) )
- {
- return GL_FALSE;
- }
-
- if( GL_FALSE == next_ins(pAsm) )
- {
- return GL_FALSE;
- }
-
- // MUL tmp.x, tmp.x, b.swizzle
- pAsm->D.dst.opcode = SQ_OP2_INST_MUL;
-
- setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE);
- pAsm->D.dst.rtype = DST_REG_TEMPORARY;
- pAsm->D.dst.reg = tmp;
- nomask_PVSDST(&(pAsm->D.dst));
-
- setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE);
- pAsm->S[0].src.rtype = SRC_REG_TEMPORARY;
- pAsm->S[0].src.reg = tmp;
- setswizzle_PVSSRC(&(pAsm->S[0].src), SQ_SEL_X);
- noneg_PVSSRC(&(pAsm->S[0].src));
-
- if( GL_FALSE == assemble_src(pAsm, 1, -1) )
- {
- return GL_FALSE;
- }
-
- if( GL_FALSE == next_ins(pAsm) )
- {
- return GL_FALSE;
- }
-
- // EX2 dst.mask, tmp.x
- // EX2 tmp.x, tmp.x
- if(8 == pAsm->unAsic)
- {
- pAsm->D.dst.opcode = EG_OP2_INST_EXP_IEEE;
- }
- else
- {
- pAsm->D.dst.opcode = SQ_OP2_INST_EXP_IEEE;
- }
- pAsm->D.dst.math = 1;
-
- setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE);
- pAsm->D.dst.rtype = DST_REG_TEMPORARY;
- pAsm->D.dst.reg = tmp;
- nomask_PVSDST(&(pAsm->D.dst));
-
- setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE);
- pAsm->S[0].src.rtype = SRC_REG_TEMPORARY;
- pAsm->S[0].src.reg = tmp;
- setswizzle_PVSSRC(&(pAsm->S[0].src), SQ_SEL_X);
- noneg_PVSSRC(&(pAsm->S[0].src));
-
- if( GL_FALSE == next_ins(pAsm) )
- {
- return GL_FALSE;
- }
-
- // Now replicate result to all necessary channels in destination
- pAsm->D.dst.opcode = SQ_OP2_INST_MOV;
-
- if( GL_FALSE == assemble_dst(pAsm) )
- {
- return GL_FALSE;
- }
-
- setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE);
- pAsm->S[0].src.rtype = DST_REG_TEMPORARY;
- pAsm->S[0].src.reg = tmp;
-
- setswizzle_PVSSRC(&(pAsm->S[0].src), SQ_SEL_X);
- noneg_PVSSRC(&(pAsm->S[0].src));
-
- if( GL_FALSE == next_ins(pAsm) )
- {
- return GL_FALSE;
- }
-
- return GL_TRUE;
-}
-
-GLboolean assemble_RCP(r700_AssemblerBase *pAsm)
-{
- if(8 == pAsm->unAsic)
- {
- return assemble_math_function(pAsm, EG_OP2_INST_RECIP_IEEE);
- }
-
- return assemble_math_function(pAsm, SQ_OP2_INST_RECIP_IEEE);
-}
-
-GLboolean assemble_RSQ(r700_AssemblerBase *pAsm)
-{
- if(8 == pAsm->unAsic)
- {
- return assemble_math_function(pAsm, EG_OP2_INST_RECIPSQRT_IEEE);
- }
-
- return assemble_math_function(pAsm, SQ_OP2_INST_RECIPSQRT_IEEE);
-}
-
-GLboolean assemble_SCS(r700_AssemblerBase *pAsm)
-{
- BITS tmp;
-
- checkop1(pAsm);
-
- tmp = gethelpr(pAsm);
-
- if(8 == pAsm->unAsic)
- {
- pAsm->D.dst.opcode = EG_OP3_INST_MULADD;
- }
- else
- {
- pAsm->D.dst.opcode = SQ_OP3_INST_MULADD;
- }
- pAsm->D.dst.op3 = 1;
-
- setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE);
- pAsm->D.dst.rtype = DST_REG_TEMPORARY;
- pAsm->D.dst.reg = tmp;
-
- assemble_src(pAsm, 0, -1);
-
- pAsm->S[1].src.rtype = SRC_REC_LITERAL;
- setswizzle_PVSSRC(&(pAsm->S[1].src), SQ_SEL_X);
-
- pAsm->S[2].src.rtype = SRC_REC_LITERAL;
- setswizzle_PVSSRC(&(pAsm->S[2].src), SQ_SEL_Y);
-
- pAsm->D2.dst2.literal_slots = 1;
- pAsm->C[0].f = 1/(3.1415926535 * 2);
- pAsm->C[1].f = 0.5F;
-
- if ( GL_FALSE == next_ins(pAsm) )
- {
- return GL_FALSE;
- }
-
- pAsm->D.dst.opcode = SQ_OP2_INST_FRACT;
-
- setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE);
- pAsm->D.dst.rtype = DST_REG_TEMPORARY;
- pAsm->D.dst.reg = tmp;
- pAsm->D.dst.writex = 1;
-
- setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE);
- pAsm->S[0].src.rtype = SRC_REG_TEMPORARY;
- pAsm->S[0].src.reg = tmp;
- setswizzle_PVSSRC(&(pAsm->S[0].src), SQ_SEL_X);
-
- if(( GL_FALSE == next_ins(pAsm) ))
- {
- return GL_FALSE;
- }
- if(8 == pAsm->unAsic)
- {
- pAsm->D.dst.opcode = EG_OP3_INST_MULADD;
- }
- else
- {
- pAsm->D.dst.opcode = SQ_OP3_INST_MULADD;
- }
- pAsm->D.dst.op3 = 1;
-
- setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE);
- pAsm->D.dst.rtype = DST_REG_TEMPORARY;
- pAsm->D.dst.reg = tmp;
-
- setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE);
- pAsm->S[0].src.rtype = SRC_REG_TEMPORARY;
- pAsm->S[0].src.reg = tmp;
- setswizzle_PVSSRC(&(pAsm->S[0].src), SQ_SEL_X);
-
- pAsm->S[1].src.rtype = SRC_REC_LITERAL;
- setswizzle_PVSSRC(&(pAsm->S[1].src), SQ_SEL_X);
-
- pAsm->S[2].src.rtype = SRC_REC_LITERAL;
- setswizzle_PVSSRC(&(pAsm->S[2].src), SQ_SEL_Y);
-
- pAsm->D2.dst2.literal_slots = 1;
-
- if(pAsm->bR6xx) {
- pAsm->C[0].f = 3.1415926535897f * 2.0f;
- pAsm->C[1].f = -3.1415926535897f;
- } else {
- pAsm->C[0].f = 1.0f;
- pAsm->C[1].f = -0.5f;
- }
-
- if(( GL_FALSE == next_ins(pAsm) ))
- {
- return GL_FALSE;
- }
-
- // COS dst.x, a.x
- if(8 == pAsm->unAsic)
- {
- pAsm->D.dst.opcode = EG_OP2_INST_COS;
- }
- else
- {
- pAsm->D.dst.opcode = SQ_OP2_INST_COS;
- }
- pAsm->D.dst.math = 1;
-
- assemble_dst(pAsm);
- /* mask y */
- pAsm->D.dst.writey = 0;
-
- setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE);
- pAsm->S[0].src.rtype = SRC_REG_TEMPORARY;
- pAsm->S[0].src.reg = tmp;
- setswizzle_PVSSRC(&(pAsm->S[0].src), SQ_SEL_X);
- noneg_PVSSRC(&(pAsm->S[0].src));
-
- if ( GL_FALSE == next_ins(pAsm) )
- {
- return GL_FALSE;
- }
-
- // SIN dst.y, a.x
- if(8 == pAsm->unAsic)
- {
- pAsm->D.dst.opcode = EG_OP2_INST_SIN;
- }
- else
- {
- pAsm->D.dst.opcode = SQ_OP2_INST_SIN;
- }
- pAsm->D.dst.math = 1;
-
- assemble_dst(pAsm);
- /* mask x */
- pAsm->D.dst.writex = 0;
-
- setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE);
- pAsm->S[0].src.rtype = SRC_REG_TEMPORARY;
- pAsm->S[0].src.reg = tmp;
- setswizzle_PVSSRC(&(pAsm->S[0].src), SQ_SEL_X);
- noneg_PVSSRC(&(pAsm->S[0].src));
-
- if( GL_FALSE == next_ins(pAsm) )
- {
- return GL_FALSE;
- }
-
- return GL_TRUE;
-}
-
-GLboolean assemble_LOGIC(r700_AssemblerBase *pAsm, BITS opcode)
-{
- if( GL_FALSE == checkop2(pAsm) )
- {
- return GL_FALSE;
- }
-
- pAsm->D.dst.opcode = opcode;
- //pAsm->D.dst.math = 1;
-
- if( GL_FALSE == assemble_dst(pAsm) )
- {
- return GL_FALSE;
- }
-
- if( GL_FALSE == assemble_src(pAsm, 0, -1) )
- {
- return GL_FALSE;
- }
-
- if( GL_FALSE == assemble_src(pAsm, 1, -1) )
- {
- return GL_FALSE;
- }
-
- if( GL_FALSE == next_ins(pAsm) )
- {
- return GL_FALSE;
- }
-
- return GL_TRUE;
-}
-
-GLboolean assemble_LOGIC_PRED(r700_AssemblerBase *pAsm, BITS opcode)
-{
- struct prog_instruction *pILInst = &(pAsm->pILInst[pAsm->uiCurInst]);
-
- pAsm->D.dst.opcode = opcode;
- pAsm->D.dst.math = 1;
- pAsm->D.dst.predicated = 1;
-
- setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE);
- pAsm->D.dst.rtype = DST_REG_TEMPORARY;
- pAsm->D.dst.reg = pAsm->uHelpReg;
- pAsm->D.dst.writex = 1;
- pAsm->D.dst.writey = pAsm->D.dst.writez = pAsm->D.dst.writew = 0;
-
- setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE);
- pAsm->S[0].src.rtype = SRC_REG_TEMPORARY;
- pAsm->S[0].src.reg = pAsm->last_cond_register + pAsm->starting_temp_register_number;
- pAsm->S[0].src.swizzlex = pILInst->DstReg.CondSwizzle & 0x7;
- noneg_PVSSRC(&(pAsm->S[0].src));
-
- pAsm->S[1].src.rtype = SRC_REG_TEMPORARY;
- pAsm->S[1].src.reg = pAsm->uHelpReg;
- setaddrmode_PVSSRC(&(pAsm->S[1].src), ADDR_ABSOLUTE);
- noneg_PVSSRC(&(pAsm->S[1].src));
- pAsm->S[1].src.swizzlex = SQ_SEL_0;
- pAsm->S[1].src.swizzley = SQ_SEL_0;
- pAsm->S[1].src.swizzlez = SQ_SEL_0;
- pAsm->S[1].src.swizzlew = SQ_SEL_0;
-
- if( GL_FALSE == next_ins(pAsm) )
- {
- return GL_FALSE;
- }
-
- return GL_TRUE;
-}
-
-GLboolean assemble_SGE(r700_AssemblerBase *pAsm)
-{
- if( GL_FALSE == checkop2(pAsm) )
- {
- return GL_FALSE;
- }
-
- pAsm->D.dst.opcode = SQ_OP2_INST_SETGE;
-
- if( GL_FALSE == assemble_dst(pAsm) )
- {
- return GL_FALSE;
- }
-
- if( GL_FALSE == assemble_src(pAsm, 0, -1) )
- {
- return GL_FALSE;
- }
-
- if( GL_FALSE == assemble_src(pAsm, 1, -1) )
- {
- return GL_FALSE;
- }
-
- if( GL_FALSE == next_ins(pAsm) )
- {
- return GL_FALSE;
- }
-
- return GL_TRUE;
-}
-
-GLboolean assemble_SLT(r700_AssemblerBase *pAsm)
-{
- if( GL_FALSE == checkop2(pAsm) )
- {
- return GL_FALSE;
- }
-
- pAsm->D.dst.opcode = SQ_OP2_INST_SETGT;
-
- if( GL_FALSE == assemble_dst(pAsm) )
- {
- return GL_FALSE;
- }
-
- if( GL_FALSE == assemble_src(pAsm, 0, 1) )
- {
- return GL_FALSE;
- }
-
- if( GL_FALSE == assemble_src(pAsm, 1, 0) )
- {
- return GL_FALSE;
- }
-
- if( GL_FALSE == next_ins(pAsm) )
- {
- return GL_FALSE;
- }
-
- return GL_TRUE;
-}
-
-GLboolean assemble_SSG(r700_AssemblerBase *pAsm)
-{
- checkop1(pAsm);
-
- GLuint tmp = gethelpr(pAsm);
- /* tmp = (src > 0 ? 1 : src) */
- if(8 == pAsm->unAsic)
- {
- pAsm->D.dst.opcode = EG_OP3_INST_CNDGT;
- }
- else
- {
- pAsm->D.dst.opcode = SQ_OP3_INST_CNDGT;
- }
- pAsm->D.dst.op3 = 1;
- pAsm->D.dst.rtype = DST_REG_TEMPORARY;
- pAsm->D.dst.reg = tmp;
-
- if( GL_FALSE == assemble_src(pAsm, 0, -1) )
- {
- return GL_FALSE;
- }
-
- setswizzle_PVSSRC(&(pAsm->S[1].src), SQ_SEL_1);
-
- if( GL_FALSE == assemble_src(pAsm, 0, 2) )
- {
- return GL_FALSE;
- }
-
- if( GL_FALSE == next_ins(pAsm) )
- {
- return GL_FALSE;
- }
-
- /* dst = (-tmp > 0 ? -1 : tmp) */
- if(8 == pAsm->unAsic)
- {
- pAsm->D.dst.opcode = EG_OP3_INST_CNDGT;
- }
- else
- {
- pAsm->D.dst.opcode = SQ_OP3_INST_CNDGT;
- }
- pAsm->D.dst.op3 = 1;
-
- if( GL_FALSE == assemble_dst(pAsm) )
- {
- return GL_FALSE;
- }
-
- setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE);
- pAsm->S[0].src.rtype = SRC_REG_TEMPORARY;
- pAsm->S[0].src.reg = tmp;
- noswizzle_PVSSRC(&(pAsm->S[0].src));
- neg_PVSSRC(&(pAsm->S[0].src));
-
- setswizzle_PVSSRC(&(pAsm->S[1].src), SQ_SEL_1);
- neg_PVSSRC(&(pAsm->S[1].src));
-
- setaddrmode_PVSSRC(&(pAsm->S[2].src), ADDR_ABSOLUTE);
- pAsm->S[2].src.rtype = SRC_REG_TEMPORARY;
- pAsm->S[2].src.reg = tmp;
- noswizzle_PVSSRC(&(pAsm->S[2].src));
-
- if( GL_FALSE == next_ins(pAsm) )
- {
- return GL_FALSE;
- }
-
- return GL_TRUE;
-}
-
-GLboolean assemble_STP(r700_AssemblerBase *pAsm)
-{
- return GL_TRUE;
-}
-
-GLboolean assemble_TEX(r700_AssemblerBase *pAsm)
-{
- GLboolean src_const;
- GLboolean need_barrier = GL_FALSE;
-
- checkop1(pAsm);
-
- switch (pAsm->pILInst[pAsm->uiCurInst].SrcReg[0].File)
- {
- case PROGRAM_UNIFORM:
- case PROGRAM_CONSTANT:
- case PROGRAM_LOCAL_PARAM:
- case PROGRAM_ENV_PARAM:
- case PROGRAM_STATE_VAR:
- src_const = GL_TRUE;
- break;
- case PROGRAM_TEMPORARY:
- case PROGRAM_INPUT:
- default:
- src_const = GL_FALSE;
- break;
- }
-
- if (GL_TRUE == src_const)
- {
- if ( GL_FALSE == mov_temp(pAsm, 0) )
- return GL_FALSE;
- need_barrier = GL_TRUE;
- }
-
- if (pAsm->pILInst[pAsm->uiCurInst].Opcode == OPCODE_TXP)
- {
- GLuint tmp = gethelpr(pAsm);
- if(8 == pAsm->unAsic)
- {
- pAsm->D.dst.opcode = EG_OP2_INST_RECIP_IEEE;
- }
- else
- {
- pAsm->D.dst.opcode = SQ_OP2_INST_RECIP_IEEE;
- }
- pAsm->D.dst.math = 1;
- setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE);
- pAsm->D.dst.rtype = DST_REG_TEMPORARY;
- pAsm->D.dst.reg = tmp;
- pAsm->D.dst.writew = 1;
-
- if( GL_FALSE == assemble_src(pAsm, 0, -1) )
- {
- return GL_FALSE;
- }
- swizzleagain_PVSSRC(&(pAsm->S[0].src), SQ_SEL_W, SQ_SEL_W, SQ_SEL_W, SQ_SEL_W);
- if( GL_FALSE == next_ins(pAsm) )
- {
- return GL_FALSE;
- }
-
- pAsm->D.dst.opcode = SQ_OP2_INST_MUL;
- setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE);
- pAsm->D.dst.rtype = DST_REG_TEMPORARY;
- pAsm->D.dst.reg = tmp;
- pAsm->D.dst.writex = 1;
- pAsm->D.dst.writey = 1;
- pAsm->D.dst.writez = 1;
- pAsm->D.dst.writew = 0;
-
- if( GL_FALSE == assemble_src(pAsm, 0, -1) )
- {
- return GL_FALSE;
- }
- setaddrmode_PVSSRC(&(pAsm->S[1].src), ADDR_ABSOLUTE);
- pAsm->S[1].src.rtype = SRC_REG_TEMPORARY;
- pAsm->S[1].src.reg = tmp;
- setswizzle_PVSSRC(&(pAsm->S[1].src), SQ_SEL_W);
-
- if( GL_FALSE == next_ins(pAsm) )
- {
- return GL_FALSE;
- }
-
- pAsm->aArgSubst[1] = tmp;
- need_barrier = GL_TRUE;
- }
-
- if (pAsm->pILInst[pAsm->uiCurInst].TexSrcTarget == TEXTURE_CUBE_INDEX )
- {
- GLuint tmp1 = gethelpr(pAsm);
- GLuint tmp2 = gethelpr(pAsm);
-
- /* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */
- if(8 == pAsm->unAsic)
- {
- pAsm->D.dst.opcode = EG_OP2_INST_CUBE;
- }
- else
- {
- pAsm->D.dst.opcode = SQ_OP2_INST_CUBE;
- }
- setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE);
- pAsm->D.dst.rtype = DST_REG_TEMPORARY;
- pAsm->D.dst.reg = tmp1;
- nomask_PVSDST(&(pAsm->D.dst));
-
- if( GL_FALSE == assemble_src(pAsm, 0, -1) )
- {
- return GL_FALSE;
- }
-
- if( GL_FALSE == assemble_src(pAsm, 0, 1) )
- {
- return GL_FALSE;
- }
-
- swizzleagain_PVSSRC(&(pAsm->S[0].src), SQ_SEL_Z, SQ_SEL_Z, SQ_SEL_X, SQ_SEL_Y);
- swizzleagain_PVSSRC(&(pAsm->S[1].src), SQ_SEL_Y, SQ_SEL_X, SQ_SEL_Z, SQ_SEL_Z);
-
- if( GL_FALSE == next_ins(pAsm) )
- {
- return GL_FALSE;
- }
-
- /* tmp1.z = RCP_e(|tmp1.z|) */
- if(8 == pAsm->unAsic)
- {
- pAsm->D.dst.opcode = EG_OP2_INST_RECIP_IEEE;
- }
- else
- {
- pAsm->D.dst.opcode = SQ_OP2_INST_RECIP_IEEE;
- }
- pAsm->D.dst.math = 1;
- setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE);
- pAsm->D.dst.rtype = DST_REG_TEMPORARY;
- pAsm->D.dst.reg = tmp1;
- pAsm->D.dst.writez = 1;
-
- setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE);
- pAsm->S[0].src.rtype = SRC_REG_TEMPORARY;
- pAsm->S[0].src.reg = tmp1;
- pAsm->S[0].src.swizzlex = SQ_SEL_Z;
- pAsm->S[0].src.abs = 1;
-
- next_ins(pAsm);
-
- /* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x
- * MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x
- * muladd has no writemask, have to use another temp
- */
- if(8 == pAsm->unAsic)
- {
- pAsm->D.dst.opcode = EG_OP3_INST_MULADD;
- }
- else
- {
- pAsm->D.dst.opcode = SQ_OP3_INST_MULADD;
- }
- pAsm->D.dst.op3 = 1;
- setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE);
- pAsm->D.dst.rtype = DST_REG_TEMPORARY;
- pAsm->D.dst.reg = tmp2;
-
- setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE);
- pAsm->S[0].src.rtype = SRC_REG_TEMPORARY;
- pAsm->S[0].src.reg = tmp1;
- noswizzle_PVSSRC(&(pAsm->S[0].src));
- setaddrmode_PVSSRC(&(pAsm->S[1].src), ADDR_ABSOLUTE);
- pAsm->S[1].src.rtype = SRC_REG_TEMPORARY;
- pAsm->S[1].src.reg = tmp1;
- setswizzle_PVSSRC(&(pAsm->S[1].src), SQ_SEL_Z);
- setaddrmode_PVSSRC(&(pAsm->S[2].src), ADDR_ABSOLUTE);
- /* immediate c 1.5 */
- pAsm->D2.dst2.literal_slots = 1;
- pAsm->C[0].f = 1.5F;
- pAsm->S[2].src.rtype = SRC_REC_LITERAL;
- pAsm->S[2].src.reg = tmp1;
- setswizzle_PVSSRC(&(pAsm->S[2].src), SQ_SEL_X);
-
- next_ins(pAsm);
-
- /* tmp1.xy = temp2.xy */
- pAsm->D.dst.opcode = SQ_OP2_INST_MOV;
- setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE);
- pAsm->D.dst.rtype = DST_REG_TEMPORARY;
- pAsm->D.dst.reg = tmp1;
- pAsm->D.dst.writex = 1;
- pAsm->D.dst.writey = 1;
- pAsm->D.dst.writez = 0;
- pAsm->D.dst.writew = 0;
-
- setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE);
- pAsm->S[0].src.rtype = SRC_REG_TEMPORARY;
- pAsm->S[0].src.reg = tmp2;
- noswizzle_PVSSRC(&(pAsm->S[0].src));
-
- next_ins(pAsm);
- pAsm->aArgSubst[1] = tmp1;
- need_barrier = GL_TRUE;
-
- }
-
- switch(pAsm->pILInst[pAsm->uiCurInst].Opcode)
- {
- case OPCODE_DDX:
- /* will these need WQM(1) on CF inst ? */
- pAsm->D.dst.opcode = SQ_TEX_INST_GET_GRADIENTS_H;
- break;
- case OPCODE_DDY:
- pAsm->D.dst.opcode = SQ_TEX_INST_GET_GRADIENTS_V;
- break;
- case OPCODE_TXB:
- /* this should actually be SAMPLE_LB but that needs bias to be
- * embedded in the instruction - cant do here */
- pAsm->D.dst.opcode = SQ_TEX_INST_SAMPLE_L;
- break;
- case OPCODE_TXL:
- pAsm->D.dst.opcode = SQ_TEX_INST_SAMPLE_L;
- break;
- default:
- if(pAsm->pILInst[pAsm->uiCurInst].TexShadow == 1)
- pAsm->D.dst.opcode = SQ_TEX_INST_SAMPLE_C;
- else
- pAsm->D.dst.opcode = SQ_TEX_INST_SAMPLE;
- }
-
- pAsm->is_tex = GL_TRUE;
- if ( GL_TRUE == need_barrier )
-
- pAsm->is_tex = GL_TRUE;
- if ( GL_TRUE == need_barrier )
- {
- pAsm->need_tex_barrier = GL_TRUE;
- }
- // Set src1 to tex unit id
- pAsm->S[1].src.reg = pAsm->SamplerUnits[pAsm->pILInst[pAsm->uiCurInst].TexSrcUnit];
- pAsm->S[1].src.rtype = SRC_REG_TEMPORARY;
-
- //No sw info from mesa compiler, so hard code here.
- pAsm->S[1].src.swizzlex = SQ_SEL_X;
- pAsm->S[1].src.swizzley = SQ_SEL_Y;
- pAsm->S[1].src.swizzlez = SQ_SEL_Z;
- pAsm->S[1].src.swizzlew = SQ_SEL_W;
-
- if( GL_FALSE == tex_dst(pAsm) )
- {
- return GL_FALSE;
- }
-
- if( GL_FALSE == tex_src(pAsm) )
- {
- return GL_FALSE;
- }
-
- if(pAsm->pILInst[pAsm->uiCurInst].Opcode == OPCODE_TXP)
- {
- /* hopefully did swizzles before */
- noswizzle_PVSSRC(&(pAsm->S[0].src));
- }
-
- if(pAsm->pILInst[pAsm->uiCurInst].TexSrcTarget == TEXTURE_CUBE_INDEX)
- {
- /* SAMPLE dst, tmp.yxwy, CUBE */
- pAsm->S[0].src.swizzlex = SQ_SEL_Y;
- pAsm->S[0].src.swizzley = SQ_SEL_X;
- pAsm->S[0].src.swizzlez = SQ_SEL_W;
- pAsm->S[0].src.swizzlew = SQ_SEL_Y;
- }
-
- if(pAsm->pILInst[pAsm->uiCurInst].TexShadow == 1)
- {
- /* compare value goes to w chan ? */
- pAsm->S[0].src.swizzlew = SQ_SEL_Z;
- }
-
- if ( GL_FALSE == next_ins(pAsm) )
- {
- return GL_FALSE;
- }
-
- /* add ARB shadow ambient but clamp to 0..1 */
- if(pAsm->pILInst[pAsm->uiCurInst].TexShadow == 1)
- {
- /* ADD_SAT dst, dst, ambient[texunit] */
- pAsm->D.dst.opcode = SQ_OP2_INST_ADD;
-
- if( GL_FALSE == assemble_dst(pAsm) )
- {
- return GL_FALSE;
- }
- pAsm->D2.dst2.SaturateMode = 1;
-
- pAsm->S[0].src.rtype = SRC_REG_TEMPORARY;
- pAsm->S[0].src.reg = pAsm->D.dst.reg;
- noswizzle_PVSSRC(&(pAsm->S[0].src));
- noneg_PVSSRC(&(pAsm->S[0].src));
-
- pAsm->S[1].src.rtype = SRC_REG_CONSTANT;
- pAsm->S[1].src.reg = pAsm->shadow_regs[pAsm->pILInst[pAsm->uiCurInst].TexSrcUnit];
- noswizzle_PVSSRC(&(pAsm->S[1].src));
- noneg_PVSSRC(&(pAsm->S[1].src));
-
- if( GL_FALSE == next_ins(pAsm) )
- {
- return GL_FALSE;
- }
-
- }
-
- return GL_TRUE;
-}
-
-GLboolean assemble_XPD(r700_AssemblerBase *pAsm)
-{
- BITS tmp1;
- BITS tmp2 = 0;
-
- if( GL_FALSE == checkop2(pAsm) )
- {
- return GL_FALSE;
- }
-
- tmp1 = gethelpr(pAsm);
-
- pAsm->D.dst.opcode = SQ_OP2_INST_MUL;
-
- setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE);
- pAsm->D.dst.rtype = DST_REG_TEMPORARY;
- pAsm->D.dst.reg = tmp1;
- nomask_PVSDST(&(pAsm->D.dst));
-
- if( GL_FALSE == assemble_src(pAsm, 0, -1) )
- {
- return GL_FALSE;
- }
-
- if( GL_FALSE == assemble_src(pAsm, 1, -1) )
- {
- return GL_FALSE;
- }
-
- swizzleagain_PVSSRC(&(pAsm->S[0].src), SQ_SEL_Z, SQ_SEL_X, SQ_SEL_Y, SQ_SEL_0);
- swizzleagain_PVSSRC(&(pAsm->S[1].src), SQ_SEL_Y, SQ_SEL_Z, SQ_SEL_X, SQ_SEL_0);
-
- if( GL_FALSE == next_ins(pAsm) )
- {
- return GL_FALSE;
- }
-
- if(8 == pAsm->unAsic)
- {
- pAsm->D.dst.opcode = EG_OP3_INST_MULADD;
- }
- else
- {
- pAsm->D.dst.opcode = SQ_OP3_INST_MULADD;
- }
- pAsm->D.dst.op3 = 1;
-
- if(0xF != pAsm->pILInst[pAsm->uiCurInst].DstReg.WriteMask)
- {
- tmp2 = gethelpr(pAsm);
-
- setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE);
- pAsm->D.dst.rtype = DST_REG_TEMPORARY;
- pAsm->D.dst.reg = tmp2;
-
- nomask_PVSDST(&(pAsm->D.dst));
- }
- else
- {
- if( GL_FALSE == assemble_dst(pAsm) )
- {
- return GL_FALSE;
- }
- }
-
- if( GL_FALSE == assemble_src(pAsm, 0, -1) )
- {
- return GL_FALSE;
- }
-
- if( GL_FALSE == assemble_src(pAsm, 1, -1) )
- {
- return GL_FALSE;
- }
-
- swizzleagain_PVSSRC(&(pAsm->S[0].src), SQ_SEL_Y, SQ_SEL_Z, SQ_SEL_X, SQ_SEL_0);
- swizzleagain_PVSSRC(&(pAsm->S[1].src), SQ_SEL_Z, SQ_SEL_X, SQ_SEL_Y, SQ_SEL_0);
-
- // result1 + (neg) result0
- setaddrmode_PVSSRC(&(pAsm->S[2].src),ADDR_ABSOLUTE);
- pAsm->S[2].src.rtype = SRC_REG_TEMPORARY;
- pAsm->S[2].src.reg = tmp1;
-
- neg_PVSSRC(&(pAsm->S[2].src));
- noswizzle_PVSSRC(&(pAsm->S[2].src));
-
- if( GL_FALSE == next_ins(pAsm) )
- {
- return GL_FALSE;
- }
-
-
- if(0xF != pAsm->pILInst[pAsm->uiCurInst].DstReg.WriteMask)
- {
- if( GL_FALSE == assemble_dst(pAsm) )
- {
- return GL_FALSE;
- }
-
- pAsm->D.dst.opcode = SQ_OP2_INST_MOV;
-
- // Use tmp as source
- setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE);
- pAsm->S[0].src.rtype = SRC_REG_TEMPORARY;
- pAsm->S[0].src.reg = tmp2;
-
- noneg_PVSSRC(&(pAsm->S[0].src));
- noswizzle_PVSSRC(&(pAsm->S[0].src));
-
- if( GL_FALSE == next_ins(pAsm) )
- {
- return GL_FALSE;
- }
- }
-
- return GL_TRUE;
-}
-
-GLboolean assemble_EXPORT(r700_AssemblerBase *pAsm)
-{
- return GL_TRUE;
-}
-
-static inline void decreaseCurrent(r700_AssemblerBase *pAsm, GLuint uReason)
-{
- switch (uReason)
- {
- case FC_PUSH_VPM:
- pAsm->CALLSTACK[pAsm->CALLSP].current--;
- break;
- case FC_PUSH_WQM:
- pAsm->CALLSTACK[pAsm->CALLSP].current -= 4;
- break;
- case FC_LOOP:
- pAsm->CALLSTACK[pAsm->CALLSP].current -= 4;
- break;
- case FC_REP:
- /* TODO : for 16 vp asic, should -= 2; */
- pAsm->CALLSTACK[pAsm->CALLSP].current -= 1;
- break;
- };
-}
-
-static inline void checkStackDepth(r700_AssemblerBase *pAsm, GLuint uReason, GLboolean bCheckMaxOnly)
-{
- if(GL_TRUE == bCheckMaxOnly)
- {
- switch (uReason)
- {
- case FC_PUSH_VPM:
- if((pAsm->CALLSTACK[pAsm->CALLSP].current + 1)
- > pAsm->CALLSTACK[pAsm->CALLSP].max)
- {
- pAsm->CALLSTACK[pAsm->CALLSP].max =
- pAsm->CALLSTACK[pAsm->CALLSP].current + 1;
- }
- break;
- case FC_PUSH_WQM:
- if((pAsm->CALLSTACK[pAsm->CALLSP].current + 4)
- > pAsm->CALLSTACK[pAsm->CALLSP].max)
- {
- pAsm->CALLSTACK[pAsm->CALLSP].max =
- pAsm->CALLSTACK[pAsm->CALLSP].current + 4;
- }
- break;
- }
- return;
- }
-
- switch (uReason)
- {
- case FC_PUSH_VPM:
- pAsm->CALLSTACK[pAsm->CALLSP].current++;
- break;
- case FC_PUSH_WQM:
- pAsm->CALLSTACK[pAsm->CALLSP].current += 4;
- break;
- case FC_LOOP:
- pAsm->CALLSTACK[pAsm->CALLSP].current += 4;
- break;
- case FC_REP:
- /* TODO : for 16 vp asic, should += 2; */
- pAsm->CALLSTACK[pAsm->CALLSP].current += 1;
- break;
- };
-
- if(pAsm->CALLSTACK[pAsm->CALLSP].current
- > pAsm->CALLSTACK[pAsm->CALLSP].max)
- {
- pAsm->CALLSTACK[pAsm->CALLSP].max =
- pAsm->CALLSTACK[pAsm->CALLSP].current;
- }
-}
-
-GLboolean jumpToOffest(r700_AssemblerBase *pAsm, GLuint pops, GLint offset)
-{
- if(GL_FALSE == add_cf_instruction(pAsm) )
- {
- return GL_FALSE;
- }
-
- if(8 == pAsm->unAsic)
- {
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- EG_CF_INST_JUMP,
- EG_CF_WORD1__CF_INST_shift, EG_CF_WORD1__CF_INST_mask);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- pops,
- EG_CF_WORD1__POP_COUNT_shift, EG_CF_WORD1__POP_COUNT_mask);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 0,
- EG_CF_WORD1__CF_CONST_shift, EG_CF_WORD1__CF_CONST_mask);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- SQ_CF_COND_ACTIVE,
- EG_CF_WORD1__COND_shift, EG_CF_WORD1__COND_mask);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 0,
- EG_CF_WORD1__COUNT_shift, EG_CF_WORD1__COUNT_mask);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 0,
- EG_CF_WORD1__VPM_shift, EG_CF_WORD1__VPM_bit);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 0,
- EG_CF_WORD1__EOP_shift, EG_CF_WORD1__EOP_bit);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 0,
- EG_CF_WORD1__WQM_shift, EG_CF_WORD1__WQM_bit);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 1,
- EG_CF_WORD1__BARRIER_shift, EG_CF_WORD1__BARRIER_bit);
- }
- else
- {
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.pop_count = pops;
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.cf_const = 0x0;
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.cond = SQ_CF_COND_ACTIVE;
-
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.end_of_program = 0x0;
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.valid_pixel_mode = 0x0;
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.cf_inst = SQ_CF_INST_JUMP;
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.whole_quad_mode = 0x0;
-
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.barrier = 0x1;
- }
-
- pAsm->cf_current_cf_clause_ptr->m_Word0.f.addr = pAsm->cf_current_cf_clause_ptr->m_uIndex + offset;
-
- return GL_TRUE;
-}
-
-GLboolean pops(r700_AssemblerBase *pAsm, GLuint pops)
-{
- if(GL_FALSE == add_cf_instruction(pAsm) )
- {
- return GL_FALSE;
- }
-
- if(8 == pAsm->unAsic)
- {
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- EG_CF_INST_POP,
- EG_CF_WORD1__CF_INST_shift, EG_CF_WORD1__CF_INST_mask);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- pops,
- EG_CF_WORD1__POP_COUNT_shift, EG_CF_WORD1__POP_COUNT_mask);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 0,
- EG_CF_WORD1__CF_CONST_shift, EG_CF_WORD1__CF_CONST_mask);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- SQ_CF_COND_ACTIVE,
- EG_CF_WORD1__COND_shift, EG_CF_WORD1__COND_mask);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 0,
- EG_CF_WORD1__EOP_shift, EG_CF_WORD1__EOP_bit);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 0,
- EG_CF_WORD1__VPM_shift, EG_CF_WORD1__VPM_bit);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 0,
- EG_CF_WORD1__WQM_shift, EG_CF_WORD1__WQM_bit);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 1,
- EG_CF_WORD1__BARRIER_shift, EG_CF_WORD1__BARRIER_bit);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 0,
- EG_CF_WORD1__COUNT_shift, EG_CF_WORD1__COUNT_mask);
- }
- else
- {
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.pop_count = pops;
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.cf_const = 0x0;
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.cond = SQ_CF_COND_ACTIVE;
-
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.end_of_program = 0x0;
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.valid_pixel_mode = 0x0;
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.cf_inst = SQ_CF_INST_POP;
-
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.whole_quad_mode = 0x0;
-
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.barrier = 0x1;
- }
- pAsm->cf_current_cf_clause_ptr->m_Word0.f.addr = pAsm->cf_current_cf_clause_ptr->m_uIndex + 1;
-
- return GL_TRUE;
-}
-
-GLboolean assemble_IF(r700_AssemblerBase *pAsm, GLboolean bHasElse)
-{
- pAsm->alu_x_opcode = SQ_CF_INST_ALU_PUSH_BEFORE;
-
- assemble_LOGIC_PRED(pAsm, SQ_OP2_INST_PRED_SETNE);
-
-
- if(GL_FALSE == add_cf_instruction(pAsm) )
- {
- return GL_FALSE;
- }
-
- if(8 == pAsm->unAsic)
- {
- if(GL_TRUE != bHasElse)
- {
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 1,
- EG_CF_WORD1__POP_COUNT_shift, EG_CF_WORD1__POP_COUNT_mask);
- }
- else
- {
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 0,
- EG_CF_WORD1__POP_COUNT_shift, EG_CF_WORD1__POP_COUNT_mask);
- }
-
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- EG_CF_INST_JUMP,
- EG_CF_WORD1__CF_INST_shift, EG_CF_WORD1__CF_INST_mask);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 0,
- EG_CF_WORD1__CF_CONST_shift, EG_CF_WORD1__CF_CONST_mask);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- SQ_CF_COND_ACTIVE,
- EG_CF_WORD1__COND_shift, EG_CF_WORD1__COND_mask);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 0,
- EG_CF_WORD1__EOP_shift, EG_CF_WORD1__EOP_bit);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 0,
- EG_CF_WORD1__VPM_shift, EG_CF_WORD1__VPM_bit);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 0,
- EG_CF_WORD1__WQM_shift, EG_CF_WORD1__WQM_bit);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 1,
- EG_CF_WORD1__BARRIER_shift, EG_CF_WORD1__BARRIER_bit);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 0,
- EG_CF_WORD1__COUNT_shift, EG_CF_WORD1__COUNT_mask);
- }
- else
- {
- if(GL_TRUE != bHasElse)
- {
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.pop_count = 1;
- }
- else
- {
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.pop_count = 0;
- }
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.cf_const = 0x0;
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.cond = SQ_CF_COND_ACTIVE;
-
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.end_of_program = 0x0;
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.valid_pixel_mode = 0x0;
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.cf_inst = SQ_CF_INST_JUMP;
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.whole_quad_mode = 0x0;
-
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.barrier = 0x1;
- }
-
- pAsm->FCSP++;
- pAsm->fc_stack[pAsm->FCSP].type = FC_IF;
- pAsm->fc_stack[pAsm->FCSP].mid = NULL;
- pAsm->fc_stack[pAsm->FCSP].midLen= 0;
- pAsm->fc_stack[pAsm->FCSP].first = pAsm->cf_current_cf_clause_ptr;
-
-#ifndef USE_CF_FOR_POP_AFTER
- if(GL_TRUE != bHasElse)
- {
- pAsm->alu_x_opcode = SQ_CF_INST_ALU_POP_AFTER;
- }
-#endif /* USE_CF_FOR_POP_AFTER */
-
- checkStackDepth(pAsm, FC_PUSH_VPM, GL_FALSE);
-
- return GL_TRUE;
-}
-
-GLboolean assemble_ELSE(r700_AssemblerBase *pAsm)
-{
- if(GL_FALSE == add_cf_instruction(pAsm) )
- {
- return GL_FALSE;
- }
-
- if(8 == pAsm->unAsic)
- {
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 1,
- EG_CF_WORD1__POP_COUNT_shift, EG_CF_WORD1__POP_COUNT_mask);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- EG_CF_INST_ELSE,
- EG_CF_WORD1__CF_INST_shift, EG_CF_WORD1__CF_INST_mask);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 0,
- EG_CF_WORD1__CF_CONST_shift, EG_CF_WORD1__CF_CONST_mask);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- SQ_CF_COND_ACTIVE,
- EG_CF_WORD1__COND_shift, EG_CF_WORD1__COND_mask);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 0,
- EG_CF_WORD1__EOP_shift, EG_CF_WORD1__EOP_bit);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 0,
- EG_CF_WORD1__VPM_shift, EG_CF_WORD1__VPM_bit);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 0,
- EG_CF_WORD1__WQM_shift, EG_CF_WORD1__WQM_bit);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 1,
- EG_CF_WORD1__BARRIER_shift, EG_CF_WORD1__BARRIER_bit);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 0,
- EG_CF_WORD1__COUNT_shift, EG_CF_WORD1__COUNT_mask);
- }
- else
- {
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.pop_count = 1; ///
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.cf_const = 0x0;
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.cond = SQ_CF_COND_ACTIVE;
-
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.end_of_program = 0x0;
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.valid_pixel_mode = 0x0;
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.cf_inst = SQ_CF_INST_ELSE;
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.whole_quad_mode = 0x0;
-
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.barrier = 0x1;
- }
-
- pAsm->fc_stack[pAsm->FCSP].mid = (R700ControlFlowGenericClause **)_mesa_realloc( (void *)pAsm->fc_stack[pAsm->FCSP].mid,
- 0,
- sizeof(R700ControlFlowGenericClause *) );
- pAsm->fc_stack[pAsm->FCSP].mid[0] = pAsm->cf_current_cf_clause_ptr;
- //pAsm->fc_stack[pAsm->FCSP].unNumMid = 1;
-
-#ifndef USE_CF_FOR_POP_AFTER
- pAsm->alu_x_opcode = SQ_CF_INST_ALU_POP_AFTER;
-#endif /* USE_CF_FOR_POP_AFTER */
-
- pAsm->fc_stack[pAsm->FCSP].first->m_Word0.f.addr = pAsm->pR700Shader->plstCFInstructions_active->uNumOfNode - 1;
-
- return GL_TRUE;
-}
-
-GLboolean assemble_ENDIF(r700_AssemblerBase *pAsm)
-{
-#ifdef USE_CF_FOR_POP_AFTER
- pops(pAsm, 1);
-#endif /* USE_CF_FOR_POP_AFTER */
-
- pAsm->alu_x_opcode = SQ_CF_INST_ALU;
-
- if(NULL == pAsm->fc_stack[pAsm->FCSP].mid)
- {
- /* no else in between */
- pAsm->fc_stack[pAsm->FCSP].first->m_Word0.f.addr = pAsm->pR700Shader->plstCFInstructions_active->uNumOfNode;
- }
- else
- {
- pAsm->fc_stack[pAsm->FCSP].mid[0]->m_Word0.f.addr = pAsm->pR700Shader->plstCFInstructions_active->uNumOfNode;
- }
-
- if(NULL != pAsm->fc_stack[pAsm->FCSP].mid)
- {
- FREE(pAsm->fc_stack[pAsm->FCSP].mid);
- }
-
- if(pAsm->fc_stack[pAsm->FCSP].type != FC_IF)
- {
- radeon_error("if/endif in shader code are not paired. \n");
- return GL_FALSE;
- }
-
- pAsm->FCSP--;
-
- decreaseCurrent(pAsm, FC_PUSH_VPM);
-
- return GL_TRUE;
-}
-
-GLboolean assemble_BGNLOOP(r700_AssemblerBase *pAsm)
-{
- if(GL_FALSE == add_cf_instruction(pAsm) )
- {
- return GL_FALSE;
- }
-
- if(8 == pAsm->unAsic)
- {
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 0,
- EG_CF_WORD1__POP_COUNT_shift, EG_CF_WORD1__POP_COUNT_mask);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- EG_CF_INST_LOOP_START_NO_AL,
- EG_CF_WORD1__CF_INST_shift, EG_CF_WORD1__CF_INST_mask);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 0,
- EG_CF_WORD1__CF_CONST_shift, EG_CF_WORD1__CF_CONST_mask);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- SQ_CF_COND_ACTIVE,
- EG_CF_WORD1__COND_shift, EG_CF_WORD1__COND_mask);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 0,
- EG_CF_WORD1__EOP_shift, EG_CF_WORD1__EOP_bit);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 0,
- EG_CF_WORD1__VPM_shift, EG_CF_WORD1__VPM_bit);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 0,
- EG_CF_WORD1__WQM_shift, EG_CF_WORD1__WQM_bit);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 1,
- EG_CF_WORD1__BARRIER_shift, EG_CF_WORD1__BARRIER_bit);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 0,
- EG_CF_WORD1__COUNT_shift, EG_CF_WORD1__COUNT_mask);
- }
- else
- {
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.pop_count = 0;
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.cf_const = 0x0;
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.cond = SQ_CF_COND_ACTIVE;
-
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.end_of_program = 0x0;
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.valid_pixel_mode = 0x0;
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.cf_inst = SQ_CF_INST_LOOP_START_NO_AL;
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.whole_quad_mode = 0x0;
-
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.barrier = 0x1;
- }
-
- pAsm->FCSP++;
- pAsm->fc_stack[pAsm->FCSP].type = FC_LOOP;
- pAsm->fc_stack[pAsm->FCSP].mid = NULL;
- pAsm->fc_stack[pAsm->FCSP].unNumMid = 0;
- pAsm->fc_stack[pAsm->FCSP].midLen = 0;
- pAsm->fc_stack[pAsm->FCSP].first = pAsm->cf_current_cf_clause_ptr;
-
- checkStackDepth(pAsm, FC_LOOP, GL_FALSE);
-
- return GL_TRUE;
-}
-
-GLboolean assemble_BRK(r700_AssemblerBase *pAsm)
-{
-#ifdef USE_CF_FOR_CONTINUE_BREAK
-
- pAsm->alu_x_opcode = SQ_CF_INST_ALU_PUSH_BEFORE;
-
- assemble_LOGIC_PRED(pAsm, SQ_OP2_INST_PRED_SETNE);
-
- unsigned int unFCSP;
- for(unFCSP=pAsm->FCSP; unFCSP>0; unFCSP--)
- {
- if(FC_LOOP == pAsm->fc_stack[unFCSP].type)
- {
- break;
- }
- }
- if(0 == FC_LOOP)
- {
- radeon_error("Break is not inside loop/endloop pair.\n");
- return GL_FALSE;
- }
-
- if(GL_FALSE == add_cf_instruction(pAsm) )
- {
- return GL_FALSE;
- }
-
- if(8 == pAsm->unAsic)
- {
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 1,
- EG_CF_WORD1__POP_COUNT_shift, EG_CF_WORD1__POP_COUNT_mask);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- EG_CF_INST_LOOP_BREAK,
- EG_CF_WORD1__CF_INST_shift, EG_CF_WORD1__CF_INST_mask);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 0,
- EG_CF_WORD1__CF_CONST_shift, EG_CF_WORD1__CF_CONST_mask);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- SQ_CF_COND_ACTIVE,
- EG_CF_WORD1__COND_shift, EG_CF_WORD1__COND_mask);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 0,
- EG_CF_WORD1__EOP_shift, EG_CF_WORD1__EOP_bit);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 0,
- EG_CF_WORD1__VPM_shift, EG_CF_WORD1__VPM_bit);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 0,
- EG_CF_WORD1__WQM_shift, EG_CF_WORD1__WQM_bit);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 1,
- EG_CF_WORD1__BARRIER_shift, EG_CF_WORD1__BARRIER_bit);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 0,
- EG_CF_WORD1__COUNT_shift, EG_CF_WORD1__COUNT_mask);
- }
- else
- {
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.pop_count = 1;
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.cf_const = 0x0;
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.cond = SQ_CF_COND_ACTIVE;
-
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.end_of_program = 0x0;
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.valid_pixel_mode = 0x0;
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.cf_inst = SQ_CF_INST_LOOP_BREAK;
-
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.whole_quad_mode = 0x0;
-
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.barrier = 0x1;
- }
-
- pAsm->fc_stack[unFCSP].mid = (R700ControlFlowGenericClause **)_mesa_realloc(
- (void *)pAsm->fc_stack[unFCSP].mid,
- sizeof(R700ControlFlowGenericClause *) * pAsm->fc_stack[unFCSP].unNumMid,
- sizeof(R700ControlFlowGenericClause *) * (pAsm->fc_stack[unFCSP].unNumMid + 1) );
- pAsm->fc_stack[unFCSP].mid[pAsm->fc_stack[unFCSP].unNumMid] = pAsm->cf_current_cf_clause_ptr;
- pAsm->fc_stack[unFCSP].unNumMid++;
-
- if(GL_FALSE == add_cf_instruction(pAsm) )
- {
- return GL_FALSE;
- }
-
- if(8 == pAsm->unAsic)
- {
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 1,
- EG_CF_WORD1__POP_COUNT_shift, EG_CF_WORD1__POP_COUNT_mask);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- EG_CF_INST_POP,
- EG_CF_WORD1__CF_INST_shift, EG_CF_WORD1__CF_INST_mask);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 0,
- EG_CF_WORD1__CF_CONST_shift, EG_CF_WORD1__CF_CONST_mask);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- SQ_CF_COND_ACTIVE,
- EG_CF_WORD1__COND_shift, EG_CF_WORD1__COND_mask);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 0,
- EG_CF_WORD1__EOP_shift, EG_CF_WORD1__EOP_bit);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 0,
- EG_CF_WORD1__VPM_shift, EG_CF_WORD1__VPM_bit);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 0,
- EG_CF_WORD1__WQM_shift, EG_CF_WORD1__WQM_bit);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 1,
- EG_CF_WORD1__BARRIER_shift, EG_CF_WORD1__BARRIER_bit);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 0,
- EG_CF_WORD1__COUNT_shift, EG_CF_WORD1__COUNT_mask);
- }
- else
- {
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.pop_count = 1;
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.cf_const = 0x0;
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.cond = SQ_CF_COND_ACTIVE;
-
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.end_of_program = 0x0;
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.valid_pixel_mode = 0x0;
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.cf_inst = SQ_CF_INST_POP;
-
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.whole_quad_mode = 0x0;
-
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.barrier = 0x1;
- }
-
- pAsm->cf_current_cf_clause_ptr->m_Word0.f.addr = pAsm->cf_current_cf_clause_ptr->m_uIndex + 1;
-
- checkStackDepth(pAsm, FC_PUSH_VPM, GL_TRUE);
-
-#endif //USE_CF_FOR_CONTINUE_BREAK
- return GL_TRUE;
-}
-
-GLboolean assemble_CONT(r700_AssemblerBase *pAsm)
-{
-#ifdef USE_CF_FOR_CONTINUE_BREAK
- pAsm->alu_x_opcode = SQ_CF_INST_ALU_PUSH_BEFORE;
-
- assemble_LOGIC_PRED(pAsm, SQ_OP2_INST_PRED_SETNE);
-
- unsigned int unFCSP;
- for(unFCSP=pAsm->FCSP; unFCSP>0; unFCSP--)
- {
- if(FC_LOOP == pAsm->fc_stack[unFCSP].type)
- {
- break;
- }
- }
- if(0 == FC_LOOP)
- {
- radeon_error("Continue is not inside loop/endloop pair.\n");
- return GL_FALSE;
- }
-
- if(GL_FALSE == add_cf_instruction(pAsm) )
- {
- return GL_FALSE;
- }
-
- if(8 == pAsm->unAsic)
- {
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 1,
- EG_CF_WORD1__POP_COUNT_shift, EG_CF_WORD1__POP_COUNT_mask);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- EG_CF_INST_LOOP_CONTINUE,
- EG_CF_WORD1__CF_INST_shift, EG_CF_WORD1__CF_INST_mask);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 0,
- EG_CF_WORD1__CF_CONST_shift, EG_CF_WORD1__CF_CONST_mask);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- SQ_CF_COND_ACTIVE,
- EG_CF_WORD1__COND_shift, EG_CF_WORD1__COND_mask);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 0,
- EG_CF_WORD1__EOP_shift, EG_CF_WORD1__EOP_bit);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 0,
- EG_CF_WORD1__VPM_shift, EG_CF_WORD1__VPM_bit);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 0,
- EG_CF_WORD1__WQM_shift, EG_CF_WORD1__WQM_bit);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 1,
- EG_CF_WORD1__BARRIER_shift, EG_CF_WORD1__BARRIER_bit);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 0,
- EG_CF_WORD1__COUNT_shift, EG_CF_WORD1__COUNT_mask);
- }
- else
- {
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.pop_count = 1;
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.cf_const = 0x0;
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.cond = SQ_CF_COND_ACTIVE;
-
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.end_of_program = 0x0;
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.valid_pixel_mode = 0x0;
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.cf_inst = SQ_CF_INST_LOOP_CONTINUE;
-
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.whole_quad_mode = 0x0;
-
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.barrier = 0x1;
- }
-
- pAsm->fc_stack[unFCSP].mid = (R700ControlFlowGenericClause **)_mesa_realloc(
- (void *)pAsm->fc_stack[unFCSP].mid,
- sizeof(R700ControlFlowGenericClause *) * pAsm->fc_stack[unFCSP].unNumMid,
- sizeof(R700ControlFlowGenericClause *) * (pAsm->fc_stack[unFCSP].unNumMid + 1) );
- pAsm->fc_stack[unFCSP].mid[pAsm->fc_stack[unFCSP].unNumMid] = pAsm->cf_current_cf_clause_ptr;
- pAsm->fc_stack[unFCSP].unNumMid++;
-
- if(GL_FALSE == add_cf_instruction(pAsm) )
- {
- return GL_FALSE;
- }
-
- if(8 == pAsm->unAsic)
- {
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 1,
- EG_CF_WORD1__POP_COUNT_shift, EG_CF_WORD1__POP_COUNT_mask);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- EG_CF_INST_POP,
- EG_CF_WORD1__CF_INST_shift, EG_CF_WORD1__CF_INST_mask);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 0,
- EG_CF_WORD1__CF_CONST_shift, EG_CF_WORD1__CF_CONST_mask);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- SQ_CF_COND_ACTIVE,
- EG_CF_WORD1__COND_shift, EG_CF_WORD1__COND_mask);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 0,
- EG_CF_WORD1__EOP_shift, EG_CF_WORD1__EOP_bit);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 0,
- EG_CF_WORD1__VPM_shift, EG_CF_WORD1__VPM_bit);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 0,
- EG_CF_WORD1__WQM_shift, EG_CF_WORD1__WQM_bit);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 1,
- EG_CF_WORD1__BARRIER_shift, EG_CF_WORD1__BARRIER_bit);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 0,
- EG_CF_WORD1__COUNT_shift, EG_CF_WORD1__COUNT_mask);
- }
- else
- {
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.pop_count = 1;
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.cf_const = 0x0;
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.cond = SQ_CF_COND_ACTIVE;
-
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.end_of_program = 0x0;
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.valid_pixel_mode = 0x0;
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.cf_inst = SQ_CF_INST_POP;
-
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.whole_quad_mode = 0x0;
-
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.barrier = 0x1;
- }
-
- pAsm->cf_current_cf_clause_ptr->m_Word0.f.addr = pAsm->cf_current_cf_clause_ptr->m_uIndex + 1;
-
- checkStackDepth(pAsm, FC_PUSH_VPM, GL_TRUE);
-
-#endif /* USE_CF_FOR_CONTINUE_BREAK */
-
- return GL_TRUE;
-}
-
-GLboolean assemble_ENDLOOP(r700_AssemblerBase *pAsm)
-{
- GLuint i;
-
- if(GL_FALSE == add_cf_instruction(pAsm) )
- {
- return GL_FALSE;
- }
-
- if(8 == pAsm->unAsic)
- {
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 0,
- EG_CF_WORD1__POP_COUNT_shift, EG_CF_WORD1__POP_COUNT_mask);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- EG_CF_INST_LOOP_END,
- EG_CF_WORD1__CF_INST_shift, EG_CF_WORD1__CF_INST_mask);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 0,
- EG_CF_WORD1__CF_CONST_shift, EG_CF_WORD1__CF_CONST_mask);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- SQ_CF_COND_ACTIVE,
- EG_CF_WORD1__COND_shift, EG_CF_WORD1__COND_mask);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 0,
- EG_CF_WORD1__EOP_shift, EG_CF_WORD1__EOP_bit);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 0,
- EG_CF_WORD1__VPM_shift, EG_CF_WORD1__VPM_bit);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 0,
- EG_CF_WORD1__WQM_shift, EG_CF_WORD1__WQM_bit);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 1,
- EG_CF_WORD1__BARRIER_shift, EG_CF_WORD1__BARRIER_bit);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 0,
- EG_CF_WORD1__COUNT_shift, EG_CF_WORD1__COUNT_mask);
- }
- else
- {
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.pop_count = 0;
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.cf_const = 0x0;
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.cond = SQ_CF_COND_ACTIVE;
-
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.end_of_program = 0x0;
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.valid_pixel_mode = 0x0;
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.cf_inst = SQ_CF_INST_LOOP_END;
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.whole_quad_mode = 0x0;
-
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.barrier = 0x1;
- }
-
- pAsm->cf_current_cf_clause_ptr->m_Word0.f.addr = pAsm->fc_stack[pAsm->FCSP].first->m_uIndex + 1;
- pAsm->fc_stack[pAsm->FCSP].first->m_Word0.f.addr = pAsm->cf_current_cf_clause_ptr->m_uIndex + 1;
-
-#ifdef USE_CF_FOR_CONTINUE_BREAK
- for(i=0; i<pAsm->fc_stack[pAsm->FCSP].unNumMid; i++)
- {
- pAsm->fc_stack[pAsm->FCSP].mid[i]->m_Word0.f.addr = pAsm->cf_current_cf_clause_ptr->m_uIndex;
- }
- if(NULL != pAsm->fc_stack[pAsm->FCSP].mid)
- {
- FREE(pAsm->fc_stack[pAsm->FCSP].mid);
- }
-#endif
-
- if(pAsm->fc_stack[pAsm->FCSP].type != FC_LOOP)
- {
- radeon_error("loop/endloop in shader code are not paired. \n");
- return GL_FALSE;
- }
-
- GLuint unFCSP;
- GLuint unIF = 0;
- if((pAsm->unCFflags & HAS_CURRENT_LOOPRET) > 0)
- {
- for(unFCSP=(pAsm->FCSP-1); unFCSP>pAsm->CALLSTACK[pAsm->CALLSP].FCSP_BeforeEntry; unFCSP--)
- {
- if(FC_LOOP == pAsm->fc_stack[unFCSP].type)
- {
- breakLoopOnFlag(pAsm, unFCSP);
- break;
- }
- else if(FC_IF == pAsm->fc_stack[unFCSP].type)
- {
- unIF++;
- }
- }
- if(unFCSP <= pAsm->CALLSTACK[pAsm->CALLSP].FCSP_BeforeEntry)
- {
-#ifdef USE_CF_FOR_POP_AFTER
- returnOnFlag(pAsm, unIF);
-#else
- returnOnFlag(pAsm, 0);
-#endif /* USE_CF_FOR_POP_AFTER */
- pAsm->unCFflags &= ~HAS_CURRENT_LOOPRET;
- }
- }
-
- pAsm->FCSP--;
-
- decreaseCurrent(pAsm, FC_LOOP);
-
- return GL_TRUE;
-}
-
-void add_return_inst(r700_AssemblerBase *pAsm)
-{
- if(GL_FALSE == add_cf_instruction(pAsm) )
- {
- return;
- }
-
- if(8 == pAsm->unAsic)
- {
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 0,
- EG_CF_WORD1__POP_COUNT_shift, EG_CF_WORD1__POP_COUNT_mask);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- EG_CF_INST_RETURN,
- EG_CF_WORD1__CF_INST_shift, EG_CF_WORD1__CF_INST_mask);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 0,
- EG_CF_WORD1__CF_CONST_shift, EG_CF_WORD1__CF_CONST_mask);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- SQ_CF_COND_ACTIVE,
- EG_CF_WORD1__COND_shift, EG_CF_WORD1__COND_mask);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 0,
- EG_CF_WORD1__EOP_shift, EG_CF_WORD1__EOP_bit);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 0,
- EG_CF_WORD1__VPM_shift, EG_CF_WORD1__VPM_bit);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 0,
- EG_CF_WORD1__WQM_shift, EG_CF_WORD1__WQM_bit);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 1,
- EG_CF_WORD1__BARRIER_shift, EG_CF_WORD1__BARRIER_bit);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 0,
- EG_CF_WORD1__COUNT_shift, EG_CF_WORD1__COUNT_mask);
- }
- else
- {
- //pAsm->cf_current_cf_clause_ptr->m_Word1.f.pop_count = 1;
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.pop_count = 0;
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.cf_const = 0x0;
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.cond = SQ_CF_COND_ACTIVE;
-
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.end_of_program = 0x0;
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.valid_pixel_mode = 0x0;
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.cf_inst = SQ_CF_INST_RETURN;
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.whole_quad_mode = 0x0;
-
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.barrier = 0x1;
- }
-}
-
-GLboolean assemble_BGNSUB(r700_AssemblerBase *pAsm, GLint nILindex, GLuint uiIL_Shift)
-{
- /* Put in sub */
- if( (pAsm->unSubArrayPointer + 1) > pAsm->unSubArraySize )
- {
- pAsm->subs = (SUB_OFFSET*)_mesa_realloc( (void *)pAsm->subs,
- sizeof(SUB_OFFSET) * pAsm->unSubArraySize,
- sizeof(SUB_OFFSET) * (pAsm->unSubArraySize + 10) );
- if(NULL == pAsm->subs)
- {
- return GL_FALSE;
- }
- pAsm->unSubArraySize += 10;
- }
-
- pAsm->subs[pAsm->unSubArrayPointer].subIL_Offset = nILindex + uiIL_Shift;
- pAsm->subs[pAsm->unSubArrayPointer].lstCFInstructions_local.pHead=NULL;
- pAsm->subs[pAsm->unSubArrayPointer].lstCFInstructions_local.pTail=NULL;
- pAsm->subs[pAsm->unSubArrayPointer].lstCFInstructions_local.uNumOfNode=0;
-
- pAsm->CALLSP++;
- pAsm->CALLSTACK[pAsm->CALLSP].subDescIndex = pAsm->unSubArrayPointer;
- pAsm->CALLSTACK[pAsm->CALLSP].FCSP_BeforeEntry = pAsm->FCSP;
- pAsm->CALLSTACK[pAsm->CALLSP].plstCFInstructions_local
- = &(pAsm->subs[pAsm->unSubArrayPointer].lstCFInstructions_local);
- pAsm->CALLSTACK[pAsm->CALLSP].max = 0;
- pAsm->CALLSTACK[pAsm->CALLSP].current = 0;
- SetActiveCFlist(pAsm->pR700Shader,
- pAsm->CALLSTACK[pAsm->CALLSP].plstCFInstructions_local);
-
- pAsm->unSubArrayPointer++;
-
- /* start sub */
- pAsm->alu_x_opcode = SQ_CF_INST_ALU;
-
- pAsm->FCSP++;
- pAsm->fc_stack[pAsm->FCSP].type = FC_REP;
-
- checkStackDepth(pAsm, FC_REP, GL_FALSE);
-
- return GL_TRUE;
-}
-
-GLboolean assemble_ENDSUB(r700_AssemblerBase *pAsm)
-{
- if(pAsm->fc_stack[pAsm->FCSP].type != FC_REP)
- {
- radeon_error("BGNSUB/ENDSUB in shader code are not paired. \n");
- return GL_FALSE;
- }
-
- /* copy max to sub structure */
- pAsm->subs[pAsm->CALLSTACK[pAsm->CALLSP].subDescIndex].unStackDepthMax
- = pAsm->CALLSTACK[pAsm->CALLSP].max;
-
- decreaseCurrent(pAsm, FC_REP);
-
- pAsm->CALLSP--;
- SetActiveCFlist(pAsm->pR700Shader,
- pAsm->CALLSTACK[pAsm->CALLSP].plstCFInstructions_local);
-
- pAsm->alu_x_opcode = SQ_CF_INST_ALU;
-
- pAsm->FCSP--;
-
- return GL_TRUE;
-}
-
-GLboolean assemble_RET(r700_AssemblerBase *pAsm)
-{
- GLuint unIF = 0;
-
- if(pAsm->CALLSP > 0)
- { /* in sub */
- GLuint unFCSP;
- for(unFCSP=pAsm->FCSP; unFCSP>pAsm->CALLSTACK[pAsm->CALLSP].FCSP_BeforeEntry; unFCSP--)
- {
- if(FC_LOOP == pAsm->fc_stack[unFCSP].type)
- {
- setRetInLoopFlag(pAsm, SQ_SEL_1);
- breakLoopOnFlag(pAsm, unFCSP);
- pAsm->unCFflags |= LOOPRET_FLAGS;
-
- return GL_TRUE;
- }
- else if(FC_IF == pAsm->fc_stack[unFCSP].type)
- {
- unIF++;
- }
- }
- }
-
-#ifdef USE_CF_FOR_POP_AFTER
- if(unIF > 0)
- {
- pops(pAsm, unIF);
- }
-#endif /* USE_CF_FOR_POP_AFTER */
-
- add_return_inst(pAsm);
-
- return GL_TRUE;
-}
-
-GLboolean assemble_CAL(r700_AssemblerBase *pAsm,
- GLint nILindex,
- GLuint uiIL_Shift,
- GLuint uiNumberInsts,
- struct prog_instruction *pILInst,
- PRESUB_DESC * pPresubDesc)
-{
- GLint uiIL_Offset;
-
- pAsm->alu_x_opcode = SQ_CF_INST_ALU;
-
- if(GL_FALSE == add_cf_instruction(pAsm) )
- {
- return GL_FALSE;
- }
-
- if(8 == pAsm->unAsic)
- {
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 0,
- EG_CF_WORD1__POP_COUNT_shift, EG_CF_WORD1__POP_COUNT_mask);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- EG_CF_INST_CALL,
- EG_CF_WORD1__CF_INST_shift, EG_CF_WORD1__CF_INST_mask);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 0,
- EG_CF_WORD1__CF_CONST_shift, EG_CF_WORD1__CF_CONST_mask);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- SQ_CF_COND_ACTIVE,
- EG_CF_WORD1__COND_shift, EG_CF_WORD1__COND_mask);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 0,
- EG_CF_WORD1__EOP_shift, EG_CF_WORD1__EOP_bit);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 0,
- EG_CF_WORD1__VPM_shift, EG_CF_WORD1__VPM_bit);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 0,
- EG_CF_WORD1__WQM_shift, EG_CF_WORD1__WQM_bit);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 1,
- EG_CF_WORD1__BARRIER_shift, EG_CF_WORD1__BARRIER_bit);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 1,
- EG_CF_WORD1__COUNT_shift, EG_CF_WORD1__COUNT_mask);
- }
- else
- {
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.call_count = 1;
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.pop_count = 0;
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.cf_const = 0x0;
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.cond = SQ_CF_COND_ACTIVE;
-
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.end_of_program = 0x0;
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.valid_pixel_mode = 0x0;
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.cf_inst = SQ_CF_INST_CALL;
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.whole_quad_mode = 0x0;
-
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.barrier = 0x1;
- }
-
- /* Put in caller */
- if( (pAsm->unCallerArrayPointer + 1) > pAsm->unCallerArraySize )
- {
- pAsm->callers = (CALLER_POINTER*)_mesa_realloc( (void *)pAsm->callers,
- sizeof(CALLER_POINTER) * pAsm->unCallerArraySize,
- sizeof(CALLER_POINTER) * (pAsm->unCallerArraySize + 10) );
- if(NULL == pAsm->callers)
- {
- return GL_FALSE;
- }
- pAsm->unCallerArraySize += 10;
- }
-
- uiIL_Offset = nILindex + uiIL_Shift;
- pAsm->callers[pAsm->unCallerArrayPointer].subIL_Offset = uiIL_Offset;
- pAsm->callers[pAsm->unCallerArrayPointer].cf_ptr = pAsm->cf_current_cf_clause_ptr;
-
- pAsm->callers[pAsm->unCallerArrayPointer].finale_cf_ptr = NULL;
- pAsm->callers[pAsm->unCallerArrayPointer].prelude_cf_ptr = NULL;
-
- pAsm->unCallerArrayPointer++;
-
- int j;
- GLuint max;
- GLuint unSubID;
- GLboolean bRet;
- for(j=0; j<pAsm->unSubArrayPointer; j++)
- {
- if(uiIL_Offset == pAsm->subs[j].subIL_Offset)
- { /* compiled before */
-
- max = pAsm->subs[j].unStackDepthMax
- + pAsm->CALLSTACK[pAsm->CALLSP].current;
- if(max > pAsm->CALLSTACK[pAsm->CALLSP].max)
- {
- pAsm->CALLSTACK[pAsm->CALLSP].max = max;
- }
-
- pAsm->callers[pAsm->unCallerArrayPointer - 1].subDescIndex = j;
- return GL_TRUE;
- }
- }
-
- pAsm->callers[pAsm->unCallerArrayPointer - 1].subDescIndex = pAsm->unSubArrayPointer;
- unSubID = pAsm->unSubArrayPointer;
-
- bRet = AssembleInstr(nILindex, uiIL_Shift, uiNumberInsts, pILInst, pAsm);
-
- if(GL_TRUE == bRet)
- {
- max = pAsm->subs[unSubID].unStackDepthMax
- + pAsm->CALLSTACK[pAsm->CALLSP].current;
- if(max > pAsm->CALLSTACK[pAsm->CALLSP].max)
- {
- pAsm->CALLSTACK[pAsm->CALLSP].max = max;
- }
-
- pAsm->subs[unSubID].pPresubDesc = pPresubDesc;
- }
-
- return bRet;
-}
-
-GLboolean setRetInLoopFlag(r700_AssemblerBase *pAsm, GLuint flagValue)
-{
- /*GLfloat fLiteral[2] = {0.1, 0.0};*/
-
- pAsm->D.dst.opcode = SQ_OP2_INST_MOV;
- pAsm->D.dst.op3 = 0;
- pAsm->D.dst.rtype = DST_REG_TEMPORARY;
- pAsm->D.dst.reg = pAsm->flag_reg_index;
- pAsm->D.dst.writex = 1;
- pAsm->D.dst.writey = 0;
- pAsm->D.dst.writez = 0;
- pAsm->D.dst.writew = 0;
- pAsm->D2.dst2.literal_slots = 1;
- pAsm->D2.dst2.SaturateMode = SATURATE_OFF;
- pAsm->D.dst.predicated = 0;
- /* in reloc where dislink flag init inst, only one slot alu inst is handled. */
- pAsm->D.dst.math = 1; /* TODO : not math really, but one channel op, more generic alu assembler needed */
- pAsm->D2.dst2.index_mode = SQ_INDEX_LOOP; /* Check this ! */
-#if 0
- pAsm->S[0].src.rtype = SRC_REC_LITERAL;
- //pAsm->S[0].src.reg = 0;
- setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE);
- noneg_PVSSRC(&(pAsm->S[0].src));
- pAsm->S[0].src.swizzlex = SQ_SEL_X;
- pAsm->S[0].src.swizzley = SQ_SEL_Y;
- pAsm->S[0].src.swizzlez = SQ_SEL_Z;
- pAsm->S[0].src.swizzlew = SQ_SEL_W;
-
- if( GL_FALSE == next_ins_literal(pAsm, &(fLiteral[0])) )
- {
- return GL_FALSE;
- }
-#else
- pAsm->S[0].src.rtype = DST_REG_TEMPORARY;
- pAsm->S[0].src.reg = 0;
- setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE);
- noneg_PVSSRC(&(pAsm->S[0].src));
- pAsm->S[0].src.swizzlex = flagValue;
- pAsm->S[0].src.swizzley = flagValue;
- pAsm->S[0].src.swizzlez = flagValue;
- pAsm->S[0].src.swizzlew = flagValue;
-
- if( GL_FALSE == next_ins(pAsm) )
- {
- return GL_FALSE;
- }
-#endif
-
- return GL_TRUE;
-}
-
-GLboolean testFlag(r700_AssemblerBase *pAsm)
-{
- /*GLfloat fLiteral[2] = {0.1, 0.0};*/
-
- //Test flag
- GLuint tmp = gethelpr(pAsm);
- pAsm->alu_x_opcode = SQ_CF_INST_ALU_PUSH_BEFORE;
-
- pAsm->D.dst.opcode = SQ_OP2_INST_PRED_SETE;
- pAsm->D.dst.math = 1;
- pAsm->D.dst.rtype = DST_REG_TEMPORARY;
- pAsm->D.dst.reg = tmp;
- pAsm->D.dst.writex = 1;
- pAsm->D.dst.writey = 0;
- pAsm->D.dst.writez = 0;
- pAsm->D.dst.writew = 0;
- pAsm->D2.dst2.literal_slots = 1;
- pAsm->D2.dst2.SaturateMode = SATURATE_OFF;
- pAsm->D.dst.predicated = 1;
- pAsm->D2.dst2.index_mode = SQ_INDEX_LOOP; /* Check this ! */
-
- pAsm->S[0].src.rtype = DST_REG_TEMPORARY;
- pAsm->S[0].src.reg = pAsm->flag_reg_index;
- setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE);
- noneg_PVSSRC(&(pAsm->S[0].src));
- pAsm->S[0].src.swizzlex = SQ_SEL_X;
- pAsm->S[0].src.swizzley = SQ_SEL_Y;
- pAsm->S[0].src.swizzlez = SQ_SEL_Z;
- pAsm->S[0].src.swizzlew = SQ_SEL_W;
-#if 0
- pAsm->S[1].src.rtype = SRC_REC_LITERAL;
- //pAsm->S[1].src.reg = 0;
- setaddrmode_PVSSRC(&(pAsm->S[1].src), ADDR_ABSOLUTE);
- noneg_PVSSRC(&(pAsm->S[1].src));
- pAsm->S[1].src.swizzlex = SQ_SEL_X;
- pAsm->S[1].src.swizzley = SQ_SEL_Y;
- pAsm->S[1].src.swizzlez = SQ_SEL_Z;
- pAsm->S[1].src.swizzlew = SQ_SEL_W;
-
- if( GL_FALSE == next_ins_literal(pAsm, &(fLiteral[0])) )
- {
- return GL_FALSE;
- }
-#else
- pAsm->S[1].src.rtype = DST_REG_TEMPORARY;
- pAsm->S[1].src.reg = 0;
- setaddrmode_PVSSRC(&(pAsm->S[1].src), ADDR_ABSOLUTE);
- noneg_PVSSRC(&(pAsm->S[1].src));
- pAsm->S[1].src.swizzlex = SQ_SEL_1;
- pAsm->S[1].src.swizzley = SQ_SEL_1;
- pAsm->S[1].src.swizzlez = SQ_SEL_1;
- pAsm->S[1].src.swizzlew = SQ_SEL_1;
-
- if( GL_FALSE == next_ins(pAsm) )
- {
- return GL_FALSE;
- }
-#endif
-
- checkStackDepth(pAsm, FC_PUSH_VPM, GL_TRUE);
-
- return GL_TRUE;
-}
-
-GLboolean returnOnFlag(r700_AssemblerBase *pAsm, GLuint unIF)
-{
- testFlag(pAsm);
- jumpToOffest(pAsm, 1, 4);
- setRetInLoopFlag(pAsm, SQ_SEL_0);
- pops(pAsm, unIF + 1);
- add_return_inst(pAsm);
-
- return GL_TRUE;
-}
-
-GLboolean breakLoopOnFlag(r700_AssemblerBase *pAsm, GLuint unFCSP)
-{
- testFlag(pAsm);
-
- //break
- if(GL_FALSE == add_cf_instruction(pAsm) )
- {
- return GL_FALSE;
- }
-
- if(8 == pAsm->unAsic)
- {
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 1,
- EG_CF_WORD1__POP_COUNT_shift, EG_CF_WORD1__POP_COUNT_mask);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- EG_CF_INST_LOOP_BREAK,
- EG_CF_WORD1__CF_INST_shift, EG_CF_WORD1__CF_INST_mask);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 0,
- EG_CF_WORD1__CF_CONST_shift, EG_CF_WORD1__CF_CONST_mask);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- SQ_CF_COND_ACTIVE,
- EG_CF_WORD1__COND_shift, EG_CF_WORD1__COND_mask);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 0,
- EG_CF_WORD1__EOP_shift, EG_CF_WORD1__EOP_bit);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 0,
- EG_CF_WORD1__VPM_shift, EG_CF_WORD1__VPM_bit);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 0,
- EG_CF_WORD1__WQM_shift, EG_CF_WORD1__WQM_bit);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 1,
- EG_CF_WORD1__BARRIER_shift, EG_CF_WORD1__BARRIER_bit);
- SETfield(pAsm->cf_current_cf_clause_ptr->m_Word1.val,
- 1,
- EG_CF_WORD1__COUNT_shift, EG_CF_WORD1__COUNT_mask);
- }
- else
- {
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.pop_count = 1;
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.cf_const = 0x0;
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.cond = SQ_CF_COND_ACTIVE;
-
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.end_of_program = 0x0;
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.valid_pixel_mode = 0x0;
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.cf_inst = SQ_CF_INST_LOOP_BREAK;
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.whole_quad_mode = 0x0;
-
- pAsm->cf_current_cf_clause_ptr->m_Word1.f.barrier = 0x1;
- }
-
- pAsm->fc_stack[unFCSP].mid = (R700ControlFlowGenericClause **)_mesa_realloc(
- (void *)pAsm->fc_stack[unFCSP].mid,
- sizeof(R700ControlFlowGenericClause *) * pAsm->fc_stack[unFCSP].unNumMid,
- sizeof(R700ControlFlowGenericClause *) * (pAsm->fc_stack[unFCSP].unNumMid + 1) );
- pAsm->fc_stack[unFCSP].mid[pAsm->fc_stack[unFCSP].unNumMid] = pAsm->cf_current_cf_clause_ptr;
- pAsm->fc_stack[unFCSP].unNumMid++;
-
- pops(pAsm, 1);
-
- return GL_TRUE;
-}
-
-GLboolean AssembleInstr(GLuint uiFirstInst,
- GLuint uiIL_Shift,
- GLuint uiNumberInsts,
- struct prog_instruction *pILInst,
- r700_AssemblerBase *pR700AsmCode)
-{
- GLuint i;
-
- pR700AsmCode->pILInst = pILInst;
- for(i=uiFirstInst; i<uiNumberInsts; i++)
- {
- pR700AsmCode->uiCurInst = i;
-
-#ifndef USE_CF_FOR_CONTINUE_BREAK
- if(OPCODE_BRK == pILInst[i+1].Opcode)
- {
- switch(pILInst[i].Opcode)
- {
- case OPCODE_SLE:
- pILInst[i].Opcode = OPCODE_SGT;
- break;
- case OPCODE_SLT:
- pILInst[i].Opcode = OPCODE_SGE;
- break;
- case OPCODE_SGE:
- pILInst[i].Opcode = OPCODE_SLT;
- break;
- case OPCODE_SGT:
- pILInst[i].Opcode = OPCODE_SLE;
- break;
- case OPCODE_SEQ:
- pILInst[i].Opcode = OPCODE_SNE;
- break;
- case OPCODE_SNE:
- pILInst[i].Opcode = OPCODE_SEQ;
- break;
- default:
- break;
- }
- }
-#endif
- if(pILInst[i].CondUpdate == 1)
- {
- /* remember dest register used for cond evaluation */
- /* XXX also handle PROGRAM_OUTPUT registers here? */
- pR700AsmCode->last_cond_register = pILInst[i].DstReg.Index;
- }
-
- switch (pILInst[i].Opcode)
- {
- case OPCODE_ABS:
- if ( GL_FALSE == assemble_ABS(pR700AsmCode) )
- return GL_FALSE;
- break;
- case OPCODE_ADD:
- case OPCODE_SUB:
- if ( GL_FALSE == assemble_ADD(pR700AsmCode) )
- return GL_FALSE;
- break;
-
- case OPCODE_ARL:
- if ( GL_FALSE == assemble_ARL(pR700AsmCode) )
- return GL_FALSE;
- break;
- case OPCODE_ARR:
- radeon_error("Not yet implemented instruction OPCODE_ARR \n");
- //if ( GL_FALSE == assemble_BAD("ARR") )
- return GL_FALSE;
- break;
-
- case OPCODE_CMP:
- if ( GL_FALSE == assemble_CMP(pR700AsmCode) )
- return GL_FALSE;
- break;
- case OPCODE_COS:
- if(8 == pR700AsmCode->unAsic)
- {
- if ( GL_FALSE == assemble_TRIG(pR700AsmCode, EG_OP2_INST_COS) )
- return GL_FALSE;
- }
- else
- {
- if ( GL_FALSE == assemble_TRIG(pR700AsmCode, SQ_OP2_INST_COS) )
- return GL_FALSE;
- }
- break;
-
- case OPCODE_DP2:
- case OPCODE_DP3:
- case OPCODE_DP4:
- case OPCODE_DPH:
- if ( GL_FALSE == assemble_DOT(pR700AsmCode) )
- return GL_FALSE;
- break;
-
- case OPCODE_DST:
- if ( GL_FALSE == assemble_DST(pR700AsmCode) )
- return GL_FALSE;
- break;
-
- case OPCODE_EX2:
- if ( GL_FALSE == assemble_EX2(pR700AsmCode) )
- return GL_FALSE;
- break;
- case OPCODE_EXP:
- if ( GL_FALSE == assemble_EXP(pR700AsmCode) )
- return GL_FALSE;
- break;
-
- case OPCODE_FLR:
- if ( GL_FALSE == assemble_FLR(pR700AsmCode) )
- return GL_FALSE;
- break;
- //case OP_FLR_INT: ;
-
- // if ( GL_FALSE == assemble_FLR_INT() )
- // return GL_FALSE;
- // break;
-
- case OPCODE_FRC:
- if ( GL_FALSE == assemble_FRC(pR700AsmCode) )
- return GL_FALSE;
- break;
-
- case OPCODE_KIL:
- case OPCODE_KIL_NV:
- if ( GL_FALSE == assemble_KIL(pR700AsmCode, SQ_OP2_INST_KILLGT) )
- return GL_FALSE;
- break;
- case OPCODE_LG2:
- if ( GL_FALSE == assemble_LG2(pR700AsmCode) )
- return GL_FALSE;
- break;
- case OPCODE_LIT:
- if ( GL_FALSE == assemble_LIT(pR700AsmCode) )
- return GL_FALSE;
- break;
- case OPCODE_LRP:
- if ( GL_FALSE == assemble_LRP(pR700AsmCode) )
- return GL_FALSE;
- break;
- case OPCODE_LOG:
- if ( GL_FALSE == assemble_LOG(pR700AsmCode) )
- return GL_FALSE;
- break;
-
- case OPCODE_MAD:
- if ( GL_FALSE == assemble_MAD(pR700AsmCode) )
- return GL_FALSE;
- break;
- case OPCODE_MAX:
- if ( GL_FALSE == assemble_MAX(pR700AsmCode) )
- return GL_FALSE;
- break;
- case OPCODE_MIN:
- if ( GL_FALSE == assemble_MIN(pR700AsmCode) )
- return GL_FALSE;
- break;
-
- case OPCODE_MOV:
- if ( GL_FALSE == assemble_MOV(pR700AsmCode) )
- return GL_FALSE;
- break;
- case OPCODE_MUL:
- if ( GL_FALSE == assemble_MUL(pR700AsmCode) )
- return GL_FALSE;
- break;
-
- case OPCODE_NOISE1:
- {
- callPreSub(pR700AsmCode,
- GLSL_NOISE1,
- &noise1_presub,
- pILInst->DstReg.Index + pR700AsmCode->starting_temp_register_number,
- 1);
- radeon_error("noise1: not yet supported shader instruction\n");
- };
- break;
- case OPCODE_NOISE2:
- radeon_error("noise2: not yet supported shader instruction\n");
- break;
- case OPCODE_NOISE3:
- radeon_error("noise3: not yet supported shader instruction\n");
- break;
- case OPCODE_NOISE4:
- radeon_error("noise4: not yet supported shader instruction\n");
- break;
-
- case OPCODE_POW:
- if ( GL_FALSE == assemble_POW(pR700AsmCode) )
- return GL_FALSE;
- break;
- case OPCODE_RCP:
- if ( GL_FALSE == assemble_RCP(pR700AsmCode) )
- return GL_FALSE;
- break;
- case OPCODE_RSQ:
- if ( GL_FALSE == assemble_RSQ(pR700AsmCode) )
- return GL_FALSE;
- break;
- case OPCODE_SIN:
- if(8 == pR700AsmCode->unAsic)
- {
- if ( GL_FALSE == assemble_TRIG(pR700AsmCode, EG_OP2_INST_SIN) )
- return GL_FALSE;
- }
- else
- {
- if ( GL_FALSE == assemble_TRIG(pR700AsmCode, SQ_OP2_INST_SIN) )
- return GL_FALSE;
- }
- break;
- case OPCODE_SCS:
- if ( GL_FALSE == assemble_SCS(pR700AsmCode) )
- return GL_FALSE;
- break;
-
- case OPCODE_SEQ:
- if ( GL_FALSE == assemble_LOGIC(pR700AsmCode, SQ_OP2_INST_SETE) )
- {
- return GL_FALSE;
- }
- break;
-
- case OPCODE_SGT:
- if ( GL_FALSE == assemble_LOGIC(pR700AsmCode, SQ_OP2_INST_SETGT) )
- {
- return GL_FALSE;
- }
- break;
-
- case OPCODE_SGE:
- if ( GL_FALSE == assemble_SGE(pR700AsmCode) )
- {
- return GL_FALSE;
- }
- break;
-
- /* NO LT, LE, TODO : use GE => LE, GT => LT : reverse 2 src order would be simpliest. Or use SQ_CF_COND_FALSE for SQ_CF_COND_ACTIVE.*/
- case OPCODE_SLT:
- {
- struct prog_src_register SrcRegSave[2];
- SrcRegSave[0] = pILInst[i].SrcReg[0];
- SrcRegSave[1] = pILInst[i].SrcReg[1];
- pILInst[i].SrcReg[0] = SrcRegSave[1];
- pILInst[i].SrcReg[1] = SrcRegSave[0];
- if ( GL_FALSE == assemble_LOGIC(pR700AsmCode, SQ_OP2_INST_SETGT) )
- {
- pILInst[i].SrcReg[0] = SrcRegSave[0];
- pILInst[i].SrcReg[1] = SrcRegSave[1];
- return GL_FALSE;
- }
- pILInst[i].SrcReg[0] = SrcRegSave[0];
- pILInst[i].SrcReg[1] = SrcRegSave[1];
- }
- break;
-
- case OPCODE_SLE:
- {
- struct prog_src_register SrcRegSave[2];
- SrcRegSave[0] = pILInst[i].SrcReg[0];
- SrcRegSave[1] = pILInst[i].SrcReg[1];
- pILInst[i].SrcReg[0] = SrcRegSave[1];
- pILInst[i].SrcReg[1] = SrcRegSave[0];
- if ( GL_FALSE == assemble_LOGIC(pR700AsmCode, SQ_OP2_INST_SETGE) )
- {
- pILInst[i].SrcReg[0] = SrcRegSave[0];
- pILInst[i].SrcReg[1] = SrcRegSave[1];
- return GL_FALSE;
- }
- pILInst[i].SrcReg[0] = SrcRegSave[0];
- pILInst[i].SrcReg[1] = SrcRegSave[1];
- }
- break;
-
- case OPCODE_SNE:
- if ( GL_FALSE == assemble_LOGIC(pR700AsmCode, SQ_OP2_INST_SETNE) )
- {
- return GL_FALSE;
- }
- break;
-
- //case OP_STP:
- // if ( GL_FALSE == assemble_STP(pR700AsmCode) )
- // return GL_FALSE;
- // break;
-
- case OPCODE_SSG:
- if ( GL_FALSE == assemble_SSG(pR700AsmCode) )
- {
- return GL_FALSE;
- }
- break;
-
- case OPCODE_SWZ:
- if ( GL_FALSE == assemble_MOV(pR700AsmCode) )
- {
- return GL_FALSE;
- }
- else
- {
- if( (i+1)<uiNumberInsts )
- {
- if(OPCODE_END != pILInst[i+1].Opcode)
- {
- if( GL_TRUE == IsTex(pILInst[i+1].Opcode) )
- {
- pR700AsmCode->pInstDeps[i+1].nDstDep = i+1; //=1?
- }
- }
- }
- }
- break;
- case OPCODE_DDX:
- case OPCODE_DDY:
- case OPCODE_TEX:
- case OPCODE_TXB:
- case OPCODE_TXL:
- case OPCODE_TXP:
- if ( GL_FALSE == assemble_TEX(pR700AsmCode) )
- return GL_FALSE;
- break;
-
- case OPCODE_TRUNC:
- if ( GL_FALSE == assemble_math_function(pR700AsmCode, SQ_OP2_INST_TRUNC) )
- return GL_FALSE;
- break;
-
- case OPCODE_XPD:
- if ( GL_FALSE == assemble_XPD(pR700AsmCode) )
- return GL_FALSE;
- break;
-
- case OPCODE_IF:
- {
- GLboolean bHasElse = GL_FALSE;
-
- if(pILInst[pILInst[i].BranchTarget].Opcode == OPCODE_ELSE)
- {
- bHasElse = GL_TRUE;
- }
-
- if ( GL_FALSE == assemble_IF(pR700AsmCode, bHasElse) )
- {
- return GL_FALSE;
- }
- }
- break;
-
- case OPCODE_ELSE :
- if ( GL_FALSE == assemble_ELSE(pR700AsmCode) )
- return GL_FALSE;
- break;
-
- case OPCODE_ENDIF:
- if ( GL_FALSE == assemble_ENDIF(pR700AsmCode) )
- return GL_FALSE;
- break;
-
- case OPCODE_BGNLOOP:
- if( GL_FALSE == assemble_BGNLOOP(pR700AsmCode) )
- {
- return GL_FALSE;
- }
- break;
-
- case OPCODE_BRK:
- if( GL_FALSE == assemble_BRK(pR700AsmCode) )
- {
- return GL_FALSE;
- }
- break;
-
- case OPCODE_CONT:
- if( GL_FALSE == assemble_CONT(pR700AsmCode) )
- {
- return GL_FALSE;
- }
- break;
-
- case OPCODE_ENDLOOP:
- if( GL_FALSE == assemble_ENDLOOP(pR700AsmCode) )
- {
- return GL_FALSE;
- }
- break;
-
- case OPCODE_BGNSUB:
- if( GL_FALSE == assemble_BGNSUB(pR700AsmCode, i, uiIL_Shift) )
- {
- return GL_FALSE;
- }
- break;
-
- case OPCODE_RET:
- if( GL_FALSE == assemble_RET(pR700AsmCode) )
- {
- return GL_FALSE;
- }
- break;
-
- case OPCODE_CAL:
- if( GL_FALSE == assemble_CAL(pR700AsmCode,
- pILInst[i].BranchTarget,
- uiIL_Shift,
- uiNumberInsts,
- pILInst,
- NULL) )
- {
- return GL_FALSE;
- }
- break;
-
- //case OPCODE_EXPORT:
- // if ( GL_FALSE == assemble_EXPORT() )
- // return GL_FALSE;
- // break;
-
- case OPCODE_ENDSUB:
- return assemble_ENDSUB(pR700AsmCode);
-
- case OPCODE_END:
- //pR700AsmCode->uiCurInst = i;
- //This is to remaind that if in later exoort there is depth/stencil
- //export, we need a mov to re-arrange DST channel, where using a
- //psuedo inst, we will use this end inst to do it.
- return GL_TRUE;
-
- default:
- radeon_error("r600: unknown instruction %d\n", pILInst[i].Opcode);
- return GL_FALSE;
- }
- }
-
- return GL_TRUE;
-}
-
-GLboolean InitShaderProgram(r700_AssemblerBase * pAsm)
-{
-#ifndef GENERATE_SHADER_FOR_2D
- setRetInLoopFlag(pAsm, SQ_SEL_0);
-#endif
-
- if((SPT_FP == pAsm->currentShaderType) && (8 == pAsm->unAsic))
- {
- EG_add_ps_interp(pAsm);
- }
-
- pAsm->alu_x_opcode = SQ_CF_INST_ALU;
- return GL_TRUE;
-}
-
-GLboolean RelocProgram(r700_AssemblerBase * pAsm, struct gl_program * pILProg)
-{
- GLuint i;
- GLuint unCFoffset;
- TypedShaderList * plstCFmain;
- TypedShaderList * plstCFsub;
-
- R700ShaderInstruction * pInst;
- R700ControlFlowGenericClause * pCFInst;
-
- R700ControlFlowALUClause * pCF_ALU;
- R700ALUInstruction * pALU;
- GLuint unConstOffset = 0;
- GLuint unRegOffset;
- GLuint unMinRegIndex;
-
- plstCFmain = pAsm->CALLSTACK[0].plstCFInstructions_local;
-
-#ifndef GENERATE_SHADER_FOR_2D
- /* remove flags init if they are not used */
- if((pAsm->unCFflags & HAS_LOOPRET) == 0)
- {
- R700ControlFlowALUClause * pCF_ALU;
- pInst = plstCFmain->pHead;
- while(pInst)
- {
- if(SIT_CF_ALU == pInst->m_ShaderInstType)
- {
- pCF_ALU = (R700ControlFlowALUClause *)pInst;
- if(0 == pCF_ALU->m_Word1.f.count)
- {
- pCF_ALU->m_Word1.f.cf_inst = SQ_CF_INST_NOP;
- }
- else
- {
- R700ALUInstruction * pALU = pCF_ALU->m_pLinkedALUInstruction;
-
- pALU->m_pLinkedALUClause = NULL;
- pALU = (R700ALUInstruction *)(pALU->pNextInst);
- pALU->m_pLinkedALUClause = pCF_ALU;
- pCF_ALU->m_pLinkedALUInstruction = pALU;
-
- pCF_ALU->m_Word1.f.count--;
- }
- break;
- }
- pInst = pInst->pNextInst;
- };
- }
-#endif /* GENERATE_SHADER_FOR_2D */
-
- if(pAsm->CALLSTACK[0].max > 0)
- {
- pAsm->pR700Shader->uStackSize = ((pAsm->CALLSTACK[0].max + 3)>>2) + 2;
- }
-
- if(0 == pAsm->unSubArrayPointer)
- {
- return GL_TRUE;
- }
-
- unCFoffset = plstCFmain->uNumOfNode;
-
- if(NULL != pILProg->Parameters)
- {
- unConstOffset = pILProg->Parameters->NumParameters;
- }
-
- /* Reloc subs */
- for(i=0; i<pAsm->unSubArrayPointer; i++)
- {
- pAsm->subs[i].unCFoffset = unCFoffset;
- plstCFsub = &(pAsm->subs[i].lstCFInstructions_local);
-
- pInst = plstCFsub->pHead;
-
- /* reloc instructions */
- while(pInst)
- {
- if(SIT_CF_GENERIC == pInst->m_ShaderInstType)
- {
- pCFInst = (R700ControlFlowGenericClause *)pInst;
-
- switch (pCFInst->m_Word1.f.cf_inst)
- {
- case SQ_CF_INST_POP:
- case SQ_CF_INST_JUMP:
- case SQ_CF_INST_ELSE:
- case SQ_CF_INST_LOOP_END:
- case SQ_CF_INST_LOOP_START:
- case SQ_CF_INST_LOOP_START_NO_AL:
- case SQ_CF_INST_LOOP_CONTINUE:
- case SQ_CF_INST_LOOP_BREAK:
- pCFInst->m_Word0.f.addr += unCFoffset;
- break;
- default:
- break;
- }
- }
-
- pInst->m_uIndex += unCFoffset;
-
- pInst = pInst->pNextInst;
- };
-
- if(NULL != pAsm->subs[i].pPresubDesc)
- {
- GLuint uNumSrc;
-
- unMinRegIndex = pAsm->subs[i].pPresubDesc->pCompiledSub->MinRegIndex;
- unRegOffset = pAsm->subs[i].pPresubDesc->maxStartReg;
- unConstOffset += pAsm->subs[i].pPresubDesc->unConstantsStart;
-
- pInst = plstCFsub->pHead;
- while(pInst)
- {
- if(SIT_CF_ALU == pInst->m_ShaderInstType)
- {
- pCF_ALU = (R700ControlFlowALUClause *)pInst;
-
- pALU = pCF_ALU->m_pLinkedALUInstruction;
- for(int j=0; j<=pCF_ALU->m_Word1.f.count; j++)
- {
- pALU->m_Word1.f.dst_gpr = pALU->m_Word1.f.dst_gpr + unRegOffset - unMinRegIndex;
-
- if(pALU->m_Word0.f.src0_sel < SQ_ALU_SRC_GPR_SIZE)
- {
- pALU->m_Word0.f.src0_sel = pALU->m_Word0.f.src0_sel + unRegOffset - unMinRegIndex;
- }
- else if(pALU->m_Word0.f.src0_sel >= SQ_ALU_SRC_CFILE_BASE)
- {
- pALU->m_Word0.f.src0_sel += unConstOffset;
- }
-
- if( ((pALU->m_Word1.val >> SQ_ALU_WORD1_OP3_ALU_INST_SHIFT) & 0x0000001F)
- >= SQ_OP3_INST_MUL_LIT )
- { /* op3 : 3 srcs */
- if(pALU->m_Word1_OP3.f.src2_sel < SQ_ALU_SRC_GPR_SIZE)
- {
- pALU->m_Word1_OP3.f.src2_sel = pALU->m_Word1_OP3.f.src2_sel + unRegOffset - unMinRegIndex;
- }
- else if(pALU->m_Word1_OP3.f.src2_sel >= SQ_ALU_SRC_CFILE_BASE)
- {
- pALU->m_Word1_OP3.f.src2_sel += unConstOffset;
- }
- if(pALU->m_Word0.f.src1_sel < SQ_ALU_SRC_GPR_SIZE)
- {
- pALU->m_Word0.f.src1_sel = pALU->m_Word0.f.src1_sel + unRegOffset - unMinRegIndex;
- }
- else if(pALU->m_Word0.f.src1_sel >= SQ_ALU_SRC_CFILE_BASE)
- {
- pALU->m_Word0.f.src1_sel += unConstOffset;
- }
- }
- else
- {
- if(8 == pAsm->unAsic)
- {
- uNumSrc = EG_GetNumOperands(pALU->m_Word1_OP2.f.alu_inst, 0);
- }
- else
- {
- if(pAsm->bR6xx)
- {
- uNumSrc = r700GetNumOperands(pALU->m_Word1_OP2.f6.alu_inst, 0);
- }
- else
- {
- uNumSrc = r700GetNumOperands(pALU->m_Word1_OP2.f.alu_inst, 0);
- }
- }
- if(2 == uNumSrc)
- { /* 2 srcs */
- if(pALU->m_Word0.f.src1_sel < SQ_ALU_SRC_GPR_SIZE)
- {
- pALU->m_Word0.f.src1_sel = pALU->m_Word0.f.src1_sel + unRegOffset - unMinRegIndex;
- }
- else if(pALU->m_Word0.f.src1_sel >= SQ_ALU_SRC_CFILE_BASE)
- {
- pALU->m_Word0.f.src1_sel += unConstOffset;
- }
- }
- }
- pALU = (R700ALUInstruction*)(pALU->pNextInst);
- }
- }
- pInst = pInst->pNextInst;
- };
- }
-
- /* Put sub into main */
- plstCFmain->pTail->pNextInst = plstCFsub->pHead;
- plstCFmain->pTail = plstCFsub->pTail;
- plstCFmain->uNumOfNode += plstCFsub->uNumOfNode;
-
- unCFoffset += plstCFsub->uNumOfNode;
- }
-
- /* reloc callers */
- for(i=0; i<pAsm->unCallerArrayPointer; i++)
- {
- pAsm->callers[i].cf_ptr->m_Word0.f.addr
- = pAsm->subs[pAsm->callers[i].subDescIndex].unCFoffset;
-
- if(NULL != pAsm->subs[pAsm->callers[i].subDescIndex].pPresubDesc)
- {
- unMinRegIndex = pAsm->subs[pAsm->callers[i].subDescIndex].pPresubDesc->pCompiledSub->MinRegIndex;
- unRegOffset = pAsm->subs[pAsm->callers[i].subDescIndex].pPresubDesc->maxStartReg;
-
- if(NULL != pAsm->callers[i].prelude_cf_ptr)
- {
- pCF_ALU = (R700ControlFlowALUClause * )(pAsm->callers[i].prelude_cf_ptr);
- pALU = pCF_ALU->m_pLinkedALUInstruction;
- for(int j=0; j<=pCF_ALU->m_Word1.f.count; j++)
- {
- pALU->m_Word1.f.dst_gpr = pALU->m_Word1.f.dst_gpr + unRegOffset - unMinRegIndex;
- pALU = (R700ALUInstruction*)(pALU->pNextInst);
- }
- }
- if(NULL != pAsm->callers[i].finale_cf_ptr)
- {
- pCF_ALU = (R700ControlFlowALUClause * )(pAsm->callers[i].finale_cf_ptr);
- pALU = pCF_ALU->m_pLinkedALUInstruction;
- for(int j=0; j<=pCF_ALU->m_Word1.f.count; j++)
- {
- pALU->m_Word0.f.src0_sel = pALU->m_Word0.f.src0_sel + unRegOffset - unMinRegIndex;
- pALU = (R700ALUInstruction*)(pALU->pNextInst);
- }
- }
- }
- }
-
- return GL_TRUE;
-}
-
-GLboolean callPreSub(r700_AssemblerBase* pAsm,
- LOADABLE_SCRIPT_SIGNITURE scriptSigniture,
- COMPILED_SUB * pCompiledSub,
- GLshort uOutReg,
- GLshort uNumValidSrc)
-{
- /* save assemble context */
- GLuint starting_temp_register_number_save;
- GLuint number_used_registers_save;
- GLuint uFirstHelpReg_save;
- GLuint uHelpReg_save;
- GLuint uiCurInst_save;
- struct prog_instruction *pILInst_save;
- PRESUB_DESC * pPresubDesc;
- GLboolean bRet;
- int i;
-
- R700ControlFlowGenericClause* prelude_cf_ptr = NULL;
-
- /* copy srcs to presub inputs */
- pAsm->alu_x_opcode = SQ_CF_INST_ALU;
- for(i=0; i<uNumValidSrc; i++)
- {
- pAsm->D.dst.opcode = SQ_OP2_INST_MOV;
- setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE);
- pAsm->D.dst.rtype = DST_REG_TEMPORARY;
- pAsm->D.dst.reg = pCompiledSub->srcRegIndex[i];
- pAsm->D.dst.writex = 1;
- pAsm->D.dst.writey = 1;
- pAsm->D.dst.writez = 1;
- pAsm->D.dst.writew = 1;
-
- if( GL_FALSE == assemble_src(pAsm, i, 0) )
- {
- return GL_FALSE;
- }
-
- next_ins(pAsm);
- }
- if(uNumValidSrc > 0)
- {
- prelude_cf_ptr = (R700ControlFlowGenericClause*) pAsm->cf_current_alu_clause_ptr;
- pAsm->alu_x_opcode = SQ_CF_INST_ALU;
- }
-
- /* browse thro existing presubs. */
- for(i=0; i<pAsm->unNumPresub; i++)
- {
- if(pAsm->presubs[i].sptSigniture == scriptSigniture)
- {
- break;
- }
- }
-
- if(i == pAsm->unNumPresub)
- { /* not loaded yet */
- /* save assemble context */
- number_used_registers_save = pAsm->number_used_registers;
- uFirstHelpReg_save = pAsm->uFirstHelpReg;
- uHelpReg_save = pAsm->uHelpReg;
- starting_temp_register_number_save = pAsm->starting_temp_register_number;
- pILInst_save = pAsm->pILInst;
- uiCurInst_save = pAsm->uiCurInst;
-
- /* alloc in presub */
- if( (pAsm->unNumPresub + 1) > pAsm->unPresubArraySize )
- {
- pAsm->presubs = (PRESUB_DESC*)_mesa_realloc( (void *)pAsm->presubs,
- sizeof(PRESUB_DESC) * pAsm->unPresubArraySize,
- sizeof(PRESUB_DESC) * (pAsm->unPresubArraySize + 4) );
- if(NULL == pAsm->presubs)
- {
- radeon_error("No memeory to allocate built in shader function description structures. \n");
- return GL_FALSE;
- }
- pAsm->unPresubArraySize += 4;
- }
-
- pPresubDesc = &(pAsm->presubs[i]);
- pPresubDesc->sptSigniture = scriptSigniture;
-
- /* constants offsets need to be final resolved at reloc. */
- if(0 == pAsm->unNumPresub)
- {
- pPresubDesc->unConstantsStart = 0;
- }
- else
- {
- pPresubDesc->unConstantsStart = pAsm->presubs[i-1].unConstantsStart
- + pAsm->presubs[i-1].pCompiledSub->NumParameters;
- }
-
- pPresubDesc->pCompiledSub = pCompiledSub;
-
- pPresubDesc->subIL_Shift = pAsm->unCurNumILInsts;
- pPresubDesc->maxStartReg = uFirstHelpReg_save;
- pAsm->unCurNumILInsts += pCompiledSub->NumInstructions;
-
- pAsm->unNumPresub++;
-
- /* setup new assemble context */
- pAsm->starting_temp_register_number = 0;
- pAsm->number_used_registers = pCompiledSub->NumTemporaries;
- pAsm->uFirstHelpReg = pAsm->number_used_registers;
- pAsm->uHelpReg = pAsm->uFirstHelpReg;
-
- bRet = assemble_CAL(pAsm,
- 0,
- pPresubDesc->subIL_Shift,
- pCompiledSub->NumInstructions,
- pCompiledSub->Instructions,
- pPresubDesc);
-
-
- pPresubDesc->number_used_registers = pAsm->number_used_registers;
-
- /* restore assemble context */
- pAsm->number_used_registers = number_used_registers_save;
- pAsm->uFirstHelpReg = uFirstHelpReg_save;
- pAsm->uHelpReg = uHelpReg_save;
- pAsm->starting_temp_register_number = starting_temp_register_number_save;
- pAsm->pILInst = pILInst_save;
- pAsm->uiCurInst = uiCurInst_save;
- }
- else
- { /* was loaded */
- pPresubDesc = &(pAsm->presubs[i]);
-
- bRet = assemble_CAL(pAsm,
- 0,
- pPresubDesc->subIL_Shift,
- pCompiledSub->NumInstructions,
- pCompiledSub->Instructions,
- pPresubDesc);
- }
-
- if(GL_FALSE == bRet)
- {
- radeon_error("Shader presub assemble failed. \n");
- }
- else
- {
- /* copy presub output to real dst */
- pAsm->alu_x_opcode = SQ_CF_INST_ALU;
- pAsm->D.dst.opcode = SQ_OP2_INST_MOV;
-
- if( GL_FALSE == assemble_dst(pAsm) )
- {
- return GL_FALSE;
- }
-
- setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE);
- pAsm->S[0].src.rtype = SRC_REG_TEMPORARY;
- pAsm->S[0].src.reg = pCompiledSub->dstRegIndex;
- pAsm->S[0].src.swizzlex = pCompiledSub->outputSwizzleX;
- pAsm->S[0].src.swizzley = pCompiledSub->outputSwizzleY;
- pAsm->S[0].src.swizzlez = pCompiledSub->outputSwizzleZ;
- pAsm->S[0].src.swizzlew = pCompiledSub->outputSwizzleW;
-
- next_ins(pAsm);
-
- pAsm->callers[pAsm->unCallerArrayPointer - 1].finale_cf_ptr = (R700ControlFlowGenericClause*) pAsm->cf_current_alu_clause_ptr;
- pAsm->callers[pAsm->unCallerArrayPointer - 1].prelude_cf_ptr = prelude_cf_ptr;
- pAsm->alu_x_opcode = SQ_CF_INST_ALU;
- }
-
- if( (pPresubDesc->number_used_registers + pAsm->uFirstHelpReg) > pAsm->number_used_registers )
- {
- pAsm->number_used_registers = pPresubDesc->number_used_registers + pAsm->uFirstHelpReg;
- }
- if(pAsm->uFirstHelpReg > pPresubDesc->maxStartReg)
- {
- pPresubDesc->maxStartReg = pAsm->uFirstHelpReg;
- }
-
- return bRet;
-}
-
-GLboolean Process_Export(r700_AssemblerBase* pAsm,
- GLuint type,
- GLuint export_starting_index,
- GLuint export_count,
- GLuint starting_register_number,
- GLboolean is_depth_export)
-{
- check_current_clause(pAsm, CF_EMPTY_CLAUSE);
- check_current_clause(pAsm, CF_EXPORT_CLAUSE); //alloc the cf_current_export_clause_ptr
-
- pAsm->cf_current_export_clause_ptr->m_Word0.f.type = type;
-
- switch (type)
- {
- case SQ_EXPORT_PIXEL:
- if(GL_TRUE == is_depth_export)
- {
- pAsm->cf_current_export_clause_ptr->m_Word0.f.array_base = SQ_CF_PIXEL_Z;
- }
- else
- {
- pAsm->cf_current_export_clause_ptr->m_Word0.f.array_base = SQ_CF_PIXEL_MRT0 + export_starting_index;
- }
- break;
-
- case SQ_EXPORT_POS:
- pAsm->cf_current_export_clause_ptr->m_Word0.f.array_base = SQ_CF_POS_0 + export_starting_index;
- break;
-
- case SQ_EXPORT_PARAM:
- pAsm->cf_current_export_clause_ptr->m_Word0.f.array_base = 0x0 + export_starting_index;
- break;
-
- default:
- radeon_error("Unknown export type: %d\n", type);
- return GL_FALSE;
- break;
- }
-
- pAsm->cf_current_export_clause_ptr->m_Word0.f.rw_gpr = starting_register_number;
-
- pAsm->cf_current_export_clause_ptr->m_Word0.f.rw_rel = SQ_ABSOLUTE;
- pAsm->cf_current_export_clause_ptr->m_Word0.f.index_gpr = 0x0;
- pAsm->cf_current_export_clause_ptr->m_Word0.f.elem_size = 0x3;
-
- if(8 == pAsm->unAsic)
- {
- SETfield(pAsm->cf_current_export_clause_ptr->m_Word1.val,
- (export_count - 1),
- EG_CF_ALLOC_EXPORT_WORD1__BURST_COUNT_shift,
- EG_CF_ALLOC_EXPORT_WORD1__BURST_COUNT_mask);
- SETfield(pAsm->cf_current_export_clause_ptr->m_Word1.val,
- 0,
- EG_CF_ALLOC_EXPORT_WORD1__EOP_shift,
- EG_CF_ALLOC_EXPORT_WORD1__EOP_bit);
- SETfield(pAsm->cf_current_export_clause_ptr->m_Word1.val,
- 0,
- EG_CF_ALLOC_EXPORT_WORD1__VPM_shift,
- EG_CF_ALLOC_EXPORT_WORD1__VPM_bit);
- SETfield(pAsm->cf_current_export_clause_ptr->m_Word1.val,
- EG_CF_INST_EXPORT,
- EG_CF_WORD1__CF_INST_shift,
- EG_CF_WORD1__CF_INST_mask);
- SETfield(pAsm->cf_current_export_clause_ptr->m_Word1.val,
- 0,
- EG_CF_ALLOC_EXPORT_WORD1__MARK_shift,
- EG_CF_ALLOC_EXPORT_WORD1__MARK_bit);
- SETfield(pAsm->cf_current_export_clause_ptr->m_Word1.val,
- 1,
- EG_CF_ALLOC_EXPORT_WORD1__BARRIER_shift,
- EG_CF_ALLOC_EXPORT_WORD1__BARRIER_bit);
- }
- else
- {
- pAsm->cf_current_export_clause_ptr->m_Word1.f.burst_count = (export_count - 1);
- pAsm->cf_current_export_clause_ptr->m_Word1.f.end_of_program = 0x0;
- pAsm->cf_current_export_clause_ptr->m_Word1.f.valid_pixel_mode = 0x0;
- pAsm->cf_current_export_clause_ptr->m_Word1.f.cf_inst = SQ_CF_INST_EXPORT; // _DONE
- pAsm->cf_current_export_clause_ptr->m_Word1.f.whole_quad_mode = 0x0;
- pAsm->cf_current_export_clause_ptr->m_Word1.f.barrier = 0x1;
- }
-
- if (export_count == 1)
- {
- assert(starting_register_number >= pAsm->starting_export_register_number);
-
- /* exports Z as a float into Red channel */
- if (GL_TRUE == is_depth_export)
- {
- pAsm->cf_current_export_clause_ptr->m_Word1_SWIZ.f.sel_x = SQ_SEL_Z;
- pAsm->cf_current_export_clause_ptr->m_Word1_SWIZ.f.sel_y = SQ_SEL_MASK;
- pAsm->cf_current_export_clause_ptr->m_Word1_SWIZ.f.sel_z = SQ_SEL_MASK;
- pAsm->cf_current_export_clause_ptr->m_Word1_SWIZ.f.sel_w = SQ_SEL_MASK;
- }
- else
- {
- pAsm->cf_current_export_clause_ptr->m_Word1_SWIZ.f.sel_x = SQ_SEL_X;
- pAsm->cf_current_export_clause_ptr->m_Word1_SWIZ.f.sel_y = SQ_SEL_Y;
- pAsm->cf_current_export_clause_ptr->m_Word1_SWIZ.f.sel_z = SQ_SEL_Z;
- pAsm->cf_current_export_clause_ptr->m_Word1_SWIZ.f.sel_w = SQ_SEL_W;
- }
- }
- else
- {
- // This should only be used if all components for all registers have been written
- pAsm->cf_current_export_clause_ptr->m_Word1_SWIZ.f.sel_x = SQ_SEL_X;
- pAsm->cf_current_export_clause_ptr->m_Word1_SWIZ.f.sel_y = SQ_SEL_Y;
- pAsm->cf_current_export_clause_ptr->m_Word1_SWIZ.f.sel_z = SQ_SEL_Z;
- pAsm->cf_current_export_clause_ptr->m_Word1_SWIZ.f.sel_w = SQ_SEL_W;
- }
-
- pAsm->cf_last_export_ptr = pAsm->cf_current_export_clause_ptr;
-
- return GL_TRUE;
-}
-
-GLboolean Process_Fragment_Exports(r700_AssemblerBase *pR700AsmCode,
- GLbitfield OutputsWritten)
-{
- unsigned int unBit;
- GLuint export_count = 0;
- unsigned int i;
-
- for (i = 0; i < FRAG_RESULT_MAX; ++i)
- {
- unBit = 1 << i;
-
- if (OutputsWritten & unBit)
- {
- GLboolean is_depth = i == FRAG_RESULT_DEPTH ? GL_TRUE : GL_FALSE;
- if (!Process_Export(pR700AsmCode, SQ_EXPORT_PIXEL, 0, 1, pR700AsmCode->uiFP_OutputMap[i], is_depth))
- return GL_FALSE;
- ++export_count;
- }
- }
-
- /* Need to export something, otherwise we'll hang
- * results are undefined anyway */
- if(export_count == 0)
- {
- Process_Export(pR700AsmCode, SQ_EXPORT_PIXEL, 0, 1, pR700AsmCode->starting_export_register_number, GL_FALSE);
- }
-
- if(pR700AsmCode->cf_last_export_ptr != NULL)
- {
- if(8 == pR700AsmCode->unAsic)
- {
- SETfield(pR700AsmCode->cf_last_export_ptr->m_Word1.val,
- 1,
- EG_CF_ALLOC_EXPORT_WORD1__EOP_shift,
- EG_CF_ALLOC_EXPORT_WORD1__EOP_bit);
- SETfield(pR700AsmCode->cf_last_export_ptr->m_Word1.val,
- EG_CF_INST_EXPORT_DONE,
- EG_CF_WORD1__CF_INST_shift,
- EG_CF_WORD1__CF_INST_mask);
- }
- else
- {
- pR700AsmCode->cf_last_export_ptr->m_Word1.f.cf_inst = SQ_CF_INST_EXPORT_DONE;
- pR700AsmCode->cf_last_export_ptr->m_Word1.f.end_of_program = 0x1;
- }
- }
-
- return GL_TRUE;
-}
-
-GLboolean Process_Vertex_Exports(r700_AssemblerBase *pR700AsmCode,
- GLbitfield OutputsWritten)
-{
- unsigned int unBit;
- unsigned int i;
-
- GLuint export_starting_index = 0;
- GLuint export_count = pR700AsmCode->number_of_exports;
-
- unBit = 1 << VERT_RESULT_HPOS;
- if(OutputsWritten & unBit)
- {
- if( GL_FALSE == Process_Export(pR700AsmCode,
- SQ_EXPORT_POS,
- export_starting_index,
- 1,
- pR700AsmCode->ucVP_OutputMap[VERT_RESULT_HPOS],
- GL_FALSE) )
- {
- return GL_FALSE;
- }
- export_starting_index++;
- export_count--;
- }
-
- unBit = 1 << VERT_RESULT_PSIZ;
- if(OutputsWritten & unBit)
- {
- if( GL_FALSE == Process_Export(pR700AsmCode,
- SQ_EXPORT_POS,
- export_starting_index,
- 1,
- pR700AsmCode->ucVP_OutputMap[VERT_RESULT_PSIZ],
- GL_FALSE) )
- {
- return GL_FALSE;
- }
- export_count--;
- }
-
- if(8 == pR700AsmCode->unAsic)
- {
- SETfield(pR700AsmCode->cf_last_export_ptr->m_Word1.val,
- EG_CF_INST_EXPORT_DONE,
- EG_CF_WORD1__CF_INST_shift,
- EG_CF_WORD1__CF_INST_mask);
- }
- else
- {
- pR700AsmCode->cf_last_export_ptr->m_Word1.f.cf_inst = SQ_CF_INST_EXPORT_DONE;
- }
-
-
- pR700AsmCode->number_of_exports = export_count;
- export_starting_index = 0;
-
- unBit = 1 << VERT_RESULT_COL0;
- if(OutputsWritten & unBit)
- {
- if( GL_FALSE == Process_Export(pR700AsmCode,
- SQ_EXPORT_PARAM,
- export_starting_index,
- 1,
- pR700AsmCode->ucVP_OutputMap[VERT_RESULT_COL0],
- GL_FALSE) )
- {
- return GL_FALSE;
- }
-
- export_starting_index++;
- }
-
- unBit = 1 << VERT_RESULT_COL1;
- if(OutputsWritten & unBit)
- {
- if( GL_FALSE == Process_Export(pR700AsmCode,
- SQ_EXPORT_PARAM,
- export_starting_index,
- 1,
- pR700AsmCode->ucVP_OutputMap[VERT_RESULT_COL1],
- GL_FALSE) )
- {
- return GL_FALSE;
- }
-
- export_starting_index++;
- }
-
- unBit = 1 << VERT_RESULT_FOGC;
- if(OutputsWritten & unBit)
- {
- if( GL_FALSE == Process_Export(pR700AsmCode,
- SQ_EXPORT_PARAM,
- export_starting_index,
- 1,
- pR700AsmCode->ucVP_OutputMap[VERT_RESULT_FOGC],
- GL_FALSE) )
- {
- return GL_FALSE;
- }
-
- export_starting_index++;
- }
-
- for(i=0; i<8; i++)
- {
- unBit = 1 << (VERT_RESULT_TEX0 + i);
- if(OutputsWritten & unBit)
- {
- if( GL_FALSE == Process_Export(pR700AsmCode,
- SQ_EXPORT_PARAM,
- export_starting_index,
- 1,
- pR700AsmCode->ucVP_OutputMap[VERT_RESULT_TEX0 + i],
- GL_FALSE) )
- {
- return GL_FALSE;
- }
-
- export_starting_index++;
- }
- }
-
- for(i=VERT_RESULT_VAR0; i<VERT_RESULT_MAX; i++)
- {
- unBit = 1 << i;
- if(OutputsWritten & unBit)
- {
- if( GL_FALSE == Process_Export(pR700AsmCode,
- SQ_EXPORT_PARAM,
- export_starting_index,
- 1,
- pR700AsmCode->ucVP_OutputMap[i],
- GL_FALSE) )
- {
- return GL_FALSE;
- }
-
- export_starting_index++;
- }
- }
-
- // At least one param should be exported
- if (export_count)
- {
- if(8 == pR700AsmCode->unAsic)
- {
- SETfield(pR700AsmCode->cf_last_export_ptr->m_Word1.val,
- EG_CF_INST_EXPORT_DONE,
- EG_CF_WORD1__CF_INST_shift,
- EG_CF_WORD1__CF_INST_mask);
- }
- else
- {
- pR700AsmCode->cf_last_export_ptr->m_Word1.f.cf_inst = SQ_CF_INST_EXPORT_DONE;
- }
- }
- else
- {
- if( GL_FALSE == Process_Export(pR700AsmCode,
- SQ_EXPORT_PARAM,
- 0,
- 1,
- pR700AsmCode->starting_export_register_number,
- GL_FALSE) )
- {
- return GL_FALSE;
- }
-
- pR700AsmCode->cf_last_export_ptr->m_Word1_SWIZ.f.sel_x = SQ_SEL_0;
- pR700AsmCode->cf_last_export_ptr->m_Word1_SWIZ.f.sel_y = SQ_SEL_0;
- pR700AsmCode->cf_last_export_ptr->m_Word1_SWIZ.f.sel_z = SQ_SEL_0;
- pR700AsmCode->cf_last_export_ptr->m_Word1_SWIZ.f.sel_w = SQ_SEL_1;
- if(8 == pR700AsmCode->unAsic)
- {
- SETfield(pR700AsmCode->cf_last_export_ptr->m_Word1.val,
- EG_CF_INST_EXPORT_DONE,
- EG_CF_WORD1__CF_INST_shift,
- EG_CF_WORD1__CF_INST_mask);
- }
- else
- {
- pR700AsmCode->cf_last_export_ptr->m_Word1.f.cf_inst = SQ_CF_INST_EXPORT_DONE;
- }
- }
-
- pR700AsmCode->cf_last_export_ptr->m_Word1.f.end_of_program = 0x1;
-
- return GL_TRUE;
-}
-
-GLboolean Clean_Up_Assembler(r700_AssemblerBase *pR700AsmCode)
-{
- if(NULL != pR700AsmCode->pInstDeps)
- {
- FREE(pR700AsmCode->pInstDeps);
- pR700AsmCode->pInstDeps = NULL;
- }
-
- if(NULL != pR700AsmCode->subs)
- {
- FREE(pR700AsmCode->subs);
- pR700AsmCode->subs = NULL;
- }
- if(NULL != pR700AsmCode->callers)
- {
- FREE(pR700AsmCode->callers);
- pR700AsmCode->callers = NULL;
- }
-
- if(NULL != pR700AsmCode->presubs)
- {
- FREE(pR700AsmCode->presubs);
- pR700AsmCode->presubs = NULL;
- }
-
- return GL_TRUE;
-}
-
+++ /dev/null
-/*
- * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Authors:
- * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
- */
-
-#ifndef _R700_ASSEMBLER_H_
-#define _R700_ASSEMBLER_H_
-
-#include "main/mtypes.h"
-#include "program/prog_instruction.h"
-
-#include "r700_chip.h"
-#include "r700_shaderinst.h"
-#include "r700_shader.h"
-
-typedef enum LOADABLE_SCRIPT_SIGNITURE
-{
- GLSL_NOISE1 = 0x10000001,
- GLSL_NOISE2 = 0x10000002,
- GLSL_NOISE3 = 0x10000003,
- GLSL_NOISE4 = 0x10000004
-}LOADABLE_SCRIPT_SIGNITURE;
-
-typedef struct COMPILED_SUB
-{
- struct prog_instruction *Instructions;
- GLuint NumInstructions;
- GLuint NumTemporaries;
- GLuint NumParameters;
- GLuint MinRegIndex;
- GLfloat (*ParameterValues)[4];
- GLbyte outputSwizzleX;
- GLbyte outputSwizzleY;
- GLbyte outputSwizzleZ;
- GLbyte outputSwizzleW;
- GLshort srcRegIndex[3];
- GLushort dstRegIndex;
-}COMPILED_SUB;
-
-typedef struct PRESUB_DESCtag
-{
- LOADABLE_SCRIPT_SIGNITURE sptSigniture;
- GLint subIL_Shift;
- struct prog_src_register InReg[3];
- struct prog_dst_register OutReg;
-
- GLushort maxStartReg;
- GLushort number_used_registers;
-
- GLuint unConstantsStart;
-
- COMPILED_SUB * pCompiledSub;
-} PRESUB_DESC;
-
-typedef enum SHADER_PIPE_TYPE
-{
- SPT_VP = 0,
- SPT_FP = 1
-} SHADER_PIPE_TYPE;
-
-typedef enum ConstantCycles
-{
- NUMBER_OF_CYCLES = 3,
- NUMBER_OF_COMPONENTS = 4
-} ConstantCycles;
-
-typedef enum HARDWARE_LIMIT_VALUES
-{
- TEMPORARY_REGISTER_OFFSET = SQ_ALU_SRC_GPR_BASE,
- MAX_TEMPORARY_REGISTERS = SQ_ALU_SRC_GPR_SIZE,
- MAX_CONSTANT_REGISTERS = SQ_ALU_SRC_CFILE_SIZE,
- CFILE_REGISTER_OFFSET = SQ_ALU_SRC_CFILE_BASE,
- NUMBER_OF_INPUT_COLORS = 2,
- NUMBER_OF_OUTPUT_COLORS = 8,
- NUMBER_OF_TEXTURE_UNITS = 16,
- MEGA_FETCH_BYTES = 32
-} HARDWARE_LIMIT_VALUES;
-
-typedef enum AddressMode
-{
- ADDR_ABSOLUTE = 0,
- ADDR_RELATIVE_A0 = 1,
- ADDR_RELATIVE_FLI_0 = 2,
- NUMBER_OF_ADDR_MOD = 3
-} AddressMode;
-
-typedef enum SrcRegisterType
-{
- SRC_REG_TEMPORARY = 0,
- SRC_REG_GPR = 1,
- SRC_REG_CONSTANT = 2,
- SRC_REG_ALT_TEMPORARY = 3,
- SRC_REC_LITERAL = 4,
- NUMBER_OF_SRC_REG_TYPE = 5
-} SrcRegisterType;
-
-typedef enum DstRegisterType
-{
- DST_REG_TEMPORARY = 0,
- DST_REG_A0 = 1,
- DST_REG_OUT = 2,
- DST_REG_OUT_X_REPL = 3,
- DST_REG_ALT_TEMPORARY = 4,
- DST_REG_INPUT = 5,
- NUMBER_OF_DST_REG_TYPE = 6
-} DstRegisterType;
-
-typedef unsigned int BITS;
-
-typedef struct PVSDSTtag
-{
-#ifdef MESA_BIG_ENDIAN
- BITS addrmode1:1; //32
- BITS addrmode0:1; //31 //29
-
- BITS dualop:1; // 30 //26
-
- BITS op3:1; // 29 Represents *_OP3_* ALU opcode
-
- BITS writew:1; //28
- BITS writez:1;
- BITS writey:1;
- BITS writex:1;
-
- BITS reg:10; //24 //20
- BITS rtype:3;
-
- BITS pred_inv :1; //11 //8
- BITS predicated:1; //10 //8
- BITS math:1;
- BITS opcode:8; //(:6) //@@@ really should be 10 bits for OP2
-#else
- BITS opcode:8; //(:6) //@@@ really should be 10 bits for OP2
- BITS math:1;
- BITS predicated:1; //10 //8
- BITS pred_inv :1; //11 //8
-
- BITS rtype:3;
- BITS reg:10; //24 //20
-
- BITS writex:1;
- BITS writey:1;
- BITS writez:1;
- BITS writew:1; //28
-
- BITS op3:1; // 29 Represents *_OP3_* ALU opcode
-
- BITS dualop:1; // 30 //26
-
- BITS addrmode0:1; //31 //29
- BITS addrmode1:1; //32
-#endif
-} PVSDST;
-
-typedef struct PVSINSTtag
-{
-#ifdef MESA_BIG_ENDIAN
- BITS index_mode :3;
- BITS SaturateMode :2;
- BITS literal_slots :2;
-#else
- BITS literal_slots :2;
- BITS SaturateMode :2;
- BITS index_mode :3;
-#endif
-} PVSINST;
-
-typedef struct PVSSRCtag
-{
-#ifdef MESA_BIG_ENDIAN
- BITS addrmode1:1; //32
- //BITS addrsel:2;
- BITS negw:1; //31
- BITS negz:1;
- BITS negy:1;
- BITS negx:1;
- BITS abs:1;
-
- BITS swizzlew:3; //26
- BITS swizzlez:3;
- BITS swizzley:3;
- BITS swizzlex:3;
- BITS reg:10; //14 (8)
- BITS addrmode0:1;
- BITS rtype:3;
-#else
- BITS rtype:3;
- BITS addrmode0:1;
- BITS reg:10; //14 (8)
- BITS swizzlex:3;
- BITS swizzley:3;
- BITS swizzlez:3;
- BITS swizzlew:3; //26
-
- BITS abs:1;
- BITS negx:1;
- BITS negy:1;
- BITS negz:1;
- BITS negw:1; //31
- //BITS addrsel:2;
- BITS addrmode1:1; //32
-#endif
-} PVSSRC;
-
-typedef struct PVSMATHtag
-{
-#ifdef MESA_BIG_ENDIAN
- BITS spare2:3;
- BITS dstcomp:2; // select dest component
- BITS negy:1;
- BITS negx:1;
- BITS opcode:4;
- BITS dstoff:2; // 2 bits of dest offset into alt ram
- BITS swizzley:3;
- BITS swizzlex:3;
- BITS reg:8;
- BITS spare:1;
- BITS rtype:4;
-#else
- BITS rtype:4;
- BITS spare:1;
- BITS reg:8;
- BITS swizzlex:3;
- BITS swizzley:3;
- BITS dstoff:2; // 2 bits of dest offset into alt ram
- BITS opcode:4;
- BITS negx:1;
- BITS negy:1;
- BITS dstcomp:2; // select dest component
- BITS spare2:3;
-#endif
-} PVSMATH;
-
-typedef union PVSDWORDtag
-{
- BITS bits;
- PVSDST dst;
- PVSINST dst2;
- PVSSRC src;
- PVSMATH math;
- float f;
-} PVSDWORD;
-
-typedef struct VAP_OUT_VTX_FMT_0tag
-{
-#ifdef MESA_BIG_ENDIAN
- BITS resvd1:12; // 20
-
- BITS viewport_index:1; // 19
- BITS kill_flag:1;
- BITS rta_index:1; // shares same channel as kill_flag
- BITS edge_flag:1;
- BITS point_size:1; // 15
-
- BITS depth:1; // 14
-
- BITS normal:1;
-
- BITS color7:1;
- BITS color6:1;
- BITS color5:1;
- BITS color4:1;
- BITS color3:1;
- BITS color2:1;
- BITS color1:1;
- BITS color0:1;
-
- BITS pos_param:1; // 4
- BITS clip_dist1:1;
- BITS clip_dist0:1;
- BITS misc:1;
- BITS pos:1; // 0
-#else
- BITS pos:1; // 0
- BITS misc:1;
- BITS clip_dist0:1;
- BITS clip_dist1:1;
- BITS pos_param:1; // 4
-
- BITS color0:1; // 5
- BITS color1:1;
- BITS color2:1;
- BITS color3:1;
- BITS color4:1;
- BITS color5:1;
- BITS color6:1;
- BITS color7:1;
-
- BITS normal:1;
-
- BITS depth:1; // 14
-
- BITS point_size:1; // 15
- BITS edge_flag:1;
- BITS rta_index:1; // shares same channel as kill_flag
- BITS kill_flag:1;
- BITS viewport_index:1; // 19
-
- BITS resvd1:12; // 20
-#endif
-} VAP_OUT_VTX_FMT_0;
-
-typedef struct VAP_OUT_VTX_FMT_1tag
-{
-#ifdef MESA_BIG_ENDIAN
- BITS resvd:8;
-
- BITS tex7comp:3;
- BITS tex6comp:3;
- BITS tex5comp:3;
- BITS tex4comp:3;
- BITS tex3comp:3;
- BITS tex2comp:3;
- BITS tex1comp:3;
- BITS tex0comp:3;
-#else
- BITS tex0comp:3;
- BITS tex1comp:3;
- BITS tex2comp:3;
- BITS tex3comp:3;
- BITS tex4comp:3;
- BITS tex5comp:3;
- BITS tex6comp:3;
- BITS tex7comp:3;
-
- BITS resvd:8;
-#endif
-} VAP_OUT_VTX_FMT_1;
-
-typedef struct VAP_OUT_VTX_FMT_2tag
-{
-#ifdef MESA_BIG_ENDIAN
- BITS resvd:8;
-
- BITS tex15comp:3;
- BITS tex14comp:3;
- BITS tex13comp:3;
- BITS tex12comp:3;
- BITS tex11comp:3;
- BITS tex10comp:3;
- BITS tex9comp:3;
- BITS tex8comp:3;
-#else
- BITS tex8comp :3;
- BITS tex9comp :3;
- BITS tex10comp:3;
- BITS tex11comp:3;
- BITS tex12comp:3;
- BITS tex13comp:3;
- BITS tex14comp:3;
- BITS tex15comp:3;
-
- BITS resvd:8;
-#endif
-} VAP_OUT_VTX_FMT_2;
-
-typedef struct OUT_FRAGMENT_FMT_0tag
-{
-#ifdef MESA_BIG_ENDIAN
- BITS resvd1:20;
-
- BITS mask:1;
- BITS coverage_to_mask:1;
- BITS stencil_ref:1;
- BITS depth:1;
-
- BITS color7:1;
- BITS color6:1;
- BITS color5:1;
- BITS color4:1;
- BITS color3:1;
- BITS color2:1;
- BITS color1:1;
- BITS color0:1;
-#else
- BITS color0:1;
- BITS color1:1;
- BITS color2:1;
- BITS color3:1;
- BITS color4:1;
- BITS color5:1;
- BITS color6:1;
- BITS color7:1;
-
- BITS depth:1;
- BITS stencil_ref:1;
- BITS coverage_to_mask:1;
- BITS mask:1;
-
- BITS resvd1:20;
-#endif
-} OUT_FRAGMENT_FMT_0;
-
-typedef enum CF_CLAUSE_TYPE
-{
- CF_EXPORT_CLAUSE,
- CF_ALU_CLAUSE,
- CF_TEX_CLAUSE,
- CF_VTX_CLAUSE,
- CF_OTHER_CLAUSE,
- CF_EMPTY_CLAUSE,
- NUMBER_CF_CLAUSE_TYPES
-} CF_CLAUSE_TYPE;
-
-enum
-{
- MAX_BOOL_CONSTANTS = 32,
- MAX_INT_CONSTANTS = 32,
- MAX_FLOAT_CONSTANTS = 256,
-
- FC_NONE = 0,
- FC_IF = 1,
- FC_LOOP = 2,
- FC_REP = 3,
- FC_PUSH_VPM = 4,
- FC_PUSH_WQM = 5,
-
- COND_NONE = 0,
- COND_BOOL = 1,
- COND_PRED = 2,
- COND_ALU = 3,
-
- SAFEDIST_TEX = 6, ///< safe distance for using result of texture lookup in alu or another tex lookup
- SAFEDIST_ALU = 6 ///< the same for alu->fc
-};
-
-typedef struct FC_LEVEL
-{
- R700ControlFlowGenericClause * first;
- R700ControlFlowGenericClause ** mid;
- unsigned int unNumMid;
- unsigned int midLen;
- unsigned int type;
- unsigned int cond;
- unsigned int inv;
- int id; ///< id of bool or int variable
-} FC_LEVEL;
-
-typedef struct VTX_FETCH_METHOD
-{
- GLboolean bEnableMini;
- GLuint mega_fetch_remainder;
-} VTX_FETCH_METHOD;
-
-typedef struct SUB_OFFSET
-{
- GLint subIL_Offset;
- GLuint unCFoffset;
- GLuint unStackDepthMax;
- PRESUB_DESC * pPresubDesc;
- TypedShaderList lstCFInstructions_local;
-} SUB_OFFSET;
-
-typedef struct CALLER_POINTER
-{
- GLint subIL_Offset;
- GLint subDescIndex;
- R700ControlFlowGenericClause* cf_ptr;
-
- R700ControlFlowGenericClause* prelude_cf_ptr;
- R700ControlFlowGenericClause* finale_cf_ptr;
-} CALLER_POINTER;
-
-#define SQ_MAX_CALL_DEPTH 0x00000020
-
-typedef struct CALL_LEVEL
-{
- unsigned int FCSP_BeforeEntry;
- GLint subDescIndex;
- GLushort current;
- GLushort max;
- TypedShaderList * plstCFInstructions_local;
-} CALL_LEVEL;
-
-#define HAS_CURRENT_LOOPRET 0x1L
-#define HAS_LOOPRET 0x2L
-#define LOOPRET_FLAGS HAS_LOOPRET | HAS_CURRENT_LOOPRET
-
-typedef struct r700_AssemblerBase
-{
- R700ControlFlowSXClause* cf_last_export_ptr;
- R700ControlFlowSXClause* cf_current_export_clause_ptr;
- R700ControlFlowALUClause* cf_current_alu_clause_ptr;
- R700ControlFlowGenericClause* cf_current_tex_clause_ptr;
- R700ControlFlowGenericClause* cf_current_vtx_clause_ptr;
- R700ControlFlowGenericClause* cf_current_cf_clause_ptr;
-
- //Result shader
- R700_Shader * pR700Shader;
-
- // No clause has been created yet
- CF_CLAUSE_TYPE cf_current_clause_type;
-
- BITS alu_x_opcode;
-
- GLuint number_of_exports;
- GLuint number_of_colorandz_exports;
- GLuint number_of_export_opcodes;
-
- PVSDWORD D;
- PVSDWORD D2;
- PVSDWORD S[3];
- PVSDWORD C[4];
-
- unsigned int uLastPosUpdate;
- unsigned int last_cond_register;
-
- OUT_FRAGMENT_FMT_0 fp_stOutFmt0;
-
- unsigned int uIIns;
- unsigned int uOIns;
- unsigned int number_used_registers;
- unsigned int uUsedConsts;
-
- unsigned int flag_reg_index;
-
- // Fragment programs
- unsigned int uiFP_AttributeMap[FRAG_ATTRIB_MAX];
- unsigned int uiFP_OutputMap[FRAG_RESULT_MAX];
- unsigned int uBoolConsts;
- unsigned int uIntConsts;
- unsigned int uInsts;
- unsigned int uConsts;
-
- // Vertex programs
- unsigned char ucVP_AttributeMap[VERT_ATTRIB_MAX];
- unsigned char ucVP_OutputMap[VERT_RESULT_MAX];
-
- //-----------------------------------------------------------------------------------
- // flow control members
- //-----------------------------------------------------------------------------------
- unsigned int FCSP;
- FC_LEVEL fc_stack[32];
-
- //-----------------------------------------------------------------------------------
- // ArgSubst used in Assemble_Source() function
- //-----------------------------------------------------------------------------------
- int aArgSubst[4];
-
- GLint hw_gpr[ NUMBER_OF_CYCLES ][ NUMBER_OF_COMPONENTS ];
- GLint hw_cfile_addr[ NUMBER_OF_COMPONENTS ];
- GLint hw_cfile_chan[ NUMBER_OF_COMPONENTS ];
-
- GLuint uOutputs;
-
- GLint color_export_register_number[NUMBER_OF_OUTPUT_COLORS];
- GLint depth_export_register_number;
-
- GLint stencil_export_register_number;
- GLint coverage_to_mask_export_register_number;
- GLint mask_export_register_number;
-
- GLuint starting_export_register_number;
- GLuint starting_vfetch_register_number;
- GLuint starting_temp_register_number;
- GLuint uHelpReg;
- GLuint uFirstHelpReg;
-
- GLboolean input_position_is_used;
- GLboolean input_normal_is_used;
-
- GLboolean input_color_is_used[NUMBER_OF_INPUT_COLORS];
-
- GLboolean input_texture_unit_is_used[NUMBER_OF_TEXTURE_UNITS];
-
- R700VertexGenericFetch* vfetch_instruction_ptr_array[VERT_ATTRIB_MAX];
-
- GLuint number_of_inputs;
-
- InstDeps *pInstDeps;
-
- SHADER_PIPE_TYPE currentShaderType;
- struct prog_instruction * pILInst;
- GLuint uiCurInst;
- GLubyte SamplerUnits[MAX_SAMPLERS];
- GLboolean bR6xx;
-
- /* TODO : merge bR6xx */
- GLuint unAsic;
-
- /* helper to decide which type of instruction to assemble */
- GLboolean is_tex;
- /* we inserted helper intructions and need barrier on next TEX ins */
- GLboolean need_tex_barrier;
-
- SUB_OFFSET * subs;
- GLuint unSubArraySize;
- GLuint unSubArrayPointer;
- CALLER_POINTER * callers;
- GLuint unCallerArraySize;
- GLuint unCallerArrayPointer;
- unsigned int CALLSP;
- CALL_LEVEL CALLSTACK[SQ_MAX_CALL_DEPTH];
-
- GLuint unCFflags;
-
- PRESUB_DESC * presubs;
- GLuint unPresubArraySize;
- GLuint unNumPresub;
- GLuint unCurNumILInsts;
-
- GLuint unVetTexBits;
-
- GLuint shadow_regs[R700_MAX_TEXTURE_UNITS];
-
- GLboolean bUseMemConstant;
- GLuint kcacheUsed;
-
-} r700_AssemblerBase;
-
-//Internal use
-BITS addrmode_PVSDST(PVSDST * pPVSDST);
-void setaddrmode_PVSDST(PVSDST * pPVSDST, BITS addrmode);
-void nomask_PVSDST(PVSDST * pPVSDST);
-BITS addrmode_PVSSRC(PVSSRC* pPVSSRC);
-void setaddrmode_PVSSRC(PVSSRC* pPVSSRC, BITS addrmode);
-void setswizzle_PVSSRC(PVSSRC* pPVSSRC, BITS swz);
-void noswizzle_PVSSRC(PVSSRC* pPVSSRC);
-void swizzleagain_PVSSRC(PVSSRC * pPVSSRC, BITS x, BITS y, BITS z, BITS w);
-void neg_PVSSRC(PVSSRC* pPVSSRC);
-void noneg_PVSSRC(PVSSRC* pPVSSRC);
-void flipneg_PVSSRC(PVSSRC* pPVSSRC);
-void zerocomp_PVSSRC(PVSSRC* pPVSSRC, int c);
-void onecomp_PVSSRC(PVSSRC* pPVSSRC, int c);
-BITS is_misc_component_exported(VAP_OUT_VTX_FMT_0* pOutVTXFmt0);
-BITS is_depth_component_exported(OUT_FRAGMENT_FMT_0* pFPOutFmt) ;
-GLboolean is_reduction_opcode(PVSDWORD * dest);
-GLuint GetSurfaceFormat(GLenum eType, GLuint nChannels, GLuint * pClient_size);
-
-unsigned int r700GetNumOperands(GLuint opcode, GLuint nIsOp3);
-
-unsigned int EG_GetNumOperands(GLuint opcode, GLuint nIsOp3);
-
-GLboolean IsTex(gl_inst_opcode Opcode);
-GLboolean IsAlu(gl_inst_opcode Opcode);
-int check_current_clause(r700_AssemblerBase* pAsm,
- CF_CLAUSE_TYPE new_clause_type);
-GLboolean add_vfetch_instruction(r700_AssemblerBase* pAsm,
- R700VertexInstruction* vertex_instruction_ptr);
-GLboolean add_tex_instruction(r700_AssemblerBase* pAsm,
- R700TextureInstruction* tex_instruction_ptr);
-GLboolean assemble_vfetch_instruction(r700_AssemblerBase* pAsm,
- GLuint gl_client_id,
- GLuint destination_register,
- GLuint number_of_elements,
- GLenum dataElementType,
- VTX_FETCH_METHOD* pFetchMethod);
-GLboolean assemble_vfetch_instruction2(r700_AssemblerBase* pAsm,
- GLuint destination_register,
- GLenum type,
- GLint size,
- GLubyte element,
- GLuint _signed,
- GLboolean normalize,
- GLenum format,
- VTX_FETCH_METHOD * pFetchMethod);
-
-GLboolean EG_assemble_vfetch_instruction(r700_AssemblerBase* pAsm,
- GLuint destination_register,
- GLenum type,
- GLint size,
- GLubyte element,
- GLuint _signed,
- GLboolean normalize,
- GLenum format,
- VTX_FETCH_METHOD * pFetchMethod);
-//-----------------------
-
-GLboolean cleanup_vfetch_instructions(r700_AssemblerBase* pAsm);
-GLuint gethelpr(r700_AssemblerBase* pAsm);
-void resethelpr(r700_AssemblerBase* pAsm);
-void checkop_init(r700_AssemblerBase* pAsm);
-GLboolean mov_temp(r700_AssemblerBase* pAsm, int src);
-GLboolean checkop1(r700_AssemblerBase* pAsm);
-GLboolean checkop2(r700_AssemblerBase* pAsm);
-GLboolean checkop3(r700_AssemblerBase* pAsm);
-GLboolean assemble_src(r700_AssemblerBase *pAsm,
- int src,
- int fld);
-GLboolean assemble_dst(r700_AssemblerBase *pAsm);
-GLboolean tex_dst(r700_AssemblerBase *pAsm);
-GLboolean tex_src(r700_AssemblerBase *pAsm);
-GLboolean assemble_tex_instruction(r700_AssemblerBase *pAsm, GLboolean normalized);
-void initialize(r700_AssemblerBase *pAsm);
-GLboolean assemble_alu_src(R700ALUInstruction* alu_instruction_ptr,
- int source_index,
- PVSSRC* pSource,
- BITS scalar_channel_index,
- r700_AssemblerBase *pAsm);
-
-GLboolean add_alu_instruction(r700_AssemblerBase* pAsm,
- R700ALUInstruction* alu_instruction_ptr,
- GLuint contiguous_slots_needed);
-
-GLboolean add_cf_instruction(r700_AssemblerBase* pAsm);
-void add_return_inst(r700_AssemblerBase *pAsm);
-
-void get_src_properties(R700ALUInstruction* alu_instruction_ptr,
- int source_index,
- BITS* psrc_sel,
- BITS* psrc_rel,
- BITS* psrc_chan,
- BITS* psrc_neg);
-int is_cfile(BITS sel);
-int is_const(BITS sel);
-int is_gpr(BITS sel);
-GLboolean reserve_cfile(r700_AssemblerBase* pAsm,
- GLuint sel,
- GLuint chan);
-GLboolean reserve_gpr(r700_AssemblerBase* pAsm, GLuint sel, GLuint chan, GLuint cycle);
-GLboolean cycle_for_scalar_bank_swizzle(const int swiz, const int sel, GLuint* pCycle);
-GLboolean cycle_for_vector_bank_swizzle(const int swiz, const int sel, GLuint* pCycle);
-GLboolean check_scalar(r700_AssemblerBase* pAsm,
- R700ALUInstruction* alu_instruction_ptr);
-GLboolean check_vector(r700_AssemblerBase* pAsm,
- R700ALUInstruction* alu_instruction_ptr);
-GLboolean assemble_alu_instruction(r700_AssemblerBase *pAsm);
-
-GLboolean pops(r700_AssemblerBase *pAsm, GLuint pops);
-GLboolean jumpToOffest(r700_AssemblerBase *pAsm, GLuint pops, GLint offset);
-GLboolean setRetInLoopFlag(r700_AssemblerBase *pAsm, GLuint flagValue);
-GLboolean testFlag(r700_AssemblerBase *pAsm);
-GLboolean breakLoopOnFlag(r700_AssemblerBase *pAsm, GLuint unFCSP);
-GLboolean returnOnFlag(r700_AssemblerBase *pAsm, GLuint unIF);
-
-GLboolean assemble_math_function(r700_AssemblerBase* pAsm, BITS opcode);
-GLboolean assemble_ABS(r700_AssemblerBase *pAsm);
-GLboolean assemble_ADD(r700_AssemblerBase *pAsm);
-GLboolean assemble_ARL(r700_AssemblerBase *pAsm);
-GLboolean assemble_BAD(char *opcode_str);
-GLboolean assemble_CMP(r700_AssemblerBase *pAsm);
-GLboolean assemble_DOT(r700_AssemblerBase *pAsm);
-GLboolean assemble_DST(r700_AssemblerBase *pAsm);
-GLboolean assemble_EX2(r700_AssemblerBase *pAsm);
-GLboolean assemble_EXP(r700_AssemblerBase *pAsm);
-GLboolean assemble_FLR(r700_AssemblerBase *pAsm);
-GLboolean assemble_FLR_INT(r700_AssemblerBase *pAsm);
-GLboolean assemble_FRC(r700_AssemblerBase *pAsm);
-GLboolean assemble_KIL(r700_AssemblerBase *pAsm, GLuint opcode);
-GLboolean assemble_LG2(r700_AssemblerBase *pAsm);
-GLboolean assemble_LRP(r700_AssemblerBase *pAsm);
-GLboolean assemble_LOG(r700_AssemblerBase *pAsm);
-GLboolean assemble_MAD(r700_AssemblerBase *pAsm);
-GLboolean assemble_LIT(r700_AssemblerBase *pAsm);
-GLboolean assemble_MAX(r700_AssemblerBase *pAsm);
-GLboolean assemble_MIN(r700_AssemblerBase *pAsm);
-GLboolean assemble_MOV(r700_AssemblerBase *pAsm);
-GLboolean assemble_MUL(r700_AssemblerBase *pAsm);
-GLboolean assemble_POW(r700_AssemblerBase *pAsm);
-GLboolean assemble_RCP(r700_AssemblerBase *pAsm);
-GLboolean assemble_RSQ(r700_AssemblerBase *pAsm);
-GLboolean assemble_SCS(r700_AssemblerBase *pAsm);
-GLboolean assemble_SGE(r700_AssemblerBase *pAsm);
-GLboolean assemble_CONT(r700_AssemblerBase *pAsm);
-
-GLboolean assemble_LOGIC(r700_AssemblerBase *pAsm, BITS opcode);
-GLboolean assemble_LOGIC_PRED(r700_AssemblerBase *pAsm, BITS opcode);
-GLboolean assemble_TRIG(r700_AssemblerBase *pAsm, BITS opcode);
-
-GLboolean assemble_SLT(r700_AssemblerBase *pAsm);
-GLboolean assemble_SSG(r700_AssemblerBase *pAsm);
-GLboolean assemble_STP(r700_AssemblerBase *pAsm);
-GLboolean assemble_TEX(r700_AssemblerBase *pAsm);
-GLboolean assemble_XPD(r700_AssemblerBase *pAsm);
-GLboolean assemble_EXPORT(r700_AssemblerBase *pAsm);
-GLboolean assemble_IF(r700_AssemblerBase *pAsm, GLboolean bHasElse);
-GLboolean assemble_ELSE(r700_AssemblerBase *pAsm);
-GLboolean assemble_ENDIF(r700_AssemblerBase *pAsm);
-
-GLboolean assemble_BGNLOOP(r700_AssemblerBase *pAsm);
-GLboolean assemble_BRK(r700_AssemblerBase *pAsm);
-GLboolean assemble_COND(r700_AssemblerBase *pAsm);
-GLboolean assemble_ENDLOOP(r700_AssemblerBase *pAsm);
-
-GLboolean assemble_BGNSUB(r700_AssemblerBase *pAsm, GLint nILindex, GLuint uiIL_Shift);
-GLboolean assemble_ENDSUB(r700_AssemblerBase *pAsm);
-GLboolean assemble_RET(r700_AssemblerBase *pAsm);
-GLboolean assemble_CAL(r700_AssemblerBase *pAsm,
- GLint nILindex,
- GLuint uiIL_Offest,
- GLuint uiNumberInsts,
- struct prog_instruction *pILInst,
- PRESUB_DESC * pPresubDesc);
-
-GLboolean Process_Export(r700_AssemblerBase* pAsm,
- GLuint type,
- GLuint export_starting_index,
- GLuint export_count,
- GLuint starting_register_number,
- GLboolean is_depth_export);
-GLboolean Move_Depth_Exports_To_Correct_Channels(r700_AssemblerBase *pAsm,
- BITS depth_channel_select);
-
-GLboolean callPreSub(r700_AssemblerBase* pAsm,
- LOADABLE_SCRIPT_SIGNITURE scriptSigniture,
- /* struct prog_instruction ** pILInstParent, */
- COMPILED_SUB * pCompiledSub,
- GLshort uOutReg,
- GLshort uNumValidSrc);
-GLboolean EG_add_ps_interp(r700_AssemblerBase* pAsm);
-
-//Interface
-GLboolean AssembleInstr(GLuint uiFirstInst,
- GLuint uiIL_Shift,
- GLuint uiNumberInsts,
- struct prog_instruction *pILInst,
- r700_AssemblerBase *pR700AsmCode);
-GLboolean Process_Fragment_Exports(r700_AssemblerBase *pR700AsmCode, GLbitfield OutputsWritten);
-GLboolean Process_Vertex_Exports(r700_AssemblerBase *pR700AsmCode, GLbitfield OutputsWritten);
-
-GLboolean RelocProgram(r700_AssemblerBase * pAsm, struct gl_program * pILProg);
-GLboolean InitShaderProgram(r700_AssemblerBase * pAsm);
-
-int Init_r700_AssemblerBase(SHADER_PIPE_TYPE spt, r700_AssemblerBase* pAsm, R700_Shader* pShader);
-GLboolean Clean_Up_Assembler(r700_AssemblerBase *pR700AsmCode);
-
-#endif //_R700_ASSEMBLER_H_
+++ /dev/null
-/*
- * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Authors:
- * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
- * CooperYuan <cooper.yuan@amd.com>, <cooperyuan@gmail.com>
- */
-
-#include "main/imports.h"
-#include "main/glheader.h"
-#include "main/simple_list.h"
-
-#include "r600_context.h"
-#include "r600_cmdbuf.h"
-
-#include "r600_tex.h"
-#include "r700_oglprog.h"
-#include "r700_fragprog.h"
-#include "r700_vertprog.h"
-
-#include "radeon_mipmap_tree.h"
-
-static void r700SendTexState(struct gl_context *ctx, struct radeon_state_atom *atom)
-{
- context_t *context = R700_CONTEXT(ctx);
- R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
-
- struct r700_vertex_program *vp = context->selected_vp;
-
- struct radeon_bo *bo = NULL;
- unsigned int i;
- BATCH_LOCALS(&context->radeon);
-
- radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
-
- for (i = 0; i < R700_TEXTURE_NUMBERUNITS; i++) {
- if (ctx->Texture.Unit[i]._ReallyEnabled) {
- radeonTexObj *t = r700->textures[i];
- if (t) {
- if (!t->image_override) {
- bo = t->mt->bo;
- } else {
- bo = t->bo;
- }
- if (bo) {
-
- r700SyncSurf(context, bo,
- RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM,
- 0, TC_ACTION_ENA_bit);
-
- BEGIN_BATCH_NO_AUTOSTATE(9 + 4);
- R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 7));
-
- if( (1<<i) & vp->r700AsmCode.unVetTexBits )
- { /* vs texture */
- R600_OUT_BATCH((i + VERT_ATTRIB_MAX + SQ_FETCH_RESOURCE_VS_OFFSET) * FETCH_RESOURCE_STRIDE);
- }
- else
- {
- R600_OUT_BATCH(i * 7);
- }
-
- R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE0);
- R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE1);
- R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE2);
- R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE3);
- R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE4);
- R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE5);
- R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE6);
- R600_OUT_BATCH_RELOC(r700->textures[i]->SQ_TEX_RESOURCE2,
- bo,
- r700->textures[i]->SQ_TEX_RESOURCE2,
- RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
- R600_OUT_BATCH_RELOC(r700->textures[i]->SQ_TEX_RESOURCE3,
- bo,
- r700->textures[i]->SQ_TEX_RESOURCE3,
- RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
- END_BATCH();
- COMMIT_BATCH();
- }
- }
- }
- }
-}
-
-#define SAMPLER_STRIDE 3
-
-static void r700SendTexSamplerState(struct gl_context *ctx, struct radeon_state_atom *atom)
-{
- context_t *context = R700_CONTEXT(ctx);
- R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
- unsigned int i;
-
- struct r700_vertex_program *vp = context->selected_vp;
-
- BATCH_LOCALS(&context->radeon);
- radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
-
- for (i = 0; i < R700_TEXTURE_NUMBERUNITS; i++) {
- if (ctx->Texture.Unit[i]._ReallyEnabled) {
- radeonTexObj *t = r700->textures[i];
- if (t) {
- BEGIN_BATCH_NO_AUTOSTATE(5);
- R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_SAMPLER, 3));
-
- if( (1<<i) & vp->r700AsmCode.unVetTexBits )
- { /* vs texture */
- R600_OUT_BATCH((i+SQ_TEX_SAMPLER_VS_OFFSET) * SAMPLER_STRIDE); //work 1
- }
- else
- {
- R600_OUT_BATCH(i * 3);
- }
-
- R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER0);
- R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER1);
- R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER2);
- END_BATCH();
- COMMIT_BATCH();
- }
- }
- }
-}
-
-static void r700SendTexBorderColorState(struct gl_context *ctx, struct radeon_state_atom *atom)
-{
- context_t *context = R700_CONTEXT(ctx);
- R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
- unsigned int i;
- BATCH_LOCALS(&context->radeon);
- radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
-
- for (i = 0; i < R700_TEXTURE_NUMBERUNITS; i++) {
- if (ctx->Texture.Unit[i]._ReallyEnabled) {
- radeonTexObj *t = r700->textures[i];
- if (t) {
- BEGIN_BATCH_NO_AUTOSTATE(2 + 4);
- R600_OUT_BATCH_REGSEQ((TD_PS_SAMPLER0_BORDER_RED + (i * 16)), 4);
- R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_RED);
- R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_GREEN);
- R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_BLUE);
- R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_ALPHA);
- END_BATCH();
- COMMIT_BATCH();
- }
- }
- }
-}
-
-extern int getTypeSize(GLenum type);
-static void r700SetupVTXConstants(struct gl_context * ctx,
- void * pAos,
- StreamDesc * pStreamDesc)
-{
- context_t *context = R700_CONTEXT(ctx);
- struct radeon_aos * paos = (struct radeon_aos *)pAos;
- BATCH_LOCALS(&context->radeon);
-
- unsigned int uSQ_VTX_CONSTANT_WORD0_0;
- unsigned int uSQ_VTX_CONSTANT_WORD1_0;
- unsigned int uSQ_VTX_CONSTANT_WORD2_0 = 0;
- unsigned int uSQ_VTX_CONSTANT_WORD3_0 = 0;
- unsigned int uSQ_VTX_CONSTANT_WORD6_0 = 0;
-
- if (!paos->bo)
- return;
-
- if ((context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV610) ||
- (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV620) ||
- (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS780) ||
- (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS880) ||
- (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV710))
- r700SyncSurf(context, paos->bo, RADEON_GEM_DOMAIN_GTT, 0, TC_ACTION_ENA_bit);
- else
- r700SyncSurf(context, paos->bo, RADEON_GEM_DOMAIN_GTT, 0, VC_ACTION_ENA_bit);
-
- uSQ_VTX_CONSTANT_WORD0_0 = paos->offset;
- uSQ_VTX_CONSTANT_WORD1_0 = paos->bo->size - paos->offset - 1;
-
- SETfield(uSQ_VTX_CONSTANT_WORD2_0, 0, BASE_ADDRESS_HI_shift, BASE_ADDRESS_HI_mask); /* TODO */
- SETfield(uSQ_VTX_CONSTANT_WORD2_0, pStreamDesc->stride, SQ_VTX_CONSTANT_WORD2_0__STRIDE_shift,
- SQ_VTX_CONSTANT_WORD2_0__STRIDE_mask);
- SETfield(uSQ_VTX_CONSTANT_WORD2_0, GetSurfaceFormat(pStreamDesc->type, pStreamDesc->size, NULL),
- SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_shift,
- SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_mask); /* TODO : trace back api for initial data type, not only GL_FLOAT */
- SETfield(uSQ_VTX_CONSTANT_WORD2_0,
-#ifdef MESA_BIG_ENDIAN
- SQ_ENDIAN_8IN32,
-#else
- SQ_ENDIAN_NONE,
-#endif
- SQ_VTX_CONSTANT_WORD2_0__ENDIAN_SWAP_shift,
- SQ_VTX_CONSTANT_WORD2_0__ENDIAN_SWAP_mask);
-
- if(GL_TRUE == pStreamDesc->normalize)
- {
- SETfield(uSQ_VTX_CONSTANT_WORD2_0, SQ_NUM_FORMAT_NORM,
- SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_shift, SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_mask);
- }
- else
- {
- SETfield(uSQ_VTX_CONSTANT_WORD2_0, SQ_NUM_FORMAT_SCALED,
- SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_shift, SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_mask);
- }
-
- if(1 == pStreamDesc->_signed)
- {
- SETbit(uSQ_VTX_CONSTANT_WORD2_0, SQ_VTX_CONSTANT_WORD2_0__FORMAT_COMP_ALL_bit);
- }
-
- SETfield(uSQ_VTX_CONSTANT_WORD3_0, 1, MEM_REQUEST_SIZE_shift, MEM_REQUEST_SIZE_mask);
- SETfield(uSQ_VTX_CONSTANT_WORD6_0, SQ_TEX_VTX_VALID_BUFFER,
- SQ_TEX_RESOURCE_WORD6_0__TYPE_shift, SQ_TEX_RESOURCE_WORD6_0__TYPE_mask);
-
- BEGIN_BATCH_NO_AUTOSTATE(9 + 2);
-
- R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 7));
- R600_OUT_BATCH((pStreamDesc->element + SQ_FETCH_RESOURCE_VS_OFFSET) * FETCH_RESOURCE_STRIDE);
- R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD0_0);
- R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD1_0);
- R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD2_0);
- R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD3_0);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD6_0);
- R600_OUT_BATCH_RELOC(uSQ_VTX_CONSTANT_WORD0_0,
- paos->bo,
- uSQ_VTX_CONSTANT_WORD0_0,
- RADEON_GEM_DOMAIN_GTT, 0, 0);
- END_BATCH();
- COMMIT_BATCH();
-
-}
-
-static void r700SendVTXState(struct gl_context *ctx, struct radeon_state_atom *atom)
-{
- context_t *context = R700_CONTEXT(ctx);
- struct r700_vertex_program *vp = context->selected_vp;
- unsigned int i, j = 0;
- BATCH_LOCALS(&context->radeon);
- (void) b_l_rmesa; /* silence unused var warning */
- radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
-
- if (context->radeon.tcl.aos_count == 0)
- return;
-
- for(i=0; i<VERT_ATTRIB_MAX; i++) {
- if(vp->mesa_program->Base.InputsRead & (1 << i))
- {
- r700SetupVTXConstants(ctx,
- (void*)(&context->radeon.tcl.aos[j]),
- &(context->stream_desc[j]));
- j++;
- }
- }
-}
-
-static void r700SetRenderTarget(context_t *context, int id)
-{
- R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
- uint32_t format = COLOR_8_8_8_8, comp_swap = SWAP_ALT, number_type = NUMBER_UNORM;
- struct radeon_renderbuffer *rrb;
- unsigned int nPitchInPixel, height;
-
- rrb = radeon_get_colorbuffer(&context->radeon);
- if (!rrb || !rrb->bo) {
- return;
- }
-
- R600_STATECHANGE(context, cb_target);
-
- /* color buffer */
- r700->render_target[id].CB_COLOR0_BASE.u32All = context->radeon.state.color.draw_offset / 256;
-
- nPitchInPixel = rrb->pitch/rrb->cpp;
-
- if (context->radeon.radeonScreen->driScreen->dri2.enabled)
- {
- height = rrb->base.Height;
- }
- else
- {
- height = context->radeon.radeonScreen->driScreen->fbHeight;
- }
-
- SETfield(r700->render_target[id].CB_COLOR0_SIZE.u32All, (nPitchInPixel/8)-1,
- PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask);
- SETfield(r700->render_target[id].CB_COLOR0_SIZE.u32All, ( (nPitchInPixel * height)/64 )-1,
- SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask);
- SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ENDIAN_NONE, ENDIAN_shift, ENDIAN_mask);
- SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ARRAY_LINEAR_GENERAL,
- CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
-
- switch (rrb->base.Format) {
- case MESA_FORMAT_RGBA8888:
- format = COLOR_8_8_8_8;
- comp_swap = SWAP_STD_REV;
- number_type = NUMBER_UNORM;
- SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
- break;
- case MESA_FORMAT_SIGNED_RGBA8888:
- format = COLOR_8_8_8_8;
- comp_swap = SWAP_STD_REV;
- number_type = NUMBER_SNORM;
- SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
- break;
- case MESA_FORMAT_RGBA8888_REV:
- format = COLOR_8_8_8_8;
- comp_swap = SWAP_STD;
- number_type = NUMBER_UNORM;
- SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
- break;
- case MESA_FORMAT_SIGNED_RGBA8888_REV:
- format = COLOR_8_8_8_8;
- comp_swap = SWAP_STD;
- number_type = NUMBER_SNORM;
- SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
- break;
- case MESA_FORMAT_ARGB8888:
- case MESA_FORMAT_XRGB8888:
- format = COLOR_8_8_8_8;
- comp_swap = SWAP_ALT;
- number_type = NUMBER_UNORM;
- SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
- break;
- case MESA_FORMAT_ARGB8888_REV:
- case MESA_FORMAT_XRGB8888_REV:
- format = COLOR_8_8_8_8;
- comp_swap = SWAP_ALT_REV;
- number_type = NUMBER_UNORM;
- SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
- break;
- case MESA_FORMAT_RGB565:
- format = COLOR_5_6_5;
- comp_swap = SWAP_STD_REV;
- number_type = NUMBER_UNORM;
- SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
- break;
- case MESA_FORMAT_RGB565_REV:
- format = COLOR_5_6_5;
- comp_swap = SWAP_STD;
- number_type = NUMBER_UNORM;
- SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
- break;
- case MESA_FORMAT_ARGB4444:
- format = COLOR_4_4_4_4;
- comp_swap = SWAP_ALT;
- number_type = NUMBER_UNORM;
- SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
- break;
- case MESA_FORMAT_ARGB4444_REV:
- format = COLOR_4_4_4_4;
- comp_swap = SWAP_ALT_REV;
- number_type = NUMBER_UNORM;
- SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
- break;
- case MESA_FORMAT_ARGB1555:
- format = COLOR_1_5_5_5;
- comp_swap = SWAP_ALT;
- number_type = NUMBER_UNORM;
- SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
- break;
- case MESA_FORMAT_ARGB1555_REV:
- format = COLOR_1_5_5_5;
- comp_swap = SWAP_ALT_REV;
- number_type = NUMBER_UNORM;
- SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
- break;
- case MESA_FORMAT_AL88:
- format = COLOR_8_8;
- comp_swap = SWAP_STD;
- number_type = NUMBER_UNORM;
- SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
- break;
- case MESA_FORMAT_AL88_REV:
- format = COLOR_8_8;
- comp_swap = SWAP_STD_REV;
- number_type = NUMBER_UNORM;
- SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
- break;
- case MESA_FORMAT_RGB332:
- format = COLOR_3_3_2;
- comp_swap = SWAP_STD_REV;
- number_type = NUMBER_UNORM;
- SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
- break;
- case MESA_FORMAT_A8:
- format = COLOR_8;
- comp_swap = SWAP_ALT_REV;
- number_type = NUMBER_UNORM;
- SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
- break;
- case MESA_FORMAT_I8:
- format = COLOR_8;
- comp_swap = SWAP_STD;
- number_type = NUMBER_UNORM;
- SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
- break;
- case MESA_FORMAT_L8:
- format = COLOR_8;
- comp_swap = SWAP_ALT;
- number_type = NUMBER_UNORM;
- SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
- break;
- case MESA_FORMAT_RGBA_FLOAT32:
- format = COLOR_32_32_32_32_FLOAT;
- comp_swap = SWAP_STD_REV;
- number_type = NUMBER_FLOAT;
- SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, BLEND_FLOAT32_bit);
- CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
- break;
- case MESA_FORMAT_RGBA_FLOAT16:
- format = COLOR_16_16_16_16_FLOAT;
- comp_swap = SWAP_STD_REV;
- number_type = NUMBER_FLOAT;
- CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
- break;
- case MESA_FORMAT_ALPHA_FLOAT32:
- format = COLOR_32_FLOAT;
- comp_swap = SWAP_ALT_REV;
- number_type = NUMBER_FLOAT;
- SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, BLEND_FLOAT32_bit);
- CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
- break;
- case MESA_FORMAT_ALPHA_FLOAT16:
- format = COLOR_16_FLOAT;
- comp_swap = SWAP_ALT_REV;
- number_type = NUMBER_FLOAT;
- CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
- break;
- case MESA_FORMAT_LUMINANCE_FLOAT32:
- format = COLOR_32_FLOAT;
- comp_swap = SWAP_ALT;
- number_type = NUMBER_FLOAT;
- SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, BLEND_FLOAT32_bit);
- CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
- break;
- case MESA_FORMAT_LUMINANCE_FLOAT16:
- format = COLOR_16_FLOAT;
- comp_swap = SWAP_ALT;
- number_type = NUMBER_FLOAT;
- CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
- break;
- case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32:
- format = COLOR_32_32_FLOAT;
- comp_swap = SWAP_ALT_REV;
- number_type = NUMBER_FLOAT;
- SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, BLEND_FLOAT32_bit);
- CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
- break;
- case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16:
- format = COLOR_16_16_FLOAT;
- comp_swap = SWAP_ALT_REV;
- number_type = NUMBER_FLOAT;
- CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
- break;
- case MESA_FORMAT_INTENSITY_FLOAT32: /* X, X, X, X */
- format = COLOR_32_FLOAT;
- comp_swap = SWAP_STD;
- number_type = NUMBER_FLOAT;
- SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, BLEND_FLOAT32_bit);
- CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
- break;
- case MESA_FORMAT_INTENSITY_FLOAT16: /* X, X, X, X */
- format = COLOR_16_FLOAT;
- comp_swap = SWAP_STD;
- number_type = NUMBER_UNORM;
- CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
- break;
- case MESA_FORMAT_X8_Z24:
- case MESA_FORMAT_S8_Z24:
- format = COLOR_8_24;
- comp_swap = SWAP_STD;
- number_type = NUMBER_UNORM;
- SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ARRAY_1D_TILED_THIN1,
- CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
- CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
- break;
- case MESA_FORMAT_Z24_S8:
- format = COLOR_24_8;
- comp_swap = SWAP_STD;
- number_type = NUMBER_UNORM;
- SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ARRAY_1D_TILED_THIN1,
- CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
- CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
- break;
- case MESA_FORMAT_Z16:
- format = COLOR_16;
- comp_swap = SWAP_STD;
- number_type = NUMBER_UNORM;
- SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ARRAY_1D_TILED_THIN1,
- CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
- CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
- break;
- case MESA_FORMAT_Z32:
- format = COLOR_32;
- comp_swap = SWAP_STD;
- number_type = NUMBER_UNORM;
- SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ARRAY_1D_TILED_THIN1,
- CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
- CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
- break;
- case MESA_FORMAT_SARGB8:
- format = COLOR_8_8_8_8;
- comp_swap = SWAP_ALT;
- number_type = NUMBER_SRGB;
- SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
- break;
- case MESA_FORMAT_SLA8:
- format = COLOR_8_8;
- comp_swap = SWAP_ALT_REV;
- number_type = NUMBER_SRGB;
- SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
- break;
- case MESA_FORMAT_SL8:
- format = COLOR_8;
- comp_swap = SWAP_ALT_REV;
- number_type = NUMBER_SRGB;
- SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
- break;
- default:
- _mesa_problem(context->radeon.glCtx, "unexpected format in r700SetRenderTarget()");
- break;
- }
-
- /* must be 0 on r7xx */
- if (context->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV770)
- CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, BLEND_FLOAT32_bit);
-
- SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, format,
- CB_COLOR0_INFO__FORMAT_shift, CB_COLOR0_INFO__FORMAT_mask);
- SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, comp_swap,
- COMP_SWAP_shift, COMP_SWAP_mask);
- SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, number_type,
- NUMBER_TYPE_shift, NUMBER_TYPE_mask);
- SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, BLEND_CLAMP_bit);
-
- r700->render_target[id].enabled = GL_TRUE;
-}
-
-static void r700SetDepthTarget(context_t *context)
-{
- R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
-
- struct radeon_renderbuffer *rrb;
- unsigned int nPitchInPixel, height;
-
- rrb = radeon_get_depthbuffer(&context->radeon);
- if (!rrb)
- return;
-
- R600_STATECHANGE(context, db_target);
-
- /* depth buf */
- r700->DB_DEPTH_SIZE.u32All = 0;
- r700->DB_DEPTH_BASE.u32All = 0;
- r700->DB_DEPTH_INFO.u32All = 0;
- r700->DB_DEPTH_VIEW.u32All = 0;
-
- nPitchInPixel = rrb->pitch/rrb->cpp;
-
- if (context->radeon.radeonScreen->driScreen->dri2.enabled)
- {
- height = rrb->base.Height;
- }
- else
- {
- height = context->radeon.radeonScreen->driScreen->fbHeight;
- }
-
- SETfield(r700->DB_DEPTH_SIZE.u32All, (nPitchInPixel/8)-1,
- PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask);
- SETfield(r700->DB_DEPTH_SIZE.u32All, ( (nPitchInPixel * height)/64 )-1,
- SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask); /* size in pixel / 64 - 1 */
-
- if(4 == rrb->cpp)
- {
- SETfield(r700->DB_DEPTH_INFO.u32All, DEPTH_8_24,
- DB_DEPTH_INFO__FORMAT_shift, DB_DEPTH_INFO__FORMAT_mask);
- }
- else
- {
- SETfield(r700->DB_DEPTH_INFO.u32All, DEPTH_16,
- DB_DEPTH_INFO__FORMAT_shift, DB_DEPTH_INFO__FORMAT_mask);
- }
- SETfield(r700->DB_DEPTH_INFO.u32All, ARRAY_1D_TILED_THIN1,
- DB_DEPTH_INFO__ARRAY_MODE_shift, DB_DEPTH_INFO__ARRAY_MODE_mask);
- /* r700->DB_PREFETCH_LIMIT.bits.DEPTH_HEIGHT_TILE_MAX = (context->currentDraw->h >> 3) - 1; */ /* z buffer sie may much bigger than what need, so use actual used h. */
-}
-
-static void r700SendDepthTargetState(struct gl_context *ctx, struct radeon_state_atom *atom)
-{
- context_t *context = R700_CONTEXT(ctx);
- R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
- struct radeon_renderbuffer *rrb;
- BATCH_LOCALS(&context->radeon);
- radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
-
- rrb = radeon_get_depthbuffer(&context->radeon);
- if (!rrb || !rrb->bo) {
- return;
- }
-
- r700SetDepthTarget(context);
-
- BEGIN_BATCH_NO_AUTOSTATE(7 + 2);
- R600_OUT_BATCH_REGSEQ(DB_DEPTH_SIZE, 2);
- R600_OUT_BATCH(r700->DB_DEPTH_SIZE.u32All);
- R600_OUT_BATCH(r700->DB_DEPTH_VIEW.u32All);
- R600_OUT_BATCH_REGSEQ(DB_DEPTH_BASE, 1);
- R600_OUT_BATCH(r700->DB_DEPTH_BASE.u32All);
- R600_OUT_BATCH_RELOC(r700->DB_DEPTH_BASE.u32All,
- rrb->bo,
- r700->DB_DEPTH_BASE.u32All,
- 0, RADEON_GEM_DOMAIN_VRAM, 0);
- END_BATCH();
- BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
- R600_OUT_BATCH_REGSEQ(DB_DEPTH_INFO, 1);
- R600_OUT_BATCH(r700->DB_DEPTH_INFO.u32All);
- R600_OUT_BATCH_RELOC(r700->DB_DEPTH_INFO.u32All,
- rrb->bo,
- r700->DB_DEPTH_INFO.u32All,
- 0, RADEON_GEM_DOMAIN_VRAM, 0);
- END_BATCH();
-
- if ((context->radeon.radeonScreen->chip_family > CHIP_FAMILY_R600) &&
- (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)) {
- BEGIN_BATCH_NO_AUTOSTATE(2);
- R600_OUT_BATCH(CP_PACKET3(R600_IT_SURFACE_BASE_UPDATE, 0));
- R600_OUT_BATCH(1 << 0);
- END_BATCH();
- }
-
- COMMIT_BATCH();
-
-}
-
-static void r700SendRenderTargetState(struct gl_context *ctx, struct radeon_state_atom *atom)
-{
- context_t *context = R700_CONTEXT(ctx);
- R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
- struct radeon_renderbuffer *rrb;
- BATCH_LOCALS(&context->radeon);
- int id = 0;
- radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
-
- rrb = radeon_get_colorbuffer(&context->radeon);
- if (!rrb || !rrb->bo) {
- return;
- }
-
- r700SetRenderTarget(context, 0);
-
- if (id > R700_MAX_RENDER_TARGETS)
- return;
-
- if (!r700->render_target[id].enabled)
- return;
-
- BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
- R600_OUT_BATCH_REGSEQ(CB_COLOR0_BASE + (4 * id), 1);
- R600_OUT_BATCH(r700->render_target[id].CB_COLOR0_BASE.u32All);
- R600_OUT_BATCH_RELOC(r700->render_target[id].CB_COLOR0_BASE.u32All,
- rrb->bo,
- r700->render_target[id].CB_COLOR0_BASE.u32All,
- 0, RADEON_GEM_DOMAIN_VRAM, 0);
- END_BATCH();
-
- if ((context->radeon.radeonScreen->chip_family > CHIP_FAMILY_R600) &&
- (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)) {
- BEGIN_BATCH_NO_AUTOSTATE(2);
- R600_OUT_BATCH(CP_PACKET3(R600_IT_SURFACE_BASE_UPDATE, 0));
- R600_OUT_BATCH((2 << id));
- END_BATCH();
- }
- /* Set CMASK & TILE buffer to the offset of color buffer as
- * we don't use those this shouldn't cause any issue and we
- * then have a valid cmd stream
- */
- BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
- R600_OUT_BATCH_REGSEQ(CB_COLOR0_TILE + (4 * id), 1);
- R600_OUT_BATCH(r700->render_target[id].CB_COLOR0_TILE.u32All);
- R600_OUT_BATCH_RELOC(r700->render_target[id].CB_COLOR0_TILE.u32All,
- rrb->bo,
- r700->render_target[id].CB_COLOR0_TILE.u32All,
- 0, RADEON_GEM_DOMAIN_VRAM, 0);
- END_BATCH();
- BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
- R600_OUT_BATCH_REGSEQ(CB_COLOR0_FRAG + (4 * id), 1);
- R600_OUT_BATCH(r700->render_target[id].CB_COLOR0_FRAG.u32All);
- R600_OUT_BATCH_RELOC(r700->render_target[id].CB_COLOR0_FRAG.u32All,
- rrb->bo,
- r700->render_target[id].CB_COLOR0_FRAG.u32All,
- 0, RADEON_GEM_DOMAIN_VRAM, 0);
- END_BATCH();
-
- BEGIN_BATCH_NO_AUTOSTATE(9);
- R600_OUT_BATCH_REGVAL(CB_COLOR0_SIZE + (4 * id), r700->render_target[id].CB_COLOR0_SIZE.u32All);
- R600_OUT_BATCH_REGVAL(CB_COLOR0_VIEW + (4 * id), r700->render_target[id].CB_COLOR0_VIEW.u32All);
- R600_OUT_BATCH_REGVAL(CB_COLOR0_MASK + (4 * id), r700->render_target[id].CB_COLOR0_MASK.u32All);
- END_BATCH();
-
- BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
- R600_OUT_BATCH_REGVAL(CB_COLOR0_INFO + (4 * id), r700->render_target[id].CB_COLOR0_INFO.u32All);
- R600_OUT_BATCH_RELOC(r700->render_target[id].CB_COLOR0_INFO.u32All,
- rrb->bo,
- r700->render_target[id].CB_COLOR0_INFO.u32All,
- 0, RADEON_GEM_DOMAIN_VRAM, 0);
-
- END_BATCH();
-
- COMMIT_BATCH();
-
-}
-
-static void r700SendPSState(struct gl_context *ctx, struct radeon_state_atom *atom)
-{
- context_t *context = R700_CONTEXT(ctx);
- R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
- struct radeon_bo * pbo;
- struct radeon_bo * pbo_const;
- BATCH_LOCALS(&context->radeon);
- radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
-
- pbo = (struct radeon_bo *)r700GetActiveFpShaderBo(GL_CONTEXT(context));
-
- if (!pbo)
- return;
-
- r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
-
- BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
- R600_OUT_BATCH_REGSEQ(SQ_PGM_START_PS, 1);
- R600_OUT_BATCH(r700->ps.SQ_PGM_START_PS.u32All);
- R600_OUT_BATCH_RELOC(r700->ps.SQ_PGM_START_PS.u32All,
- pbo,
- r700->ps.SQ_PGM_START_PS.u32All,
- RADEON_GEM_DOMAIN_GTT, 0, 0);
- END_BATCH();
-
- BEGIN_BATCH_NO_AUTOSTATE(9);
- R600_OUT_BATCH_REGVAL(SQ_PGM_RESOURCES_PS, r700->ps.SQ_PGM_RESOURCES_PS.u32All);
- R600_OUT_BATCH_REGVAL(SQ_PGM_EXPORTS_PS, r700->ps.SQ_PGM_EXPORTS_PS.u32All);
- R600_OUT_BATCH_REGVAL(SQ_PGM_CF_OFFSET_PS, r700->ps.SQ_PGM_CF_OFFSET_PS.u32All);
- END_BATCH();
-
- BEGIN_BATCH_NO_AUTOSTATE(3);
- R600_OUT_BATCH_REGVAL(SQ_LOOP_CONST_0, 0x01000FFF);
- END_BATCH();
-
- pbo_const = (struct radeon_bo *)r700GetActiveFpShaderConstBo(GL_CONTEXT(context));
- //TODO : set up shader const
-
- COMMIT_BATCH();
-
-}
-
-static void r700SendVSState(struct gl_context *ctx, struct radeon_state_atom *atom)
-{
- context_t *context = R700_CONTEXT(ctx);
- R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
- struct radeon_bo * pbo;
- struct radeon_bo * pbo_const;
- BATCH_LOCALS(&context->radeon);
- radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
-
- pbo = (struct radeon_bo *)r700GetActiveVpShaderBo(GL_CONTEXT(context));
-
- if (!pbo)
- return;
-
- r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
-
- BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
- R600_OUT_BATCH_REGSEQ(SQ_PGM_START_VS, 1);
- R600_OUT_BATCH(r700->vs.SQ_PGM_START_VS.u32All);
- R600_OUT_BATCH_RELOC(r700->vs.SQ_PGM_START_VS.u32All,
- pbo,
- r700->vs.SQ_PGM_START_VS.u32All,
- RADEON_GEM_DOMAIN_GTT, 0, 0);
- END_BATCH();
-
- BEGIN_BATCH_NO_AUTOSTATE(6);
- R600_OUT_BATCH_REGVAL(SQ_PGM_RESOURCES_VS, r700->vs.SQ_PGM_RESOURCES_VS.u32All);
- R600_OUT_BATCH_REGVAL(SQ_PGM_CF_OFFSET_VS, r700->vs.SQ_PGM_CF_OFFSET_VS.u32All);
- END_BATCH();
-
- BEGIN_BATCH_NO_AUTOSTATE(3);
- R600_OUT_BATCH_REGVAL((SQ_LOOP_CONST_0 + 32*4), 0x0100000F);
- //R600_OUT_BATCH_REGVAL((SQ_LOOP_CONST_0 + (SQ_LOOP_CONST_vs<2)), 0x0100000F);
- END_BATCH();
-
- /* TODO : handle 4 bufs */
- if(GL_TRUE == r700->bShaderUseMemConstant)
- {
- pbo_const = (struct radeon_bo *)r700GetActiveVpShaderConstBo(GL_CONTEXT(context));
- if(NULL != pbo_const)
- {
- r700SyncSurf(context, pbo_const, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit); /* TODO : Check kc bit. */
-
- BEGIN_BATCH_NO_AUTOSTATE(3);
- R600_OUT_BATCH_REGVAL(SQ_ALU_CONST_BUFFER_SIZE_VS_0, (r700->vs.num_consts * 4)/16 );
- END_BATCH();
-
- BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
- R600_OUT_BATCH_REGSEQ(SQ_ALU_CONST_CACHE_VS_0, 1);
- R600_OUT_BATCH(r700->vs.SQ_ALU_CONST_CACHE_VS_0.u32All);
- R600_OUT_BATCH_RELOC(r700->vs.SQ_ALU_CONST_CACHE_VS_0.u32All,
- pbo_const,
- r700->vs.SQ_ALU_CONST_CACHE_VS_0.u32All,
- RADEON_GEM_DOMAIN_GTT, 0, 0);
- END_BATCH();
- }
- }
-
- COMMIT_BATCH();
-}
-
-static void r700SendFSState(struct gl_context *ctx, struct radeon_state_atom *atom)
-{
- context_t *context = R700_CONTEXT(ctx);
- R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
- struct radeon_bo * pbo;
- BATCH_LOCALS(&context->radeon);
- radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
-
- /* XXX fixme
- * R6xx chips require a FS be emitted, even if it's not used.
- * since we aren't using FS yet, just send the VS address to make
- * the kernel command checker happy
- */
- pbo = (struct radeon_bo *)r700GetActiveVpShaderBo(GL_CONTEXT(context));
- r700->fs.SQ_PGM_START_FS.u32All = r700->vs.SQ_PGM_START_VS.u32All;
- r700->fs.SQ_PGM_RESOURCES_FS.u32All = 0;
- r700->fs.SQ_PGM_CF_OFFSET_FS.u32All = 0;
- /* XXX */
-
- if (!pbo)
- return;
-
- r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
-
- BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
- R600_OUT_BATCH_REGSEQ(SQ_PGM_START_FS, 1);
- R600_OUT_BATCH(r700->fs.SQ_PGM_START_FS.u32All);
- R600_OUT_BATCH_RELOC(r700->fs.SQ_PGM_START_FS.u32All,
- pbo,
- r700->fs.SQ_PGM_START_FS.u32All,
- RADEON_GEM_DOMAIN_GTT, 0, 0);
- END_BATCH();
-
- BEGIN_BATCH_NO_AUTOSTATE(6);
- R600_OUT_BATCH_REGVAL(SQ_PGM_RESOURCES_FS, r700->fs.SQ_PGM_RESOURCES_FS.u32All);
- R600_OUT_BATCH_REGVAL(SQ_PGM_CF_OFFSET_FS, r700->fs.SQ_PGM_CF_OFFSET_FS.u32All);
- END_BATCH();
-
- COMMIT_BATCH();
-
-}
-
-static void r700SendViewportState(struct gl_context *ctx, struct radeon_state_atom *atom)
-{
- context_t *context = R700_CONTEXT(ctx);
- R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
- BATCH_LOCALS(&context->radeon);
- int id = 0;
- radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
-
- if (id > R700_MAX_VIEWPORTS)
- return;
-
- if (!r700->viewport[id].enabled)
- return;
-
- BEGIN_BATCH_NO_AUTOSTATE(16);
- R600_OUT_BATCH_REGSEQ(PA_SC_VPORT_SCISSOR_0_TL + (8 * id), 2);
- R600_OUT_BATCH(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All);
- R600_OUT_BATCH(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All);
- R600_OUT_BATCH_REGSEQ(PA_SC_VPORT_ZMIN_0 + (8 * id), 2);
- R600_OUT_BATCH(r700->viewport[id].PA_SC_VPORT_ZMIN_0.u32All);
- R600_OUT_BATCH(r700->viewport[id].PA_SC_VPORT_ZMAX_0.u32All);
- R600_OUT_BATCH_REGSEQ(PA_CL_VPORT_XSCALE_0 + (24 * id), 6);
- R600_OUT_BATCH(r700->viewport[id].PA_CL_VPORT_XSCALE.u32All);
- R600_OUT_BATCH(r700->viewport[id].PA_CL_VPORT_XOFFSET.u32All);
- R600_OUT_BATCH(r700->viewport[id].PA_CL_VPORT_YSCALE.u32All);
- R600_OUT_BATCH(r700->viewport[id].PA_CL_VPORT_YOFFSET.u32All);
- R600_OUT_BATCH(r700->viewport[id].PA_CL_VPORT_ZSCALE.u32All);
- R600_OUT_BATCH(r700->viewport[id].PA_CL_VPORT_ZOFFSET.u32All);
- END_BATCH();
-
- COMMIT_BATCH();
-
-}
-
-static void r700SendSQConfig(struct gl_context *ctx, struct radeon_state_atom *atom)
-{
- context_t *context = R700_CONTEXT(ctx);
- R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
- BATCH_LOCALS(&context->radeon);
- radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
-
- BEGIN_BATCH_NO_AUTOSTATE(34);
- R600_OUT_BATCH_REGSEQ(SQ_CONFIG, 6);
- R600_OUT_BATCH(r700->sq_config.SQ_CONFIG.u32All);
- R600_OUT_BATCH(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All);
- R600_OUT_BATCH(r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All);
- R600_OUT_BATCH(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All);
- R600_OUT_BATCH(r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All);
- R600_OUT_BATCH(r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All);
-
- R600_OUT_BATCH_REGVAL(TA_CNTL_AUX, r700->TA_CNTL_AUX.u32All);
- R600_OUT_BATCH_REGVAL(VC_ENHANCE, r700->VC_ENHANCE.u32All);
- R600_OUT_BATCH_REGVAL(R7xx_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, r700->SQ_DYN_GPR_CNTL_PS_FLUSH_REQ.u32All);
- R600_OUT_BATCH_REGVAL(DB_DEBUG, r700->DB_DEBUG.u32All);
- R600_OUT_BATCH_REGVAL(DB_WATERMARKS, r700->DB_WATERMARKS.u32All);
-
- R600_OUT_BATCH_REGSEQ(SQ_ESGS_RING_ITEMSIZE, 9);
- R600_OUT_BATCH(r700->SQ_ESGS_RING_ITEMSIZE.u32All);
- R600_OUT_BATCH(r700->SQ_GSVS_RING_ITEMSIZE.u32All);
- R600_OUT_BATCH(r700->SQ_ESTMP_RING_ITEMSIZE.u32All);
- R600_OUT_BATCH(r700->SQ_GSTMP_RING_ITEMSIZE.u32All);
- R600_OUT_BATCH(r700->SQ_VSTMP_RING_ITEMSIZE.u32All);
- R600_OUT_BATCH(r700->SQ_PSTMP_RING_ITEMSIZE.u32All);
- R600_OUT_BATCH(r700->SQ_FBUF_RING_ITEMSIZE.u32All);
- R600_OUT_BATCH(r700->SQ_REDUC_RING_ITEMSIZE.u32All);
- R600_OUT_BATCH(r700->SQ_GS_VERT_ITEMSIZE.u32All);
- END_BATCH();
-
- COMMIT_BATCH();
-}
-
-static void r700SendUCPState(struct gl_context *ctx, struct radeon_state_atom *atom)
-{
- context_t *context = R700_CONTEXT(ctx);
- R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
- BATCH_LOCALS(&context->radeon);
- int i;
- radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
-
- for (i = 0; i < R700_MAX_UCP; i++) {
- if (r700->ucp[i].enabled) {
- BEGIN_BATCH_NO_AUTOSTATE(6);
- R600_OUT_BATCH_REGSEQ(PA_CL_UCP_0_X + (16 * i), 4);
- R600_OUT_BATCH(r700->ucp[i].PA_CL_UCP_0_X.u32All);
- R600_OUT_BATCH(r700->ucp[i].PA_CL_UCP_0_Y.u32All);
- R600_OUT_BATCH(r700->ucp[i].PA_CL_UCP_0_Z.u32All);
- R600_OUT_BATCH(r700->ucp[i].PA_CL_UCP_0_W.u32All);
- END_BATCH();
- COMMIT_BATCH();
- }
- }
-}
-
-static void r700SendSPIState(struct gl_context *ctx, struct radeon_state_atom *atom)
-{
- context_t *context = R700_CONTEXT(ctx);
- R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
- BATCH_LOCALS(&context->radeon);
- unsigned int ui;
- radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
-
- BEGIN_BATCH_NO_AUTOSTATE(59 + R700_MAX_SHADER_EXPORTS);
-
- R600_OUT_BATCH_REGSEQ(SQ_VTX_SEMANTIC_0, 32);
- R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_0.u32All);
- R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_1.u32All);
- R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_2.u32All);
- R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_3.u32All);
- R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_4.u32All);
- R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_5.u32All);
- R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_6.u32All);
- R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_7.u32All);
- R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_8.u32All);
- R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_9.u32All);
- R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_10.u32All);
- R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_11.u32All);
- R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_12.u32All);
- R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_13.u32All);
- R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_14.u32All);
- R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_15.u32All);
- R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_16.u32All);
- R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_17.u32All);
- R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_18.u32All);
- R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_19.u32All);
- R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_20.u32All);
- R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_21.u32All);
- R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_22.u32All);
- R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_23.u32All);
- R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_24.u32All);
- R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_25.u32All);
- R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_26.u32All);
- R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_27.u32All);
- R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_28.u32All);
- R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_29.u32All);
- R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_30.u32All);
- R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_31.u32All);
-
- R600_OUT_BATCH_REGSEQ(SPI_VS_OUT_ID_0, 10);
- R600_OUT_BATCH(r700->SPI_VS_OUT_ID_0.u32All);
- R600_OUT_BATCH(r700->SPI_VS_OUT_ID_1.u32All);
- R600_OUT_BATCH(r700->SPI_VS_OUT_ID_2.u32All);
- R600_OUT_BATCH(r700->SPI_VS_OUT_ID_3.u32All);
- R600_OUT_BATCH(r700->SPI_VS_OUT_ID_4.u32All);
- R600_OUT_BATCH(r700->SPI_VS_OUT_ID_5.u32All);
- R600_OUT_BATCH(r700->SPI_VS_OUT_ID_6.u32All);
- R600_OUT_BATCH(r700->SPI_VS_OUT_ID_7.u32All);
- R600_OUT_BATCH(r700->SPI_VS_OUT_ID_8.u32All);
- R600_OUT_BATCH(r700->SPI_VS_OUT_ID_9.u32All);
-
- R600_OUT_BATCH_REGSEQ(SPI_VS_OUT_CONFIG, 9);
- R600_OUT_BATCH(r700->SPI_VS_OUT_CONFIG.u32All);
- R600_OUT_BATCH(r700->SPI_THREAD_GROUPING.u32All);
- R600_OUT_BATCH(r700->SPI_PS_IN_CONTROL_0.u32All);
- R600_OUT_BATCH(r700->SPI_PS_IN_CONTROL_1.u32All);
- R600_OUT_BATCH(r700->SPI_INTERP_CONTROL_0.u32All);
- R600_OUT_BATCH(r700->SPI_INPUT_Z.u32All);
- R600_OUT_BATCH(r700->SPI_FOG_CNTL.u32All);
- R600_OUT_BATCH(r700->SPI_FOG_FUNC_SCALE.u32All);
- R600_OUT_BATCH(r700->SPI_FOG_FUNC_BIAS.u32All);
-
- R600_OUT_BATCH_REGSEQ(SPI_PS_INPUT_CNTL_0, R700_MAX_SHADER_EXPORTS);
- for(ui = 0; ui < R700_MAX_SHADER_EXPORTS; ui++)
- R600_OUT_BATCH(r700->SPI_PS_INPUT_CNTL[ui].u32All);
-
- END_BATCH();
- COMMIT_BATCH();
-}
-
-static void r700SendVGTState(struct gl_context *ctx, struct radeon_state_atom *atom)
-{
- context_t *context = R700_CONTEXT(ctx);
- R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
- BATCH_LOCALS(&context->radeon);
- radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
-
- BEGIN_BATCH_NO_AUTOSTATE(41);
-
- R600_OUT_BATCH_REGSEQ(VGT_MAX_VTX_INDX, 4);
- R600_OUT_BATCH(r700->VGT_MAX_VTX_INDX.u32All);
- R600_OUT_BATCH(r700->VGT_MIN_VTX_INDX.u32All);
- R600_OUT_BATCH(r700->VGT_INDX_OFFSET.u32All);
- R600_OUT_BATCH(r700->VGT_MULTI_PRIM_IB_RESET_INDX.u32All);
-
- R600_OUT_BATCH_REGSEQ(VGT_OUTPUT_PATH_CNTL, 13);
- R600_OUT_BATCH(r700->VGT_OUTPUT_PATH_CNTL.u32All);
- R600_OUT_BATCH(r700->VGT_HOS_CNTL.u32All);
- R600_OUT_BATCH(r700->VGT_HOS_MAX_TESS_LEVEL.u32All);
- R600_OUT_BATCH(r700->VGT_HOS_MIN_TESS_LEVEL.u32All);
- R600_OUT_BATCH(r700->VGT_HOS_REUSE_DEPTH.u32All);
- R600_OUT_BATCH(r700->VGT_GROUP_PRIM_TYPE.u32All);
- R600_OUT_BATCH(r700->VGT_GROUP_FIRST_DECR.u32All);
- R600_OUT_BATCH(r700->VGT_GROUP_DECR.u32All);
- R600_OUT_BATCH(r700->VGT_GROUP_VECT_0_CNTL.u32All);
- R600_OUT_BATCH(r700->VGT_GROUP_VECT_1_CNTL.u32All);
- R600_OUT_BATCH(r700->VGT_GROUP_VECT_0_FMT_CNTL.u32All);
- R600_OUT_BATCH(r700->VGT_GROUP_VECT_1_FMT_CNTL.u32All);
- R600_OUT_BATCH(r700->VGT_GS_MODE.u32All);
-
- R600_OUT_BATCH_REGVAL(VGT_PRIMITIVEID_EN, r700->VGT_PRIMITIVEID_EN.u32All);
- R600_OUT_BATCH_REGVAL(VGT_MULTI_PRIM_IB_RESET_EN, r700->VGT_MULTI_PRIM_IB_RESET_EN.u32All);
- R600_OUT_BATCH_REGVAL(VGT_INSTANCE_STEP_RATE_0, r700->VGT_INSTANCE_STEP_RATE_0.u32All);
- R600_OUT_BATCH_REGVAL(VGT_INSTANCE_STEP_RATE_1, r700->VGT_INSTANCE_STEP_RATE_1.u32All);
-
- R600_OUT_BATCH_REGSEQ(VGT_STRMOUT_EN, 3);
- R600_OUT_BATCH(r700->VGT_STRMOUT_EN.u32All);
- R600_OUT_BATCH(r700->VGT_REUSE_OFF.u32All);
- R600_OUT_BATCH(r700->VGT_VTX_CNT_EN.u32All);
-
- R600_OUT_BATCH_REGVAL(VGT_STRMOUT_BUFFER_EN, r700->VGT_STRMOUT_BUFFER_EN.u32All);
-
- END_BATCH();
- COMMIT_BATCH();
-}
-
-static void r700SendSXState(struct gl_context *ctx, struct radeon_state_atom *atom)
-{
- context_t *context = R700_CONTEXT(ctx);
- R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
- BATCH_LOCALS(&context->radeon);
- radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
-
- BEGIN_BATCH_NO_AUTOSTATE(9);
- R600_OUT_BATCH_REGVAL(SX_MISC, r700->SX_MISC.u32All);
- R600_OUT_BATCH_REGVAL(SX_ALPHA_TEST_CONTROL, r700->SX_ALPHA_TEST_CONTROL.u32All);
- R600_OUT_BATCH_REGVAL(SX_ALPHA_REF, r700->SX_ALPHA_REF.u32All);
- END_BATCH();
- COMMIT_BATCH();
-}
-
-static void r700SendDBState(struct gl_context *ctx, struct radeon_state_atom *atom)
-{
- context_t *context = R700_CONTEXT(ctx);
- R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
- BATCH_LOCALS(&context->radeon);
- radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
-
- BEGIN_BATCH_NO_AUTOSTATE(17);
-
- R600_OUT_BATCH_REGSEQ(DB_STENCIL_CLEAR, 2);
- R600_OUT_BATCH(r700->DB_STENCIL_CLEAR.u32All);
- R600_OUT_BATCH(r700->DB_DEPTH_CLEAR.u32All);
-
- R600_OUT_BATCH_REGVAL(DB_DEPTH_CONTROL, r700->DB_DEPTH_CONTROL.u32All);
- R600_OUT_BATCH_REGVAL(DB_SHADER_CONTROL, r700->DB_SHADER_CONTROL.u32All);
-
- R600_OUT_BATCH_REGSEQ(DB_RENDER_CONTROL, 2);
- R600_OUT_BATCH(r700->DB_RENDER_CONTROL.u32All);
- R600_OUT_BATCH(r700->DB_RENDER_OVERRIDE.u32All);
-
- R600_OUT_BATCH_REGVAL(DB_ALPHA_TO_MASK, r700->DB_ALPHA_TO_MASK.u32All);
-
- END_BATCH();
- COMMIT_BATCH();
-}
-
-static void r700SendStencilState(struct gl_context *ctx, struct radeon_state_atom *atom)
-{
- context_t *context = R700_CONTEXT(ctx);
- R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
- BATCH_LOCALS(&context->radeon);
-
- BEGIN_BATCH_NO_AUTOSTATE(4);
- R600_OUT_BATCH_REGSEQ(DB_STENCILREFMASK, 2);
- R600_OUT_BATCH(r700->DB_STENCILREFMASK.u32All);
- R600_OUT_BATCH(r700->DB_STENCILREFMASK_BF.u32All);
- END_BATCH();
- COMMIT_BATCH();
-}
-
-static void r700SendCBState(struct gl_context *ctx, struct radeon_state_atom *atom)
-{
- context_t *context = R700_CONTEXT(ctx);
- R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
- BATCH_LOCALS(&context->radeon);
- radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
-
- if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) {
- BEGIN_BATCH_NO_AUTOSTATE(11);
- R600_OUT_BATCH_REGSEQ(CB_CLEAR_RED, 4);
- R600_OUT_BATCH(r700->CB_CLEAR_RED_R6XX.u32All);
- R600_OUT_BATCH(r700->CB_CLEAR_GREEN_R6XX.u32All);
- R600_OUT_BATCH(r700->CB_CLEAR_BLUE_R6XX.u32All);
- R600_OUT_BATCH(r700->CB_CLEAR_ALPHA_R6XX.u32All);
- R600_OUT_BATCH_REGSEQ(CB_FOG_RED, 3);
- R600_OUT_BATCH(r700->CB_FOG_RED_R6XX.u32All);
- R600_OUT_BATCH(r700->CB_FOG_GREEN_R6XX.u32All);
- R600_OUT_BATCH(r700->CB_FOG_BLUE_R6XX.u32All);
- END_BATCH();
- }
-
- BEGIN_BATCH_NO_AUTOSTATE(7);
- R600_OUT_BATCH_REGSEQ(CB_TARGET_MASK, 2);
- R600_OUT_BATCH(r700->CB_TARGET_MASK.u32All);
- R600_OUT_BATCH(r700->CB_SHADER_MASK.u32All);
- R600_OUT_BATCH_REGVAL(R7xx_CB_SHADER_CONTROL, r700->CB_SHADER_CONTROL.u32All);
- END_BATCH();
- COMMIT_BATCH();
-}
-
-static void r700SendCBCLRCMPState(struct gl_context *ctx, struct radeon_state_atom *atom)
-{
- context_t *context = R700_CONTEXT(ctx);
- R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
- BATCH_LOCALS(&context->radeon);
-
- BEGIN_BATCH_NO_AUTOSTATE(6);
- R600_OUT_BATCH_REGSEQ(CB_CLRCMP_CONTROL, 4);
- R600_OUT_BATCH(r700->CB_CLRCMP_CONTROL.u32All);
- R600_OUT_BATCH(r700->CB_CLRCMP_SRC.u32All);
- R600_OUT_BATCH(r700->CB_CLRCMP_DST.u32All);
- R600_OUT_BATCH(r700->CB_CLRCMP_MSK.u32All);
- END_BATCH();
- COMMIT_BATCH();
-}
-
-static void r700SendCBBlendState(struct gl_context *ctx, struct radeon_state_atom *atom)
-{
- context_t *context = R700_CONTEXT(ctx);
- R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
- BATCH_LOCALS(&context->radeon);
- unsigned int ui;
- radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
-
- if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) {
- BEGIN_BATCH_NO_AUTOSTATE(3);
- R600_OUT_BATCH_REGVAL(CB_BLEND_CONTROL, r700->CB_BLEND_CONTROL.u32All);
- END_BATCH();
- }
-
- BEGIN_BATCH_NO_AUTOSTATE(3);
- R600_OUT_BATCH_REGVAL(CB_COLOR_CONTROL, r700->CB_COLOR_CONTROL.u32All);
- END_BATCH();
-
- if (context->radeon.radeonScreen->chip_family > CHIP_FAMILY_R600) {
- for (ui = 0; ui < R700_MAX_RENDER_TARGETS; ui++) {
- if (r700->render_target[ui].enabled) {
- BEGIN_BATCH_NO_AUTOSTATE(3);
- R600_OUT_BATCH_REGVAL(CB_BLEND0_CONTROL + (4 * ui),
- r700->render_target[ui].CB_BLEND0_CONTROL.u32All);
- END_BATCH();
- }
- }
- }
-
- COMMIT_BATCH();
-}
-
-static void r700SendCBBlendColorState(struct gl_context *ctx, struct radeon_state_atom *atom)
-{
- context_t *context = R700_CONTEXT(ctx);
- R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
- BATCH_LOCALS(&context->radeon);
- radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
-
- BEGIN_BATCH_NO_AUTOSTATE(6);
- R600_OUT_BATCH_REGSEQ(CB_BLEND_RED, 4);
- R600_OUT_BATCH(r700->CB_BLEND_RED.u32All);
- R600_OUT_BATCH(r700->CB_BLEND_GREEN.u32All);
- R600_OUT_BATCH(r700->CB_BLEND_BLUE.u32All);
- R600_OUT_BATCH(r700->CB_BLEND_ALPHA.u32All);
- END_BATCH();
- COMMIT_BATCH();
-}
-
-static void r700SendSUState(struct gl_context *ctx, struct radeon_state_atom *atom)
-{
- context_t *context = R700_CONTEXT(ctx);
- R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
- BATCH_LOCALS(&context->radeon);
-
- BEGIN_BATCH_NO_AUTOSTATE(9);
- R600_OUT_BATCH_REGVAL(PA_SU_SC_MODE_CNTL, r700->PA_SU_SC_MODE_CNTL.u32All);
- R600_OUT_BATCH_REGSEQ(PA_SU_POINT_SIZE, 4);
- R600_OUT_BATCH(r700->PA_SU_POINT_SIZE.u32All);
- R600_OUT_BATCH(r700->PA_SU_POINT_MINMAX.u32All);
- R600_OUT_BATCH(r700->PA_SU_LINE_CNTL.u32All);
- R600_OUT_BATCH(r700->PA_SU_VTX_CNTL.u32All);
- END_BATCH();
- COMMIT_BATCH();
-
-}
-
-static void r700SendPolyState(struct gl_context *ctx, struct radeon_state_atom *atom)
-{
- context_t *context = R700_CONTEXT(ctx);
- R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
- BATCH_LOCALS(&context->radeon);
-
- BEGIN_BATCH_NO_AUTOSTATE(10);
- R600_OUT_BATCH_REGSEQ(PA_SU_POLY_OFFSET_DB_FMT_CNTL, 2);
- R600_OUT_BATCH(r700->PA_SU_POLY_OFFSET_DB_FMT_CNTL.u32All);
- R600_OUT_BATCH(r700->PA_SU_POLY_OFFSET_CLAMP.u32All);
- R600_OUT_BATCH_REGSEQ(PA_SU_POLY_OFFSET_FRONT_SCALE, 4);
- R600_OUT_BATCH(r700->PA_SU_POLY_OFFSET_FRONT_SCALE.u32All);
- R600_OUT_BATCH(r700->PA_SU_POLY_OFFSET_FRONT_OFFSET.u32All);
- R600_OUT_BATCH(r700->PA_SU_POLY_OFFSET_BACK_SCALE.u32All);
- R600_OUT_BATCH(r700->PA_SU_POLY_OFFSET_BACK_OFFSET.u32All);
- END_BATCH();
- COMMIT_BATCH();
-
-}
-
-static void r700SendCLState(struct gl_context *ctx, struct radeon_state_atom *atom)
-{
- context_t *context = R700_CONTEXT(ctx);
- R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
- BATCH_LOCALS(&context->radeon);
- radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
-
- BEGIN_BATCH_NO_AUTOSTATE(12);
- R600_OUT_BATCH_REGVAL(PA_CL_CLIP_CNTL, r700->PA_CL_CLIP_CNTL.u32All);
- R600_OUT_BATCH_REGVAL(PA_CL_VTE_CNTL, r700->PA_CL_VTE_CNTL.u32All);
- R600_OUT_BATCH_REGVAL(PA_CL_VS_OUT_CNTL, r700->PA_CL_VS_OUT_CNTL.u32All);
- R600_OUT_BATCH_REGVAL(PA_CL_NANINF_CNTL, r700->PA_CL_NANINF_CNTL.u32All);
- END_BATCH();
- COMMIT_BATCH();
-}
-
-static void r700SendGBState(struct gl_context *ctx, struct radeon_state_atom *atom)
-{
- context_t *context = R700_CONTEXT(ctx);
- R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
- BATCH_LOCALS(&context->radeon);
-
- BEGIN_BATCH_NO_AUTOSTATE(6);
- R600_OUT_BATCH_REGSEQ(PA_CL_GB_VERT_CLIP_ADJ, 4);
- R600_OUT_BATCH(r700->PA_CL_GB_VERT_CLIP_ADJ.u32All);
- R600_OUT_BATCH(r700->PA_CL_GB_VERT_DISC_ADJ.u32All);
- R600_OUT_BATCH(r700->PA_CL_GB_HORZ_CLIP_ADJ.u32All);
- R600_OUT_BATCH(r700->PA_CL_GB_HORZ_DISC_ADJ.u32All);
- END_BATCH();
- COMMIT_BATCH();
-}
-
-static void r700SendScissorState(struct gl_context *ctx, struct radeon_state_atom *atom)
-{
- context_t *context = R700_CONTEXT(ctx);
- R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
- BATCH_LOCALS(&context->radeon);
- radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
-
- BEGIN_BATCH_NO_AUTOSTATE(22);
- R600_OUT_BATCH_REGSEQ(PA_SC_SCREEN_SCISSOR_TL, 2);
- R600_OUT_BATCH(r700->PA_SC_SCREEN_SCISSOR_TL.u32All);
- R600_OUT_BATCH(r700->PA_SC_SCREEN_SCISSOR_BR.u32All);
-
- R600_OUT_BATCH_REGSEQ(PA_SC_WINDOW_OFFSET, 12);
- R600_OUT_BATCH(r700->PA_SC_WINDOW_OFFSET.u32All);
- R600_OUT_BATCH(r700->PA_SC_WINDOW_SCISSOR_TL.u32All);
- R600_OUT_BATCH(r700->PA_SC_WINDOW_SCISSOR_BR.u32All);
- R600_OUT_BATCH(r700->PA_SC_CLIPRECT_RULE.u32All);
- R600_OUT_BATCH(r700->PA_SC_CLIPRECT_0_TL.u32All);
- R600_OUT_BATCH(r700->PA_SC_CLIPRECT_0_BR.u32All);
- R600_OUT_BATCH(r700->PA_SC_CLIPRECT_1_TL.u32All);
- R600_OUT_BATCH(r700->PA_SC_CLIPRECT_1_BR.u32All);
- R600_OUT_BATCH(r700->PA_SC_CLIPRECT_2_TL.u32All);
- R600_OUT_BATCH(r700->PA_SC_CLIPRECT_2_BR.u32All);
- R600_OUT_BATCH(r700->PA_SC_CLIPRECT_3_TL.u32All);
- R600_OUT_BATCH(r700->PA_SC_CLIPRECT_3_BR.u32All);
-
- R600_OUT_BATCH_REGSEQ(PA_SC_GENERIC_SCISSOR_TL, 2);
- R600_OUT_BATCH(r700->PA_SC_GENERIC_SCISSOR_TL.u32All);
- R600_OUT_BATCH(r700->PA_SC_GENERIC_SCISSOR_BR.u32All);
- END_BATCH();
- COMMIT_BATCH();
-}
-
-static void r700SendSCState(struct gl_context *ctx, struct radeon_state_atom *atom)
-{
- context_t *context = R700_CONTEXT(ctx);
- R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
- BATCH_LOCALS(&context->radeon);
- radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
-
- BEGIN_BATCH_NO_AUTOSTATE(15);
- R600_OUT_BATCH_REGVAL(R7xx_PA_SC_EDGERULE, r700->PA_SC_EDGERULE.u32All);
- R600_OUT_BATCH_REGVAL(PA_SC_LINE_STIPPLE, r700->PA_SC_LINE_STIPPLE.u32All);
- R600_OUT_BATCH_REGVAL(PA_SC_MPASS_PS_CNTL, r700->PA_SC_MPASS_PS_CNTL.u32All);
- R600_OUT_BATCH_REGVAL(PA_SC_MODE_CNTL, r700->PA_SC_MODE_CNTL.u32All);
- R600_OUT_BATCH_REGVAL(PA_SC_LINE_CNTL, r700->PA_SC_LINE_CNTL.u32All);
- END_BATCH();
- COMMIT_BATCH();
-}
-
-static void r700SendAAState(struct gl_context *ctx, struct radeon_state_atom *atom)
-{
- context_t *context = R700_CONTEXT(ctx);
- R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
- BATCH_LOCALS(&context->radeon);
-
- BEGIN_BATCH_NO_AUTOSTATE(12);
- R600_OUT_BATCH_REGVAL(PA_SC_AA_CONFIG, r700->PA_SC_AA_CONFIG.u32All);
- R600_OUT_BATCH_REGVAL(PA_SC_AA_SAMPLE_LOCS_MCTX, r700->PA_SC_AA_SAMPLE_LOCS_MCTX.u32All);
- R600_OUT_BATCH_REGVAL(PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX, r700->PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX.u32All);
- R600_OUT_BATCH_REGVAL(PA_SC_AA_MASK, r700->PA_SC_AA_MASK.u32All);
- END_BATCH();
- COMMIT_BATCH();
-}
-
-static void r700SendPSConsts(struct gl_context *ctx, struct radeon_state_atom *atom)
-{
- context_t *context = R700_CONTEXT(ctx);
- R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
- int i;
- BATCH_LOCALS(&context->radeon);
-
- if (r700->ps.num_consts == 0)
- return;
-
- BEGIN_BATCH_NO_AUTOSTATE(2 + (r700->ps.num_consts * 4));
- R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_ALU_CONST, (r700->ps.num_consts * 4)));
- /* assembler map const from very beginning. */
- R600_OUT_BATCH(SQ_ALU_CONSTANT_PS_OFFSET * 4);
- for (i = 0; i < r700->ps.num_consts; i++) {
- R600_OUT_BATCH(r700->ps.consts[i][0].u32All);
- R600_OUT_BATCH(r700->ps.consts[i][1].u32All);
- R600_OUT_BATCH(r700->ps.consts[i][2].u32All);
- R600_OUT_BATCH(r700->ps.consts[i][3].u32All);
- }
- END_BATCH();
- COMMIT_BATCH();
-}
-
-static void r700SendVSConsts(struct gl_context *ctx, struct radeon_state_atom *atom)
-{
- context_t *context = R700_CONTEXT(ctx);
- R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
- int i;
- BATCH_LOCALS(&context->radeon);
- radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
-
- if (r700->vs.num_consts == 0)
- return;
-
- BEGIN_BATCH_NO_AUTOSTATE(2 + (r700->vs.num_consts * 4));
- R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_ALU_CONST, (r700->vs.num_consts * 4)));
- /* assembler map const from very beginning. */
- R600_OUT_BATCH(SQ_ALU_CONSTANT_VS_OFFSET * 4);
- for (i = 0; i < r700->vs.num_consts; i++) {
- R600_OUT_BATCH(r700->vs.consts[i][0].u32All);
- R600_OUT_BATCH(r700->vs.consts[i][1].u32All);
- R600_OUT_BATCH(r700->vs.consts[i][2].u32All);
- R600_OUT_BATCH(r700->vs.consts[i][3].u32All);
- }
- END_BATCH();
- COMMIT_BATCH();
-}
-
-static void r700SendQueryBegin(struct gl_context *ctx, struct radeon_state_atom *atom)
-{
- radeonContextPtr radeon = RADEON_CONTEXT(ctx);
- struct radeon_query_object *query = radeon->query.current;
- BATCH_LOCALS(radeon);
- radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
-
- /* clear the buffer */
- radeon_bo_map(query->bo, GL_FALSE);
- memset(query->bo->ptr, 0, 4 * 2 * sizeof(uint64_t)); /* 4 DBs, 2 qwords each */
- radeon_bo_unmap(query->bo);
-
- radeon_cs_space_check_with_bo(radeon->cmdbuf.cs,
- query->bo,
- 0, RADEON_GEM_DOMAIN_GTT);
-
- BEGIN_BATCH_NO_AUTOSTATE(4 + 2);
- R600_OUT_BATCH(CP_PACKET3(R600_IT_EVENT_WRITE, 2));
- R600_OUT_BATCH(R600_EVENT_TYPE(ZPASS_DONE) | R600_EVENT_INDEX(1));
- R600_OUT_BATCH(query->curr_offset); /* hw writes qwords */
- R600_OUT_BATCH(0x00000000);
- R600_OUT_BATCH_RELOC(VGT_EVENT_INITIATOR, query->bo, 0, 0, RADEON_GEM_DOMAIN_GTT, 0);
- END_BATCH();
- query->emitted_begin = GL_TRUE;
-}
-
-static int check_always(struct gl_context *ctx, struct radeon_state_atom *atom)
-{
- return atom->cmd_size;
-}
-
-static int check_cb(struct gl_context *ctx, struct radeon_state_atom *atom)
-{
- context_t *context = R700_CONTEXT(ctx);
- int count = 7;
-
- if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
- count += 11;
- radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
-
- return count;
-}
-
-static int check_blnd(struct gl_context *ctx, struct radeon_state_atom *atom)
-{
- context_t *context = R700_CONTEXT(ctx);
- R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
- unsigned int ui;
- int count = 3;
-
- if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
- count += 3;
-
- if (context->radeon.radeonScreen->chip_family > CHIP_FAMILY_R600) {
- /* targets are enabled in r700SetRenderTarget but state
- size is calculated before that. Until MRT's are done
- hardcode target0 as enabled. */
- count += 3;
- for (ui = 1; ui < R700_MAX_RENDER_TARGETS; ui++) {
- if (r700->render_target[ui].enabled)
- count += 3;
- }
- }
- radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
-
- return count;
-}
-
-static int check_ucp(struct gl_context *ctx, struct radeon_state_atom *atom)
-{
- context_t *context = R700_CONTEXT(ctx);
- R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
- int i;
- int count = 0;
-
- for (i = 0; i < R700_MAX_UCP; i++) {
- if (r700->ucp[i].enabled)
- count += 6;
- }
- radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
- return count;
-}
-
-static int check_vtx(struct gl_context *ctx, struct radeon_state_atom *atom)
-{
- context_t *context = R700_CONTEXT(ctx);
- int count = context->radeon.tcl.aos_count * 18;
-
- radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
- return count;
-}
-
-static int check_tx(struct gl_context *ctx, struct radeon_state_atom *atom)
-{
- context_t *context = R700_CONTEXT(ctx);
- unsigned int i, count = 0;
- R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
-
- for (i = 0; i < R700_TEXTURE_NUMBERUNITS; i++) {
- if (ctx->Texture.Unit[i]._ReallyEnabled) {
- radeonTexObj *t = r700->textures[i];
- if (t)
- count++;
- }
- }
- radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
- return count * 31;
-}
-
-static int check_ps_consts(struct gl_context *ctx, struct radeon_state_atom *atom)
-{
- context_t *context = R700_CONTEXT(ctx);
- R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
- int count = r700->ps.num_consts * 4;
-
- if (count)
- count += 2;
- radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
-
- return count;
-}
-
-static int check_vs_consts(struct gl_context *ctx, struct radeon_state_atom *atom)
-{
- context_t *context = R700_CONTEXT(ctx);
- R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
- int count = r700->vs.num_consts * 4;
-
- if (count)
- count += 2;
- radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
-
- return count;
-}
-
-static int check_queryobj(struct gl_context *ctx, struct radeon_state_atom *atom)
-{
- radeonContextPtr radeon = RADEON_CONTEXT(ctx);
- struct radeon_query_object *query = radeon->query.current;
- int count;
-
- if (!query || query->emitted_begin)
- count = 0;
- else
- count = atom->cmd_size;
- radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
- return count;
-}
-
-#define ALLOC_STATE( ATOM, CHK, SZ, EMIT ) \
-do { \
- context->atoms.ATOM.cmd_size = (SZ); \
- context->atoms.ATOM.cmd = NULL; \
- context->atoms.ATOM.name = #ATOM; \
- context->atoms.ATOM.idx = 0; \
- context->atoms.ATOM.check = check_##CHK; \
- context->atoms.ATOM.dirty = GL_FALSE; \
- context->atoms.ATOM.emit = (EMIT); \
- context->radeon.hw.max_state_size += (SZ); \
- insert_at_tail(&context->radeon.hw.atomlist, &context->atoms.ATOM); \
-} while (0)
-
-static void r600_init_query_stateobj(radeonContextPtr radeon, int SZ)
-{
- radeon->query.queryobj.cmd_size = (SZ);
- radeon->query.queryobj.cmd = NULL;
- radeon->query.queryobj.name = "queryobj";
- radeon->query.queryobj.idx = 0;
- radeon->query.queryobj.check = check_queryobj;
- radeon->query.queryobj.dirty = GL_FALSE;
- radeon->query.queryobj.emit = r700SendQueryBegin;
- radeon->hw.max_state_size += (SZ);
- insert_at_tail(&radeon->hw.atomlist, &radeon->query.queryobj);
-}
-
-void r600InitAtoms(context_t *context)
-{
- R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
- radeon_print(RADEON_STATE, RADEON_NORMAL, "%s %p\n", __func__, context);
- context->radeon.hw.max_state_size = 10 + 5 + 14; /* start 3d, idle, cb/db flush */
-
- /* Setup the atom linked list */
- make_empty_list(&context->radeon.hw.atomlist);
- context->radeon.hw.atomlist.name = "atom-list";
-
- ALLOC_STATE(sq, always, 34, r700SendSQConfig);
- ALLOC_STATE(db, always, 17, r700SendDBState);
- ALLOC_STATE(stencil, always, 4, r700SendStencilState);
- ALLOC_STATE(db_target, always, 16, r700SendDepthTargetState);
- ALLOC_STATE(sc, always, 15, r700SendSCState);
- ALLOC_STATE(scissor, always, 22, r700SendScissorState);
- ALLOC_STATE(aa, always, 12, r700SendAAState);
- ALLOC_STATE(cl, always, 12, r700SendCLState);
- ALLOC_STATE(gb, always, 6, r700SendGBState);
- ALLOC_STATE(ucp, ucp, (R700_MAX_UCP * 6), r700SendUCPState);
- ALLOC_STATE(su, always, 9, r700SendSUState);
- ALLOC_STATE(poly, always, 10, r700SendPolyState);
- ALLOC_STATE(cb, cb, 18, r700SendCBState);
- ALLOC_STATE(clrcmp, always, 6, r700SendCBCLRCMPState);
- ALLOC_STATE(cb_target, always, 31, r700SendRenderTargetState);
- ALLOC_STATE(blnd, blnd, (6 + (R700_MAX_RENDER_TARGETS * 3)), r700SendCBBlendState);
- ALLOC_STATE(blnd_clr, always, 6, r700SendCBBlendColorState);
- ALLOC_STATE(sx, always, 9, r700SendSXState);
- ALLOC_STATE(vgt, always, 41, r700SendVGTState);
- ALLOC_STATE(spi, always, (59 + R700_MAX_SHADER_EXPORTS), r700SendSPIState);
- ALLOC_STATE(vpt, always, 16, r700SendViewportState);
- ALLOC_STATE(fs, always, 18, r700SendFSState);
- if(GL_TRUE == r700->bShaderUseMemConstant)
- {
- ALLOC_STATE(vs, always, 36, r700SendVSState);
- ALLOC_STATE(ps, always, 24, r700SendPSState); /* TODO : not imp yet, fix later. */
- }
- else
- {
- ALLOC_STATE(vs, always, 21, r700SendVSState);
- ALLOC_STATE(ps, always, 24, r700SendPSState);
- ALLOC_STATE(vs_consts, vs_consts, (2 + (R700_MAX_DX9_CONSTS * 4)), r700SendVSConsts);
- ALLOC_STATE(ps_consts, ps_consts, (2 + (R700_MAX_DX9_CONSTS * 4)), r700SendPSConsts);
- }
-
- ALLOC_STATE(vtx, vtx, (VERT_ATTRIB_MAX * 18), r700SendVTXState);
- ALLOC_STATE(tx, tx, (R700_TEXTURE_NUMBERUNITS * 20), r700SendTexState);
- ALLOC_STATE(tx_smplr, tx, (R700_TEXTURE_NUMBERUNITS * 5), r700SendTexSamplerState);
- ALLOC_STATE(tx_brdr_clr, tx, (R700_TEXTURE_NUMBERUNITS * 6), r700SendTexBorderColorState);
- r600_init_query_stateobj(&context->radeon, 6 * 2);
-
- context->radeon.hw.is_dirty = GL_TRUE;
- context->radeon.hw.all_dirty = GL_TRUE;
-}
+++ /dev/null
-/*
- * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Authors:
- * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
- */
-
-#ifndef _R700_CHIP_H_
-#define _R700_CHIP_H_
-
-#include <GL/gl.h>
-
-#include "radeon_common_context.h"
-
-#include "r600_reg.h"
-#include "r600_reg_auto_r6xx.h"
-#include "r600_reg_r6xx.h"
-#include "r600_reg_r7xx.h"
-
-#include "r700_chipoffset.h"
-
-#define SETfield(x, val, shift, mask) ( (x) = ((x) & ~(mask)) | (((val) << (shift)) & (mask)) )/* u32All */
-#define CLEARfield(x, mask) ( (x) &= ~(mask) )
-#define SETbit(x, bit) ( (x) |= (bit) )
-#define CLEARbit(x, bit) ( (x) &= ~(bit) )
-
-#define GETbits(x, shift, mask) ( ((x) & (mask)) >> (shift) )
-
-#define R700_TEXTURE_NUMBERUNITS 16
-#define R700_MAX_RENDER_TARGETS 8
-#define R700_MAX_VIEWPORTS 16
-#define R700_MAX_SHADER_EXPORTS 32
-#define R700_MAX_UCP 6
-#define R700_MAX_DX9_CONSTS 256
-
-/* Enum not show in r600_*.h */
-
-#define FETCH_RESOURCE_STRIDE 7
-
-#define ASIC_CONFIG_BASE_INDEX 0x2000
-#define ASIC_CONTEXT_BASE_INDEX 0xA000
-#define ASIC_CTL_CONST_BASE_INDEX 0xF3FC
-
-
-enum
-{
- SQ_ABSOLUTE = 0x00000000,
- SQ_RELATIVE = 0x00000001,
-};
-
-enum
-{
- SQ_ALU_SCL_210 = 0x00000000,
- SQ_ALU_SCL_122 = 0x00000001,
- SQ_ALU_SCL_212 = 0x00000002,
- SQ_ALU_SCL_221 = 0x00000003,
-};
-
-enum
-{
- SQ_TEX_UNNORMALIZED = 0x00000000,
- SQ_TEX_NORMALIZED = 0x00000001,
-};
-
-enum
-{
- SQ_CF_PIXEL_MRT0 = 0x00000000,
- SQ_CF_PIXEL_MRT1 = 0x00000001,
- SQ_CF_PIXEL_MRT2 = 0x00000002,
- SQ_CF_PIXEL_MRT3 = 0x00000003,
- SQ_CF_PIXEL_MRT4 = 0x00000004,
- SQ_CF_PIXEL_MRT5 = 0x00000005,
- SQ_CF_PIXEL_MRT6 = 0x00000006,
- SQ_CF_PIXEL_MRT7 = 0x00000007,
- SQ_CF_PIXEL_Z = 0x0000003d,
-};
-
-typedef enum ENUM_SQ_CF_ARRAY_BASE_POS {
-SQ_CF_POS_0 = 0x0000003c,
-SQ_CF_POS_1 = 0x0000003d,
-SQ_CF_POS_2 = 0x0000003e,
-SQ_CF_POS_3 = 0x0000003f,
-} ENUM_SQ_CF_ARRAY_BASE_POS;
-
-enum
-{
- PGM_RESOURCES__PRIME_CACHE_ON_DRAW_bit = 23,
-};
-
-enum
-{
- TEX_XYFilter_Point = 0x00000000,
- TEX_XYFilter_Linear = 0x00000001,
- TEX_XYFilter_Cubic = 0x00000002,
- TEX_XYFilter_Cleartype = 0x00000003,
-
- TEX_MipFilter_None = 0x00000000,
- TEX_MipFilter_Point = 0x00000001,
- TEX_MipFilter_Linear = 0x00000002,
-};
-
-enum
-{
- SQ_EXPORT_WRITE = 0x00000000,
- SQ_EXPORT_WRITE_IND = 0x00000001,
- SQ_EXPORT_WRITE_ACK = 0x00000002,
- SQ_EXPORT_WRITE_IND_ACK = 0x00000003,
-};
-
-/* --------------------------------- */
-
-enum
-{
- R700_PM4_PACKET0_NOP = 0x00000000,
- R700_PM4_PACKET1_NOP = 0x40000000,
- R700_PM4_PACKET2_NOP = 0x80000000,
- R700_PM4_PACKET3_NOP = 0xC0000000,
-};
-
-#define PM4_OPCODE_SET_INDEX_TYPE (R700_PM4_PACKET3_NOP | (IT_INDEX_TYPE << 8))
-
-#define PM4_OPCODE_DRAW_INDEX_AUTO (R700_PM4_PACKET3_NOP | (IT_DRAW_INDEX_AUTO << 8))
-#define PM4_OPCODE_DRAW_INDEX_IMMD (R700_PM4_PACKET3_NOP | (IT_DRAW_INDEX_IMMD << 8))
-#define PM4_OPCODE_WAIT_REG_MEM (R700_PM4_PACKET3_NOP | (IT_WAIT_REG_MEM << 8))
-#define PM4_OPCODE_SET_CONTEXT_REG (R700_PM4_PACKET3_NOP | (IT_SET_CONTEXT_REG << 8))
-#define PM4_OPCODE_SET_CONFIG_REG (R700_PM4_PACKET3_NOP | (IT_SET_CONFIG_REG << 8))
-#define PM4_OPCODE_SET_ALU_CONST (R700_PM4_PACKET3_NOP | (IT_SET_ALU_CONST << 8))
-#define PM4_OPCODE_SET_RESOURCE (R700_PM4_PACKET3_NOP | (IT_SET_RESOURCE << 8))
-#define PM4_OPCODE_SET_SAMPLER (R700_PM4_PACKET3_NOP | (IT_SET_SAMPLER << 8))
-#define PM4_OPCODE_CONTEXT_CONTROL (R700_PM4_PACKET3_NOP | (IT_CONTEXT_CONTROL << 8))
-
-union UINT_FLOAT
-{
- unsigned int u32All;
- float f32All;
-};
-
-#if 0
-typedef struct _TEXTURE_STATE_STRUCT
-{
- union UINT_FLOAT SQ_TEX_RESOURCE0;
- union UINT_FLOAT SQ_TEX_RESOURCE1;
- union UINT_FLOAT SQ_TEX_RESOURCE2;
- union UINT_FLOAT SQ_TEX_RESOURCE3;
- union UINT_FLOAT SQ_TEX_RESOURCE4;
- union UINT_FLOAT SQ_TEX_RESOURCE5;
- union UINT_FLOAT SQ_TEX_RESOURCE6;
- GLboolean enabled;
-} TEXTURE_STATE_STRUCT;
-
-typedef struct _SAMPLER_STATE_STRUCT
-{
- union UINT_FLOAT SQ_TEX_SAMPLER0;
- union UINT_FLOAT SQ_TEX_SAMPLER1;
- union UINT_FLOAT SQ_TEX_SAMPLER2;
- GLboolean enabled;
-} SAMPLER_STATE_STRUCT;
-
-typedef struct _R700_TEXTURE_STATES
-{
- TEXTURE_STATE_STRUCT *textures[R700_TEXTURE_NUMBERUNITS];
- SAMPLER_STATE_STRUCT *samplers[R700_TEXTURE_NUMBERUNITS];
-} R700_TEXTURE_STATES;
-#endif
-
-typedef struct _RENDER_TARGET_STATE_STRUCT
-{
- union UINT_FLOAT CB_COLOR0_BASE; /* 0xA010 */
- union UINT_FLOAT CB_COLOR0_SIZE; /* 0xA018 */
- union UINT_FLOAT CB_COLOR0_VIEW; /* 0xA020 */
- union UINT_FLOAT CB_COLOR0_INFO; /* 0xA028 */
- union UINT_FLOAT CB_COLOR0_TILE; /* 0xA030 */
- union UINT_FLOAT CB_COLOR0_FRAG; /* 0xA038 */
- union UINT_FLOAT CB_COLOR0_MASK; /* 0xA040 */
- union UINT_FLOAT CB_BLEND0_CONTROL; /* 0xA1E0 */
- GLboolean enabled;
- GLboolean dirty;
-} RENDER_TARGET_STATE_STRUCT;
-
-typedef struct _VIEWPORT_STATE_STRUCT
-{
- union UINT_FLOAT PA_SC_VPORT_SCISSOR_0_TL; /* 0xA094 */
- union UINT_FLOAT PA_SC_VPORT_SCISSOR_0_BR; /* 0xA095 */
- union UINT_FLOAT PA_SC_VPORT_ZMIN_0; /* 0xA0B4 */
- union UINT_FLOAT PA_SC_VPORT_ZMAX_0; /* 0xA0B5 */
- union UINT_FLOAT PA_CL_VPORT_XSCALE; /* 0xA10F */
- union UINT_FLOAT PA_CL_VPORT_XOFFSET; /* 0xA110 */
- union UINT_FLOAT PA_CL_VPORT_YSCALE; /* 0xA111 */
- union UINT_FLOAT PA_CL_VPORT_YOFFSET; /* 0xA112 */
- union UINT_FLOAT PA_CL_VPORT_ZSCALE; /* 0xA113 */
- union UINT_FLOAT PA_CL_VPORT_ZOFFSET; /* 0xA114 */
- GLboolean enabled;
- GLboolean dirty;
-} VIEWPORT_STATE_STRUCT;
-
-typedef struct _UCP_STATE_STRUCT
-{
- union UINT_FLOAT PA_CL_UCP_0_X;
- union UINT_FLOAT PA_CL_UCP_0_Y;
- union UINT_FLOAT PA_CL_UCP_0_Z;
- union UINT_FLOAT PA_CL_UCP_0_W;
- GLboolean enabled;
- GLboolean dirty;
-} UCP_STATE_STRUCT;
-
-typedef struct _PS_STATE_STRUCT
-{
- union UINT_FLOAT SQ_PGM_START_PS ; /* 0xA210 */
- union UINT_FLOAT SQ_PGM_RESOURCES_PS ; /* 0xA214 */
- union UINT_FLOAT SQ_PGM_EXPORTS_PS ; /* 0xA215 */
- union UINT_FLOAT SQ_PGM_CF_OFFSET_PS ; /* 0xA233 */
- GLboolean dirty;
- int num_consts;
- union UINT_FLOAT consts[R700_MAX_DX9_CONSTS][4];
-} PS_STATE_STRUCT;
-
-typedef struct _VS_STATE_STRUCT
-{
- union UINT_FLOAT SQ_PGM_START_VS ; /* 0xA216 */
- union UINT_FLOAT SQ_PGM_RESOURCES_VS ; /* 0xA21A */
- union UINT_FLOAT SQ_PGM_CF_OFFSET_VS ; /* 0xA234 */
- GLboolean dirty;
- int num_consts;
-
- union UINT_FLOAT SQ_ALU_CONST_CACHE_VS_0;
-
- union UINT_FLOAT consts[R700_MAX_DX9_CONSTS][4];
-} VS_STATE_STRUCT;
-
-typedef struct _GS_STATE_STRUCT
-{
- union UINT_FLOAT SQ_PGM_START_GS ; /* 0xA21B */
- union UINT_FLOAT SQ_PGM_RESOURCES_GS ; /* 0xA21F */
- union UINT_FLOAT SQ_PGM_CF_OFFSET_GS ; /* 0xA235 */
- GLboolean dirty;
-} GS_STATE_STRUCT;
-
-typedef struct _ES_STATE_STRUCT
-{
- union UINT_FLOAT SQ_PGM_START_ES ; /* 0xA220 */
- union UINT_FLOAT SQ_PGM_RESOURCES_ES ; /* 0xA224 */
- union UINT_FLOAT SQ_PGM_CF_OFFSET_ES ; /* 0xA236 */
- GLboolean dirty;
-} ES_STATE_STRUCT;
-
-typedef struct _FS_STATE_STRUCT
-{
- union UINT_FLOAT SQ_PGM_START_FS ; /* 0xA225 */
- union UINT_FLOAT SQ_PGM_RESOURCES_FS ; /* 0xA229 */
- union UINT_FLOAT SQ_PGM_CF_OFFSET_FS ; /* 0xA237 */
- GLboolean dirty;
-} FS_STATE_STRUCT;
-
-typedef struct _SQ_CONFIG_STRUCT
-{
- union UINT_FLOAT SQ_CONFIG ; /* 0x2300 */
- union UINT_FLOAT SQ_GPR_RESOURCE_MGMT_1 ; /* 0x2301 */
- union UINT_FLOAT SQ_GPR_RESOURCE_MGMT_2 ; /* 0x2302 */
- union UINT_FLOAT SQ_THREAD_RESOURCE_MGMT ; /* 0x2303 */
- union UINT_FLOAT SQ_STACK_RESOURCE_MGMT_1 ; /* 0x2304 */
- union UINT_FLOAT SQ_STACK_RESOURCE_MGMT_2 ; /* 0x2305 */
-} SQ_CONFIG_STRUCT;
-
-typedef struct _R700_CHIP_CONTEXT
-{
- // DB
- union UINT_FLOAT DB_DEPTH_SIZE ; /* 0xA000 */
- union UINT_FLOAT DB_DEPTH_VIEW ; /* 0xA001 */
- union UINT_FLOAT DB_DEPTH_BASE ; /* 0xA003 */
- union UINT_FLOAT DB_DEPTH_INFO ; /* 0xA004 */
- GLboolean db_target_dirty;
- union UINT_FLOAT DB_HTILE_DATA_BASE ; /* 0xA005 */
- union UINT_FLOAT DB_STENCIL_CLEAR ; /* 0xA00A */
- union UINT_FLOAT DB_DEPTH_CLEAR ; /* 0xA00B */
- union UINT_FLOAT DB_STENCILREFMASK ; /* 0xA10C */
- union UINT_FLOAT DB_STENCILREFMASK_BF ; /* 0xA10D */
- union UINT_FLOAT DB_RENDER_CONTROL ; /* 0xA343 */
- union UINT_FLOAT DB_RENDER_OVERRIDE ; /* 0xA344 */
- union UINT_FLOAT DB_HTILE_SURFACE ; /* 0xA349 */
- union UINT_FLOAT DB_ALPHA_TO_MASK ; /* 0xA351 */
- union UINT_FLOAT DB_DEPTH_CONTROL ; /* 0xA200 */
- union UINT_FLOAT DB_SHADER_CONTROL ; /* 0xA203 */
- GLboolean db_dirty;
-
- // SC
- union UINT_FLOAT PA_SC_SCREEN_SCISSOR_TL ; /* 0xA00C */
- union UINT_FLOAT PA_SC_SCREEN_SCISSOR_BR ; /* 0xA00D */
- union UINT_FLOAT PA_SC_WINDOW_OFFSET ; /* 0xA080 */
- union UINT_FLOAT PA_SC_WINDOW_SCISSOR_TL ; /* 0xA081 */
- union UINT_FLOAT PA_SC_WINDOW_SCISSOR_BR ; /* 0xA082 */
- union UINT_FLOAT PA_SC_CLIPRECT_RULE ; /* 0xA083 */
- union UINT_FLOAT PA_SC_CLIPRECT_0_TL ; /* 0xA084 */
- union UINT_FLOAT PA_SC_CLIPRECT_0_BR ; /* 0xA085 */
- union UINT_FLOAT PA_SC_CLIPRECT_1_TL ; /* 0xA086 */
- union UINT_FLOAT PA_SC_CLIPRECT_1_BR ; /* 0xA087 */
- union UINT_FLOAT PA_SC_CLIPRECT_2_TL ; /* 0xA088 */
- union UINT_FLOAT PA_SC_CLIPRECT_2_BR ; /* 0xA089 */
- union UINT_FLOAT PA_SC_CLIPRECT_3_TL ; /* 0xA08A */
- union UINT_FLOAT PA_SC_CLIPRECT_3_BR ; /* 0xA08B */
- union UINT_FLOAT PA_SC_EDGERULE ; /* 0xA08C */
- union UINT_FLOAT PA_SC_GENERIC_SCISSOR_TL ; /* 0xA090 */
- union UINT_FLOAT PA_SC_GENERIC_SCISSOR_BR ; /* 0xA091 */
- GLboolean scissor_dirty;
-
- union UINT_FLOAT PA_SC_LINE_STIPPLE ; /* 0xA283 */
- union UINT_FLOAT PA_SC_LINE_CNTL ; /* 0xA300 */
- union UINT_FLOAT PA_SC_AA_CONFIG ; /* 0xA301 */
- union UINT_FLOAT PA_SC_MPASS_PS_CNTL ; /* 0xA292 */
- union UINT_FLOAT PA_SC_MODE_CNTL ; /* 0xA293 */
- union UINT_FLOAT PA_SC_AA_SAMPLE_LOCS_MCTX ; /* 0xA307 */
- union UINT_FLOAT PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX; /* 0xA308 */
- union UINT_FLOAT PA_SC_AA_MASK ; /* 0xA312 */
- GLboolean sc_dirty;
-
- // CL
- union UINT_FLOAT PA_CL_CLIP_CNTL ; /* 0xA204 */
- union UINT_FLOAT PA_CL_VTE_CNTL ; /* 0xA206 */
- union UINT_FLOAT PA_CL_VS_OUT_CNTL ; /* 0xA207 */
- union UINT_FLOAT PA_CL_NANINF_CNTL ; /* 0xA208 */
- union UINT_FLOAT PA_CL_GB_VERT_CLIP_ADJ ; /* 0xA303 */
- union UINT_FLOAT PA_CL_GB_VERT_DISC_ADJ ; /* 0xA304 */
- union UINT_FLOAT PA_CL_GB_HORZ_CLIP_ADJ ; /* 0xA305 */
- union UINT_FLOAT PA_CL_GB_HORZ_DISC_ADJ ; /* 0xA306 */
- GLboolean cl_dirty;
-
- // SU
- union UINT_FLOAT PA_SU_SC_MODE_CNTL ; /* 0xA205 */
- union UINT_FLOAT PA_SU_POINT_SIZE ; /* 0xA280 */
- union UINT_FLOAT PA_SU_POINT_MINMAX ; /* 0xA281 */
- union UINT_FLOAT PA_SU_LINE_CNTL ; /* 0xA282 */
- union UINT_FLOAT PA_SU_VTX_CNTL ; /* 0xA302 */
- union UINT_FLOAT PA_SU_POLY_OFFSET_DB_FMT_CNTL; /* 0xA37E */
- union UINT_FLOAT PA_SU_POLY_OFFSET_CLAMP ; /* 0xA37F */
- union UINT_FLOAT PA_SU_POLY_OFFSET_FRONT_SCALE; /* 0xA380 */
- union UINT_FLOAT PA_SU_POLY_OFFSET_FRONT_OFFSET; /* 0xA381 */
- union UINT_FLOAT PA_SU_POLY_OFFSET_BACK_SCALE; /* 0xA382 */
- union UINT_FLOAT PA_SU_POLY_OFFSET_BACK_OFFSET; /* 0xA383 */
- GLboolean su_dirty;
-
- VIEWPORT_STATE_STRUCT viewport[R700_MAX_VIEWPORTS];
- UCP_STATE_STRUCT ucp[R700_MAX_UCP];
-
- // CB
- union UINT_FLOAT CB_CLEAR_RED_R6XX ; /* 0xA048 */
- union UINT_FLOAT CB_CLEAR_GREEN_R6XX ; /* 0xA049 */
- union UINT_FLOAT CB_CLEAR_BLUE_R6XX ; /* 0xA04A */
- union UINT_FLOAT CB_CLEAR_ALPHA_R6XX ; /* 0xA04B */
- union UINT_FLOAT CB_TARGET_MASK ; /* 0xA08E */
- union UINT_FLOAT CB_SHADER_MASK ; /* 0xA08F */
- union UINT_FLOAT CB_BLEND_RED ; /* 0xA105 */
- union UINT_FLOAT CB_BLEND_GREEN ; /* 0xA106 */
- union UINT_FLOAT CB_BLEND_BLUE ; /* 0xA107 */
- union UINT_FLOAT CB_BLEND_ALPHA ; /* 0xA108 */
- union UINT_FLOAT CB_FOG_RED_R6XX ; /* 0xA109 */
- union UINT_FLOAT CB_FOG_GREEN_R6XX ; /* 0xA10A */
- union UINT_FLOAT CB_FOG_BLUE_R6XX ; /* 0xA10B */
- union UINT_FLOAT CB_SHADER_CONTROL ; /* 0xA1E8 */
- union UINT_FLOAT CB_COLOR_CONTROL ; /* 0xA202 */
- union UINT_FLOAT CB_CLRCMP_CONTROL ; /* 0xA30C */
- union UINT_FLOAT CB_CLRCMP_SRC ; /* 0xA30D */
- union UINT_FLOAT CB_CLRCMP_DST ; /* 0xA30E */
- union UINT_FLOAT CB_CLRCMP_MSK ; /* 0xA30F */
- union UINT_FLOAT CB_BLEND_CONTROL ; /* 0xABD0 */
- GLboolean cb_dirty;
- RENDER_TARGET_STATE_STRUCT render_target[R700_MAX_RENDER_TARGETS];
-
- // SX
- union UINT_FLOAT SX_MISC ; /* 0xA0D4 */
- union UINT_FLOAT SX_ALPHA_TEST_CONTROL ; /* 0xA104 */
- union UINT_FLOAT SX_ALPHA_REF ; /* 0xA10E */
- GLboolean sx_dirty;
-
- // VGT
- union UINT_FLOAT VGT_MAX_VTX_INDX ; /* 0xA100 */
- union UINT_FLOAT VGT_MIN_VTX_INDX ; /* 0xA101 */
- union UINT_FLOAT VGT_INDX_OFFSET ; /* 0xA102 */
- union UINT_FLOAT VGT_MULTI_PRIM_IB_RESET_INDX; /* 0xA103 */
- union UINT_FLOAT VGT_OUTPUT_PATH_CNTL ; /* 0xA284 */
- union UINT_FLOAT VGT_HOS_CNTL ; /* 0xA285 */
- union UINT_FLOAT VGT_HOS_MAX_TESS_LEVEL ; /* 0xA286 */
- union UINT_FLOAT VGT_HOS_MIN_TESS_LEVEL ; /* 0xA287 */
- union UINT_FLOAT VGT_HOS_REUSE_DEPTH ; /* 0xA288 */
- union UINT_FLOAT VGT_GROUP_PRIM_TYPE ; /* 0xA289 */
- union UINT_FLOAT VGT_GROUP_FIRST_DECR ; /* 0xA28A */
- union UINT_FLOAT VGT_GROUP_DECR ; /* 0xA28B */
- union UINT_FLOAT VGT_GROUP_VECT_0_CNTL ; /* 0xA28C */
- union UINT_FLOAT VGT_GROUP_VECT_1_CNTL ; /* 0xA28D */
- union UINT_FLOAT VGT_GROUP_VECT_0_FMT_CNTL ; /* 0xA28E */
- union UINT_FLOAT VGT_GROUP_VECT_1_FMT_CNTL ; /* 0xA28F */
- union UINT_FLOAT VGT_GS_MODE ; /* 0xA290 */
- union UINT_FLOAT VGT_PRIMITIVEID_EN ; /* 0xA2A1 */
- union UINT_FLOAT VGT_MULTI_PRIM_IB_RESET_EN; /* 0xA2A5 */
- union UINT_FLOAT VGT_INSTANCE_STEP_RATE_0 ; /* 0xA2A8 */
- union UINT_FLOAT VGT_INSTANCE_STEP_RATE_1 ; /* 0xA2A9 */
- union UINT_FLOAT VGT_STRMOUT_EN ; /* 0xA2AC */
- union UINT_FLOAT VGT_REUSE_OFF ; /* 0xA2AD */
- union UINT_FLOAT VGT_VTX_CNT_EN ; /* 0xA2AE */
- union UINT_FLOAT VGT_STRMOUT_BUFFER_EN ; /* 0xA2C8 */
- GLboolean vgt_dirty;
-
- // SPI
- union UINT_FLOAT SPI_VS_OUT_ID_0 ; /* 0xA185 */
- union UINT_FLOAT SPI_VS_OUT_ID_1 ; /* 0xA186 */
- union UINT_FLOAT SPI_VS_OUT_ID_2 ; /* 0xA187 */
- union UINT_FLOAT SPI_VS_OUT_ID_3 ; /* 0xA188 */
- union UINT_FLOAT SPI_VS_OUT_ID_4 ; /* 0xA189 */
- union UINT_FLOAT SPI_VS_OUT_ID_5 ; /* 0xA18A */
- union UINT_FLOAT SPI_VS_OUT_ID_6 ; /* 0xA18B */
- union UINT_FLOAT SPI_VS_OUT_ID_7 ; /* 0xA18C */
- union UINT_FLOAT SPI_VS_OUT_ID_8 ; /* 0xA18D */
- union UINT_FLOAT SPI_VS_OUT_ID_9 ; /* 0xA18E */
- union UINT_FLOAT SPI_VS_OUT_CONFIG ; /* 0xA1B1 */
- union UINT_FLOAT SPI_THREAD_GROUPING ; /* 0xA1B2 */
- union UINT_FLOAT SPI_PS_IN_CONTROL_0 ; /* 0xA1B3 */
- union UINT_FLOAT SPI_PS_IN_CONTROL_1 ; /* 0xA1B4 */
- union UINT_FLOAT SPI_INTERP_CONTROL_0 ; /* 0xA1B5 */
- union UINT_FLOAT SPI_INPUT_Z ; /* 0xA1B6 */
- union UINT_FLOAT SPI_FOG_CNTL ; /* 0xA1B7 */
- union UINT_FLOAT SPI_FOG_FUNC_SCALE ; /* 0xA1B8 */
- union UINT_FLOAT SPI_FOG_FUNC_BIAS ; /* 0xA1B9 */
-
- union UINT_FLOAT SQ_VTX_SEMANTIC_0 ; /* 0xA0E0 */
- union UINT_FLOAT SQ_VTX_SEMANTIC_1 ; /* 0xA0E1 */
- union UINT_FLOAT SQ_VTX_SEMANTIC_2 ; /* 0xA0E2 */
- union UINT_FLOAT SQ_VTX_SEMANTIC_3 ; /* 0xA0E3 */
- union UINT_FLOAT SQ_VTX_SEMANTIC_4 ; /* 0xA0E4 */
- union UINT_FLOAT SQ_VTX_SEMANTIC_5 ; /* 0xA0E5 */
- union UINT_FLOAT SQ_VTX_SEMANTIC_6 ; /* 0xA0E6 */
- union UINT_FLOAT SQ_VTX_SEMANTIC_7 ; /* 0xA0E7 */
- union UINT_FLOAT SQ_VTX_SEMANTIC_8 ; /* 0xA0E8 */
- union UINT_FLOAT SQ_VTX_SEMANTIC_9 ; /* 0xA0E9 */
- union UINT_FLOAT SQ_VTX_SEMANTIC_10 ; /* 0xA0EA */
- union UINT_FLOAT SQ_VTX_SEMANTIC_11 ; /* 0xA0EB */
- union UINT_FLOAT SQ_VTX_SEMANTIC_12 ; /* 0xA0EC */
- union UINT_FLOAT SQ_VTX_SEMANTIC_13 ; /* 0xA0ED */
- union UINT_FLOAT SQ_VTX_SEMANTIC_14 ; /* 0xA0EE */
- union UINT_FLOAT SQ_VTX_SEMANTIC_15 ; /* 0xA0EF */
- union UINT_FLOAT SQ_VTX_SEMANTIC_16 ; /* 0xA0F0 */
- union UINT_FLOAT SQ_VTX_SEMANTIC_17 ; /* 0xA0F1 */
- union UINT_FLOAT SQ_VTX_SEMANTIC_18 ; /* 0xA0F2 */
- union UINT_FLOAT SQ_VTX_SEMANTIC_19 ; /* 0xA0F3 */
- union UINT_FLOAT SQ_VTX_SEMANTIC_20 ; /* 0xA0F4 */
- union UINT_FLOAT SQ_VTX_SEMANTIC_21 ; /* 0xA0F5 */
- union UINT_FLOAT SQ_VTX_SEMANTIC_22 ; /* 0xA0F6 */
- union UINT_FLOAT SQ_VTX_SEMANTIC_23 ; /* 0xA0F7 */
- union UINT_FLOAT SQ_VTX_SEMANTIC_24 ; /* 0xA0F8 */
- union UINT_FLOAT SQ_VTX_SEMANTIC_25 ; /* 0xA0F9 */
- union UINT_FLOAT SQ_VTX_SEMANTIC_26 ; /* 0xA0FA */
- union UINT_FLOAT SQ_VTX_SEMANTIC_27 ; /* 0xA0FB */
- union UINT_FLOAT SQ_VTX_SEMANTIC_28 ; /* 0xA0FC */
- union UINT_FLOAT SQ_VTX_SEMANTIC_29 ; /* 0xA0FD */
- union UINT_FLOAT SQ_VTX_SEMANTIC_30 ; /* 0xA0FE */
- union UINT_FLOAT SQ_VTX_SEMANTIC_31 ; /* 0xA0FF */
- union UINT_FLOAT SPI_PS_INPUT_CNTL[R700_MAX_SHADER_EXPORTS];
- GLboolean spi_dirty;
-
- // shaders
- PS_STATE_STRUCT ps;
- VS_STATE_STRUCT vs;
- GS_STATE_STRUCT gs;
- ES_STATE_STRUCT es;
- FS_STATE_STRUCT fs;
-
- // SQ CONFIG
- SQ_CONFIG_STRUCT sq_config;
- // misc
- union UINT_FLOAT TA_CNTL_AUX ; /* 0x2542 */
- union UINT_FLOAT VC_ENHANCE ; /* 0x25C5 */
- union UINT_FLOAT SQ_DYN_GPR_CNTL_PS_FLUSH_REQ; /* 0x2363 */
- union UINT_FLOAT DB_DEBUG ; /* 0x260C */
- union UINT_FLOAT DB_WATERMARKS ; /* 0x260E */
- // SQ
- union UINT_FLOAT SQ_ESGS_RING_ITEMSIZE ; /* 0xA22A */
- union UINT_FLOAT SQ_GSVS_RING_ITEMSIZE ; /* 0xA22B */
- union UINT_FLOAT SQ_ESTMP_RING_ITEMSIZE ; /* 0xA22C */
- union UINT_FLOAT SQ_GSTMP_RING_ITEMSIZE ; /* 0xA22D */
- union UINT_FLOAT SQ_VSTMP_RING_ITEMSIZE ; /* 0xA22E */
- union UINT_FLOAT SQ_PSTMP_RING_ITEMSIZE ; /* 0xA22F */
- union UINT_FLOAT SQ_FBUF_RING_ITEMSIZE ; /* 0xA230 */
- union UINT_FLOAT SQ_REDUC_RING_ITEMSIZE ; /* 0xA231 */
- union UINT_FLOAT SQ_GS_VERT_ITEMSIZE ; /* 0xA232 */
- GLboolean sq_dirty;
-
- radeonTexObj* textures[R700_TEXTURE_NUMBERUNITS];
-
- GLboolean bEnablePerspective;
-
- GLboolean bShaderUseMemConstant;
-
-} R700_CHIP_CONTEXT;
-
-#endif /* _R700_CHIP_H_ */
-
+++ /dev/null
-/*
- * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Authors:
- * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
- * CooperYuan <cooper.yuan@amd.com>, <cooperyuan@gmail.com>
- */
-
-#ifndef _R700_CHIPOFFSET_H_
-#define _R700_CHIPOFFSET_H_
-
-#define mmWAIT_UNTIL 0x2010
-#define mmSCRATCH_REG0 0x2140
-#define mmGUI_SCRATCH_REG0 0x2140
-#define mmSCRATCH_REG1 0x2141
-#define mmGUI_SCRATCH_REG1 0x2141
-#define mmSCRATCH_REG2 0x2142
-#define mmGUI_SCRATCH_REG2 0x2142
-#define mmSCRATCH_REG3 0x2143
-#define mmGUI_SCRATCH_REG3 0x2143
-#define mmSCRATCH_REG4 0x2144
-#define mmGUI_SCRATCH_REG4 0x2144
-#define mmSCRATCH_REG5 0x2145
-#define mmGUI_SCRATCH_REG5 0x2145
-#define mmSCRATCH_REG6 0x2146
-#define mmGUI_SCRATCH_REG6 0x2146
-#define mmSCRATCH_REG7 0x2147
-#define mmGUI_SCRATCH_REG7 0x2147
-
-#define mmCP_COHER_CNTL 0x217C
-#define mmCP_COHER_SIZE 0x217D
-#define mmCP_COHER_BASE 0x217E
-#define mmCP_COHER_STATUS 0x217F
-
-#define mmTA_CNTL_AUX 0x2542
-#define mmVC_ENHANCE 0x25C5
-#define mmSQ_DYN_GPR_CNTL_PS_FLUSH_REQ 0x2363
-#define mmDB_DEBUG 0x260C
-#define mmDB_WATERMARKS 0x260E
-
-#define mmPA_CL_VPORT_XSCALE 0xA10F
-#define mmPA_CL_VPORT_XOFFSET 0xA110
-#define mmPA_CL_VPORT_YSCALE 0xA111
-#define mmPA_CL_VPORT_YOFFSET 0xA112
-#define mmPA_CL_VPORT_ZSCALE 0xA113
-#define mmPA_CL_VPORT_ZOFFSET 0xA114
-#define mmPA_CL_VPORT_XSCALE_1 0xA115
-#define mmPA_CL_VPORT_XSCALE_2 0xA11B
-#define mmPA_CL_VPORT_XSCALE_3 0xA121
-#define mmPA_CL_VPORT_XSCALE_4 0xA127
-#define mmPA_CL_VPORT_XSCALE_5 0xA12D
-#define mmPA_CL_VPORT_XSCALE_6 0xA133
-#define mmPA_CL_VPORT_XSCALE_7 0xA139
-#define mmPA_CL_VPORT_XSCALE_8 0xA13F
-#define mmPA_CL_VPORT_XSCALE_9 0xA145
-#define mmPA_CL_VPORT_XSCALE_10 0xA14B
-#define mmPA_CL_VPORT_XSCALE_11 0xA151
-#define mmPA_CL_VPORT_XSCALE_12 0xA157
-#define mmPA_CL_VPORT_XSCALE_13 0xA15D
-#define mmPA_CL_VPORT_XSCALE_14 0xA163
-#define mmPA_CL_VPORT_XSCALE_15 0xA169
-#define mmPA_CL_VPORT_XOFFSET_1 0xA116
-#define mmPA_CL_VPORT_XOFFSET_2 0xA11C
-#define mmPA_CL_VPORT_XOFFSET_3 0xA122
-#define mmPA_CL_VPORT_XOFFSET_4 0xA128
-#define mmPA_CL_VPORT_XOFFSET_5 0xA12E
-#define mmPA_CL_VPORT_XOFFSET_6 0xA134
-#define mmPA_CL_VPORT_XOFFSET_7 0xA13A
-#define mmPA_CL_VPORT_XOFFSET_8 0xA140
-#define mmPA_CL_VPORT_XOFFSET_9 0xA146
-#define mmPA_CL_VPORT_XOFFSET_10 0xA14C
-#define mmPA_CL_VPORT_XOFFSET_11 0xA152
-#define mmPA_CL_VPORT_XOFFSET_12 0xA158
-#define mmPA_CL_VPORT_XOFFSET_13 0xA15E
-#define mmPA_CL_VPORT_XOFFSET_14 0xA164
-#define mmPA_CL_VPORT_XOFFSET_15 0xA16A
-#define mmPA_CL_VPORT_YSCALE_1 0xA117
-#define mmPA_CL_VPORT_YSCALE_2 0xA11D
-#define mmPA_CL_VPORT_YSCALE_3 0xA123
-#define mmPA_CL_VPORT_YSCALE_4 0xA129
-#define mmPA_CL_VPORT_YSCALE_5 0xA12F
-#define mmPA_CL_VPORT_YSCALE_6 0xA135
-#define mmPA_CL_VPORT_YSCALE_7 0xA13B
-#define mmPA_CL_VPORT_YSCALE_8 0xA141
-#define mmPA_CL_VPORT_YSCALE_9 0xA147
-#define mmPA_CL_VPORT_YSCALE_10 0xA14D
-#define mmPA_CL_VPORT_YSCALE_11 0xA153
-#define mmPA_CL_VPORT_YSCALE_12 0xA159
-#define mmPA_CL_VPORT_YSCALE_13 0xA15F
-#define mmPA_CL_VPORT_YSCALE_14 0xA165
-#define mmPA_CL_VPORT_YSCALE_15 0xA16B
-#define mmPA_CL_VPORT_YOFFSET_1 0xA118
-#define mmPA_CL_VPORT_YOFFSET_2 0xA11E
-#define mmPA_CL_VPORT_YOFFSET_3 0xA124
-#define mmPA_CL_VPORT_YOFFSET_4 0xA12A
-#define mmPA_CL_VPORT_YOFFSET_5 0xA130
-#define mmPA_CL_VPORT_YOFFSET_6 0xA136
-#define mmPA_CL_VPORT_YOFFSET_7 0xA13C
-#define mmPA_CL_VPORT_YOFFSET_8 0xA142
-#define mmPA_CL_VPORT_YOFFSET_9 0xA148
-#define mmPA_CL_VPORT_YOFFSET_10 0xA14E
-#define mmPA_CL_VPORT_YOFFSET_11 0xA154
-#define mmPA_CL_VPORT_YOFFSET_12 0xA15A
-#define mmPA_CL_VPORT_YOFFSET_13 0xA160
-#define mmPA_CL_VPORT_YOFFSET_14 0xA166
-#define mmPA_CL_VPORT_YOFFSET_15 0xA16C
-#define mmPA_CL_VPORT_ZSCALE_1 0xA119
-#define mmPA_CL_VPORT_ZSCALE_2 0xA11F
-#define mmPA_CL_VPORT_ZSCALE_3 0xA125
-#define mmPA_CL_VPORT_ZSCALE_4 0xA12B
-#define mmPA_CL_VPORT_ZSCALE_5 0xA131
-#define mmPA_CL_VPORT_ZSCALE_6 0xA137
-#define mmPA_CL_VPORT_ZSCALE_7 0xA13D
-#define mmPA_CL_VPORT_ZSCALE_8 0xA143
-#define mmPA_CL_VPORT_ZSCALE_9 0xA149
-#define mmPA_CL_VPORT_ZSCALE_10 0xA14F
-#define mmPA_CL_VPORT_ZSCALE_11 0xA155
-#define mmPA_CL_VPORT_ZSCALE_12 0xA15B
-#define mmPA_CL_VPORT_ZSCALE_13 0xA161
-#define mmPA_CL_VPORT_ZSCALE_14 0xA167
-#define mmPA_CL_VPORT_ZSCALE_15 0xA16D
-#define mmPA_CL_VPORT_ZOFFSET_1 0xA11A
-#define mmPA_CL_VPORT_ZOFFSET_2 0xA120
-#define mmPA_CL_VPORT_ZOFFSET_3 0xA126
-#define mmPA_CL_VPORT_ZOFFSET_4 0xA12C
-#define mmPA_CL_VPORT_ZOFFSET_5 0xA132
-#define mmPA_CL_VPORT_ZOFFSET_6 0xA138
-#define mmPA_CL_VPORT_ZOFFSET_7 0xA13E
-#define mmPA_CL_VPORT_ZOFFSET_8 0xA144
-#define mmPA_CL_VPORT_ZOFFSET_9 0xA14A
-#define mmPA_CL_VPORT_ZOFFSET_10 0xA150
-#define mmPA_CL_VPORT_ZOFFSET_11 0xA156
-#define mmPA_CL_VPORT_ZOFFSET_12 0xA15C
-#define mmPA_CL_VPORT_ZOFFSET_13 0xA162
-#define mmPA_CL_VPORT_ZOFFSET_14 0xA168
-#define mmPA_CL_VPORT_ZOFFSET_15 0xA16E
-#define mmPA_CL_VTE_CNTL 0xA206
-#define mmPA_CL_VS_OUT_CNTL 0xA207
-#define mmPA_CL_NANINF_CNTL 0xA208
-#define mmPA_CL_CLIP_CNTL 0xA204
-#define mmPA_CL_GB_VERT_CLIP_ADJ 0xA303
-#define mmPA_CL_GB_VERT_DISC_ADJ 0xA304
-#define mmPA_CL_GB_HORZ_CLIP_ADJ 0xA305
-#define mmPA_CL_GB_HORZ_DISC_ADJ 0xA306
-#define mmPA_CL_UCP_0_X 0xA388
-#define mmPA_CL_UCP_0_Y 0xA389
-#define mmPA_CL_UCP_0_Z 0xA38A
-#define mmPA_CL_UCP_0_W 0xA38B
-#define mmPA_CL_UCP_1_X 0xA38C
-#define mmPA_CL_UCP_1_Y 0xA38D
-#define mmPA_CL_UCP_1_Z 0xA38E
-#define mmPA_CL_UCP_1_W 0xA38F
-#define mmPA_CL_UCP_2_X 0xA390
-#define mmPA_CL_UCP_2_Y 0xA391
-#define mmPA_CL_UCP_2_Z 0xA392
-#define mmPA_CL_UCP_2_W 0xA393
-#define mmPA_CL_UCP_3_X 0xA394
-#define mmPA_CL_UCP_3_Y 0xA395
-#define mmPA_CL_UCP_3_Z 0xA396
-#define mmPA_CL_UCP_3_W 0xA397
-#define mmPA_CL_UCP_4_X 0xA398
-#define mmPA_CL_UCP_4_Y 0xA399
-#define mmPA_CL_UCP_4_Z 0xA39A
-#define mmPA_CL_UCP_4_W 0xA39B
-#define mmPA_CL_UCP_5_X 0xA39C
-#define mmPA_CL_UCP_5_Y 0xA39D
-#define mmPA_CL_UCP_5_Z 0xA39E
-#define mmPA_CL_UCP_5_W 0xA39F
-#define mmPA_CL_POINT_X_RAD 0xA384
-#define mmPA_CL_POINT_Y_RAD 0xA385
-#define mmPA_CL_POINT_SIZE 0xA386
-#define mmPA_CL_POINT_CULL_RAD 0xA387
-
-#define mmPA_SU_VTX_CNTL 0xA302
-#define mmPA_SU_POINT_SIZE 0xA280
-#define mmPA_SU_POINT_MINMAX 0xA281
-#define mmPA_SU_LINE_CNTL 0xA282
-#define mmPA_SU_SC_MODE_CNTL 0xA205
-#define mmPA_SU_POLY_OFFSET_DB_FMT_CNTL 0xA37E
-#define mmPA_SU_POLY_OFFSET_CLAMP 0xA37F
-#define mmPA_SU_POLY_OFFSET_FRONT_SCALE 0xA380
-#define mmPA_SU_POLY_OFFSET_FRONT_OFFSET 0xA381
-#define mmPA_SU_POLY_OFFSET_BACK_SCALE 0xA382
-#define mmPA_SU_POLY_OFFSET_BACK_OFFSET 0xA383
-
-#define mmPA_SC_WINDOW_OFFSET 0xA080
-#define mmPA_SC_AA_CONFIG 0xA301
-#define mmPA_SC_AA_MASK 0xA312
-#define mmPA_SC_AA_SAMPLE_LOCS_MCTX 0xA307
-#define mmPA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX 0xA308
-#define mmPA_SC_LINE_STIPPLE 0xA283
-#define mmPA_SC_LINE_CNTL 0xA300
-#define mmPA_SC_SCREEN_SCISSOR_TL 0xA00C
-#define mmPA_SC_SCREEN_SCISSOR_BR 0xA00D
-#define mmPA_SC_WINDOW_SCISSOR_TL 0xA081
-#define mmPA_SC_WINDOW_SCISSOR_BR 0xA082
-#define mmPA_SC_CLIPRECT_RULE 0xA083
-#define mmPA_SC_CLIPRECT_0_TL 0xA084
-#define mmPA_SC_CLIPRECT_0_BR 0xA085
-#define mmPA_SC_CLIPRECT_1_TL 0xA086
-#define mmPA_SC_CLIPRECT_1_BR 0xA087
-#define mmPA_SC_CLIPRECT_2_TL 0xA088
-#define mmPA_SC_CLIPRECT_2_BR 0xA089
-#define mmPA_SC_CLIPRECT_3_TL 0xA08A
-#define mmPA_SC_CLIPRECT_3_BR 0xA08B
-#define mmPA_SC_EDGERULE 0xA08C
-#define mmPA_SC_GENERIC_SCISSOR_TL 0xA090
-#define mmPA_SC_GENERIC_SCISSOR_BR 0xA091
-#define mmPA_SC_VPORT_SCISSOR_0_TL 0xA094
-#define mmPA_SC_VPORT_SCISSOR_1_TL 0xA096
-#define mmPA_SC_VPORT_SCISSOR_2_TL 0xA098
-#define mmPA_SC_VPORT_SCISSOR_3_TL 0xA09A
-#define mmPA_SC_VPORT_SCISSOR_4_TL 0xA09C
-#define mmPA_SC_VPORT_SCISSOR_5_TL 0xA09E
-#define mmPA_SC_VPORT_SCISSOR_6_TL 0xA0A0
-#define mmPA_SC_VPORT_SCISSOR_7_TL 0xA0A2
-#define mmPA_SC_VPORT_SCISSOR_8_TL 0xA0A4
-#define mmPA_SC_VPORT_SCISSOR_9_TL 0xA0A6
-#define mmPA_SC_VPORT_SCISSOR_10_TL 0xA0A8
-#define mmPA_SC_VPORT_SCISSOR_11_TL 0xA0AA
-#define mmPA_SC_VPORT_SCISSOR_12_TL 0xA0AC
-#define mmPA_SC_VPORT_SCISSOR_13_TL 0xA0AE
-#define mmPA_SC_VPORT_SCISSOR_14_TL 0xA0B0
-#define mmPA_SC_VPORT_SCISSOR_15_TL 0xA0B2
-#define mmPA_SC_VPORT_SCISSOR_0_BR 0xA095
-#define mmPA_SC_VPORT_SCISSOR_1_BR 0xA097
-#define mmPA_SC_VPORT_SCISSOR_2_BR 0xA099
-#define mmPA_SC_VPORT_SCISSOR_3_BR 0xA09B
-#define mmPA_SC_VPORT_SCISSOR_4_BR 0xA09D
-#define mmPA_SC_VPORT_SCISSOR_5_BR 0xA09F
-#define mmPA_SC_VPORT_SCISSOR_6_BR 0xA0A1
-#define mmPA_SC_VPORT_SCISSOR_7_BR 0xA0A3
-#define mmPA_SC_VPORT_SCISSOR_8_BR 0xA0A5
-#define mmPA_SC_VPORT_SCISSOR_9_BR 0xA0A7
-#define mmPA_SC_VPORT_SCISSOR_10_BR 0xA0A9
-#define mmPA_SC_VPORT_SCISSOR_11_BR 0xA0AB
-#define mmPA_SC_VPORT_SCISSOR_12_BR 0xA0AD
-#define mmPA_SC_VPORT_SCISSOR_13_BR 0xA0AF
-#define mmPA_SC_VPORT_SCISSOR_14_BR 0xA0B1
-#define mmPA_SC_VPORT_SCISSOR_15_BR 0xA0B3
-#define mmPA_SC_VPORT_ZMIN_0 0xA0B4
-#define mmPA_SC_VPORT_ZMIN_1 0xA0B6
-#define mmPA_SC_VPORT_ZMIN_2 0xA0B8
-#define mmPA_SC_VPORT_ZMIN_3 0xA0BA
-#define mmPA_SC_VPORT_ZMIN_4 0xA0BC
-#define mmPA_SC_VPORT_ZMIN_5 0xA0BE
-#define mmPA_SC_VPORT_ZMIN_6 0xA0C0
-#define mmPA_SC_VPORT_ZMIN_7 0xA0C2
-#define mmPA_SC_VPORT_ZMIN_8 0xA0C4
-#define mmPA_SC_VPORT_ZMIN_9 0xA0C6
-#define mmPA_SC_VPORT_ZMIN_10 0xA0C8
-#define mmPA_SC_VPORT_ZMIN_11 0xA0CA
-#define mmPA_SC_VPORT_ZMIN_12 0xA0CC
-#define mmPA_SC_VPORT_ZMIN_13 0xA0CE
-#define mmPA_SC_VPORT_ZMIN_14 0xA0D0
-#define mmPA_SC_VPORT_ZMIN_15 0xA0D2
-#define mmPA_SC_VPORT_ZMAX_0 0xA0B5
-#define mmPA_SC_VPORT_ZMAX_1 0xA0B7
-#define mmPA_SC_VPORT_ZMAX_2 0xA0B9
-#define mmPA_SC_VPORT_ZMAX_3 0xA0BB
-#define mmPA_SC_VPORT_ZMAX_4 0xA0BD
-#define mmPA_SC_VPORT_ZMAX_5 0xA0BF
-#define mmPA_SC_VPORT_ZMAX_6 0xA0C1
-#define mmPA_SC_VPORT_ZMAX_7 0xA0C3
-#define mmPA_SC_VPORT_ZMAX_8 0xA0C5
-#define mmPA_SC_VPORT_ZMAX_9 0xA0C7
-#define mmPA_SC_VPORT_ZMAX_10 0xA0C9
-#define mmPA_SC_VPORT_ZMAX_11 0xA0CB
-#define mmPA_SC_VPORT_ZMAX_12 0xA0CD
-#define mmPA_SC_VPORT_ZMAX_13 0xA0CF
-#define mmPA_SC_VPORT_ZMAX_14 0xA0D1
-#define mmPA_SC_VPORT_ZMAX_15 0xA0D3
-#define mmPA_SC_MODE_CNTL 0xA293
-#define mmPA_SC_MPASS_PS_CNTL 0xA292
-
-#define mmVGT_DRAW_INITIATOR 0xA1FC
-#define mmVGT_EVENT_INITIATOR 0xA2A4
-#define mmVGT_EVENT_ADDRESS_REG 0xA1FE
-#define mmVGT_DMA_BASE_HI 0xA1F9
-#define mmVGT_DMA_BASE 0xA1FA
-#define mmVGT_DMA_INDEX_TYPE 0xA29F
-#define mmVGT_DMA_NUM_INSTANCES 0xA2A2
-#define mmVGT_DMA_SIZE 0xA29D
-
-#define mmVGT_IMMED_DATA 0xA1FD
-#define mmVGT_INDEX_TYPE 0x2257
-#define mmVGT_NUM_INDICES 0x225C
-#define mmVGT_NUM_INSTANCES 0x225D
-#define mmVGT_PRIMITIVE_TYPE 0x2256
-#define mmVGT_PRIMITIVEID_EN 0xA2A1
-#define mmVGT_VTX_CNT_EN 0xA2AE
-#define mmVGT_REUSE_OFF 0xA2AD
-#define mmVGT_INSTANCE_STEP_RATE_0 0xA2A8
-#define mmVGT_INSTANCE_STEP_RATE_1 0xA2A9
-#define mmVGT_MAX_VTX_INDX 0xA100
-#define mmVGT_MIN_VTX_INDX 0xA101
-#define mmVGT_INDX_OFFSET 0xA102
-#define mmVGT_VERTEX_REUSE_BLOCK_CNTL 0xA316
-#define mmVGT_OUT_DEALLOC_CNTL 0xA317
-#define mmVGT_MULTI_PRIM_IB_RESET_INDX 0xA103
-#define mmVGT_MULTI_PRIM_IB_RESET_EN 0xA2A5
-#define mmVGT_ENHANCE 0xA294
-#define mmVGT_OUTPUT_PATH_CNTL 0xA284
-#define mmVGT_HOS_CNTL 0xA285
-#define mmVGT_HOS_MAX_TESS_LEVEL 0xA286
-#define mmVGT_HOS_MIN_TESS_LEVEL 0xA287
-#define mmVGT_HOS_REUSE_DEPTH 0xA288
-#define mmVGT_GROUP_PRIM_TYPE 0xA289
-#define mmVGT_GROUP_FIRST_DECR 0xA28A
-#define mmVGT_GROUP_DECR 0xA28B
-#define mmVGT_GROUP_VECT_0_CNTL 0xA28C
-#define mmVGT_GROUP_VECT_1_CNTL 0xA28D
-#define mmVGT_GROUP_VECT_0_FMT_CNTL 0xA28E
-#define mmVGT_GROUP_VECT_1_FMT_CNTL 0xA28F
-#define mmVGT_GS_MODE 0xA290
-#define mmVGT_GS_OUT_PRIM_TYPE 0xA29B
-
-#define mmVGT_STRMOUT_EN 0xA2AC
-#define mmVGT_STRMOUT_BUFFER_SIZE_0 0xA2B4
-#define mmVGT_STRMOUT_BUFFER_SIZE_1 0xA2B8
-#define mmVGT_STRMOUT_BUFFER_SIZE_2 0xA2BC
-#define mmVGT_STRMOUT_BUFFER_SIZE_3 0xA2C0
-#define mmVGT_STRMOUT_BUFFER_OFFSET_0 0xA2B7
-#define mmVGT_STRMOUT_BUFFER_OFFSET_1 0xA2BB
-#define mmVGT_STRMOUT_BUFFER_OFFSET_2 0xA2BF
-#define mmVGT_STRMOUT_BUFFER_OFFSET_3 0xA2C3
-#define mmVGT_STRMOUT_VTX_STRIDE_0 0xA2B5
-#define mmVGT_STRMOUT_VTX_STRIDE_1 0xA2B9
-#define mmVGT_STRMOUT_VTX_STRIDE_2 0xA2BD
-#define mmVGT_STRMOUT_VTX_STRIDE_3 0xA2C1
-#define mmVGT_STRMOUT_BUFFER_BASE_0 0xA2B6
-#define mmVGT_STRMOUT_BUFFER_BASE_1 0xA2BA
-#define mmVGT_STRMOUT_BUFFER_BASE_2 0xA2BE
-#define mmVGT_STRMOUT_BUFFER_BASE_3 0xA2C2
-#define mmVGT_STRMOUT_BUFFER_EN 0xA2C8
-#define mmVGT_STRMOUT_BASE_OFFSET_0 0xA2C4
-#define mmVGT_STRMOUT_BASE_OFFSET_1 0xA2C5
-#define mmVGT_STRMOUT_BASE_OFFSET_2 0xA2C6
-#define mmVGT_STRMOUT_BASE_OFFSET_3 0xA2C7
-#define mmVGT_STRMOUT_BASE_OFFSET_HI_0 0xA2D1
-#define mmVGT_STRMOUT_BASE_OFFSET_HI_1 0xA2D2
-#define mmVGT_STRMOUT_BASE_OFFSET_HI_2 0xA2D3
-#define mmVGT_STRMOUT_BASE_OFFSET_HI_3 0xA2D4
-#define mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET 0xA2CA
-#define mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE 0xA2CB
-#define mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE 0xA2CC
-
-#define mmSQ_PGM_START_PS 0xA210
-#define mmSQ_PGM_CF_OFFSET_PS 0xA233
-#define mmSQ_PGM_RESOURCES_PS 0xA214
-#define mmSQ_PGM_EXPORTS_PS 0xA215
-#define mmSQ_PGM_START_VS 0xA216
-#define mmSQ_PGM_CF_OFFSET_VS 0xA234
-#define mmSQ_PGM_RESOURCES_VS 0xA21A
-#define mmSQ_PGM_START_GS 0xA21B
-#define mmSQ_PGM_CF_OFFSET_GS 0xA235
-#define mmSQ_PGM_RESOURCES_GS 0xA21F
-#define mmSQ_PGM_START_ES 0xA220
-#define mmSQ_PGM_CF_OFFSET_ES 0xA236
-#define mmSQ_PGM_RESOURCES_ES 0xA224
-#define mmSQ_PGM_START_FS 0xA225
-#define mmSQ_PGM_CF_OFFSET_FS 0xA237
-#define mmSQ_PGM_RESOURCES_FS 0xA229
-#define mmSQ_ESGS_RING_ITEMSIZE 0xA22A
-#define mmSQ_GSVS_RING_ITEMSIZE 0xA22B
-#define mmSQ_ESTMP_RING_ITEMSIZE 0xA22C
-#define mmSQ_GSTMP_RING_ITEMSIZE 0xA22D
-#define mmSQ_VSTMP_RING_ITEMSIZE 0xA22E
-#define mmSQ_PSTMP_RING_ITEMSIZE 0xA22F
-#define mmSQ_FBUF_RING_ITEMSIZE 0xA230
-#define mmSQ_REDUC_RING_ITEMSIZE 0xA231
-#define mmSQ_GS_VERT_ITEMSIZE 0xA232
-#define mmSQ_VTX_SEMANTIC_CLEAR 0xA238
-
-#define mmSQ_VTX_SEMANTIC_0 0xA0E0
-#define mmSQ_VTX_SEMANTIC_1 0xA0E1
-#define mmSQ_VTX_SEMANTIC_2 0xA0E2
-#define mmSQ_VTX_SEMANTIC_3 0xA0E3
-#define mmSQ_VTX_SEMANTIC_4 0xA0E4
-#define mmSQ_VTX_SEMANTIC_5 0xA0E5
-#define mmSQ_VTX_SEMANTIC_6 0xA0E6
-#define mmSQ_VTX_SEMANTIC_7 0xA0E7
-#define mmSQ_VTX_SEMANTIC_8 0xA0E8
-#define mmSQ_VTX_SEMANTIC_9 0xA0E9
-#define mmSQ_VTX_SEMANTIC_10 0xA0EA
-#define mmSQ_VTX_SEMANTIC_11 0xA0EB
-#define mmSQ_VTX_SEMANTIC_12 0xA0EC
-#define mmSQ_VTX_SEMANTIC_13 0xA0ED
-#define mmSQ_VTX_SEMANTIC_14 0xA0EE
-#define mmSQ_VTX_SEMANTIC_15 0xA0EF
-#define mmSQ_VTX_SEMANTIC_16 0xA0F0
-#define mmSQ_VTX_SEMANTIC_17 0xA0F1
-#define mmSQ_VTX_SEMANTIC_18 0xA0F2
-#define mmSQ_VTX_SEMANTIC_19 0xA0F3
-#define mmSQ_VTX_SEMANTIC_20 0xA0F4
-#define mmSQ_VTX_SEMANTIC_21 0xA0F5
-#define mmSQ_VTX_SEMANTIC_22 0xA0F6
-#define mmSQ_VTX_SEMANTIC_23 0xA0F7
-#define mmSQ_VTX_SEMANTIC_24 0xA0F8
-#define mmSQ_VTX_SEMANTIC_25 0xA0F9
-#define mmSQ_VTX_SEMANTIC_26 0xA0FA
-#define mmSQ_VTX_SEMANTIC_27 0xA0FB
-#define mmSQ_VTX_SEMANTIC_28 0xA0FC
-#define mmSQ_VTX_SEMANTIC_29 0xA0FD
-#define mmSQ_VTX_SEMANTIC_30 0xA0FE
-#define mmSQ_VTX_SEMANTIC_31 0xA0FF
-
-#define mmSQ_ALU_CONST_CACHE_PS_0 0xA250
-#define mmSQ_ALU_CONST_CACHE_PS_1 0xA251
-#define mmSQ_ALU_CONST_CACHE_PS_2 0xA252
-#define mmSQ_ALU_CONST_CACHE_PS_3 0xA253
-#define mmSQ_ALU_CONST_CACHE_PS_4 0xA254
-#define mmSQ_ALU_CONST_CACHE_PS_5 0xA255
-#define mmSQ_ALU_CONST_CACHE_PS_6 0xA256
-#define mmSQ_ALU_CONST_CACHE_PS_7 0xA257
-#define mmSQ_ALU_CONST_CACHE_PS_8 0xA258
-#define mmSQ_ALU_CONST_CACHE_PS_9 0xA259
-#define mmSQ_ALU_CONST_CACHE_PS_10 0xA25A
-#define mmSQ_ALU_CONST_CACHE_PS_11 0xA25B
-#define mmSQ_ALU_CONST_CACHE_PS_12 0xA25C
-#define mmSQ_ALU_CONST_CACHE_PS_13 0xA25D
-#define mmSQ_ALU_CONST_CACHE_PS_14 0xA25E
-#define mmSQ_ALU_CONST_CACHE_PS_15 0xA25F
-#define mmSQ_ALU_CONST_CACHE_VS_0 0xA260
-#define mmSQ_ALU_CONST_CACHE_VS_1 0xA261
-#define mmSQ_ALU_CONST_CACHE_VS_2 0xA262
-#define mmSQ_ALU_CONST_CACHE_VS_3 0xA263
-#define mmSQ_ALU_CONST_CACHE_VS_4 0xA264
-#define mmSQ_ALU_CONST_CACHE_VS_5 0xA265
-#define mmSQ_ALU_CONST_CACHE_VS_6 0xA266
-#define mmSQ_ALU_CONST_CACHE_VS_7 0xA267
-#define mmSQ_ALU_CONST_CACHE_VS_8 0xA268
-#define mmSQ_ALU_CONST_CACHE_VS_9 0xA269
-#define mmSQ_ALU_CONST_CACHE_VS_10 0xA26A
-#define mmSQ_ALU_CONST_CACHE_VS_11 0xA26B
-#define mmSQ_ALU_CONST_CACHE_VS_12 0xA26C
-#define mmSQ_ALU_CONST_CACHE_VS_13 0xA26D
-#define mmSQ_ALU_CONST_CACHE_VS_14 0xA26E
-#define mmSQ_ALU_CONST_CACHE_VS_15 0xA26F
-#define mmSQ_ALU_CONST_CACHE_GS_0 0xA270
-#define mmSQ_ALU_CONST_CACHE_GS_1 0xA271
-#define mmSQ_ALU_CONST_CACHE_GS_2 0xA272
-#define mmSQ_ALU_CONST_CACHE_GS_3 0xA273
-#define mmSQ_ALU_CONST_CACHE_GS_4 0xA274
-#define mmSQ_ALU_CONST_CACHE_GS_5 0xA275
-#define mmSQ_ALU_CONST_CACHE_GS_6 0xA276
-#define mmSQ_ALU_CONST_CACHE_GS_7 0xA277
-#define mmSQ_ALU_CONST_CACHE_GS_8 0xA278
-#define mmSQ_ALU_CONST_CACHE_GS_9 0xA279
-#define mmSQ_ALU_CONST_CACHE_GS_10 0xA27A
-#define mmSQ_ALU_CONST_CACHE_GS_11 0xA27B
-#define mmSQ_ALU_CONST_CACHE_GS_12 0xA27C
-#define mmSQ_ALU_CONST_CACHE_GS_13 0xA27D
-#define mmSQ_ALU_CONST_CACHE_GS_14 0xA27E
-#define mmSQ_ALU_CONST_CACHE_GS_15 0xA27F
-#define mmSQ_ALU_CONST_BUFFER_SIZE_PS_0 0xA050
-#define mmSQ_ALU_CONST_BUFFER_SIZE_PS_1 0xA051
-#define mmSQ_ALU_CONST_BUFFER_SIZE_PS_2 0xA052
-#define mmSQ_ALU_CONST_BUFFER_SIZE_PS_3 0xA053
-#define mmSQ_ALU_CONST_BUFFER_SIZE_PS_4 0xA054
-#define mmSQ_ALU_CONST_BUFFER_SIZE_PS_5 0xA055
-#define mmSQ_ALU_CONST_BUFFER_SIZE_PS_6 0xA056
-#define mmSQ_ALU_CONST_BUFFER_SIZE_PS_7 0xA057
-#define mmSQ_ALU_CONST_BUFFER_SIZE_PS_8 0xA058
-#define mmSQ_ALU_CONST_BUFFER_SIZE_PS_9 0xA059
-#define mmSQ_ALU_CONST_BUFFER_SIZE_PS_10 0xA05A
-#define mmSQ_ALU_CONST_BUFFER_SIZE_PS_11 0xA05B
-#define mmSQ_ALU_CONST_BUFFER_SIZE_PS_12 0xA05C
-#define mmSQ_ALU_CONST_BUFFER_SIZE_PS_13 0xA05D
-#define mmSQ_ALU_CONST_BUFFER_SIZE_PS_14 0xA05E
-#define mmSQ_ALU_CONST_BUFFER_SIZE_PS_15 0xA05F
-#define mmSQ_ALU_CONST_BUFFER_SIZE_VS_0 0xA060
-#define mmSQ_ALU_CONST_BUFFER_SIZE_VS_1 0xA061
-#define mmSQ_ALU_CONST_BUFFER_SIZE_VS_2 0xA062
-#define mmSQ_ALU_CONST_BUFFER_SIZE_VS_3 0xA063
-#define mmSQ_ALU_CONST_BUFFER_SIZE_VS_4 0xA064
-#define mmSQ_ALU_CONST_BUFFER_SIZE_VS_5 0xA065
-#define mmSQ_ALU_CONST_BUFFER_SIZE_VS_6 0xA066
-#define mmSQ_ALU_CONST_BUFFER_SIZE_VS_7 0xA067
-#define mmSQ_ALU_CONST_BUFFER_SIZE_VS_8 0xA068
-#define mmSQ_ALU_CONST_BUFFER_SIZE_VS_9 0xA069
-#define mmSQ_ALU_CONST_BUFFER_SIZE_VS_10 0xA06A
-#define mmSQ_ALU_CONST_BUFFER_SIZE_VS_11 0xA06B
-#define mmSQ_ALU_CONST_BUFFER_SIZE_VS_12 0xA06C
-#define mmSQ_ALU_CONST_BUFFER_SIZE_VS_13 0xA06D
-#define mmSQ_ALU_CONST_BUFFER_SIZE_VS_14 0xA06E
-#define mmSQ_ALU_CONST_BUFFER_SIZE_VS_15 0xA06F
-#define mmSQ_ALU_CONST_BUFFER_SIZE_GS_0 0xA070
-#define mmSQ_ALU_CONST_BUFFER_SIZE_GS_1 0xA071
-#define mmSQ_ALU_CONST_BUFFER_SIZE_GS_2 0xA072
-#define mmSQ_ALU_CONST_BUFFER_SIZE_GS_3 0xA073
-#define mmSQ_ALU_CONST_BUFFER_SIZE_GS_4 0xA074
-#define mmSQ_ALU_CONST_BUFFER_SIZE_GS_5 0xA075
-#define mmSQ_ALU_CONST_BUFFER_SIZE_GS_6 0xA076
-#define mmSQ_ALU_CONST_BUFFER_SIZE_GS_7 0xA077
-#define mmSQ_ALU_CONST_BUFFER_SIZE_GS_8 0xA078
-#define mmSQ_ALU_CONST_BUFFER_SIZE_GS_9 0xA079
-#define mmSQ_ALU_CONST_BUFFER_SIZE_GS_10 0xA07A
-#define mmSQ_ALU_CONST_BUFFER_SIZE_GS_11 0xA07B
-#define mmSQ_ALU_CONST_BUFFER_SIZE_GS_12 0xA07C
-#define mmSQ_ALU_CONST_BUFFER_SIZE_GS_13 0xA07D
-#define mmSQ_ALU_CONST_BUFFER_SIZE_GS_14 0xA07E
-#define mmSQ_ALU_CONST_BUFFER_SIZE_GS_15 0xA07F
-
-#define mmSPI_VS_OUT_ID_0 0xA185
-#define mmSPI_VS_OUT_ID_1 0xA186
-#define mmSPI_VS_OUT_ID_2 0xA187
-#define mmSPI_VS_OUT_ID_3 0xA188
-#define mmSPI_VS_OUT_ID_4 0xA189
-#define mmSPI_VS_OUT_ID_5 0xA18A
-#define mmSPI_VS_OUT_ID_6 0xA18B
-#define mmSPI_VS_OUT_ID_7 0xA18C
-#define mmSPI_VS_OUT_ID_8 0xA18D
-#define mmSPI_VS_OUT_ID_9 0xA18E
-#define mmSPI_PS_INPUT_CNTL_0 0xA191
-#define mmSPI_PS_INPUT_CNTL_1 0xA192
-#define mmSPI_PS_INPUT_CNTL_2 0xA193
-#define mmSPI_PS_INPUT_CNTL_3 0xA194
-#define mmSPI_PS_INPUT_CNTL_4 0xA195
-#define mmSPI_PS_INPUT_CNTL_5 0xA196
-#define mmSPI_PS_INPUT_CNTL_6 0xA197
-#define mmSPI_PS_INPUT_CNTL_7 0xA198
-#define mmSPI_PS_INPUT_CNTL_8 0xA199
-#define mmSPI_PS_INPUT_CNTL_9 0xA19A
-#define mmSPI_PS_INPUT_CNTL_10 0xA19B
-#define mmSPI_PS_INPUT_CNTL_11 0xA19C
-#define mmSPI_PS_INPUT_CNTL_12 0xA19D
-#define mmSPI_PS_INPUT_CNTL_13 0xA19E
-#define mmSPI_PS_INPUT_CNTL_14 0xA19F
-#define mmSPI_PS_INPUT_CNTL_15 0xA1A0
-#define mmSPI_PS_INPUT_CNTL_16 0xA1A1
-#define mmSPI_PS_INPUT_CNTL_17 0xA1A2
-#define mmSPI_PS_INPUT_CNTL_18 0xA1A3
-#define mmSPI_PS_INPUT_CNTL_19 0xA1A4
-#define mmSPI_PS_INPUT_CNTL_20 0xA1A5
-#define mmSPI_PS_INPUT_CNTL_21 0xA1A6
-#define mmSPI_PS_INPUT_CNTL_22 0xA1A7
-#define mmSPI_PS_INPUT_CNTL_23 0xA1A8
-#define mmSPI_PS_INPUT_CNTL_24 0xA1A9
-#define mmSPI_PS_INPUT_CNTL_25 0xA1AA
-#define mmSPI_PS_INPUT_CNTL_26 0xA1AB
-#define mmSPI_PS_INPUT_CNTL_27 0xA1AC
-#define mmSPI_PS_INPUT_CNTL_28 0xA1AD
-#define mmSPI_PS_INPUT_CNTL_29 0xA1AE
-#define mmSPI_PS_INPUT_CNTL_30 0xA1AF
-#define mmSPI_PS_INPUT_CNTL_31 0xA1B0
-#define mmSPI_VS_OUT_CONFIG 0xA1B1
-#define mmSPI_THREAD_GROUPING 0xA1B2
-#define mmSPI_PS_IN_CONTROL_0 0xA1B3
-#define mmSPI_PS_IN_CONTROL_1 0xA1B4
-#define mmSPI_INTERP_CONTROL_0 0xA1B5
-#define mmSPI_INPUT_Z 0xA1B6
-#define mmSPI_FOG_CNTL 0xA1B7
-#define mmSPI_FOG_FUNC_SCALE 0xA1B8
-#define mmSPI_FOG_FUNC_BIAS 0xA1B9
-
-#define mmSX_MISC 0xA0D4
-#define mmSX_ALPHA_TEST_CONTROL 0xA104
-#define mmSX_ALPHA_REF 0xA10E
-
-#define mmDB_DEPTH_BASE 0xA003
-#define mmDB_DEPTH_INFO 0xA004
-#define mmDB_HTILE_DATA_BASE 0xA005
-#define mmDB_DEPTH_SIZE 0xA000
-#define mmDB_DEPTH_VIEW 0xA001
-#define mmDB_RENDER_CONTROL 0xA343
-#define mmDB_RENDER_OVERRIDE 0xA344
-#define mmDB_SHADER_CONTROL 0xA203
-#define mmDB_STENCIL_CLEAR 0xA00A
-#define mmDB_DEPTH_CLEAR 0xA00B
-#define mmDB_HTILE_SURFACE 0xA349
-#define mmDB_PRELOAD_CONTROL 0xA34C
-#define mmDB_PREFETCH_LIMIT 0xA34D
-#define mmDB_STENCILREFMASK 0xA10C
-#define mmDB_STENCILREFMASK_BF 0xA10D
-#define mmDB_SRESULTS_COMPARE_STATE0 0xA34A
-#define mmDB_SRESULTS_COMPARE_STATE1 0xA34B
-#define mmDB_DEPTH_CONTROL 0xA200
-#define mmDB_ALPHA_TO_MASK 0xA351
-
-#define mmCB_CLEAR_RED_R6XX 0xA048
-#define mmCB_CLEAR_GREEN_R6XX 0xA049
-#define mmCB_CLEAR_BLUE_R6XX 0xA04A
-#define mmCB_CLEAR_ALPHA_R6XX 0xA04B
-#define mmCB_BLEND_RED 0xA105
-#define mmCB_BLEND_GREEN 0xA106
-#define mmCB_BLEND_BLUE 0xA107
-#define mmCB_BLEND_ALPHA 0xA108
-#define mmCB_FOG_RED_R6XX 0xA109
-#define mmCB_FOG_GREEN_R6XX 0xA10A
-#define mmCB_FOG_BLUE_R6XX 0xA10B
-#define mmCB_BLEND_CONTROL 0xA201
-#define mmCB_COLOR_CONTROL 0xA202
-#define mmCB_BLEND0_CONTROL 0xA1E0
-#define mmCB_BLEND1_CONTROL 0xA1E1
-#define mmCB_BLEND2_CONTROL 0xA1E2
-#define mmCB_BLEND3_CONTROL 0xA1E3
-#define mmCB_BLEND4_CONTROL 0xA1E4
-#define mmCB_BLEND5_CONTROL 0xA1E5
-#define mmCB_BLEND6_CONTROL 0xA1E6
-#define mmCB_BLEND7_CONTROL 0xA1E7
-#define mmCB_CLRCMP_CONTROL 0xA30C
-#define mmCB_CLRCMP_SRC 0xA30D
-#define mmCB_CLRCMP_DST 0xA30E
-#define mmCB_CLRCMP_MSK 0xA30F
-#define mmCB_COLOR0_BASE 0xA010
-#define mmCB_COLOR1_BASE 0xA011
-#define mmCB_COLOR2_BASE 0xA012
-#define mmCB_COLOR3_BASE 0xA013
-#define mmCB_COLOR4_BASE 0xA014
-#define mmCB_COLOR5_BASE 0xA015
-#define mmCB_COLOR6_BASE 0xA016
-#define mmCB_COLOR7_BASE 0xA017
-#define mmCB_COLOR0_SIZE 0xA018
-#define mmCB_COLOR1_SIZE 0xA019
-#define mmCB_COLOR2_SIZE 0xA01A
-#define mmCB_COLOR3_SIZE 0xA01B
-#define mmCB_COLOR4_SIZE 0xA01C
-#define mmCB_COLOR5_SIZE 0xA01D
-#define mmCB_COLOR6_SIZE 0xA01E
-#define mmCB_COLOR7_SIZE 0xA01F
-#define mmCB_COLOR0_VIEW 0xA020
-#define mmCB_COLOR1_VIEW 0xA021
-#define mmCB_COLOR2_VIEW 0xA022
-#define mmCB_COLOR3_VIEW 0xA023
-#define mmCB_COLOR4_VIEW 0xA024
-#define mmCB_COLOR5_VIEW 0xA025
-#define mmCB_COLOR6_VIEW 0xA026
-#define mmCB_COLOR7_VIEW 0xA027
-#define mmCB_COLOR0_INFO 0xA028
-#define mmCB_COLOR1_INFO 0xA029
-#define mmCB_COLOR2_INFO 0xA02A
-#define mmCB_COLOR3_INFO 0xA02B
-#define mmCB_COLOR4_INFO 0xA02C
-#define mmCB_COLOR5_INFO 0xA02D
-#define mmCB_COLOR6_INFO 0xA02E
-#define mmCB_COLOR7_INFO 0xA02F
-#define mmCB_COLOR0_TILE 0xA030
-#define mmCB_COLOR1_TILE 0xA031
-#define mmCB_COLOR2_TILE 0xA032
-#define mmCB_COLOR3_TILE 0xA033
-#define mmCB_COLOR4_TILE 0xA034
-#define mmCB_COLOR5_TILE 0xA035
-#define mmCB_COLOR6_TILE 0xA036
-#define mmCB_COLOR7_TILE 0xA037
-#define mmCB_COLOR0_FRAG 0xA038
-#define mmCB_COLOR1_FRAG 0xA039
-#define mmCB_COLOR2_FRAG 0xA03A
-#define mmCB_COLOR3_FRAG 0xA03B
-#define mmCB_COLOR4_FRAG 0xA03C
-#define mmCB_COLOR5_FRAG 0xA03D
-#define mmCB_COLOR6_FRAG 0xA03E
-#define mmCB_COLOR7_FRAG 0xA03F
-#define mmCB_COLOR0_MASK 0xA040
-#define mmCB_COLOR1_MASK 0xA041
-#define mmCB_COLOR2_MASK 0xA042
-#define mmCB_COLOR3_MASK 0xA043
-#define mmCB_COLOR4_MASK 0xA044
-#define mmCB_COLOR5_MASK 0xA045
-#define mmCB_COLOR6_MASK 0xA046
-#define mmCB_COLOR7_MASK 0xA047
-#define mmCB_CLEAR_RED_R6XX 0xA048
-#define mmCB_CLEAR_GREEN_R6XX 0xA049
-#define mmCB_CLEAR_BLUE_R6XX 0xA04A
-#define mmCB_CLEAR_ALPHA_R6XX 0xA04B
-#define mmCB_TARGET_MASK 0xA08E
-#define mmCB_SHADER_MASK 0xA08F
-#define mmCB_SHADER_CONTROL 0xA1E8
-
-#define mmSQ_VTX_BASE_VTX_LOC 0xF3FC
-#define mmSQ_VTX_START_INST_LOC 0xF3FD
-
-#endif /* _R700_CHIPOFFSET_H_ */
-
+++ /dev/null
-/*
- * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Authors:
- * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
- * CooperYuan <cooper.yuan@amd.com>, <cooperyuan@gmail.com>
- */
-
-#include "main/glheader.h"
-#include "main/context.h"
-#include "main/macros.h"
-#include "main/imports.h"
-#include "main/mtypes.h"
-#include "main/enums.h"
-#include "swrast/swrast.h"
-
-#include "radeon_lock.h"
-#include "r600_context.h"
-
-#include "r700_shaderinst.h"
-#include "r700_clear.h"
-
-static GLboolean r700ClearFast(context_t *context, GLbitfield mask)
-{
- /* TODO, fast clear need implementation */
- return GL_FALSE;
-}
-
-void r700Clear(struct gl_context * ctx, GLbitfield mask)
-{
- context_t *context = R700_CONTEXT(ctx);
- radeonContextPtr radeon = &context->radeon;
- __DRIdrawable *dPriv = radeon_get_drawable(&context->radeon);
- const GLuint colorMask = *((GLuint *) & ctx->Color.ColorMask[0]);
- GLbitfield swrast_mask = 0, tri_mask = 0;
- int i;
- struct gl_framebuffer *fb = ctx->DrawBuffer;
-
- radeon_print(RADEON_RENDER, RADEON_VERBOSE, "%s %x\n", __func__, mask);
-
- if (mask & (BUFFER_BIT_FRONT_LEFT | BUFFER_BIT_FRONT_RIGHT)) {
- context->radeon.front_buffer_dirty = GL_TRUE;
- }
-
- radeon_prepare_render(radeon);
-
- if( GL_TRUE == r700ClearFast(context, mask) )
- {
- return;
- }
- if (!context->radeon.radeonScreen->driScreen->dri2.enabled) {
- LOCK_HARDWARE(&context->radeon);
- UNLOCK_HARDWARE(&context->radeon);
- if (dPriv->numClipRects == 0)
- return;
- }
-
- R600_NEWPRIM(context);
-
- if (colorMask == ~0)
- tri_mask |= (mask & BUFFER_BITS_COLOR);
- else
- tri_mask |= (mask & (BUFFER_BIT_FRONT_LEFT | BUFFER_BIT_BACK_LEFT));
-
-
- /* HW stencil */
- if (mask & BUFFER_BIT_STENCIL) {
- tri_mask |= BUFFER_BIT_STENCIL;
- }
-
- /* HW depth */
- if (mask & BUFFER_BIT_DEPTH) {
- tri_mask |= BUFFER_BIT_DEPTH;
- }
-
- /* If we're doing a tri pass for depth/stencil, include a likely color
- * buffer with it.
- */
-
- for (i = 0; i < BUFFER_COUNT; i++) {
- GLuint bufBit = 1 << i;
- if ((tri_mask) & bufBit) {
- if (!fb->Attachment[i].Renderbuffer->ClassID) {
- tri_mask &= ~bufBit;
- swrast_mask |= bufBit;
- }
- }
- }
-
- /* SW fallback clearing */
- swrast_mask = mask & ~tri_mask;
-
- if (tri_mask) {
- radeonUserClear(ctx, tri_mask);
- }
-
- if (swrast_mask) {
- radeon_print(RADEON_FALLBACKS, RADEON_IMPORTANT, "%s: swrast clear, mask: %x\n",
- __FUNCTION__, swrast_mask);
- _swrast_Clear(ctx, swrast_mask);
- }
-
-}
-
-
+++ /dev/null
-/*
- * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Authors:
- * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
- * CooperYuan <cooper.yuan@amd.com>, <cooperyuan@gmail.com>
- */
-
-#ifndef __r700_CLEAR_H__
-#define __r700_CLEAR_H__
-
-extern void r700Clear(struct gl_context * ctx, GLbitfield mask);
-
-#endif /* __r700_CLEAR_H__ */
+++ /dev/null
-/*
- * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Authors:
- * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
- * CooperYuan <cooper.yuan@amd.com>, <cooperyuan@gmail.com>
- */
-
-#include "r700_debug.h"
-#include "radeon_debug.h"
-
-void DumpHwBinary(int type, void *addr, int size)
-{
- int i;
- unsigned int *pHw = (unsigned int *)addr;
-
- return;
-
- switch (type)
- {
- case DUMP_PIXEL_SHADER:
- radeon_print(RADEON_SHADER, RADEON_TRACE, "Pixel Shader\n");
- break;
- case DUMP_VERTEX_SHADER:
- radeon_print(RADEON_SHADER, RADEON_TRACE, "Vertex Shader\n");
- break;
- case DUMP_FETCH_SHADER:
- radeon_print(RADEON_SHADER, RADEON_TRACE, "Fetch Shader\n");
- break;
- }
-
- for (i = 0; i < size; i++)
- {
- radeon_print(RADEON_SHADER, RADEON_TRACE, "0x%08x,\t", *pHw);
- if (i%4 == 3)
- radeon_print(RADEON_SHADER, RADEON_TRACE, "0x%08x\n", *pHw);
- pHw++;
-
- }
-}
-
+++ /dev/null
-/*
- * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Authors:
- * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
- * CooperYuan <cooper.yuan@amd.com>, <cooperyuan@gmail.com>
- */
-
-#ifndef _R700_DEBUG_H_
-#define _R700_DEBUG_H_
-enum R700_DUMP_TYPE
-{
- DUMP_VERTEX_SHADER = 0x1,
- DUMP_PIXEL_SHADER = 0x2,
- DUMP_FETCH_SHADER = 0x4,
-};
-
-extern void DumpHwBinary(int, void *, int);
-
-#endif /*_R700_DEBUG_H_*/
+++ /dev/null
-/*
- * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Authors:
- * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
- */
-
-#ifndef _R700_DRICONF_H_
-#define _R700_DRICONF_H_
-
-#define DRI_CONF_FP_OPTIMIZATION_SPEED 0
-#define DRI_CONF_FP_OPTIMIZATION_QUALITY 1
-
-#endif /* _R700_DRICONF_H_ */
+++ /dev/null
-/*
- * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Authors:
- * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
- * CooperYuan <cooper.yuan@amd.com>, <cooperyuan@gmail.com>
- */
-
-#include <stdio.h>
-#include <stdarg.h>
-#include <stdlib.h>
-#include <string.h>
-#include <math.h>
-
-#include "main/imports.h"
-#include "program/prog_parameter.h"
-#include "program/prog_statevars.h"
-#include "program/program.h"
-
-#include "r600_context.h"
-#include "r600_cmdbuf.h"
-#include "r600_emit.h"
-
-#include "r700_fragprog.h"
-
-#include "r700_debug.h"
-
-void insert_wpos_code(struct gl_context *ctx, struct gl_fragment_program *fprog)
-{
- static const gl_state_index winstate[STATE_LENGTH]
- = { STATE_INTERNAL, STATE_FB_WPOS_Y_TRANSFORM, 0, 0, 0};
- struct prog_instruction *newInst, *inst;
- GLint win_size; /* state reference */
- GLuint wpos_temp; /* temp register */
- int i, j;
-
- /* PARAM win_size = STATE_FB_WPOS_Y_TRANSFORM */
- win_size = _mesa_add_state_reference(fprog->Base.Parameters, winstate);
-
- wpos_temp = fprog->Base.NumTemporaries++;
-
- /* scan program where WPOS is used and replace with wpos_temp */
- inst = fprog->Base.Instructions;
- for (i = 0; i < fprog->Base.NumInstructions; i++) {
- for (j=0; j < 3; j++) {
- if(inst->SrcReg[j].File == PROGRAM_INPUT &&
- inst->SrcReg[j].Index == FRAG_ATTRIB_WPOS) {
- inst->SrcReg[j].File = PROGRAM_TEMPORARY;
- inst->SrcReg[j].Index = wpos_temp;
- }
- }
- inst++;
- }
-
- _mesa_insert_instructions(&(fprog->Base), 0, 1);
-
- newInst = fprog->Base.Instructions;
- /* possibly invert wpos.y depending on STATE_FB_WPOS_Y_TRANSFORM var */
- newInst[0].Opcode = OPCODE_MAD;
- newInst[0].DstReg.File = PROGRAM_TEMPORARY;
- newInst[0].DstReg.Index = wpos_temp;
- newInst[0].DstReg.WriteMask = WRITEMASK_XYZW;
-
- newInst[0].SrcReg[0].File = PROGRAM_INPUT;
- newInst[0].SrcReg[0].Index = FRAG_ATTRIB_WPOS;
- newInst[0].SrcReg[0].Swizzle = SWIZZLE_XYZW;
-
- newInst[0].SrcReg[1].File = PROGRAM_STATE_VAR;
- newInst[0].SrcReg[1].Index = win_size;
- newInst[0].SrcReg[1].Swizzle = MAKE_SWIZZLE4(SWIZZLE_ONE, SWIZZLE_X, SWIZZLE_ONE, SWIZZLE_ONE);
-
- newInst[0].SrcReg[2].File = PROGRAM_STATE_VAR;
- newInst[0].SrcReg[2].Index = win_size;
- newInst[0].SrcReg[2].Swizzle = MAKE_SWIZZLE4(SWIZZLE_ZERO, SWIZZLE_Y, SWIZZLE_ZERO, SWIZZLE_ZERO);
-
-}
-
-//TODO : Validate FP input with VP output.
-void Map_Fragment_Program(r700_AssemblerBase *pAsm,
- struct gl_fragment_program *mesa_fp,
- struct gl_context *ctx)
-{
- unsigned int unBit;
- unsigned int i;
-
- /* match fp inputs with vp exports. */
- struct r700_vertex_program_cont *vpc =
- (struct r700_vertex_program_cont *)ctx->VertexProgram._Current;
- GLbitfield OutputsWritten = vpc->mesa_program.Base.OutputsWritten;
-
- pAsm->number_used_registers = 0;
-
-//Input mapping : mesa_fp->Base.InputsRead set the flag, set in
- //The flags parsed in parse_attrib_binding. FRAG_ATTRIB_COLx, FRAG_ATTRIB_TEXx, ...
- //MUST match order in Map_Vertex_Output
- unBit = 1 << FRAG_ATTRIB_WPOS;
- if(mesa_fp->Base.InputsRead & unBit)
- {
- pAsm->uiFP_AttributeMap[FRAG_ATTRIB_WPOS] = pAsm->number_used_registers++;
- }
-
- unBit = 1 << VERT_RESULT_COL0;
- if(OutputsWritten & unBit)
- {
- pAsm->uiFP_AttributeMap[FRAG_ATTRIB_COL0] = pAsm->number_used_registers++;
- }
-
- unBit = 1 << VERT_RESULT_COL1;
- if(OutputsWritten & unBit)
- {
- pAsm->uiFP_AttributeMap[FRAG_ATTRIB_COL1] = pAsm->number_used_registers++;
- }
-
- unBit = 1 << VERT_RESULT_FOGC;
- if(OutputsWritten & unBit)
- {
- pAsm->uiFP_AttributeMap[FRAG_ATTRIB_FOGC] = pAsm->number_used_registers++;
- }
-
- for(i=0; i<8; i++)
- {
- unBit = 1 << (VERT_RESULT_TEX0 + i);
- if(OutputsWritten & unBit)
- {
- pAsm->uiFP_AttributeMap[FRAG_ATTRIB_TEX0 + i] = pAsm->number_used_registers++;
- }
- }
-
-/* order has been taken care of */
-#if 1
- for(i=VERT_RESULT_VAR0; i<VERT_RESULT_MAX; i++)
- {
- unBit = 1 << i;
- if(OutputsWritten & unBit)
- {
- pAsm->uiFP_AttributeMap[i-VERT_RESULT_VAR0+FRAG_ATTRIB_VAR0] = pAsm->number_used_registers++;
- }
- }
-#else
- if( (mesa_fp->Base.InputsRead >> FRAG_ATTRIB_VAR0) > 0 )
- {
- struct r700_vertex_program_cont *vpc =
- (struct r700_vertex_program_cont *)ctx->VertexProgram._Current;
- struct gl_program_parameter_list * VsVarying = vpc->mesa_program.Base.Varying;
- struct gl_program_parameter_list * PsVarying = mesa_fp->Base.Varying;
- struct gl_program_parameter * pVsParam;
- struct gl_program_parameter * pPsParam;
- GLuint j, k;
- GLuint unMaxVarying = 0;
-
- for(i=0; i<VsVarying->NumParameters; i++)
- {
- pAsm->uiFP_AttributeMap[i + FRAG_ATTRIB_VAR0] = 0;
- }
-
- for(i=FRAG_ATTRIB_VAR0; i<FRAG_ATTRIB_MAX; i++)
- {
- unBit = 1 << i;
- if(mesa_fp->Base.InputsRead & unBit)
- {
- j = i - FRAG_ATTRIB_VAR0;
- pPsParam = PsVarying->Parameters + j;
-
- for(k=0; k<VsVarying->NumParameters; k++)
- {
- pVsParam = VsVarying->Parameters + k;
-
- if( strcmp(pPsParam->Name, pVsParam->Name) == 0)
- {
- pAsm->uiFP_AttributeMap[i] = pAsm->number_used_registers + k;
- if(k > unMaxVarying)
- {
- unMaxVarying = k;
- }
- break;
- }
- }
- }
- }
-
- pAsm->number_used_registers += unMaxVarying + 1;
- }
-#endif
- unBit = 1 << FRAG_ATTRIB_FACE;
- if(mesa_fp->Base.InputsRead & unBit)
- {
- pAsm->uiFP_AttributeMap[FRAG_ATTRIB_FACE] = pAsm->number_used_registers++;
- }
-
- unBit = 1 << FRAG_ATTRIB_PNTC;
- if(mesa_fp->Base.InputsRead & unBit)
- {
- pAsm->uiFP_AttributeMap[FRAG_ATTRIB_PNTC] = pAsm->number_used_registers++;
- }
-
-/* Map temporary registers (GPRs) */
- pAsm->starting_temp_register_number = pAsm->number_used_registers;
-
- if(mesa_fp->Base.NumNativeTemporaries >= mesa_fp->Base.NumTemporaries)
- {
- pAsm->number_used_registers += mesa_fp->Base.NumNativeTemporaries;
- }
- else
- {
- pAsm->number_used_registers += mesa_fp->Base.NumTemporaries;
- }
-
-/* Output mapping */
- pAsm->number_of_exports = 0;
- pAsm->number_of_colorandz_exports = 0; /* don't include stencil and mask out. */
- pAsm->starting_export_register_number = pAsm->number_used_registers;
-
- for (i = 0; i < FRAG_RESULT_MAX; ++i)
- {
- unBit = 1 << i;
- if (mesa_fp->Base.OutputsWritten & unBit)
- {
- if (i == FRAG_RESULT_DEPTH)
- {
- pAsm->depth_export_register_number = pAsm->number_used_registers;
- pAsm->pR700Shader->depthIsExported = 1;
- }
-
- pAsm->uiFP_OutputMap[i] = pAsm->number_used_registers++;
- ++pAsm->number_of_exports;
- ++pAsm->number_of_colorandz_exports;
- }
- }
-
- pAsm->flag_reg_index = pAsm->number_used_registers++;
-
- pAsm->uFirstHelpReg = pAsm->number_used_registers;
-}
-
-GLboolean Find_Instruction_Dependencies_fp(struct r700_fragment_program *fp,
- struct gl_fragment_program *mesa_fp)
-{
- GLuint i, j;
- GLint * puiTEMPwrites;
- GLint * puiTEMPreads;
- struct prog_instruction * pILInst;
- InstDeps *pInstDeps;
- struct prog_instruction * texcoord_DepInst;
- GLint nDepInstID;
-
- puiTEMPwrites = (GLint*) MALLOC(sizeof(GLuint)*mesa_fp->Base.NumTemporaries);
- puiTEMPreads = (GLint*) MALLOC(sizeof(GLuint)*mesa_fp->Base.NumTemporaries);
-
- for(i=0; i<mesa_fp->Base.NumTemporaries; i++)
- {
- puiTEMPwrites[i] = -1;
- puiTEMPreads[i] = -1;
- }
-
- pInstDeps = (InstDeps*)MALLOC(sizeof(InstDeps)*mesa_fp->Base.NumInstructions);
-
- for(i=0; i<mesa_fp->Base.NumInstructions; i++)
- {
- pInstDeps[i].nDstDep = -1;
- pILInst = &(mesa_fp->Base.Instructions[i]);
-
- //Dst
- if(pILInst->DstReg.File == PROGRAM_TEMPORARY)
- {
- //Set lastwrite for the temp
- puiTEMPwrites[pILInst->DstReg.Index] = i;
- }
-
- //Src
- for(j=0; j<3; j++)
- {
- if(pILInst->SrcReg[j].File == PROGRAM_TEMPORARY)
- {
- //Set dep.
- pInstDeps[i].nSrcDeps[j] = puiTEMPwrites[pILInst->SrcReg[j].Index];
- //Set first read
- if(puiTEMPreads[pILInst->SrcReg[j].Index] < 0 )
- {
- puiTEMPreads[pILInst->SrcReg[j].Index] = i;
- }
- }
- else
- {
- pInstDeps[i].nSrcDeps[j] = -1;
- }
- }
- }
-
- fp->r700AsmCode.pInstDeps = pInstDeps;
-
- //Find dep for tex inst
- for(i=0; i<mesa_fp->Base.NumInstructions; i++)
- {
- pILInst = &(mesa_fp->Base.Instructions[i]);
-
- if(GL_TRUE == IsTex(pILInst->Opcode))
- { //src0 is the tex coord register, src1 is texunit, src2 is textype
- nDepInstID = pInstDeps[i].nSrcDeps[0];
- if(nDepInstID >= 0)
- {
- texcoord_DepInst = &(mesa_fp->Base.Instructions[nDepInstID]);
- if(GL_TRUE == IsAlu(texcoord_DepInst->Opcode) )
- {
- pInstDeps[nDepInstID].nDstDep = i;
- pInstDeps[i].nDstDep = i;
- }
- else if(GL_TRUE == IsTex(texcoord_DepInst->Opcode) )
- {
- pInstDeps[i].nDstDep = i;
- }
- else
- { //... other deps?
- }
- }
- // make sure that we dont overwrite src used earlier
- nDepInstID = puiTEMPreads[pILInst->DstReg.Index];
- if(nDepInstID < i)
- {
- pInstDeps[i].nDstDep = puiTEMPreads[pILInst->DstReg.Index];
- texcoord_DepInst = &(mesa_fp->Base.Instructions[nDepInstID]);
- if(GL_TRUE == IsAlu(texcoord_DepInst->Opcode) )
- {
- pInstDeps[nDepInstID].nDstDep = i;
- }
-
- }
-
- }
- }
-
- FREE(puiTEMPwrites);
- FREE(puiTEMPreads);
-
- return GL_TRUE;
-}
-
-GLboolean r700TranslateFragmentShader(struct r700_fragment_program *fp,
- struct gl_fragment_program *mesa_fp,
- struct gl_context *ctx)
-{
- context_t *context = R700_CONTEXT(ctx);
- R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
-
- GLuint number_of_colors_exported;
- GLboolean z_enabled = GL_FALSE;
- GLuint unBit, shadow_unit;
- int i;
- struct prog_instruction *inst;
- gl_state_index shadow_ambient[STATE_LENGTH]
- = { STATE_INTERNAL, STATE_SHADOW_AMBIENT, 0, 0, 0};
-
- //Init_Program
- Init_r700_AssemblerBase( SPT_FP, &(fp->r700AsmCode), &(fp->r700Shader) );
-
- if(GL_TRUE == r700->bShaderUseMemConstant)
- {
- fp->r700AsmCode.bUseMemConstant = GL_TRUE;
- }
- else
- {
- fp->r700AsmCode.bUseMemConstant = GL_FALSE;
- }
-
- fp->r700AsmCode.unAsic = 7;
-
- if(mesa_fp->Base.InputsRead & FRAG_BIT_WPOS)
- {
- insert_wpos_code(ctx, mesa_fp);
- }
-
- /* add/map consts for ARB_shadow_ambient */
- if(mesa_fp->Base.ShadowSamplers)
- {
- inst = mesa_fp->Base.Instructions;
- for (i = 0; i < mesa_fp->Base.NumInstructions; i++)
- {
- if(inst->TexShadow == 1)
- {
- shadow_unit = inst->TexSrcUnit;
- shadow_ambient[2] = shadow_unit;
- fp->r700AsmCode.shadow_regs[shadow_unit] =
- _mesa_add_state_reference(mesa_fp->Base.Parameters, shadow_ambient);
- }
- inst++;
- }
- }
-
- Map_Fragment_Program(&(fp->r700AsmCode), mesa_fp, ctx);
-
- if( GL_FALSE == Find_Instruction_Dependencies_fp(fp, mesa_fp) )
- {
- return GL_FALSE;
- }
-
- InitShaderProgram(&(fp->r700AsmCode));
-
- for(i=0; i < MAX_SAMPLERS; i++)
- {
- fp->r700AsmCode.SamplerUnits[i] = fp->mesa_program.Base.SamplerUnits[i];
- }
-
- fp->r700AsmCode.unCurNumILInsts = mesa_fp->Base.NumInstructions;
-
- if( GL_FALSE == AssembleInstr(0,
- 0,
- mesa_fp->Base.NumInstructions,
- &(mesa_fp->Base.Instructions[0]),
- &(fp->r700AsmCode)) )
- {
- return GL_FALSE;
- }
-
- if(GL_FALSE == Process_Fragment_Exports(&(fp->r700AsmCode), mesa_fp->Base.OutputsWritten) )
- {
- return GL_FALSE;
- }
-
- if( GL_FALSE == RelocProgram(&(fp->r700AsmCode), &(mesa_fp->Base)) )
- {
- return GL_FALSE;
- }
-
- fp->r700Shader.nRegs = (fp->r700AsmCode.number_used_registers == 0) ? 0
- : (fp->r700AsmCode.number_used_registers - 1);
-
- fp->r700Shader.nParamExports = fp->r700AsmCode.number_of_exports;
-
- number_of_colors_exported = fp->r700AsmCode.number_of_colorandz_exports;
-
- unBit = 1 << FRAG_RESULT_DEPTH;
- if(mesa_fp->Base.OutputsWritten & unBit)
- {
- z_enabled = GL_TRUE;
- number_of_colors_exported--;
- }
-
- /* illegal to set this to 0 */
- if(number_of_colors_exported || z_enabled)
- {
- fp->r700Shader.exportMode = number_of_colors_exported << 1 | z_enabled;
- }
- else
- {
- fp->r700Shader.exportMode = (1 << 1);
- }
-
- fp->translated = GL_TRUE;
-
- return GL_TRUE;
-}
-
-void r700SelectFragmentShader(struct gl_context *ctx)
-{
- context_t *context = R700_CONTEXT(ctx);
- struct r700_fragment_program *fp = (struct r700_fragment_program *)
- (ctx->FragmentProgram._Current);
- if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
- {
- fp->r700AsmCode.bR6xx = 1;
- }
-
- if (GL_FALSE == fp->translated)
- r700TranslateFragmentShader(fp, &(fp->mesa_program), ctx);
-}
-
-void * r700GetActiveFpShaderBo(struct gl_context * ctx)
-{
- struct r700_fragment_program *fp = (struct r700_fragment_program *)
- (ctx->FragmentProgram._Current);
-
- return fp->shaderbo;
-}
-
-void * r700GetActiveFpShaderConstBo(struct gl_context * ctx)
-{
- struct r700_fragment_program *fp = (struct r700_fragment_program *)
- (ctx->FragmentProgram._Current);
-
- return fp->constbo0;
-}
-
-GLboolean r700SetupFragmentProgram(struct gl_context * ctx)
-{
- context_t *context = R700_CONTEXT(ctx);
- R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
- struct r700_fragment_program *fp = (struct r700_fragment_program *)
- (ctx->FragmentProgram._Current);
- r700_AssemblerBase *pAsm = &(fp->r700AsmCode);
- struct gl_fragment_program *mesa_fp = &(fp->mesa_program);
- struct gl_program_parameter_list *paramList;
- unsigned int unNumParamData;
- unsigned int ui, i;
- unsigned int unNumOfReg;
- unsigned int unBit;
- unsigned int num_sq_ps_gprs;
- GLuint exportCount;
- GLboolean point_sprite = GL_FALSE;
-
- if(GL_FALSE == fp->loaded)
- {
- if(fp->r700Shader.bNeedsAssembly == GL_TRUE)
- {
- Assemble( &(fp->r700Shader) );
- }
-
- /* Load fp to gpu */
- r600EmitShader(ctx,
- &(fp->shaderbo),
- (GLvoid *)(fp->r700Shader.pProgram),
- fp->r700Shader.uShaderBinaryDWORDSize,
- "FS");
-
- fp->loaded = GL_TRUE;
- }
-
- DumpHwBinary(DUMP_PIXEL_SHADER, (GLvoid *)(fp->r700Shader.pProgram),
- fp->r700Shader.uShaderBinaryDWORDSize);
-
- /* TODO : enable this after MemUse fixed *=
- (context->chipobj.MemUse)(context, fp->shadercode.buf->id);
- */
-
- R600_STATECHANGE(context, ps);
-
- r700->ps.SQ_PGM_RESOURCES_PS.u32All = 0;
- SETbit(r700->ps.SQ_PGM_RESOURCES_PS.u32All, PGM_RESOURCES__PRIME_CACHE_ON_DRAW_bit);
-
- r700->ps.SQ_PGM_START_PS.u32All = 0; /* set from buffer obj */
-
- R600_STATECHANGE(context, spi);
-
- unNumOfReg = fp->r700Shader.nRegs + 1;
-
- ui = (r700->SPI_PS_IN_CONTROL_0.u32All & NUM_INTERP_mask) / (1 << NUM_INTERP_shift);
-
- /* PS uses fragment.position */
- if (mesa_fp->Base.InputsRead & (1 << FRAG_ATTRIB_WPOS))
- {
- ui += 1;
- SETfield(r700->SPI_PS_IN_CONTROL_0.u32All, ui, NUM_INTERP_shift, NUM_INTERP_mask);
- SETfield(r700->SPI_PS_IN_CONTROL_0.u32All, CENTERS_ONLY, BARYC_SAMPLE_CNTL_shift, BARYC_SAMPLE_CNTL_mask);
- SETbit(r700->SPI_PS_IN_CONTROL_0.u32All, POSITION_ENA_bit);
- SETbit(r700->SPI_INPUT_Z.u32All, PROVIDE_Z_TO_SPI_bit);
- }
- else
- {
- CLEARbit(r700->SPI_PS_IN_CONTROL_0.u32All, POSITION_ENA_bit);
- CLEARbit(r700->SPI_INPUT_Z.u32All, PROVIDE_Z_TO_SPI_bit);
- }
-
- if (mesa_fp->Base.InputsRead & (1 << FRAG_ATTRIB_FACE))
- {
- ui += 1;
- SETfield(r700->SPI_PS_IN_CONTROL_0.u32All, ui, NUM_INTERP_shift, NUM_INTERP_mask);
- SETbit(r700->SPI_PS_IN_CONTROL_1.u32All, FRONT_FACE_ENA_bit);
- SETbit(r700->SPI_PS_IN_CONTROL_1.u32All, FRONT_FACE_ALL_BITS_bit);
- SETfield(r700->SPI_PS_IN_CONTROL_1.u32All, pAsm->uiFP_AttributeMap[FRAG_ATTRIB_FACE], FRONT_FACE_ADDR_shift, FRONT_FACE_ADDR_mask);
- }
- else
- {
- CLEARbit(r700->SPI_PS_IN_CONTROL_1.u32All, FRONT_FACE_ENA_bit);
- }
-
- /* see if we need any point_sprite replacements, also increase num_interp
- * as there's no vp output for them */
- if (ctx->Point.PointSprite)
- {
- for (i = FRAG_ATTRIB_TEX0; i<= FRAG_ATTRIB_TEX7; i++)
- {
- if (ctx->Point.CoordReplace[i - FRAG_ATTRIB_TEX0] == GL_TRUE)
- {
- ui++;
- point_sprite = GL_TRUE;
- }
- }
- }
-
- if( mesa_fp->Base.InputsRead & (1 << FRAG_ATTRIB_PNTC))
- ui++;
-
- if ((mesa_fp->Base.InputsRead & (1 << FRAG_ATTRIB_PNTC)) || point_sprite)
- {
- SETfield(r700->SPI_PS_IN_CONTROL_0.u32All, ui, NUM_INTERP_shift, NUM_INTERP_mask);
- SETbit(r700->SPI_INTERP_CONTROL_0.u32All, PNT_SPRITE_ENA_bit);
- SETfield(r700->SPI_INTERP_CONTROL_0.u32All, SPI_PNT_SPRITE_SEL_S, PNT_SPRITE_OVRD_X_shift, PNT_SPRITE_OVRD_X_mask);
- SETfield(r700->SPI_INTERP_CONTROL_0.u32All, SPI_PNT_SPRITE_SEL_T, PNT_SPRITE_OVRD_Y_shift, PNT_SPRITE_OVRD_Y_mask);
- SETfield(r700->SPI_INTERP_CONTROL_0.u32All, SPI_PNT_SPRITE_SEL_0, PNT_SPRITE_OVRD_Z_shift, PNT_SPRITE_OVRD_Z_mask);
- SETfield(r700->SPI_INTERP_CONTROL_0.u32All, SPI_PNT_SPRITE_SEL_1, PNT_SPRITE_OVRD_W_shift, PNT_SPRITE_OVRD_W_mask);
- /* Like e.g. viewport and winding, point sprite coordinates are
- * inverted when rendering to FBO. */
- if ((ctx->Point.SpriteOrigin == GL_LOWER_LEFT) == !ctx->DrawBuffer->Name)
- SETbit(r700->SPI_INTERP_CONTROL_0.u32All, PNT_SPRITE_TOP_1_bit);
- else
- CLEARbit(r700->SPI_INTERP_CONTROL_0.u32All, PNT_SPRITE_TOP_1_bit);
- }
- else
- {
- CLEARbit(r700->SPI_INTERP_CONTROL_0.u32All, PNT_SPRITE_ENA_bit);
- }
-
-
- ui = (unNumOfReg < ui) ? ui : unNumOfReg;
-
- SETfield(r700->ps.SQ_PGM_RESOURCES_PS.u32All, ui, NUM_GPRS_shift, NUM_GPRS_mask);
-
- num_sq_ps_gprs = ((r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All & NUM_PS_GPRS_mask) >> NUM_PS_GPRS_shift);
-
- if(ui > num_sq_ps_gprs)
- {
- /* care! thich changes sq - needs idle state */
- R600_STATECHANGE(context, sq);
- SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All, ui, NUM_PS_GPRS_shift, NUM_PS_GPRS_mask);
- }
-
- CLEARbit(r700->ps.SQ_PGM_RESOURCES_PS.u32All, UNCACHED_FIRST_INST_bit);
-
- if(fp->r700Shader.uStackSize) /* we don't use branch for now, it should be zero. */
- {
- SETfield(r700->ps.SQ_PGM_RESOURCES_PS.u32All, fp->r700Shader.uStackSize,
- STACK_SIZE_shift, STACK_SIZE_mask);
- }
-
- SETfield(r700->ps.SQ_PGM_EXPORTS_PS.u32All, fp->r700Shader.exportMode,
- EXPORT_MODE_shift, EXPORT_MODE_mask);
-
- // emit ps input map
- struct r700_vertex_program_cont *vpc =
- (struct r700_vertex_program_cont *)ctx->VertexProgram._Current;
- GLbitfield OutputsWritten = vpc->mesa_program.Base.OutputsWritten;
-
- for(ui = 0; ui < R700_MAX_SHADER_EXPORTS; ui++)
- r700->SPI_PS_INPUT_CNTL[ui].u32All = 0;
-
- unBit = 1 << FRAG_ATTRIB_WPOS;
- if(mesa_fp->Base.InputsRead & unBit)
- {
- ui = pAsm->uiFP_AttributeMap[FRAG_ATTRIB_WPOS];
- SETbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, SEL_CENTROID_bit);
- SETfield(r700->SPI_PS_INPUT_CNTL[ui].u32All, ui,
- SEMANTIC_shift, SEMANTIC_mask);
- CLEARbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit);
- }
-
- unBit = 1 << VERT_RESULT_COL0;
- if(OutputsWritten & unBit)
- {
- ui = pAsm->uiFP_AttributeMap[FRAG_ATTRIB_COL0];
- SETbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, SEL_CENTROID_bit);
- SETfield(r700->SPI_PS_INPUT_CNTL[ui].u32All, ui,
- SEMANTIC_shift, SEMANTIC_mask);
- if (r700->SPI_INTERP_CONTROL_0.u32All & FLAT_SHADE_ENA_bit)
- SETbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit);
- else
- CLEARbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit);
- }
-
- unBit = 1 << VERT_RESULT_COL1;
- if(OutputsWritten & unBit)
- {
- ui = pAsm->uiFP_AttributeMap[FRAG_ATTRIB_COL1];
- SETbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, SEL_CENTROID_bit);
- SETfield(r700->SPI_PS_INPUT_CNTL[ui].u32All, ui,
- SEMANTIC_shift, SEMANTIC_mask);
- if (r700->SPI_INTERP_CONTROL_0.u32All & FLAT_SHADE_ENA_bit)
- SETbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit);
- else
- CLEARbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit);
- }
-
- unBit = 1 << VERT_RESULT_FOGC;
- if(OutputsWritten & unBit)
- {
- ui = pAsm->uiFP_AttributeMap[FRAG_ATTRIB_FOGC];
- SETbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, SEL_CENTROID_bit);
- SETfield(r700->SPI_PS_INPUT_CNTL[ui].u32All, ui,
- SEMANTIC_shift, SEMANTIC_mask);
- CLEARbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit);
- }
-
- for(i=0; i<8; i++)
- {
- GLboolean coord_replace = ctx->Point.PointSprite && ctx->Point.CoordReplace[i];
- unBit = 1 << (VERT_RESULT_TEX0 + i);
- if ((OutputsWritten & unBit) || coord_replace)
- {
- ui = pAsm->uiFP_AttributeMap[FRAG_ATTRIB_TEX0 + i];
- SETbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, SEL_CENTROID_bit);
- SETfield(r700->SPI_PS_INPUT_CNTL[ui].u32All, ui,
- SEMANTIC_shift, SEMANTIC_mask);
- CLEARbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit);
- /* ARB_point_sprite */
- if (coord_replace)
- {
- SETbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, PT_SPRITE_TEX_bit);
- }
- }
- }
-
- unBit = 1 << FRAG_ATTRIB_FACE;
- if(mesa_fp->Base.InputsRead & unBit)
- {
- ui = pAsm->uiFP_AttributeMap[FRAG_ATTRIB_FACE];
- SETbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, SEL_CENTROID_bit);
- SETfield(r700->SPI_PS_INPUT_CNTL[ui].u32All, ui,
- SEMANTIC_shift, SEMANTIC_mask);
- CLEARbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit);
- }
- unBit = 1 << FRAG_ATTRIB_PNTC;
- if(mesa_fp->Base.InputsRead & unBit)
- {
- ui = pAsm->uiFP_AttributeMap[FRAG_ATTRIB_PNTC];
- SETbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, SEL_CENTROID_bit);
- SETfield(r700->SPI_PS_INPUT_CNTL[ui].u32All, ui,
- SEMANTIC_shift, SEMANTIC_mask);
- if (r700->SPI_INTERP_CONTROL_0.u32All & FLAT_SHADE_ENA_bit)
- SETbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit);
- else
- CLEARbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit);
- SETbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, PT_SPRITE_TEX_bit);
- }
-
-
-
-
- for(i=VERT_RESULT_VAR0; i<VERT_RESULT_MAX; i++)
- {
- unBit = 1 << i;
- if(OutputsWritten & unBit)
- {
- ui = pAsm->uiFP_AttributeMap[i-VERT_RESULT_VAR0+FRAG_ATTRIB_VAR0];
- SETbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, SEL_CENTROID_bit);
- SETfield(r700->SPI_PS_INPUT_CNTL[ui].u32All, ui,
- SEMANTIC_shift, SEMANTIC_mask);
- CLEARbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit);
- }
- }
-
- exportCount = (r700->ps.SQ_PGM_EXPORTS_PS.u32All & EXPORT_MODE_mask) / (1 << EXPORT_MODE_shift);
- if (r700->CB_SHADER_CONTROL.u32All != ((1 << exportCount) - 1))
- {
- R600_STATECHANGE(context, cb);
- r700->CB_SHADER_CONTROL.u32All = (1 << exportCount) - 1;
- }
-
- /* sent out shader constants. */
- paramList = fp->mesa_program.Base.Parameters;
-
- if(NULL != paramList)
- {
- _mesa_load_state_parameters(ctx, paramList);
-
- if (paramList->NumParameters > R700_MAX_DX9_CONSTS)
- return GL_FALSE;
-
- R600_STATECHANGE(context, ps_consts);
-
- r700->ps.num_consts = paramList->NumParameters;
-
- unNumParamData = paramList->NumParameters;
-
- for(ui=0; ui<unNumParamData; ui++) {
- r700->ps.consts[ui][0].f32All = paramList->ParameterValues[ui][0].f;
- r700->ps.consts[ui][1].f32All = paramList->ParameterValues[ui][1].f;
- r700->ps.consts[ui][2].f32All = paramList->ParameterValues[ui][2].f;
- r700->ps.consts[ui][3].f32All = paramList->ParameterValues[ui][3].f;
- }
-
- /* Load fp constants to gpu */
- if( (GL_TRUE == r700->bShaderUseMemConstant) && (unNumParamData > 0) )
- {
- r600EmitShader(ctx,
- &(fp->constbo0),
- (GLvoid *)&(paramList->ParameterValues[0][0]),
- unNumParamData * 4,
- "FS Const");
- }
-
- } else
- r700->ps.num_consts = 0;
-
- COMPILED_SUB * pCompiledSub;
- GLuint uj;
- GLuint unConstOffset = r700->ps.num_consts;
- for(ui=0; ui<pAsm->unNumPresub; ui++)
- {
- pCompiledSub = pAsm->presubs[ui].pCompiledSub;
-
- r700->ps.num_consts += pCompiledSub->NumParameters;
-
- for(uj=0; uj<pCompiledSub->NumParameters; uj++)
- {
- r700->ps.consts[uj + unConstOffset][0].f32All = pCompiledSub->ParameterValues[uj][0];
- r700->ps.consts[uj + unConstOffset][1].f32All = pCompiledSub->ParameterValues[uj][1];
- r700->ps.consts[uj + unConstOffset][2].f32All = pCompiledSub->ParameterValues[uj][2];
- r700->ps.consts[uj + unConstOffset][3].f32All = pCompiledSub->ParameterValues[uj][3];
- }
- unConstOffset += pCompiledSub->NumParameters;
- }
-
- return GL_TRUE;
-}
-
+++ /dev/null
-/*
- * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Authors:
- * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
- */
-
-#ifndef _R700_FRAGPROG_H_
-#define _R700_FRAGPROG_H_
-
-#include "r600_context.h"
-#include "r700_assembler.h"
-
-struct r700_fragment_program
-{
- struct gl_fragment_program mesa_program;
-
- r700_AssemblerBase r700AsmCode;
- R700_Shader r700Shader;
-
- GLboolean translated;
- GLboolean loaded;
- GLboolean error;
-
- void * shaderbo;
-
- GLuint k0used;
- void * constbo0;
-
- GLboolean WritesDepth;
- GLuint optimization;
-};
-
-/* Internal */
-void insert_wpos_code(struct gl_context *ctx, struct gl_fragment_program *fprog);
-
-void Map_Fragment_Program(r700_AssemblerBase *pAsm,
- struct gl_fragment_program *mesa_fp,
- struct gl_context *ctx);
-GLboolean Find_Instruction_Dependencies_fp(struct r700_fragment_program *fp,
- struct gl_fragment_program *mesa_fp);
-
-GLboolean r700TranslateFragmentShader(struct r700_fragment_program *fp,
- struct gl_fragment_program *mesa_vp,
- struct gl_context *ctx);
-
-/* Interface */
-extern void r700SelectFragmentShader(struct gl_context *ctx);
-
-extern GLboolean r700SetupFragmentProgram(struct gl_context * ctx);
-
-extern void * r700GetActiveFpShaderBo(struct gl_context * ctx);
-
-extern void * r700GetActiveFpShaderConstBo(struct gl_context * ctx);
-
-#endif /*_R700_FRAGPROG_H_*/
+++ /dev/null
-/*
- * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Authors:
- * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
- */
-
-#include <sched.h>
-#include <errno.h>
-
-#include "main/glheader.h"
-#include "main/imports.h"
-#include "main/macros.h"
-#include "main/context.h"
-#include "main/simple_list.h"
-
-#include "radeon_common.h"
-#include "r600_context.h"
-
-#include "r700_ioctl.h"
-#include "r700_clear.h"
-
-
-void r700InitIoctlFuncs(struct dd_function_table *functions)
-{
- functions->Clear = r700Clear;
- functions->Finish = radeonFinish;
- functions->Flush = radeonFlush;
-}
+++ /dev/null
-/*
- * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Authors:
- * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
- */
-
-#ifndef __R700_IOCTL_H__
-#define __R700_IOCTL_H__
-
-#include "r600_context.h"
-#include "radeon_drm.h"
-
-extern void r700InitIoctlFuncs(struct dd_function_table *functions);
-
-#endif /* __R700_IOCTL_H__ */
+++ /dev/null
-/*
- * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Authors:
- * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
- */
-
-#include <string.h>
-
-#include "main/glheader.h"
-#include "main/imports.h"
-
-#include "program/program.h"
-#include "tnl/tnl.h"
-
-#include "r600_context.h"
-#include "r600_emit.h"
-
-#include "r700_oglprog.h"
-#include "r700_fragprog.h"
-#include "r700_vertprog.h"
-
-
-static void freeVertProgCache(struct gl_context *ctx, struct r700_vertex_program_cont *cache)
-{
- struct r700_vertex_program *tmp, *vp = cache->progs;
-
- while (vp) {
- tmp = vp->next;
- /* Release DMA region */
- r600DeleteShader(ctx, vp->shaderbo);
-
- if(NULL != vp->constbo0)
- {
- r600DeleteShader(ctx, vp->constbo0);
- }
-
- /* Clean up */
- Clean_Up_Assembler(&(vp->r700AsmCode));
- Clean_Up_Shader(&(vp->r700Shader));
-
- _mesa_reference_vertprog(ctx, &vp->mesa_program, NULL);
- free(vp);
- vp = tmp;
- }
-}
-
-static struct gl_program *r700NewProgram(struct gl_context * ctx,
- GLenum target,
- GLuint id)
-{
- struct gl_program *pProgram = NULL;
-
- struct r700_vertex_program_cont *vpc;
- struct r700_fragment_program *fp;
-
- radeon_print(RADEON_SHADER, RADEON_VERBOSE,
- "%s %u, %u\n", __func__, target, id);
-
- switch (target)
- {
- case GL_VERTEX_STATE_PROGRAM_NV:
- case GL_VERTEX_PROGRAM_ARB:
- vpc = CALLOC_STRUCT(r700_vertex_program_cont);
- pProgram = _mesa_init_vertex_program(ctx,
- &vpc->mesa_program,
- target,
- id);
-
- break;
- case GL_FRAGMENT_PROGRAM_NV:
- case GL_FRAGMENT_PROGRAM_ARB:
- fp = CALLOC_STRUCT(r700_fragment_program);
- pProgram = _mesa_init_fragment_program(ctx,
- &fp->mesa_program,
- target,
- id);
- fp->translated = GL_FALSE;
- fp->loaded = GL_FALSE;
-
- fp->shaderbo = NULL;
-
- fp->constbo0 = NULL;
-
- break;
- default:
- _mesa_problem(ctx, "Bad target in r700NewProgram");
- }
-
- return pProgram;
-}
-
-static void r700DeleteProgram(struct gl_context * ctx, struct gl_program *prog)
-{
- struct r700_vertex_program_cont *vpc = (struct r700_vertex_program_cont *)prog;
- struct r700_fragment_program * fp;
-
- radeon_print(RADEON_SHADER, RADEON_VERBOSE,
- "%s %p\n", __func__, prog);
-
- switch (prog->Target)
- {
- case GL_VERTEX_STATE_PROGRAM_NV:
- case GL_VERTEX_PROGRAM_ARB:
- freeVertProgCache(ctx, vpc);
- break;
- case GL_FRAGMENT_PROGRAM_NV:
- case GL_FRAGMENT_PROGRAM_ARB:
- fp = (struct r700_fragment_program*)prog;
- /* Release DMA region */
-
- r600DeleteShader(ctx, fp->shaderbo);
-
- if(NULL != fp->constbo0)
- {
- r600DeleteShader(ctx, fp->constbo0);
- }
-
- /* Clean up */
- Clean_Up_Assembler(&(fp->r700AsmCode));
- Clean_Up_Shader(&(fp->r700Shader));
- break;
- default:
- _mesa_problem(ctx, "Bad target in r700NewProgram");
- }
-
- _mesa_delete_program(ctx, prog);
-}
-
-static GLboolean
-r700ProgramStringNotify(struct gl_context * ctx, GLenum target, struct gl_program *prog)
-{
- struct r700_vertex_program_cont *vpc = (struct r700_vertex_program_cont *)prog;
- struct r700_fragment_program * fp = (struct r700_fragment_program*)prog;
-
- switch (target) {
- case GL_VERTEX_PROGRAM_ARB:
- freeVertProgCache(ctx, vpc);
- vpc->progs = NULL;
- break;
- case GL_FRAGMENT_PROGRAM_ARB:
- r600DeleteShader(ctx, fp->shaderbo);
-
- if(NULL != fp->constbo0)
- {
- r600DeleteShader(ctx, fp->constbo0);
- fp->constbo0 = NULL;
- }
-
- Clean_Up_Assembler(&(fp->r700AsmCode));
- Clean_Up_Shader(&(fp->r700Shader));
- fp->translated = GL_FALSE;
- fp->loaded = GL_FALSE;
- fp->shaderbo = NULL;
- break;
- }
-
- /* XXX check if program is legal, within limits */
- return GL_TRUE;
-}
-
-static GLboolean r700IsProgramNative(struct gl_context * ctx, GLenum target, struct gl_program *prog)
-{
-
- return GL_TRUE;
-}
-
-void r700InitShaderFuncs(struct dd_function_table *functions)
-{
- functions->NewProgram = r700NewProgram;
- functions->DeleteProgram = r700DeleteProgram;
- functions->ProgramStringNotify = r700ProgramStringNotify;
- functions->IsProgramNative = r700IsProgramNative;
-}
+++ /dev/null
-/*
- * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Authors:
- * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
- * CooperYuan <cooper.yuan@amd.com>, <cooperyuan@gmail.com>
- */
-
-#ifndef _R700_OGLPROG_H_
-#define _R700_OGLPROG_H_
-#include "main/dd.h"
-
-extern void r700InitShaderFuncs(struct dd_function_table *functions);
-
-#endif /*_R700_OGLPROG_H_*/
+++ /dev/null
-/*
- * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Authors:
- * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
- * CooperYuan <cooper.yuan@amd.com>, <cooperyuan@gmail.com>
- */
-
-#include "main/glheader.h"
-#include "main/state.h"
-#include "main/imports.h"
-#include "main/enums.h"
-#include "main/macros.h"
-#include "main/context.h"
-#include "main/dd.h"
-#include "main/simple_list.h"
-#include "main/api_arrayelt.h"
-#include "swrast/swrast.h"
-#include "swrast_setup/swrast_setup.h"
-#include "vbo/vbo.h"
-
-#include "tnl/tnl.h"
-#include "tnl/t_vp_build.h"
-#include "tnl/t_context.h"
-#include "tnl/t_vertex.h"
-#include "vbo/vbo_context.h"
-
-#include "r600_context.h"
-#include "r600_cmdbuf.h"
-
-#include "r600_tex.h"
-
-#include "r700_vertprog.h"
-#include "r700_fragprog.h"
-#include "r700_state.h"
-
-#include "radeon_buffer_objects.h"
-#include "radeon_common_context.h"
-
-void r700WaitForIdle(context_t *context);
-void r700WaitForIdleClean(context_t *context);
-static unsigned int r700PrimitiveType(int prim);
-GLboolean r700SyncSurf(context_t *context,
- struct radeon_bo *pbo,
- uint32_t read_domain,
- uint32_t write_domain,
- uint32_t sync_type);
-
-void r700WaitForIdle(context_t *context)
-{
- BATCH_LOCALS(&context->radeon);
- radeon_print(RADEON_RENDER | RADEON_STATE, RADEON_TRACE, "%s\n", __func__);
- BEGIN_BATCH_NO_AUTOSTATE(3);
-
- R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1));
- R600_OUT_BATCH(mmWAIT_UNTIL - ASIC_CONFIG_BASE_INDEX);
- R600_OUT_BATCH(WAIT_3D_IDLE_bit);
-
- END_BATCH();
- COMMIT_BATCH();
-}
-
-void r700WaitForIdleClean(context_t *context)
-{
- BATCH_LOCALS(&context->radeon);
- radeon_print(RADEON_RENDER | RADEON_STATE, RADEON_TRACE, "%s\n", __func__);
- BEGIN_BATCH_NO_AUTOSTATE(5);
-
- R600_OUT_BATCH(CP_PACKET3(R600_IT_EVENT_WRITE, 0));
- R600_OUT_BATCH(CACHE_FLUSH_AND_INV_EVENT);
-
- R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1));
- R600_OUT_BATCH(mmWAIT_UNTIL - ASIC_CONFIG_BASE_INDEX);
- R600_OUT_BATCH(WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
-
- END_BATCH();
- COMMIT_BATCH();
-}
-
-void r700Start3D(context_t *context)
-{
- BATCH_LOCALS(&context->radeon);
- radeon_print(RADEON_RENDER | RADEON_STATE, RADEON_TRACE, "%s\n", __func__);
- if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
- {
- BEGIN_BATCH_NO_AUTOSTATE(2);
- R600_OUT_BATCH(CP_PACKET3(R600_IT_START_3D_CMDBUF, 0));
- R600_OUT_BATCH(0);
- END_BATCH();
- }
-
- BEGIN_BATCH_NO_AUTOSTATE(3);
- R600_OUT_BATCH(CP_PACKET3(R600_IT_CONTEXT_CONTROL, 1));
- R600_OUT_BATCH(0x80000000);
- R600_OUT_BATCH(0x80000000);
- END_BATCH();
-
- COMMIT_BATCH();
-}
-
-GLboolean r700SyncSurf(context_t *context,
- struct radeon_bo *pbo,
- uint32_t read_domain,
- uint32_t write_domain,
- uint32_t sync_type)
-{
- BATCH_LOCALS(&context->radeon);
- radeon_print(RADEON_RENDER | RADEON_STATE, RADEON_TRACE, "%s\n", __func__);
- uint32_t cp_coher_size;
-
- if (!pbo)
- return GL_FALSE;
-
- if (pbo->size == 0xffffffff)
- cp_coher_size = 0xffffffff;
- else
- cp_coher_size = ((pbo->size + 255) >> 8);
-
- BEGIN_BATCH_NO_AUTOSTATE(5 + 2);
- R600_OUT_BATCH(CP_PACKET3(R600_IT_SURFACE_SYNC, 3));
- R600_OUT_BATCH(sync_type);
- R600_OUT_BATCH(cp_coher_size);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(10);
- R600_OUT_BATCH_RELOC(0,
- pbo,
- 0,
- read_domain, write_domain, 0);
- END_BATCH();
- COMMIT_BATCH();
-
- return GL_TRUE;
-}
-
-static unsigned int r700PrimitiveType(int prim)
-{
- switch (prim & PRIM_MODE_MASK)
- {
- case GL_POINTS:
- return DI_PT_POINTLIST;
- break;
- case GL_LINES:
- return DI_PT_LINELIST;
- break;
- case GL_LINE_STRIP:
- return DI_PT_LINESTRIP;
- break;
- case GL_LINE_LOOP:
- return DI_PT_LINELOOP;
- break;
- case GL_TRIANGLES:
- return DI_PT_TRILIST;
- break;
- case GL_TRIANGLE_STRIP:
- return DI_PT_TRISTRIP;
- break;
- case GL_TRIANGLE_FAN:
- return DI_PT_TRIFAN;
- break;
- case GL_QUADS:
- return DI_PT_QUADLIST;
- break;
- case GL_QUAD_STRIP:
- return DI_PT_QUADSTRIP;
- break;
- case GL_POLYGON:
- return DI_PT_POLYGON;
- break;
- default:
- assert(0);
- return -1;
- break;
- }
-}
-
-static int r700NumVerts(int num_verts, int prim)
-{
- int verts_off = 0;
-
- switch (prim & PRIM_MODE_MASK) {
- case GL_POINTS:
- verts_off = 0;
- break;
- case GL_LINES:
- verts_off = num_verts % 2;
- break;
- case GL_LINE_STRIP:
- if (num_verts < 2)
- verts_off = num_verts;
- break;
- case GL_LINE_LOOP:
- if (num_verts < 2)
- verts_off = num_verts;
- break;
- case GL_TRIANGLES:
- verts_off = num_verts % 3;
- break;
- case GL_TRIANGLE_STRIP:
- if (num_verts < 3)
- verts_off = num_verts;
- break;
- case GL_TRIANGLE_FAN:
- if (num_verts < 3)
- verts_off = num_verts;
- break;
- case GL_QUADS:
- verts_off = num_verts % 4;
- break;
- case GL_QUAD_STRIP:
- if (num_verts < 4)
- verts_off = num_verts;
- else
- verts_off = num_verts % 2;
- break;
- case GL_POLYGON:
- if (num_verts < 3)
- verts_off = num_verts;
- break;
- default:
- assert(0);
- return -1;
- break;
- }
-
- return num_verts - verts_off;
-}
-
-static void r700RunRenderPrimitive(struct gl_context * ctx, int start, int end,
- int prim, GLint basevertex)
-{
- context_t *context = R700_CONTEXT(ctx);
- BATCH_LOCALS(&context->radeon);
- int type, total_emit;
- int num_indices;
- uint32_t vgt_draw_initiator = 0;
- uint32_t vgt_index_type = 0;
- uint32_t vgt_primitive_type = 0;
- uint32_t vgt_num_indices = 0;
-
- type = r700PrimitiveType(prim);
- num_indices = r700NumVerts(end - start, prim);
-
- radeon_print(RADEON_RENDER, RADEON_TRACE,
- "%s type %x num_indices %d\n",
- __func__, type, num_indices);
-
- if (type < 0 || num_indices <= 0)
- return;
-
- SETfield(vgt_primitive_type, type,
- VGT_PRIMITIVE_TYPE__PRIM_TYPE_shift, VGT_PRIMITIVE_TYPE__PRIM_TYPE_mask);
-
- SETfield(vgt_index_type, DI_INDEX_SIZE_32_BIT, INDEX_TYPE_shift, INDEX_TYPE_mask);
-
- if(GL_TRUE != context->ind_buf.is_32bit)
- {
- SETfield(vgt_index_type, DI_INDEX_SIZE_16_BIT, INDEX_TYPE_shift, INDEX_TYPE_mask);
- }
-
- /* 16-bit indexes are packed in a 32-bit value */
- SETfield(vgt_index_type,
-#if MESA_BIG_ENDIAN
- VGT_DMA_SWAP_32_BIT,
-#else
- VGT_DMA_SWAP_NONE,
-#endif
- SWAP_MODE_shift, SWAP_MODE_mask);
-
-
- vgt_num_indices = num_indices;
- SETfield(vgt_draw_initiator, DI_SRC_SEL_DMA, SOURCE_SELECT_shift, SOURCE_SELECT_mask);
- SETfield(vgt_draw_initiator, DI_MAJOR_MODE_0, MAJOR_MODE_shift, MAJOR_MODE_mask);
-
- total_emit = 3 /* VGT_PRIMITIVE_TYPE */
- + 2 /* VGT_INDEX_TYPE */
- + 2 /* NUM_INSTANCES */
- + 4 /* VTX_BASE_VTX_LOC + VTX_START_INST_LOC */
- + 5 + 2; /* DRAW_INDEX */
-
- BEGIN_BATCH_NO_AUTOSTATE(total_emit);
- // prim
- R600_OUT_BATCH_REGSEQ(VGT_PRIMITIVE_TYPE, 1);
- R600_OUT_BATCH(vgt_primitive_type);
- // index type
- R600_OUT_BATCH(CP_PACKET3(R600_IT_INDEX_TYPE, 0));
- R600_OUT_BATCH(vgt_index_type);
- // num instances
- R600_OUT_BATCH(CP_PACKET3(R600_IT_NUM_INSTANCES, 0));
- R600_OUT_BATCH(1);
- /* offset */
- R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 2));
- R600_OUT_BATCH(mmSQ_VTX_BASE_VTX_LOC - ASIC_CTL_CONST_BASE_INDEX);
- R600_OUT_BATCH(basevertex); //VTX_BASE_VTX_LOC
- R600_OUT_BATCH(0); //VTX_START_INST_LOC
- // draw packet
- R600_OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX, 3));
- R600_OUT_BATCH(context->ind_buf.bo_offset);
- R600_OUT_BATCH(0);
- R600_OUT_BATCH(vgt_num_indices);
- R600_OUT_BATCH(vgt_draw_initiator);
- R600_OUT_BATCH_RELOC(context->ind_buf.bo_offset,
- context->ind_buf.bo,
- context->ind_buf.bo_offset,
- RADEON_GEM_DOMAIN_GTT, 0, 0);
- END_BATCH();
- COMMIT_BATCH();
-}
-
-static void r700RunRenderPrimitiveImmediate(struct gl_context * ctx, int start, int end, int prim)
-{
- context_t *context = R700_CONTEXT(ctx);
- BATCH_LOCALS(&context->radeon);
- int type;
- uint32_t num_indices, total_emit = 0;
- uint32_t vgt_draw_initiator = 0;
- uint32_t vgt_index_type = 0;
- uint32_t vgt_primitive_type = 0;
- uint32_t vgt_num_indices = 0;
-
- type = r700PrimitiveType(prim);
- num_indices = r700NumVerts(end - start, prim);
-
- radeon_print(RADEON_RENDER, RADEON_TRACE,
- "%s type %x num_indices %d\n",
- __func__, type, num_indices);
-
- if (type < 0 || num_indices <= 0)
- return;
-
- SETfield(vgt_primitive_type, type,
- VGT_PRIMITIVE_TYPE__PRIM_TYPE_shift, VGT_PRIMITIVE_TYPE__PRIM_TYPE_mask);
-
- if (num_indices > 0xffff)
- {
- SETfield(vgt_index_type, DI_INDEX_SIZE_32_BIT, INDEX_TYPE_shift, INDEX_TYPE_mask);
- }
- else
- {
- SETfield(vgt_index_type, DI_INDEX_SIZE_16_BIT, INDEX_TYPE_shift, INDEX_TYPE_mask);
- }
-
- /* 16-bit indexes are packed in a 32-bit value */
- SETfield(vgt_index_type,
-#if MESA_BIG_ENDIAN
- VGT_DMA_SWAP_32_BIT,
-#else
- VGT_DMA_SWAP_NONE,
-#endif
- SWAP_MODE_shift, SWAP_MODE_mask);
-
- vgt_num_indices = num_indices;
- SETfield(vgt_draw_initiator, DI_MAJOR_MODE_0, MAJOR_MODE_shift, MAJOR_MODE_mask);
-
- SETfield(vgt_draw_initiator, DI_SRC_SEL_AUTO_INDEX, SOURCE_SELECT_shift, SOURCE_SELECT_mask);
-
- total_emit += 3 /* VGT_PRIMITIVE_TYPE */
- + 2 /* VGT_INDEX_TYPE */
- + 2 /* NUM_INSTANCES */
- + 4 /* VTX_BASE_VTX_LOC + VTX_START_INST_LOC */
- + 3; /* DRAW */
-
- BEGIN_BATCH_NO_AUTOSTATE(total_emit);
- // prim
- R600_OUT_BATCH_REGSEQ(VGT_PRIMITIVE_TYPE, 1);
- R600_OUT_BATCH(vgt_primitive_type);
- // index type
- R600_OUT_BATCH(CP_PACKET3(R600_IT_INDEX_TYPE, 0));
- R600_OUT_BATCH(vgt_index_type);
- // num instances
- R600_OUT_BATCH(CP_PACKET3(R600_IT_NUM_INSTANCES, 0));
- R600_OUT_BATCH(1);
- /* offset */
- R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 2));
- R600_OUT_BATCH(mmSQ_VTX_BASE_VTX_LOC - ASIC_CTL_CONST_BASE_INDEX);
- R600_OUT_BATCH(start); //VTX_BASE_VTX_LOC
- R600_OUT_BATCH(0); //VTX_START_INST_LOC
- // draw packet
-
- R600_OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX_AUTO, 1));
- R600_OUT_BATCH(vgt_num_indices);
- R600_OUT_BATCH(vgt_draw_initiator);
-
- END_BATCH();
- COMMIT_BATCH();
-}
-
-/* start 3d, idle, cb/db flush */
-#define PRE_EMIT_STATE_BUFSZ 5 + 5 + 14
-
-static GLuint r700PredictRenderSize(struct gl_context* ctx,
- const struct _mesa_prim *prim,
- const struct _mesa_index_buffer *ib,
- GLuint nr_prims)
-{
- context_t *context = R700_CONTEXT(ctx);
- GLboolean flushed;
- GLuint dwords, i;
- GLuint state_size;
-
- dwords = PRE_EMIT_STATE_BUFSZ;
- if (ib)
- dwords += nr_prims * 18;
- else {
- for (i = 0; i < nr_prims; ++i)
- {
- dwords += 14;
- }
- }
-
- state_size = radeonCountStateEmitSize(&context->radeon);
- flushed = rcommonEnsureCmdBufSpace(&context->radeon,
- dwords + state_size,
- __FUNCTION__);
- if (flushed)
- dwords += radeonCountStateEmitSize(&context->radeon);
- else
- dwords += state_size;
-
- radeon_print(RADEON_RENDER, RADEON_VERBOSE, "%s: total prediction size is %d.\n", __FUNCTION__, dwords);
- return dwords;
-
-}
-
-#define CONVERT( TYPE, MACRO ) do { \
- GLuint i, j, sz; \
- sz = input->Size; \
- if (input->Normalized) { \
- for (i = 0; i < count; i++) { \
- const TYPE *in = (TYPE *)src_ptr; \
- for (j = 0; j < sz; j++) { \
- *dst_ptr++ = MACRO(*in); \
- in++; \
- } \
- src_ptr += stride; \
- } \
- } else { \
- for (i = 0; i < count; i++) { \
- const TYPE *in = (TYPE *)src_ptr; \
- for (j = 0; j < sz; j++) { \
- *dst_ptr++ = (GLfloat)(*in); \
- in++; \
- } \
- src_ptr += stride; \
- } \
- } \
-} while (0)
-
-/**
- * Convert attribute data type to float
- * If the attribute uses named buffer object replace the bo with newly allocated bo
- */
-static void r700ConvertAttrib(struct gl_context *ctx, int count,
- const struct gl_client_array *input,
- struct StreamDesc *attr)
-{
- context_t *context = R700_CONTEXT(ctx);
- const GLvoid *src_ptr;
- GLboolean mapped_named_bo = GL_FALSE;
- GLfloat *dst_ptr;
- GLuint stride;
-
- stride = (input->StrideB == 0) ? getTypeSize(input->Type) * input->Size : input->StrideB;
-
- /* Convert value for first element only */
- if (input->StrideB == 0)
- {
- count = 1;
- }
-
- if (input->BufferObj->Name)
- {
- if (!input->BufferObj->Pointer)
- {
- ctx->Driver.MapBufferRange(ctx, 0, input->BufferObj->Size,
- GL_MAP_READ_BIT, input->BufferObj);
- mapped_named_bo = GL_TRUE;
- }
-
- src_ptr = ADD_POINTERS(input->BufferObj->Pointer, input->Ptr);
- }
- else
- {
- src_ptr = input->Ptr;
- }
-
- radeonAllocDmaRegion(&context->radeon, &attr->bo, &attr->bo_offset,
- sizeof(GLfloat) * input->Size * count, 32);
-
- radeon_bo_map(attr->bo, 1);
-
- dst_ptr = (GLfloat *)ADD_POINTERS(attr->bo->ptr, attr->bo_offset);
-
- assert(src_ptr != NULL);
-
- switch (input->Type)
- {
- case GL_DOUBLE:
- CONVERT(GLdouble, (GLfloat));
- break;
- case GL_UNSIGNED_INT:
- CONVERT(GLuint, UINT_TO_FLOAT);
- break;
- case GL_INT:
- CONVERT(GLint, INT_TO_FLOAT);
- break;
- case GL_UNSIGNED_SHORT:
- CONVERT(GLushort, USHORT_TO_FLOAT);
- break;
- case GL_SHORT:
- CONVERT(GLshort, SHORT_TO_FLOAT);
- break;
- case GL_UNSIGNED_BYTE:
- assert(input->Format != GL_BGRA);
- CONVERT(GLubyte, UBYTE_TO_FLOAT);
- break;
- case GL_BYTE:
- CONVERT(GLbyte, BYTE_TO_FLOAT);
- break;
- default:
- assert(0);
- break;
- }
-
- radeon_bo_unmap(attr->bo);
-
- if (mapped_named_bo)
- {
- ctx->Driver.UnmapBuffer(ctx, input->BufferObj);
- }
-}
-
-#if 0 /* unused */
-static void r700AlignDataToDword(struct gl_context *ctx,
- const struct gl_client_array *input,
- int count,
- struct StreamDesc *attr)
-{
- context_t *context = R700_CONTEXT(ctx);
- const int dst_stride = (input->StrideB + 3) & ~3;
- const int size = getTypeSize(input->Type) * input->Size * count;
- GLboolean mapped_named_bo = GL_FALSE;
-
- radeonAllocDmaRegion(&context->radeon, &attr->bo, &attr->bo_offset, size, 32);
-
- radeon_bo_map(attr->bo, 1);
-
- if (!input->BufferObj->Pointer)
- {
- ctx->Driver.MapBufferRange(ctx, 0, input->BufferObj->Size,
- GL_MAP_READ_BIT, input->BufferObj);
- mapped_named_bo = GL_TRUE;
- }
-
- {
- GLvoid *src_ptr = ADD_POINTERS(input->BufferObj->Pointer, input->Ptr);
- GLvoid *dst_ptr = ADD_POINTERS(attr->bo->ptr, attr->bo_offset);
- int i;
-
- for (i = 0; i < count; ++i)
- {
- memcpy(dst_ptr, src_ptr, input->StrideB);
- src_ptr += input->StrideB;
- dst_ptr += dst_stride;
- }
- }
-
- radeon_bo_unmap(attr->bo);
- if (mapped_named_bo)
- {
- ctx->Driver.UnmapBuffer(ctx, input->BufferObj);
- }
-
- attr->stride = dst_stride;
-}
-#endif
-
-static void r700SetupStreams(struct gl_context *ctx, const struct gl_client_array *input[], int count)
-{
- context_t *context = R700_CONTEXT(ctx);
- GLuint stride;
- int ret;
- int i, index;
-
- R600_STATECHANGE(context, vtx);
-
- for(index = 0; index < context->nNumActiveAos; index++)
- {
- struct radeon_aos *aos = &context->radeon.tcl.aos[index];
- i = context->stream_desc[index].element;
-
- stride = (input[i]->StrideB == 0) ? getTypeSize(input[i]->Type) * input[i]->Size : input[i]->StrideB;
-
- if (input[i]->Type == GL_DOUBLE || input[i]->Type == GL_UNSIGNED_INT || input[i]->Type == GL_INT
-#if MESA_BIG_ENDIAN
- || getTypeSize(input[i]->Type) != 4
-#endif
- )
- {
- assert(count);
- r700ConvertAttrib(ctx, count, input[i], &context->stream_desc[index]);
- }
- else
- {
- if (input[i]->BufferObj->Name)
- {
- context->stream_desc[index].stride = input[i]->StrideB;
- context->stream_desc[index].bo_offset = (intptr_t) input[i]->Ptr;
- context->stream_desc[index].bo = get_radeon_buffer_object(input[i]->BufferObj)->bo;
- context->stream_desc[index].is_named_bo = GL_TRUE;
- }
- else
- {
- int size;
- int local_count = count;
- uint32_t *dst;
-
- if (input[i]->StrideB == 0)
- {
- size = getTypeSize(input[i]->Type) * input[i]->Size;
- local_count = 1;
- }
- else
- {
- size = getTypeSize(input[i]->Type) * input[i]->Size * local_count;
- }
-
- radeonAllocDmaRegion(&context->radeon, &context->stream_desc[index].bo,
- &context->stream_desc[index].bo_offset, size, 32);
-
- radeon_bo_map(context->stream_desc[index].bo, 1);
- assert(context->stream_desc[index].bo->ptr != NULL);
-
-
- dst = (uint32_t *)ADD_POINTERS(context->stream_desc[index].bo->ptr,
- context->stream_desc[index].bo_offset);
-
- switch (context->stream_desc[index].dwords)
- {
- case 1:
- radeonEmitVec4(dst, input[i]->Ptr, input[i]->StrideB, local_count);
- break;
- case 2:
- radeonEmitVec8(dst, input[i]->Ptr, input[i]->StrideB, local_count);
- break;
- case 3:
- radeonEmitVec12(dst, input[i]->Ptr, input[i]->StrideB, local_count);
- break;
- case 4:
- radeonEmitVec16(dst, input[i]->Ptr, input[i]->StrideB, local_count);
- break;
- default:
- assert(0);
- break;
- }
- radeon_bo_unmap(context->stream_desc[index].bo);
- }
- }
-
- aos->count = context->stream_desc[index].stride == 0 ? 1 : count;
- aos->stride = context->stream_desc[index].stride / sizeof(float);
- aos->components = context->stream_desc[index].dwords;
- aos->bo = context->stream_desc[index].bo;
- aos->offset = context->stream_desc[index].bo_offset;
-
- if(context->stream_desc[index].is_named_bo)
- {
- radeon_cs_space_add_persistent_bo(context->radeon.cmdbuf.cs,
- context->stream_desc[index].bo,
- RADEON_GEM_DOMAIN_GTT, 0);
- }
- }
-
- ret = radeon_cs_space_check_with_bo(context->radeon.cmdbuf.cs,
- first_elem(&context->radeon.dma.reserved)->bo,
- RADEON_GEM_DOMAIN_GTT, 0);
-}
-
-static void r700FreeData(struct gl_context *ctx)
-{
- /* Need to zero tcl.aos[n].bo and tcl.elt_dma_bo
- * to prevent double unref in radeonReleaseArrays
- * called during context destroy
- */
- context_t *context = R700_CONTEXT(ctx);
-
- int i;
-
- for (i = 0; i < context->nNumActiveAos; i++)
- {
- if (!context->stream_desc[i].is_named_bo)
- {
- radeon_bo_unref(context->stream_desc[i].bo);
- }
- context->radeon.tcl.aos[i].bo = NULL;
- }
-
- if (context->ind_buf.bo != NULL)
- {
- radeon_bo_unref(context->ind_buf.bo);
- }
-}
-
-static void r700FixupIndexBuffer(struct gl_context *ctx, const struct _mesa_index_buffer *mesa_ind_buf)
-{
- context_t *context = R700_CONTEXT(ctx);
- GLvoid *src_ptr;
- GLuint *out;
- int i;
- GLboolean mapped_named_bo = GL_FALSE;
-
- if (mesa_ind_buf->obj->Name && !mesa_ind_buf->obj->Pointer)
- {
- ctx->Driver.MapBufferRange(ctx, 0, mesa_ind_buf->obj->Size,
- GL_MAP_READ_BIT, mesa_ind_buf->obj);
- mapped_named_bo = GL_TRUE;
- assert(mesa_ind_buf->obj->Pointer != NULL);
- }
- src_ptr = ADD_POINTERS(mesa_ind_buf->obj->Pointer, mesa_ind_buf->ptr);
-
- if (mesa_ind_buf->type == GL_UNSIGNED_BYTE)
- {
- GLuint size = sizeof(GLushort) * ((mesa_ind_buf->count + 1) & ~1);
- GLubyte *in = (GLubyte *)src_ptr;
-
- radeonAllocDmaRegion(&context->radeon, &context->ind_buf.bo,
- &context->ind_buf.bo_offset, size, 4);
-
- radeon_bo_map(context->ind_buf.bo, 1);
- assert(context->ind_buf.bo->ptr != NULL);
- out = (GLuint *)ADD_POINTERS(context->ind_buf.bo->ptr, context->ind_buf.bo_offset);
-
- for (i = 0; i + 1 < mesa_ind_buf->count; i += 2)
- {
- *out++ = in[i] | in[i + 1] << 16;
- }
-
- if (i < mesa_ind_buf->count)
- {
- *out++ = in[i];
- }
-
- radeon_bo_unmap(context->ind_buf.bo);
-#if MESA_BIG_ENDIAN
- }
- else
- { /* if (mesa_ind_buf->type == GL_UNSIGNED_SHORT) */
- GLushort *in = (GLushort *)src_ptr;
- GLuint size = sizeof(GLushort) * ((mesa_ind_buf->count + 1) & ~1);
-
- radeonAllocDmaRegion(&context->radeon, &context->ind_buf.bo,
- &context->ind_buf.bo_offset, size, 4);
-
- radeon_bo_map(context->ind_buf.bo, 1);
- assert(context->ind_buf.bo->ptr != NULL);
- out = (GLuint *)ADD_POINTERS(context->ind_buf.bo->ptr, context->ind_buf.bo_offset);
-
- for (i = 0; i + 1 < mesa_ind_buf->count; i += 2)
- {
- *out++ = in[i] | in[i + 1] << 16;
- }
-
- if (i < mesa_ind_buf->count)
- {
- *out++ = in[i];
- }
- radeon_bo_unmap(context->ind_buf.bo);
-#endif
- }
-
- context->ind_buf.is_32bit = GL_FALSE;
- context->ind_buf.count = mesa_ind_buf->count;
-
- if (mapped_named_bo)
- {
- ctx->Driver.UnmapBuffer(ctx, mesa_ind_buf->obj);
- }
-}
-
-static void r700SetupIndexBuffer(struct gl_context *ctx, const struct _mesa_index_buffer *mesa_ind_buf)
-{
- context_t *context = R700_CONTEXT(ctx);
-
- if (!mesa_ind_buf) {
- context->ind_buf.bo = NULL;
- return;
- }
-
-#if MESA_BIG_ENDIAN
- if (mesa_ind_buf->type == GL_UNSIGNED_INT)
-#else
- if (mesa_ind_buf->type != GL_UNSIGNED_BYTE)
-#endif
- {
- const GLvoid *src_ptr;
- GLvoid *dst_ptr;
- GLboolean mapped_named_bo = GL_FALSE;
-
- if (mesa_ind_buf->obj->Name && !mesa_ind_buf->obj->Pointer)
- {
- ctx->Driver.MapBufferRange(ctx, 0, mesa_ind_buf->obj->Size,
- GL_MAP_READ_BIT, mesa_ind_buf->obj);
- assert(mesa_ind_buf->obj->Pointer != NULL);
- mapped_named_bo = GL_TRUE;
- }
-
- src_ptr = ADD_POINTERS(mesa_ind_buf->obj->Pointer, mesa_ind_buf->ptr);
-
- const GLuint size = mesa_ind_buf->count * getTypeSize(mesa_ind_buf->type);
-
- radeonAllocDmaRegion(&context->radeon, &context->ind_buf.bo,
- &context->ind_buf.bo_offset, size, 4);
- radeon_bo_map(context->ind_buf.bo, 1);
- assert(context->ind_buf.bo->ptr != NULL);
- dst_ptr = ADD_POINTERS(context->ind_buf.bo->ptr, context->ind_buf.bo_offset);
-
- memcpy(dst_ptr, src_ptr, size);
-
- radeon_bo_unmap(context->ind_buf.bo);
- context->ind_buf.is_32bit = (mesa_ind_buf->type == GL_UNSIGNED_INT);
- context->ind_buf.count = mesa_ind_buf->count;
-
- if (mapped_named_bo)
- {
- ctx->Driver.UnmapBuffer(ctx, mesa_ind_buf->obj);
- }
- }
- else
- {
- r700FixupIndexBuffer(ctx, mesa_ind_buf);
- }
-}
-
-static GLboolean check_fallbacks(struct gl_context *ctx)
-{
- if (ctx->RenderMode != GL_RENDER)
- return GL_TRUE;
-
- return GL_FALSE;
-}
-
-static GLboolean r700TryDrawPrims(struct gl_context *ctx,
- const struct gl_client_array *arrays[],
- const struct _mesa_prim *prim,
- GLuint nr_prims,
- const struct _mesa_index_buffer *ib,
- GLuint min_index,
- GLuint max_index )
-{
- context_t *context = R700_CONTEXT(ctx);
- radeonContextPtr radeon = &context->radeon;
- GLuint i, id = 0;
- struct radeon_renderbuffer *rrb;
-
- if (ctx->NewState)
- _mesa_update_state( ctx );
-
- if (check_fallbacks(ctx))
- return GL_FALSE;
-
- _tnl_UpdateFixedFunctionProgram(ctx);
- r700SetVertexFormat(ctx, arrays, max_index + 1);
- /* shaders need to be updated before buffers are validated */
- r700UpdateShaders(ctx);
- if (!r600ValidateBuffers(ctx))
- return GL_FALSE;
-
- /* always emit CB base to prevent
- * lock ups on some chips.
- */
- R600_STATECHANGE(context, cb_target);
- /* mark vtx as dirty since it changes per-draw */
- R600_STATECHANGE(context, vtx);
-
- r700SetScissor(context);
- r700SetupVertexProgram(ctx);
- r700SetupFragmentProgram(ctx);
- r700UpdateShaderStates(ctx);
-
- GLuint emit_end = r700PredictRenderSize(ctx, prim, ib, nr_prims)
- + context->radeon.cmdbuf.cs->cdw;
-
- r700SetupIndexBuffer(ctx, ib);
- r700SetupStreams(ctx, arrays, max_index + 1);
-
- radeonEmitState(radeon);
-
- radeon_debug_add_indent();
- for (i = 0; i < nr_prims; ++i)
- {
- if (context->ind_buf.bo)
- r700RunRenderPrimitive(ctx,
- prim[i].start,
- prim[i].start + prim[i].count,
- prim[i].mode,
- prim[i].basevertex);
- else
- r700RunRenderPrimitiveImmediate(ctx,
- prim[i].start,
- prim[i].start + prim[i].count,
- prim[i].mode);
- }
- radeon_debug_remove_indent();
-
- /* Flush render op cached for last several quads. */
- /* XXX drm should handle this in fence submit */
- r700WaitForIdleClean(context);
-
- rrb = radeon_get_colorbuffer(&context->radeon);
- if (rrb && rrb->bo)
- r700SyncSurf(context, rrb->bo, 0, RADEON_GEM_DOMAIN_VRAM,
- CB_ACTION_ENA_bit | (1 << (id + 6)));
-
- rrb = radeon_get_depthbuffer(&context->radeon);
- if (rrb && rrb->bo)
- r700SyncSurf(context, rrb->bo, 0, RADEON_GEM_DOMAIN_VRAM,
- DB_ACTION_ENA_bit | DB_DEST_BASE_ENA_bit);
-
- r700FreeData(ctx);
-
- if (emit_end < context->radeon.cmdbuf.cs->cdw)
- {
- WARN_ONCE("Rendering was %d commands larger than predicted size."
- " We might overflow command buffer.\n", context->radeon.cmdbuf.cs->cdw - emit_end);
- }
-
- return GL_TRUE;
-}
-
-static void r700DrawPrims(struct gl_context *ctx,
- const struct gl_client_array *arrays[],
- const struct _mesa_prim *prim,
- GLuint nr_prims,
- const struct _mesa_index_buffer *ib,
- GLboolean index_bounds_valid,
- GLuint min_index,
- GLuint max_index)
-{
- GLboolean retval = GL_FALSE;
-
- context_t *context = R700_CONTEXT(ctx);
- radeonContextPtr radeon = &context->radeon;
- radeon_prepare_render(radeon);
-
- /* This check should get folded into just the places that
- * min/max index are really needed.
- */
-
- if (!vbo_all_varyings_in_vbos(arrays)) {
- if (!index_bounds_valid)
- vbo_get_minmax_index(ctx, prim, ib, &min_index, &max_index);
- /* do we want to rebase, minimizes the
- * amount of data to upload? */
- if (min_index) {
- vbo_rebase_prims( ctx, arrays, prim, nr_prims, ib, min_index, max_index, r700DrawPrims );
- return;
- }
- }
- /* Make an attempt at drawing */
- retval = r700TryDrawPrims(ctx, arrays, prim, nr_prims, ib, min_index, max_index);
-
- /* If failed run tnl pipeline - it should take care of fallbacks */
- if (!retval) {
- _swsetup_Wakeup(ctx);
- _tnl_draw_prims(ctx, arrays, prim, nr_prims, ib, min_index, max_index);
- }
-}
-
-void r700InitDraw(struct gl_context *ctx)
-{
- struct vbo_context *vbo = vbo_context(ctx);
-
- /* to be enabled */
- vbo->draw_prims = r700DrawPrims;
-}
-
-
+++ /dev/null
-/*
- * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Authors:
- * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
- */
-
-#include <stdio.h>
-#include <stdarg.h>
-#include <stdlib.h>
-#include <string.h>
-#include <math.h>
-
-#include "main/imports.h"
-
-#include "main/glheader.h"
-
-#include "r600_context.h"
-
-#include "r700_shader.h"
-
-void r700ShaderInit(struct gl_context * ctx)
-{
-}
-
-void AddInstToList(TypedShaderList * plstCFInstructions, R700ShaderInstruction * pInst)
-{
- if(NULL == plstCFInstructions->pTail)
- { //first
- plstCFInstructions->pHead = pInst;
- plstCFInstructions->pTail = pInst;
- }
- else
- {
- plstCFInstructions->pTail->pNextInst = pInst;
- plstCFInstructions->pTail = pInst;
- }
- pInst->pNextInst = NULL;
-
- plstCFInstructions->uNumOfNode++;
-}
-
-void TakeInstOutFromList(TypedShaderList * plstCFInstructions, R700ShaderInstruction * pInst)
-{
- GLuint ulIndex = 0;
- GLboolean bFound = GL_FALSE;
- R700ShaderInstruction * pPrevInst = NULL;
- R700ShaderInstruction * pCurInst = plstCFInstructions->pHead;
-
- /* Need go thro list to make sure pInst is there. */
- while(NULL != pCurInst)
- {
- if(pCurInst == pInst)
- {
- bFound = GL_TRUE;
- break;
- }
-
- pPrevInst = pCurInst;
- pCurInst = pCurInst->pNextInst;
- }
- if(GL_TRUE == bFound)
- {
- plstCFInstructions->uNumOfNode--;
-
- pCurInst = pInst->pNextInst;
- ulIndex = pInst->m_uIndex;
- while(NULL != pCurInst)
- {
- pCurInst->m_uIndex = ulIndex;
- ulIndex++;
- pCurInst = pCurInst->pNextInst;
- }
-
- if(plstCFInstructions->pHead == pInst)
- {
- plstCFInstructions->pHead = pInst->pNextInst;
- }
- if(plstCFInstructions->pTail == pInst)
- {
- plstCFInstructions->pTail = pPrevInst;
- }
- if(NULL != pPrevInst)
- {
- pPrevInst->pNextInst = pInst->pNextInst;
- }
-
- FREE(pInst);
- }
-}
-
-void Init_R700_Shader(R700_Shader * pShader)
-{
- pShader->Type = R700_SHADER_INVALID;
- pShader->pProgram = NULL;
- pShader->bBinaryShader = GL_FALSE;
- pShader->bFetchShaderRequired = GL_FALSE;
- pShader->bNeedsAssembly = GL_FALSE;
- pShader->bLinksDirty = GL_TRUE;
- pShader->uShaderBinaryDWORDSize = 0;
- pShader->nRegs = 0;
- pShader->nParamExports = 0;
- pShader->nMemExports = 0;
- pShader->resource = 0;
-
- pShader->exportMode = 0;
- pShader->depthIsImported = GL_FALSE;
-
- pShader->positionVectorIsExported = GL_FALSE;
- pShader->miscVectorIsExported = GL_FALSE;
- pShader->renderTargetArrayIndexIsExported = GL_FALSE;
- pShader->ccDist0VectorIsExported = GL_FALSE;
- pShader->ccDist1VectorIsExported = GL_FALSE;
-
-
- pShader->depthIsExported = GL_FALSE;
- pShader->stencilRefIsExported = GL_FALSE;
- pShader->coverageToMaskIsExported = GL_FALSE;
- pShader->maskIsExported = GL_FALSE;
- pShader->killIsUsed = GL_FALSE;
-
- pShader->uCFOffset = 0;
- pShader->uStackSize = 0;
- pShader->uMaxCallDepth = 0;
-
- pShader->bSurfAllocated = GL_FALSE;
-
- pShader->lstCFInstructions.pHead=NULL;
- pShader->lstCFInstructions.pTail=NULL;
- pShader->lstCFInstructions.uNumOfNode=0;
- pShader->lstALUInstructions.pHead=NULL;
- pShader->lstALUInstructions.pTail=NULL;
- pShader->lstALUInstructions.uNumOfNode=0;
- pShader->lstTEXInstructions.pHead=NULL;
- pShader->lstTEXInstructions.pTail=NULL;
- pShader->lstTEXInstructions.uNumOfNode=0;
- pShader->lstVTXInstructions.pHead=NULL;
- pShader->lstVTXInstructions.pTail=NULL;
- pShader->lstVTXInstructions.uNumOfNode=0;
-}
-
-void SetActiveCFlist(R700_Shader *pShader, TypedShaderList * plstCF)
-{
- pShader->plstCFInstructions_active = plstCF;
-}
-
-void AddCFInstruction(R700_Shader *pShader, R700ControlFlowInstruction *pCFInst)
-{
- R700ControlFlowSXClause* pSXClause;
- R700ControlFlowSMXClause* pSMXClause;
-
- pCFInst->m_uIndex = pShader->plstCFInstructions_active->uNumOfNode;
- AddInstToList(pShader->plstCFInstructions_active,
- (R700ShaderInstruction*)pCFInst);
- pShader->uShaderBinaryDWORDSize += GetInstructionSize(pCFInst->m_ShaderInstType);
-
- pSXClause = NULL;
- pSMXClause = NULL;
- switch (pCFInst->m_ShaderInstType)
- {
- case SIT_CF_ALL_EXP_SX:
- pSXClause = (R700ControlFlowSXClause*)pCFInst;
- break;
- case SIT_CF_ALL_EXP_SMX:
- pSMXClause = (R700ControlFlowSMXClause*)pCFInst;
- break;
- default:
- break;
- };
-
- if((pSXClause != NULL) && (pSXClause->m_Word0.f.type == SQ_EXPORT_PARAM))
- {
- pShader->nParamExports += pSXClause->m_Word1.f.burst_count + 1;
- }
- else if ((pSMXClause != NULL) && (pSMXClause->m_Word1.f.cf_inst == SQ_CF_INST_MEM_RING) &&
- (pSMXClause->m_Word0.f.type == SQ_EXPORT_WRITE || pSMXClause->m_Word0.f.type == SQ_EXPORT_WRITE_IND))
- {
- pShader->nMemExports += pSMXClause->m_Word1.f.burst_count + 1;
- }
-
- pShader->bLinksDirty = GL_TRUE;
- pShader->bNeedsAssembly = GL_TRUE;
-
- pCFInst->useCount++;
-}
-
-void AddVTXInstruction(R700_Shader *pShader, R700VertexInstruction *pVTXInst)
-{
- pVTXInst->m_uIndex = pShader->lstVTXInstructions.uNumOfNode;
- AddInstToList(&(pShader->lstVTXInstructions),
- (R700ShaderInstruction*)pVTXInst);
- pShader->uShaderBinaryDWORDSize += GetInstructionSize(pVTXInst->m_ShaderInstType);
-
- if(pVTXInst->m_ShaderInstType == SIT_VTX_GENERIC)
- {
- R700VertexGenericFetch* pVTXGenericClause = (R700VertexGenericFetch*)pVTXInst;
- pShader->nRegs = (pShader->nRegs < pVTXGenericClause->m_Word1_GPR.f.dst_gpr) ? pVTXGenericClause->m_Word1_GPR.f.dst_gpr : pShader->nRegs;
- }
-
- pShader->bLinksDirty = GL_TRUE;
- pShader->bNeedsAssembly = GL_TRUE;
-
- pVTXInst->useCount++;
-}
-
-void AddTEXInstruction(R700_Shader *pShader, R700TextureInstruction *pTEXInst)
-{
- pTEXInst->m_uIndex = pShader->lstTEXInstructions.uNumOfNode;
- AddInstToList(&(pShader->lstTEXInstructions),
- (R700ShaderInstruction*)pTEXInst);
- pShader->uShaderBinaryDWORDSize += GetInstructionSize(pTEXInst->m_ShaderInstType);
-
- pShader->nRegs = (pShader->nRegs < pTEXInst->m_Word1.f.dst_gpr) ? pTEXInst->m_Word1.f.dst_gpr : pShader->nRegs;
-
- pShader->bLinksDirty = GL_TRUE;
- pShader->bNeedsAssembly = GL_TRUE;
-
- pTEXInst->useCount++;
-}
-
-void AddALUInstruction(R700_Shader *pShader, R700ALUInstruction *pALUInst)
-{
- pALUInst->m_uIndex = pShader->lstALUInstructions.uNumOfNode;
- AddInstToList(&(pShader->lstALUInstructions),
- (R700ShaderInstruction*)pALUInst);
- pShader->uShaderBinaryDWORDSize += GetInstructionSize(pALUInst->m_ShaderInstType);
-
- pShader->nRegs = (pShader->nRegs < pALUInst->m_Word1.f.dst_gpr) ? pALUInst->m_Word1.f.dst_gpr : pShader->nRegs;
-
- pShader->bLinksDirty = GL_TRUE;
- pShader->bNeedsAssembly = GL_TRUE;
-
- pALUInst->useCount++;
-}
-
-void ResolveLinks(R700_Shader *pShader)
-{
- GLuint uiSize;
- R700ShaderInstruction *pInst;
- R700ALUInstruction *pALUinst;
- R700TextureInstruction *pTEXinst;
- R700VertexInstruction *pVTXinst;
-
- GLuint vtxOffset;
-
- GLuint cfOffset = 0x0;
-
- GLuint aluOffset = cfOffset + pShader->lstCFInstructions.uNumOfNode * GetInstructionSize(SIT_CF);
-
- GLuint texOffset = aluOffset; // + m_lstALUInstructions.size() * R700ALUInstruction::SIZE,
-
- pInst = pShader->lstALUInstructions.pHead;
- while(NULL != pInst)
- {
- texOffset += GetInstructionSize(pInst->m_ShaderInstType);
-
- pInst = pInst->pNextInst;
- };
-
- vtxOffset = texOffset + pShader->lstTEXInstructions.uNumOfNode * GetInstructionSize(SIT_TEX);
-
- if ( ((pShader->lstTEXInstructions.uNumOfNode > 0) && (texOffset % 4 != 0)) ||
- ((pShader->lstVTXInstructions.uNumOfNode > 0) && (vtxOffset % 4 != 0)) )
- {
- pALUinst = (R700ALUInstruction*) CALLOC_STRUCT(R700ALUInstruction);
- Init_R700ALUInstruction(pALUinst);
- AddALUInstruction(pShader, pALUinst);
- texOffset += GetInstructionSize(SIT_ALU);
- vtxOffset += GetInstructionSize(SIT_ALU);
- }
-
- pInst = pShader->lstALUInstructions.pHead;
- uiSize = 0;
- while(NULL != pInst)
- {
- pALUinst = (R700ALUInstruction*)pInst;
-
- if(pALUinst->m_pLinkedALUClause != NULL)
- {
- // This address is quad-word aligned
- pALUinst->m_pLinkedALUClause->m_Word0.f.addr = (aluOffset + uiSize) >> 1;
- }
-
- uiSize += GetInstructionSize(pALUinst->m_ShaderInstType);
-
- pInst = pInst->pNextInst;
- };
-
- pInst = pShader->lstTEXInstructions.pHead;
- uiSize = 0;
- while(NULL != pInst)
- {
- pTEXinst = (R700TextureInstruction*)pInst;
-
- if (pTEXinst->m_pLinkedGenericClause != NULL)
- {
- pTEXinst->m_pLinkedGenericClause->m_Word0.f.addr = (texOffset + uiSize) >> 1;
- }
-
- uiSize += GetInstructionSize(pTEXinst->m_ShaderInstType);
-
- pInst = pInst->pNextInst;
- };
-
- pInst = pShader->lstVTXInstructions.pHead;
- uiSize = 0;
- while(NULL != pInst)
- {
- pVTXinst = (R700VertexInstruction*)pInst;
-
- if (pVTXinst->m_pLinkedGenericClause != NULL)
- {
- pVTXinst->m_pLinkedGenericClause->m_Word0.f.addr = (vtxOffset + uiSize) >> 1;
- }
-
- uiSize += GetInstructionSize(pVTXinst->m_ShaderInstType);
-
- pInst = pInst->pNextInst;
- };
-
- pShader->bLinksDirty = GL_FALSE;
-}
-
-void Assemble(R700_Shader *pShader)
-{
- GLuint i;
- GLuint *pShaderBinary;
- GLuint size_of_program;
- GLuint *pCurrPos;
-
- GLuint end_of_cf_instructions;
- GLuint number_of_alu_dwords;
-
- R700ShaderInstruction *pInst;
-
- if(GL_TRUE == pShader->bBinaryShader)
- {
- return;
- }
-
- if(pShader->bLinksDirty == GL_TRUE)
- {
- ResolveLinks(pShader);
- }
-
- size_of_program = pShader->uShaderBinaryDWORDSize;
-
- pShaderBinary = (GLuint*) MALLOC(sizeof(GLuint)*size_of_program);
-
- pCurrPos = pShaderBinary;
-
- for (i = 0; i < size_of_program; i++)
- {
- pShaderBinary[i] = 0;
- }
-
- pInst = pShader->lstCFInstructions.pHead;
- while(NULL != pInst)
- {
- switch (pInst->m_ShaderInstType)
- {
- case SIT_CF_GENERIC:
- {
- R700ControlFlowGenericClause* pCFgeneric = (R700ControlFlowGenericClause*)pInst;
- *pCurrPos++ = pCFgeneric->m_Word0.val;
- *pCurrPos++ = pCFgeneric->m_Word1.val;
- }
- break;
- case SIT_CF_ALU:
- {
- R700ControlFlowALUClause* pCFalu = (R700ControlFlowALUClause*)pInst;
- *pCurrPos++ = pCFalu->m_Word0.val;
- *pCurrPos++ = pCFalu->m_Word1.val;
- }
- break;
- case SIT_CF_ALL_EXP_SX:
- {
- R700ControlFlowSXClause* pCFsx = (R700ControlFlowSXClause*)pInst;
- *pCurrPos++ = pCFsx->m_Word0.val;
- *pCurrPos++ = (pCFsx->m_Word1.val | pCFsx->m_Word1_SWIZ.val);
- }
- break;
- case SIT_CF_ALL_EXP_SMX:
- {
- R700ControlFlowSMXClause* pCFsmx = (R700ControlFlowSMXClause*)pInst;
- *pCurrPos++ = pCFsmx->m_Word0.val;
- *pCurrPos++ = (pCFsmx->m_Word1.val | pCFsmx->m_Word1_BUF.val);
- }
- break;
- default:
- break;
- }
-
- pInst = pInst->pNextInst;
- };
-
- number_of_alu_dwords = 0;
- pInst = pShader->lstALUInstructions.pHead;
- while(NULL != pInst)
- {
- switch (pInst->m_ShaderInstType)
- {
- case SIT_ALU:
- {
- R700ALUInstruction* pALU = (R700ALUInstruction*)pInst;
-
- *pCurrPos++ = pALU->m_Word0.val;
- *pCurrPos++ = (pALU->m_Word1.val | pALU->m_Word1_OP2.val | pALU->m_Word1_OP3.val);
-
- number_of_alu_dwords += 2;
- }
- break;
- case SIT_ALU_HALF_LIT:
- {
- R700ALUInstructionHalfLiteral* pALUhalf = (R700ALUInstructionHalfLiteral*)pInst;
-
- *pCurrPos++ = pALUhalf->m_Word0.val;
- *pCurrPos++ = (pALUhalf->m_Word1.val | pALUhalf->m_Word1_OP2.val | pALUhalf->m_Word1_OP3.val);
- *pCurrPos++ = *((GLuint*)&(pALUhalf->m_fLiteralX));
- *pCurrPos++ = *((GLuint*)&(pALUhalf->m_fLiteralY));
-
- number_of_alu_dwords += 4;
- }
- break;
- case SIT_ALU_FALL_LIT:
- {
- R700ALUInstructionFullLiteral* pALUfull = (R700ALUInstructionFullLiteral*)pInst;
-
- *pCurrPos++ = pALUfull->m_Word0.val;
- *pCurrPos++ = (pALUfull->m_Word1.val | pALUfull->m_Word1_OP2.val | pALUfull->m_Word1_OP3.val);
-
- *pCurrPos++ = *((GLuint*)&(pALUfull->m_fLiteralX));
- *pCurrPos++ = *((GLuint*)&(pALUfull->m_fLiteralY));
- *pCurrPos++ = *((GLuint*)&(pALUfull->m_fLiteralZ));
- *pCurrPos++ = *((GLuint*)&(pALUfull->m_fLiteralW));
-
- number_of_alu_dwords += 6;
- }
- break;
- default:
- break;
- }
-
- pInst = pInst->pNextInst;
- };
-
- pInst = pShader->lstTEXInstructions.pHead;
- while(NULL != pInst)
- {
- R700TextureInstruction* pTEX = (R700TextureInstruction*)pInst;
-
- *pCurrPos++ = pTEX->m_Word0.val;
- *pCurrPos++ = pTEX->m_Word1.val;
- *pCurrPos++ = pTEX->m_Word2.val;
- *pCurrPos++ = 0x0beadeaf;
-
- pInst = pInst->pNextInst;
- };
-
- pInst = pShader->lstVTXInstructions.pHead;
- while(NULL != pInst)
- {
- switch (pInst->m_ShaderInstType)
- {
- case SIT_VTX_SEM: //
- {
- R700VertexSemanticFetch* pVTXsem = (R700VertexSemanticFetch*)pInst;
-
- *pCurrPos++ = pVTXsem->m_Word0.val;
- *pCurrPos++ = (pVTXsem->m_Word1.val | pVTXsem->m_Word1_SEM.val);
- *pCurrPos++ = pVTXsem->m_Word2.val;
- *pCurrPos++ = 0x0beadeaf;
- }
- break;
- case SIT_VTX_GENERIC: //
- {
- R700VertexGenericFetch* pVTXgeneric = (R700VertexGenericFetch*)pInst;
-
- *pCurrPos++ = pVTXgeneric->m_Word0.val;
- *pCurrPos++ = (pVTXgeneric->m_Word1.val | pVTXgeneric->m_Word1_GPR.val);
- *pCurrPos++ = pVTXgeneric->m_Word2.val;
- *pCurrPos++ = 0x0beadeaf;
- }
- break;
- default:
- break;
- }
-
- pInst = pInst->pNextInst;
- };
-
- if(NULL != pShader->pProgram)
- {
- FREE(pShader->pProgram);
- }
- pShader->pProgram = (GLubyte*)pShaderBinary;
-
- end_of_cf_instructions = pShader->uCFOffset + pShader->lstCFInstructions.uNumOfNode * GetInstructionSize(SIT_CF);
-
- pShader->uEndOfCF = end_of_cf_instructions >> 1;
-
- pShader->uEndOfALU = (end_of_cf_instructions + number_of_alu_dwords) >> 1;
-
- pShader->uEndOfFetch = (pShader->uCFOffset + pShader->uShaderBinaryDWORDSize) >> 1;
-
- pShader->bNeedsAssembly = GL_FALSE;
-}
-
-void LoadProgram(R700_Shader *pShader) //context
-{
-}
-
-void UpdateShaderRegisters(R700_Shader *pShader) //context
-{
-}
-
-void DeleteInstructions(R700_Shader *pShader)
-{
-}
-
-void DebugPrint(void)
-{
-}
-
-void cleanup_vfetch_shaderinst(R700_Shader *pShader)
-{
- R700ShaderInstruction *pInst;
- R700ShaderInstruction *pInstToFree;
- R700VertexInstruction *pVTXInst;
- R700ControlFlowInstruction *pCFInst;
-
- pInst = pShader->lstVTXInstructions.pHead;
- while(NULL != pInst)
- {
- pVTXInst = (R700VertexInstruction *)pInst;
- pShader->uShaderBinaryDWORDSize -= GetInstructionSize(pVTXInst->m_ShaderInstType);
-
- if(NULL != pVTXInst->m_pLinkedGenericClause)
- {
- pCFInst = (R700ControlFlowInstruction*)(pVTXInst->m_pLinkedGenericClause);
-
- TakeInstOutFromList(&(pShader->lstCFInstructions),
- (R700ShaderInstruction*)pCFInst);
-
- pShader->uShaderBinaryDWORDSize -= GetInstructionSize(pCFInst->m_ShaderInstType);
- }
-
- pInst = pInst->pNextInst;
- };
-
- //destroy each item in pShader->lstVTXInstructions;
- pInst = pShader->lstVTXInstructions.pHead;
- while(NULL != pInst)
- {
- pInstToFree = pInst;
- pInst = pInst->pNextInst;
- FREE(pInstToFree);
- };
-
- //set NULL pShader->lstVTXInstructions
- pShader->lstVTXInstructions.pHead=NULL;
- pShader->lstVTXInstructions.pTail=NULL;
- pShader->lstVTXInstructions.uNumOfNode=0;
-}
-
-void Clean_Up_Shader(R700_Shader *pShader)
-{
- if(NULL != pShader->pProgram)
- {
- FREE(pShader->pProgram);
- pShader->pProgram = NULL;
- }
-
- R700ShaderInstruction *pInst;
- R700ShaderInstruction *pInstToFree;
-
- pInst = pShader->lstCFInstructions.pHead;
- while(NULL != pInst)
- {
- pInstToFree = pInst;
- pInst = pInst->pNextInst;
- FREE(pInstToFree);
- };
- pShader->lstCFInstructions.pHead = NULL;
-
- pInst = pShader->lstALUInstructions.pHead;
- while(NULL != pInst)
- {
- pInstToFree = pInst;
- pInst = pInst->pNextInst;
- FREE(pInstToFree);
- };
- pShader->lstALUInstructions.pHead = NULL;
-
- pInst = pShader->lstTEXInstructions.pHead;
- while(NULL != pInst)
- {
- pInstToFree = pInst;
- pInst = pInst->pNextInst;
- FREE(pInstToFree);
- };
- pShader->lstTEXInstructions.pHead = NULL;
-
- pInst = pShader->lstVTXInstructions.pHead;
- while(NULL != pInst)
- {
- pInstToFree = pInst;
- pInst = pInst->pNextInst;
- FREE(pInstToFree);
- };
- pShader->lstVTXInstructions.pHead = NULL;
-}
-
+++ /dev/null
-/*
- * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Authors:
- * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
- */
-
-
-#ifndef __R700_SHADER_H__
-#define __R700_SHADER_H__
-
-#include "main/mtypes.h"
-
-#include "r700_shaderinst.h"
-
-
-void r700ShaderInit(struct gl_context * ctx);
-
-typedef enum R700ShaderType
-{
- R700_SHADER_FS = 0x0,
- R700_SHADER_ES = 0x1,
- R700_SHADER_GS = 0x2,
- R700_SHADER_VS = 0x3,
- R700_SHADER_PS = 0x4,
- R700_SHADER_INVALID = 0x5,
-} R700ShaderType;
-
-typedef struct TypedShaderList
-{
- R700ShaderInstruction * pHead;
- R700ShaderInstruction * pTail;
- GLuint uNumOfNode;
-} TypedShaderList;
-
-typedef struct RealRegister
-{
- GLuint uAddr;
- GLuint uValue;
-} RealRegister;
-
-typedef struct InstDeps
-{
- GLint nDstDep;
- GLint nSrcDeps[3];
-} InstDeps;
-
-typedef struct R700_Shader
-{
- R700ShaderType Type;
-
- GLubyte* pProgram;
-
- GLboolean bBinaryShader;
- GLboolean bFetchShaderRequired;
- GLboolean bNeedsAssembly;
- GLboolean bLinksDirty;
-
- GLuint uShaderBinaryDWORDSize; // in DWORDS
- GLuint nRegs;
- GLuint nParamExports; // VS_ EXPORT_COUNT (1 based, the actual register is 0 based!)
- GLuint nMemExports;
- GLuint resource; // VS and PS _RESOURCE
- GLuint exportMode; // VS and PS _EXPORT_MODE
-
- GLboolean depthIsImported;
-
- // Vertex program exports
- GLboolean positionVectorIsExported;
-
- GLboolean miscVectorIsExported;
- GLboolean renderTargetArrayIndexIsExported;
-
- GLboolean ccDist0VectorIsExported;
- GLboolean ccDist1VectorIsExported;
-
- // Pixel program exports
- GLboolean depthIsExported;
- GLboolean stencilRefIsExported;
- GLboolean coverageToMaskIsExported;
- GLboolean maskIsExported;
-
- GLboolean killIsUsed;
-
- GLuint uStartAddr;
- GLuint uCFOffset;
- GLuint uEndOfCF;
- GLuint uEndOfALU;
- GLuint uEndOfFetch;
- GLuint uStackSize;
- GLuint uMaxCallDepth;
-
- TypedShaderList * plstCFInstructions_active;
- TypedShaderList lstCFInstructions;
- TypedShaderList lstALUInstructions;
- TypedShaderList lstTEXInstructions;
- TypedShaderList lstVTXInstructions;
-
- RealRegister RegStartAddr;
- RealRegister RegCFOffset;
- RealRegister RegEndCF;
- RealRegister RegEndALU;
- RealRegister egEndFetcg;
-
- // -------- constants
- GLfloat ConstantArray[SQ_ALU_CONSTANT_PS_COUNT * 4];
-
- GLboolean bSurfAllocated;
-} R700_Shader;
-
-//Internal
-void AddInstToList(TypedShaderList * plstCFInstructions, R700ShaderInstruction * pInst);
-void TakeInstOutFromList(TypedShaderList * plstCFInstructions, R700ShaderInstruction * pInst);
-void ResolveLinks(R700_Shader *pShader);
-void Assemble(R700_Shader *pShader);
-
-//Interface
-void Init_R700_Shader(R700_Shader * pShader);
-void AddCFInstruction(R700_Shader *pShader, R700ControlFlowInstruction *pCFInst);
-void AddVTXInstruction(R700_Shader *pShader, R700VertexInstruction *pVTXInst);
-void AddTEXInstruction(R700_Shader *pShader, R700TextureInstruction *pTEXInst);
-void AddALUInstruction(R700_Shader *pShader, R700ALUInstruction *pALUInst);
-void SetActiveCFlist(R700_Shader *pShader, TypedShaderList * plstCF);
-
-void LoadProgram(R700_Shader *pShader);
-void UpdateShaderRegisters(R700_Shader *pShader);
-void DeleteInstructions(R700_Shader *pShader);
-void DebugPrint(void);
-void cleanup_vfetch_shaderinst(R700_Shader *pShader);
-
-void Clean_Up_Shader(R700_Shader *pShader);
-
-#endif /*__R700_SHADER_H__*/
-
+++ /dev/null
-/*
- * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Authors:
- * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
- */
-
-
-#include "main/mtypes.h"
-
-#include "radeon_debug.h"
-#include "r700_shaderinst.h"
-
-void Init_R700ControlFlowGenericClause(R700ControlFlowGenericClause* pInst)
-{
- pInst->m_Word0.val = 0x00000000;
- pInst->m_Word1.val = 0x00000000;
-
- pInst->m_pLinkedVTXInstruction = 0;
- pInst->m_pLinkedTEXInstruction = 0;
-
- pInst->useCount = 0;
-
- pInst->m_ShaderInstType = SIT_CF_GENERIC;
-}
-
-void Init_R700ControlFlowALUClause(R700ControlFlowALUClause* pInst)
-{
- pInst->m_Word0.val = 0x00000000;
- pInst->m_Word1.val = 0x00000000;
-
- pInst->m_pLinkedALUInstruction = 0;
-
- pInst->useCount = 0;
-
- pInst->m_ShaderInstType = SIT_CF_ALU;
-}
-
-void Init_R700ControlFlowSXClause(R700ControlFlowSXClause* pInst)
-{
- pInst->m_Word0.val = 0x00000000;
- pInst->m_Word1.val = 0x00000000;
- pInst->m_Word1_SWIZ.val = 0x00000000;
-
- pInst->useCount = 0;
-
- pInst->m_ShaderInstType = SIT_CF_ALL_EXP_SX;
-}
-
-void Init_R700ControlFlowSMXClause(R700ControlFlowSMXClause* pInst)
-{
- pInst->m_Word0.val = 0x00000000;
- pInst->m_Word1.val = 0x00000000;
- pInst->m_Word1_BUF.val = 0x00000000;
-
- pInst->useCount = 0;
-
- pInst->m_ShaderInstType = SIT_CF_ALL_EXP_SMX;
-}
-
-void Init_R700ALUInstruction(R700ALUInstruction* pInst)
-{
- pInst->m_Word0.val = 0x00000000;
- pInst->m_Word1.val = 0x00000000;
- pInst->m_Word1_OP2.val = 0x00000000;
- pInst->m_Word1_OP3.val = 0x00000000;
-
- pInst->m_pLinkedALUClause = 0;
-
- pInst->useCount = 0;
-
- pInst->m_ShaderInstType = SIT_ALU;
-}
-
-void Init_R700ALUInstructionHalfLiteral(R700ALUInstructionHalfLiteral* pInst, GLfloat x, GLfloat y)
-{
- pInst->m_Word0.val = 0x00000000;
- pInst->m_Word1.val = 0x00000000;
- pInst->m_Word1_OP2.val = 0x00000000;
- pInst->m_Word1_OP3.val = 0x00000000;
-
- pInst->m_pLinkedALUClause = 0;
-
- pInst->m_fLiteralX = x;
- pInst->m_fLiteralY = y;
-
- pInst->useCount = 0;
-
- pInst->m_ShaderInstType = SIT_ALU_HALF_LIT;
-}
-
-void Init_R700ALUInstructionFullLiteral(R700ALUInstructionFullLiteral* pInst, GLfloat x, GLfloat y, GLfloat z, GLfloat w)
-{
- pInst->m_Word0.val = 0x00000000;
- pInst->m_Word1.val = 0x00000000;
- pInst->m_Word1_OP2.val = 0x00000000;
- pInst->m_Word1_OP3.val = 0x00000000;
-
- pInst->m_pLinkedALUClause = 0;
-
- pInst->m_fLiteralX = x;
- pInst->m_fLiteralY = y;
- pInst->m_fLiteralZ = z;
- pInst->m_fLiteralW = w;
-
- pInst->useCount = 0;
-
- pInst->m_ShaderInstType = SIT_ALU_FALL_LIT;
-}
-
-void Init_R700TextureInstruction(R700TextureInstruction* pInst)
-{
- pInst->m_Word0.val = 0x00000000;
- pInst->m_Word1.val = 0x00000000;
- pInst->m_Word2.val = 0x00000000;
-
- pInst->m_pLinkedGenericClause = 0;
-
- pInst->useCount = 0;
-
- pInst->m_ShaderInstType = SIT_TEX;
-}
-
-void Init_R700VertexSemanticFetch(R700VertexSemanticFetch* pInst)
-{
- pInst->m_Word0.val = 0x00000000;
- pInst->m_Word1.val = 0x00000000;
- pInst->m_Word1_SEM.val = 0x00000000;
- pInst->m_Word2.val = 0x00000000;
-
- pInst->m_pLinkedGenericClause = 0;
-
- pInst->useCount = 0;
-
- pInst->m_ShaderInstType = SIT_VTX_SEM;
-}
-
-void Init_R700VertexGenericFetch(R700VertexGenericFetch* pInst)
-{
- pInst->m_Word0.val = 0x00000000;
- pInst->m_Word1.val = 0x00000000;
- pInst->m_Word1_GPR.val = 0x00000000;
- pInst->m_Word2.val = 0x00000000;
-
- pInst->m_pLinkedGenericClause = 0;
-
- pInst->useCount = 0;
-
- pInst->m_ShaderInstType = SIT_VTX_GENERIC;
-}
-
-unsigned int GetInstructionSize(ShaderInstType instType)
-{
- switch(instType)
- {
- case SIT_ALU_HALF_LIT:
- case SIT_TEX:
- case SIT_VTX:
- case SIT_VTX_GENERIC:
- case SIT_VTX_SEM:
- return 4;
- case SIT_ALU_FALL_LIT:
- return 6;
- default:
- break;
- }
-
- return 2;
-}
-
-unsigned int GetCFMaxInstructions(ShaderInstType instType)
-{
- switch (instType)
- {
- case SIT_CF_ALL_EXP:
- case SIT_CF_ALL_EXP_SX:
- case SIT_CF_ALL_EXP_SMX:
- return 0x10;
- case SIT_CF_GENERIC:
- return 0x8; //For tex and vtx
- case SIT_CF_ALU:
- return 0x80;
- default:
- break;
- }
- return 0x10;
-}
-
-GLboolean LinkVertexInstruction(R700ControlFlowGenericClause *pCFGeneric,
- R700VertexInstruction *pVTXInstruction)
-{
- if (pCFGeneric->m_pLinkedTEXInstruction != 0)
- {
- radeon_error("This instruction is already linked to a texture instruction.\n");
- return GL_FALSE;
- }
-
- pCFGeneric->m_pLinkedVTXInstruction = pVTXInstruction;
- pVTXInstruction->m_pLinkedGenericClause = pCFGeneric;
-
- return GL_TRUE;
-}
-
-
-
+++ /dev/null
-/*
- * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Authors:
- * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
- */
-
-
-#ifndef _R700_SHADERINST_H_
-#define _R700_SHADERINST_H_
-
-#include "main/glheader.h"
-
-#include "defaultendian.h"
-#include "sq_micro_reg.h"
-
-#define SQ_ALU_CONSTANT_PS_OFFSET 0x00000000
-#define SQ_ALU_CONSTANT_PS_COUNT 0x00000100
-#define SQ_ALU_CONSTANT_VS_OFFSET 0x00000100
-#define SQ_ALU_CONSTANT_VS_COUNT 0x00000100
-#define SQ_FETCH_RESOURCE_PS_OFFSET 0x00000000
-#define SQ_FETCH_RESOURCE_PS_COUNT 0x000000a0
-#define SQ_FETCH_RESOURCE_VS_OFFSET 0x000000a0
-#define SQ_FETCH_RESOURCE_VS_COUNT 0x000000b0
-
-//richard dec.10 glsl
-#define SQ_TEX_SAMPLER_PS_OFFSET 0x00000000
-#define SQ_TEX_SAMPLER_PS_COUNT 0x00000012
-#define SQ_TEX_SAMPLER_VS_OFFSET 0x00000012
-#define SQ_TEX_SAMPLER_VS_COUNT 0x00000012
-//-------------------
-
-#define SHADERINST_TYPEMASK_CF 0x10
-#define SHADERINST_TYPEMASK_ALU 0x20
-#define SHADERINST_TYPEMASK_TEX 0x40
-#define SHADERINST_TYPEMASK_VTX 0x80
-
-typedef enum ShaderInstType
-{
- SIT_CF = 0x10, /*SIZE = 0x2*/
- SIT_CF_ALL_EXP = 0x14, /*SIZE = 0x2, MAX_INSTRUCTIONS = 0x10;*/
- SIT_CF_ALL_EXP_SX = 0x15, /*SIZE = 0x2, MAX_INSTRUCTIONS = 0x10;*/
- SIT_CF_ALL_EXP_SMX= 0x16, /*SIZE = 0x2, MAX_INSTRUCTIONS = 0x10;*/
- SIT_CF_GENERIC = 0x18, /*SIZE = 0x2, MAX_INSTRUCTIONS = 0x8; //For tex and vtx*/
- SIT_CF_ALU = 0x19, /*SIZE = 0x2, MAX_INSTRUCTIONS = 0x80;*/
- SIT_ALU = 0x20, /*SIZE = 0x2,*/
- SIT_ALU_HALF_LIT = 0x21, /*SIZE = 0x4,*/
- SIT_ALU_FALL_LIT = 0x22, /*SIZE = 0x6,*/
- SIT_TEX = 0x40, /*SIZE = 0x4,*/
- SIT_VTX = 0x80, /*SIZE = 0x4, MEGA_FETCH_BYTES = 0x20*/
- SIT_VTX_GENERIC = 0x81, /*SIZE = 0x4, MEGA_FETCH_BYTES = 0x20*/
- SIT_VTX_SEM = 0x82 /*SIZE = 0x4, MEGA_FETCH_BYTES = 0x20*/
-} ShaderInstType;
-
-typedef struct R700ShaderInstruction
-{
- ShaderInstType m_ShaderInstType;
- struct R700ShaderInstruction *pNextInst;
- GLuint m_uIndex;
- GLuint useCount;
-} R700ShaderInstruction;
-
-// ------------------ CF insts ---------------------------
-
-typedef R700ShaderInstruction R700ControlFlowInstruction;
-
-typedef struct R700ControlFlowAllocExportClause
-{
- ShaderInstType m_ShaderInstType;
- R700ShaderInstruction * pNextInst;
- GLuint m_uIndex;
- GLuint useCount;
-
- sq_cf_alloc_export_word0_u m_Word0;
- sq_cf_alloc_export_word1_u m_Word1;
-} R700ControlFlowAllocExportClause;
-
-typedef struct R700ControlFlowSXClause
-{
- ShaderInstType m_ShaderInstType;
- R700ShaderInstruction * pNextInst;
- //R700ControlFlowAllocExportClause
- //R700ControlFlowInstruction
- //R700ShaderInstruction
- GLuint m_uIndex;
- GLuint useCount;
- //---------------------
- //---------------------------
- sq_cf_alloc_export_word0_u m_Word0;
- sq_cf_alloc_export_word1_u m_Word1;
- //-------------------------------------
-
- sq_cf_alloc_export_word1_swiz_u m_Word1_SWIZ;
-} R700ControlFlowSXClause;
-
-typedef struct R700ControlFlowSMXClause
-{
- ShaderInstType m_ShaderInstType;
- R700ShaderInstruction * pNextInst;
- //R700ControlFlowAllocExportClause
- //R700ControlFlowInstruction
- //R700ShaderInstruction
- GLuint m_uIndex;
- GLuint useCount;
- //---------------------
- //---------------------------
- sq_cf_alloc_export_word0_u m_Word0;
- sq_cf_alloc_export_word1_u m_Word1;
- //-------------------------------
-
- sq_cf_alloc_export_word1_buf_u m_Word1_BUF;
-} R700ControlFlowSMXClause;
-
-typedef struct R700ControlFlowGenericClause
-{
- ShaderInstType m_ShaderInstType;
- R700ShaderInstruction * pNextInst;
- //R700ControlFlowInstruction
- //R700ShaderInstruction
- GLuint m_uIndex;
- GLuint useCount;
- //---------------------
- //---------------------
-
- sq_cf_word0_u m_Word0;
- sq_cf_word1_u m_Word1;
-
- struct R700VertexInstruction *m_pLinkedVTXInstruction;
- struct R700TextureInstruction *m_pLinkedTEXInstruction;
-} R700ControlFlowGenericClause;
-
-typedef struct R700ControlFlowALUClause
-{
- ShaderInstType m_ShaderInstType;
- R700ShaderInstruction * pNextInst;
- //R700ControlFlowInstruction
- //R700ShaderInstruction
- GLuint m_uIndex;
- GLuint useCount;
- //---------------------
- //---------------------
-
- sq_cf_alu_word0_u m_Word0;
- sq_cf_alu_word1_u m_Word1;
-
- struct R700ALUInstruction *m_pLinkedALUInstruction;
-} R700ControlFlowALUClause;
-
-// ------------------- End of CF Inst ------------------------
-
-// ------------------- ALU Inst ------------------------------
-typedef struct R700ALUInstruction
-{
- ShaderInstType m_ShaderInstType;
- R700ShaderInstruction * pNextInst;
- //R700ShaderInstruction
- GLuint m_uIndex;
- GLuint useCount;
- //---------------------
-
- sq_alu_word0_u m_Word0;
- sq_alu_word1_u m_Word1;
- sq_alu_word1_op2_v2_u m_Word1_OP2;
- sq_alu_word1_op3_u m_Word1_OP3;
-
- struct R700ControlFlowALUClause *m_pLinkedALUClause;
-} R700ALUInstruction;
-
-typedef struct R700ALUInstructionHalfLiteral
-{
- ShaderInstType m_ShaderInstType;
- R700ShaderInstruction * pNextInst;
- //R700ALUInstruction
- //R700ShaderInstruction
- GLuint m_uIndex;
- GLuint useCount;
- //---------------------
-
- sq_alu_word0_u m_Word0;
- sq_alu_word1_u m_Word1;
- sq_alu_word1_op2_v2_u m_Word1_OP2;
- sq_alu_word1_op3_u m_Word1_OP3;
-
- struct R700ControlFlowALUClause *m_pLinkedALUClause;
- //-------------------
-
- GLfloat m_fLiteralX,
- m_fLiteralY;
-} R700ALUInstructionHalfLiteral;
-
-typedef struct R700ALUInstructionFullLiteral
-{
- ShaderInstType m_ShaderInstType;
- R700ShaderInstruction * pNextInst;
- //R700ALUInstruction
- //R700ShaderInstruction
- GLuint m_uIndex;
- GLuint useCount;
- //---------------------
-
- sq_alu_word0_u m_Word0;
- sq_alu_word1_u m_Word1;
- sq_alu_word1_op2_v2_u m_Word1_OP2;
- sq_alu_word1_op3_u m_Word1_OP3;
-
- struct R700ControlFlowALUClause *m_pLinkedALUClause;
- //-------------------
-
- GLfloat m_fLiteralX,
- m_fLiteralY,
- m_fLiteralZ,
- m_fLiteralW;
-} R700ALUInstructionFullLiteral;
-// ------------------- End of ALU Inst -----------------------
-
-// ------------------- Textuer/Vertex Instruction --------------------
-
-typedef struct R700TextureInstruction
-{
- ShaderInstType m_ShaderInstType;
- R700ShaderInstruction * pNextInst;
- //R700ShaderInstruction
- GLuint m_uIndex;
- GLuint useCount;
- //---------------------
-
- sq_tex_word0_u m_Word0;
- sq_tex_word1_u m_Word1;
- sq_tex_word2_u m_Word2;
-
- struct R700ControlFlowGenericClause *m_pLinkedGenericClause;
-} R700TextureInstruction;
-
-typedef struct R700VertexInstruction
-{
- ShaderInstType m_ShaderInstType;
- R700ShaderInstruction * pNextInst;
- //R700ShaderInstruction
- GLuint m_uIndex;
- GLuint useCount;
- //---------------------
-
- sq_vtx_word0_u m_Word0;
- sq_vtx_word1_u m_Word1;
- sq_vtx_word2_u m_Word2;
-
- struct R700ControlFlowGenericClause *m_pLinkedGenericClause;
-} R700VertexInstruction;
-//
-typedef struct R700VertexSemanticFetch
-{
- ShaderInstType m_ShaderInstType;
- R700ShaderInstruction * pNextInst;
- //R700VertexInstruction
- //R700ShaderInstruction
- GLuint m_uIndex;
- GLuint useCount;
- //---------------------
-
- sq_vtx_word0_u m_Word0;
- sq_vtx_word1_u m_Word1;
- sq_vtx_word2_u m_Word2;
-
- struct R700ControlFlowGenericClause *m_pLinkedGenericClause;
- //---------------------------
-
- sq_vtx_word1_sem_u m_Word1_SEM;
-} R700VertexSemanticFetch;
-//
-typedef struct R700VertexGenericFetch
-{
- ShaderInstType m_ShaderInstType;
- R700ShaderInstruction * pNextInst;
- //R700VertexInstruction
- //R700ShaderInstruction
- GLuint m_uIndex;
- GLuint useCount;
- //---------------------
-
- sq_vtx_word0_u m_Word0;
- sq_vtx_word1_u m_Word1;
- sq_vtx_word2_u m_Word2;
-
- struct R700ControlFlowGenericClause *m_pLinkedGenericClause;
- //---------------------------
-
- sq_vtx_word1_gpr_u m_Word1_GPR;
-} R700VertexGenericFetch;
-
-// ------------------- End of Texture Vertex Instruction --------------------
-
-void Init_R700ControlFlowGenericClause(R700ControlFlowGenericClause* pInst);
-void Init_R700ControlFlowALUClause(R700ControlFlowALUClause* pInst);
-void Init_R700ControlFlowSXClause(R700ControlFlowSXClause* pInst);
-void Init_R700ControlFlowSMXClause(R700ControlFlowSMXClause* pInst);
-void Init_R700ALUInstruction(R700ALUInstruction* pInst);
-void Init_R700ALUInstructionHalfLiteral(R700ALUInstructionHalfLiteral* pInst, GLfloat x, GLfloat y);
-void Init_R700ALUInstructionFullLiteral(R700ALUInstructionFullLiteral* pInst, GLfloat x, GLfloat y, GLfloat z, GLfloat w);
-void Init_R700TextureInstruction(R700TextureInstruction* pInst);
-void Init_R700VertexSemanticFetch(R700VertexSemanticFetch* pInst);
-void Init_R700VertexGenericFetch(R700VertexGenericFetch* pInst);
-
-unsigned int GetInstructionSize(ShaderInstType instType);
-unsigned int GetCFMaxInstructions(ShaderInstType instType);
-
-GLboolean LinkVertexInstruction(R700ControlFlowGenericClause *pCFGeneric,
- R700VertexInstruction *pVTXInstruction);
-
-#endif //_R700_SHADERINST_H_
+++ /dev/null
-/*
- * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Authors:
- * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
- */
-
-#include "main/glheader.h"
-#include "main/mtypes.h"
-#include "main/imports.h"
-#include "main/enums.h"
-#include "main/macros.h"
-#include "main/context.h"
-#include "main/dd.h"
-#include "main/simple_list.h"
-#include "main/state.h"
-
-#include "tnl/tnl.h"
-#include "tnl/t_pipeline.h"
-#include "swrast/swrast.h"
-#include "swrast_setup/swrast_setup.h"
-#include "main/api_arrayelt.h"
-#include "main/framebuffer.h"
-#include "drivers/common/meta.h"
-
-#include "program/prog_parameter.h"
-#include "program/prog_statevars.h"
-#include "vbo/vbo.h"
-
-#include "r600_context.h"
-
-#include "r700_state.h"
-
-#include "r700_fragprog.h"
-#include "r700_vertprog.h"
-
-void r600UpdateTextureState(struct gl_context * ctx);
-static void r700SetClipPlaneState(struct gl_context * ctx, GLenum cap, GLboolean state);
-static void r700UpdatePolygonMode(struct gl_context * ctx);
-static void r700SetPolygonOffsetState(struct gl_context * ctx, GLboolean state);
-static void r700SetStencilState(struct gl_context * ctx, GLboolean state);
-static void r700UpdateWindow(struct gl_context * ctx, int id);
-
-void r700UpdateShaders(struct gl_context * ctx)
-{
- context_t *context = R700_CONTEXT(ctx);
-
- /* should only happenen once, just after context is created */
- /* TODO: shouldn't we fallback to sw here? */
- if (!ctx->FragmentProgram._Current) {
- fprintf(stderr, "No ctx->FragmentProgram._Current!!\n");
- return;
- }
-
- r700SelectFragmentShader(ctx);
-
- r700SelectVertexShader(ctx);
- r700UpdateStateParameters(ctx, _NEW_PROGRAM | _NEW_PROGRAM_CONSTANTS);
- context->radeon.NewGLState = 0;
-}
-
-/*
- * To correctly position primitives:
- */
-void r700UpdateViewportOffset(struct gl_context * ctx) //------------------
-{
- context_t *context = R700_CONTEXT(ctx);
- R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
- __DRIdrawable *dPriv = radeon_get_drawable(&context->radeon);
- GLfloat xoffset = (GLfloat) dPriv->x;
- GLfloat yoffset = (GLfloat) dPriv->y + dPriv->h;
- const GLfloat *v = ctx->Viewport._WindowMap.m;
- int id = 0;
-
- GLfloat tx = v[MAT_TX] + xoffset;
- GLfloat ty = (-v[MAT_TY]) + yoffset;
-
- if (r700->viewport[id].PA_CL_VPORT_XOFFSET.f32All != tx ||
- r700->viewport[id].PA_CL_VPORT_YOFFSET.f32All != ty) {
- /* Note: this should also modify whatever data the context reset
- * code uses...
- */
- R600_STATECHANGE(context, vpt);
- r700->viewport[id].PA_CL_VPORT_XOFFSET.f32All = tx;
- r700->viewport[id].PA_CL_VPORT_YOFFSET.f32All = ty;
- }
-
- radeonUpdateScissor(ctx);
-}
-
-void r700UpdateStateParameters(struct gl_context * ctx, GLuint new_state) //--------------------
-{
- struct r700_fragment_program *fp =
- (struct r700_fragment_program *)ctx->FragmentProgram._Current;
- struct gl_program_parameter_list *paramList;
-
- if (!(new_state & (_NEW_BUFFERS | _NEW_PROGRAM | _NEW_PROGRAM_CONSTANTS)))
- return;
-
- if (!ctx->FragmentProgram._Current || !fp)
- return;
-
- paramList = ctx->FragmentProgram._Current->Base.Parameters;
-
- if (!paramList)
- return;
-
- _mesa_load_state_parameters(ctx, paramList);
-
-}
-
-/**
- * Called by Mesa after an internal state update.
- */
-static void r700InvalidateState(struct gl_context * ctx, GLuint new_state) //-------------------
-{
- context_t *context = R700_CONTEXT(ctx);
-
- R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
-
- _swrast_InvalidateState(ctx, new_state);
- _swsetup_InvalidateState(ctx, new_state);
- _vbo_InvalidateState(ctx, new_state);
- _tnl_InvalidateState(ctx, new_state);
- _ae_invalidate_state(ctx, new_state);
-
- if (new_state & _NEW_BUFFERS) {
- _mesa_update_framebuffer(ctx);
- /* this updates the DrawBuffer's Width/Height if it's a FBO */
- _mesa_update_draw_buffer_bounds(ctx);
-
- R600_STATECHANGE(context, cb_target);
- R600_STATECHANGE(context, db_target);
- }
-
- if (new_state & (_NEW_LIGHT)) {
- R600_STATECHANGE(context, su);
- if (ctx->Light.ProvokingVertex == GL_LAST_VERTEX_CONVENTION)
- SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, PROVOKING_VTX_LAST_bit);
- else
- CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, PROVOKING_VTX_LAST_bit);
- }
-
- r700UpdateStateParameters(ctx, new_state);
-
- R600_STATECHANGE(context, cl);
- R600_STATECHANGE(context, spi);
-
- if(GL_TRUE == r700->bEnablePerspective)
- {
- /* Do scale XY and Z by 1/W0 for perspective correction on pos. For orthogonal case, set both to one. */
- CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
- CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
-
- SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
-
- SETbit(r700->SPI_PS_IN_CONTROL_0.u32All, PERSP_GRADIENT_ENA_bit);
- CLEARbit(r700->SPI_PS_IN_CONTROL_0.u32All, LINEAR_GRADIENT_ENA_bit);
- }
- else
- {
- /* For orthogonal case. */
- SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
- SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
-
- SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
-
- CLEARbit(r700->SPI_PS_IN_CONTROL_0.u32All, PERSP_GRADIENT_ENA_bit);
- SETbit(r700->SPI_PS_IN_CONTROL_0.u32All, LINEAR_GRADIENT_ENA_bit);
- }
-
- context->radeon.NewGLState |= new_state;
-}
-
-static void r700SetDBRenderState(struct gl_context * ctx)
-{
- context_t *context = R700_CONTEXT(ctx);
- R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
- struct r700_fragment_program *fp = (struct r700_fragment_program *)
- (ctx->FragmentProgram._Current);
-
- R600_STATECHANGE(context, db);
-
- SETbit(r700->DB_SHADER_CONTROL.u32All, DUAL_EXPORT_ENABLE_bit);
- SETfield(r700->DB_SHADER_CONTROL.u32All, EARLY_Z_THEN_LATE_Z, Z_ORDER_shift, Z_ORDER_mask);
- /* XXX need to enable htile for hiz/s */
- SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIZ_ENABLE_shift, FORCE_HIZ_ENABLE_mask);
- SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE0_shift, FORCE_HIS_ENABLE0_mask);
- SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE1_shift, FORCE_HIS_ENABLE1_mask);
-
- if (context->radeon.query.current)
- {
- SETbit(r700->DB_RENDER_OVERRIDE.u32All, NOOP_CULL_DISABLE_bit);
- if (context->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV770)
- {
- SETbit(r700->DB_RENDER_CONTROL.u32All, PERFECT_ZPASS_COUNTS_bit);
- }
- }
- else
- {
- CLEARbit(r700->DB_RENDER_OVERRIDE.u32All, NOOP_CULL_DISABLE_bit);
- if (context->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV770)
- {
- CLEARbit(r700->DB_RENDER_CONTROL.u32All, PERFECT_ZPASS_COUNTS_bit);
- }
- }
-
- if (fp)
- {
- if (fp->r700Shader.killIsUsed)
- {
- SETbit(r700->DB_SHADER_CONTROL.u32All, KILL_ENABLE_bit);
- }
- else
- {
- CLEARbit(r700->DB_SHADER_CONTROL.u32All, KILL_ENABLE_bit);
- }
-
- if (fp->r700Shader.depthIsExported)
- {
- SETbit(r700->DB_SHADER_CONTROL.u32All, Z_EXPORT_ENABLE_bit);
- }
- else
- {
- CLEARbit(r700->DB_SHADER_CONTROL.u32All, Z_EXPORT_ENABLE_bit);
- }
- }
-}
-
-void r700UpdateShaderStates(struct gl_context * ctx)
-{
- r700SetDBRenderState(ctx);
- r600UpdateTextureState(ctx);
-}
-
-static void r700SetDepthState(struct gl_context * ctx)
-{
- struct radeon_renderbuffer *rrb;
- context_t *context = R700_CONTEXT(ctx);
- R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
-
- R600_STATECHANGE(context, db);
-
- rrb = radeon_get_depthbuffer(&context->radeon);
-
- if (ctx->Depth.Test && rrb && rrb->bo)
- {
- SETbit(r700->DB_DEPTH_CONTROL.u32All, Z_ENABLE_bit);
- if (ctx->Depth.Mask)
- {
- SETbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
- }
- else
- {
- CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
- }
-
- switch (ctx->Depth.Func)
- {
- case GL_NEVER:
- SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_NEVER,
- ZFUNC_shift, ZFUNC_mask);
- break;
- case GL_LESS:
- SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_LESS,
- ZFUNC_shift, ZFUNC_mask);
- break;
- case GL_EQUAL:
- SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_EQUAL,
- ZFUNC_shift, ZFUNC_mask);
- break;
- case GL_LEQUAL:
- SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_LEQUAL,
- ZFUNC_shift, ZFUNC_mask);
- break;
- case GL_GREATER:
- SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_GREATER,
- ZFUNC_shift, ZFUNC_mask);
- break;
- case GL_NOTEQUAL:
- SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_NOTEQUAL,
- ZFUNC_shift, ZFUNC_mask);
- break;
- case GL_GEQUAL:
- SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_GEQUAL,
- ZFUNC_shift, ZFUNC_mask);
- break;
- case GL_ALWAYS:
- SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_ALWAYS,
- ZFUNC_shift, ZFUNC_mask);
- break;
- default:
- SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_ALWAYS,
- ZFUNC_shift, ZFUNC_mask);
- break;
- }
- }
- else
- {
- CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_ENABLE_bit);
- CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
- }
-}
-
-static void r700SetAlphaState(struct gl_context * ctx)
-{
- context_t *context = R700_CONTEXT(ctx);
- R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
- uint32_t alpha_func = REF_ALWAYS;
- GLboolean really_enabled = ctx->Color.AlphaEnabled;
-
- R600_STATECHANGE(context, sx);
-
- switch (ctx->Color.AlphaFunc) {
- case GL_NEVER:
- alpha_func = REF_NEVER;
- break;
- case GL_LESS:
- alpha_func = REF_LESS;
- break;
- case GL_EQUAL:
- alpha_func = REF_EQUAL;
- break;
- case GL_LEQUAL:
- alpha_func = REF_LEQUAL;
- break;
- case GL_GREATER:
- alpha_func = REF_GREATER;
- break;
- case GL_NOTEQUAL:
- alpha_func = REF_NOTEQUAL;
- break;
- case GL_GEQUAL:
- alpha_func = REF_GEQUAL;
- break;
- case GL_ALWAYS:
- /*alpha_func = REF_ALWAYS; */
- really_enabled = GL_FALSE;
- break;
- }
-
- if (really_enabled) {
- SETfield(r700->SX_ALPHA_TEST_CONTROL.u32All, alpha_func,
- ALPHA_FUNC_shift, ALPHA_FUNC_mask);
- SETbit(r700->SX_ALPHA_TEST_CONTROL.u32All, ALPHA_TEST_ENABLE_bit);
- r700->SX_ALPHA_REF.f32All = ctx->Color.AlphaRef;
- } else {
- CLEARbit(r700->SX_ALPHA_TEST_CONTROL.u32All, ALPHA_TEST_ENABLE_bit);
- }
-
-}
-
-static void r700AlphaFunc(struct gl_context * ctx, GLenum func, GLfloat ref) //---------------
-{
- (void)func;
- (void)ref;
- r700SetAlphaState(ctx);
-}
-
-
-static void r700BlendColor(struct gl_context * ctx, const GLfloat cf[4]) //----------------
-{
- context_t *context = R700_CONTEXT(ctx);
- R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
-
- R600_STATECHANGE(context, blnd_clr);
-
- r700->CB_BLEND_RED.f32All = cf[0];
- r700->CB_BLEND_GREEN.f32All = cf[1];
- r700->CB_BLEND_BLUE.f32All = cf[2];
- r700->CB_BLEND_ALPHA.f32All = cf[3];
-}
-
-static int blend_factor(GLenum factor, GLboolean is_src)
-{
- switch (factor) {
- case GL_ZERO:
- return BLEND_ZERO;
- break;
- case GL_ONE:
- return BLEND_ONE;
- break;
- case GL_DST_COLOR:
- return BLEND_DST_COLOR;
- break;
- case GL_ONE_MINUS_DST_COLOR:
- return BLEND_ONE_MINUS_DST_COLOR;
- break;
- case GL_SRC_COLOR:
- return BLEND_SRC_COLOR;
- break;
- case GL_ONE_MINUS_SRC_COLOR:
- return BLEND_ONE_MINUS_SRC_COLOR;
- break;
- case GL_SRC_ALPHA:
- return BLEND_SRC_ALPHA;
- break;
- case GL_ONE_MINUS_SRC_ALPHA:
- return BLEND_ONE_MINUS_SRC_ALPHA;
- break;
- case GL_DST_ALPHA:
- return BLEND_DST_ALPHA;
- break;
- case GL_ONE_MINUS_DST_ALPHA:
- return BLEND_ONE_MINUS_DST_ALPHA;
- break;
- case GL_SRC_ALPHA_SATURATE:
- return (is_src) ? BLEND_SRC_ALPHA_SATURATE : BLEND_ZERO;
- break;
- case GL_CONSTANT_COLOR:
- return BLEND_CONSTANT_COLOR;
- break;
- case GL_ONE_MINUS_CONSTANT_COLOR:
- return BLEND_ONE_MINUS_CONSTANT_COLOR;
- break;
- case GL_CONSTANT_ALPHA:
- return BLEND_CONSTANT_ALPHA;
- break;
- case GL_ONE_MINUS_CONSTANT_ALPHA:
- return BLEND_ONE_MINUS_CONSTANT_ALPHA;
- break;
- default:
- fprintf(stderr, "unknown blend factor %x\n", factor);
- return (is_src) ? BLEND_ONE : BLEND_ZERO;
- break;
- }
-}
-
-static void r700SetBlendState(struct gl_context * ctx)
-{
- context_t *context = R700_CONTEXT(ctx);
- R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
- int id = 0;
- uint32_t blend_reg = 0, eqn, eqnA;
-
- R600_STATECHANGE(context, blnd);
-
- if (ctx->Color.ColorLogicOpEnabled || !ctx->Color.BlendEnabled) {
- SETfield(blend_reg,
- BLEND_ONE, COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
- SETfield(blend_reg,
- BLEND_ZERO, COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
- SETfield(blend_reg,
- COMB_DST_PLUS_SRC, COLOR_COMB_FCN_shift, COLOR_COMB_FCN_mask);
- SETfield(blend_reg,
- BLEND_ONE, ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
- SETfield(blend_reg,
- BLEND_ZERO, ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
- SETfield(blend_reg,
- COMB_DST_PLUS_SRC, ALPHA_COMB_FCN_shift, ALPHA_COMB_FCN_mask);
- if (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_R600)
- r700->CB_BLEND_CONTROL.u32All = blend_reg;
- else
- r700->render_target[id].CB_BLEND0_CONTROL.u32All = blend_reg;
- return;
- }
-
- SETfield(blend_reg,
- blend_factor(ctx->Color.Blend[0].SrcRGB, GL_TRUE),
- COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
- SETfield(blend_reg,
- blend_factor(ctx->Color.Blend[0].DstRGB, GL_FALSE),
- COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
-
- switch (ctx->Color.Blend[0].EquationRGB) {
- case GL_FUNC_ADD:
- eqn = COMB_DST_PLUS_SRC;
- break;
- case GL_FUNC_SUBTRACT:
- eqn = COMB_SRC_MINUS_DST;
- break;
- case GL_FUNC_REVERSE_SUBTRACT:
- eqn = COMB_DST_MINUS_SRC;
- break;
- case GL_MIN:
- eqn = COMB_MIN_DST_SRC;
- SETfield(blend_reg,
- BLEND_ONE,
- COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
- SETfield(blend_reg,
- BLEND_ONE,
- COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
- break;
- case GL_MAX:
- eqn = COMB_MAX_DST_SRC;
- SETfield(blend_reg,
- BLEND_ONE,
- COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
- SETfield(blend_reg,
- BLEND_ONE,
- COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
- break;
-
- default:
- fprintf(stderr,
- "[%s:%u] Invalid RGB blend equation (0x%04x).\n",
- __FUNCTION__, __LINE__, ctx->Color.Blend[0].EquationRGB);
- return;
- }
- SETfield(blend_reg,
- eqn, COLOR_COMB_FCN_shift, COLOR_COMB_FCN_mask);
-
- SETfield(blend_reg,
- blend_factor(ctx->Color.Blend[0].SrcA, GL_TRUE),
- ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
- SETfield(blend_reg,
- blend_factor(ctx->Color.Blend[0].DstA, GL_FALSE),
- ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
-
- switch (ctx->Color.Blend[0].EquationA) {
- case GL_FUNC_ADD:
- eqnA = COMB_DST_PLUS_SRC;
- break;
- case GL_FUNC_SUBTRACT:
- eqnA = COMB_SRC_MINUS_DST;
- break;
- case GL_FUNC_REVERSE_SUBTRACT:
- eqnA = COMB_DST_MINUS_SRC;
- break;
- case GL_MIN:
- eqnA = COMB_MIN_DST_SRC;
- SETfield(blend_reg,
- BLEND_ONE,
- ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
- SETfield(blend_reg,
- BLEND_ONE,
- ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
- break;
- case GL_MAX:
- eqnA = COMB_MAX_DST_SRC;
- SETfield(blend_reg,
- BLEND_ONE,
- ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
- SETfield(blend_reg,
- BLEND_ONE,
- ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
- break;
- default:
- fprintf(stderr,
- "[%s:%u] Invalid A blend equation (0x%04x).\n",
- __FUNCTION__, __LINE__, ctx->Color.Blend[0].EquationA);
- return;
- }
-
- SETfield(blend_reg,
- eqnA, ALPHA_COMB_FCN_shift, ALPHA_COMB_FCN_mask);
-
- SETbit(blend_reg, SEPARATE_ALPHA_BLEND_bit);
-
- if (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_R600)
- r700->CB_BLEND_CONTROL.u32All = blend_reg;
- else {
- r700->render_target[id].CB_BLEND0_CONTROL.u32All = blend_reg;
- SETbit(r700->CB_COLOR_CONTROL.u32All, PER_MRT_BLEND_bit);
- }
- SETfield(r700->CB_COLOR_CONTROL.u32All, (1 << id),
- TARGET_BLEND_ENABLE_shift, TARGET_BLEND_ENABLE_mask);
-
-}
-
-static void r700BlendEquationSeparate(struct gl_context * ctx,
- GLenum modeRGB, GLenum modeA) //-----------------
-{
- r700SetBlendState(ctx);
-}
-
-static void r700BlendFuncSeparate(struct gl_context * ctx,
- GLenum sfactorRGB, GLenum dfactorRGB,
- GLenum sfactorA, GLenum dfactorA) //------------------------
-{
- r700SetBlendState(ctx);
-}
-
-/**
- * Translate LogicOp enums into hardware representation.
- */
-static GLuint translate_logicop(GLenum logicop)
-{
- switch (logicop) {
- case GL_CLEAR:
- return 0x00;
- case GL_SET:
- return 0xff;
- case GL_COPY:
- return 0xcc;
- case GL_COPY_INVERTED:
- return 0x33;
- case GL_NOOP:
- return 0xaa;
- case GL_INVERT:
- return 0x55;
- case GL_AND:
- return 0x88;
- case GL_NAND:
- return 0x77;
- case GL_OR:
- return 0xee;
- case GL_NOR:
- return 0x11;
- case GL_XOR:
- return 0x66;
- case GL_EQUIV:
- return 0x99;
- case GL_AND_REVERSE:
- return 0x44;
- case GL_AND_INVERTED:
- return 0x22;
- case GL_OR_REVERSE:
- return 0xdd;
- case GL_OR_INVERTED:
- return 0xbb;
- default:
- fprintf(stderr, "unknown blend logic operation %x\n", logicop);
- return 0xcc;
- }
-}
-
-/**
- * Used internally to update the r300->hw hardware state to match the
- * current OpenGL state.
- */
-static void r700SetLogicOpState(struct gl_context *ctx)
-{
- context_t *context = R700_CONTEXT(ctx);
- R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
-
- R600_STATECHANGE(context, blnd);
-
- if (ctx->Color.ColorLogicOpEnabled)
- SETfield(r700->CB_COLOR_CONTROL.u32All,
- translate_logicop(ctx->Color.LogicOp), ROP3_shift, ROP3_mask);
- else
- SETfield(r700->CB_COLOR_CONTROL.u32All, 0xCC, ROP3_shift, ROP3_mask);
-}
-
-/**
- * Called by Mesa when an application program changes the LogicOp state
- * via glLogicOp.
- */
-static void r700LogicOpcode(struct gl_context *ctx, GLenum logicop)
-{
- if (ctx->Color.ColorLogicOpEnabled)
- r700SetLogicOpState(ctx);
-}
-
-static void r700UpdateCulling(struct gl_context * ctx)
-{
- context_t *context = R700_CONTEXT(ctx);
- R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
-
- R600_STATECHANGE(context, su);
-
- CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
- CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
- CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
-
- if (ctx->Polygon.CullFlag)
- {
- switch (ctx->Polygon.CullFaceMode)
- {
- case GL_FRONT:
- SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
- CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
- break;
- case GL_BACK:
- CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
- SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
- break;
- case GL_FRONT_AND_BACK:
- SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
- SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
- break;
- default:
- CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
- CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
- break;
- }
- }
-
- switch (ctx->Polygon.FrontFace)
- {
- case GL_CW:
- SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
- break;
- case GL_CCW:
- CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
- break;
- default:
- CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit); /* default: ccw */
- break;
- }
-
- /* Winding is inverted when rendering to FBO */
- if (ctx->DrawBuffer && ctx->DrawBuffer->Name)
- r700->PA_SU_SC_MODE_CNTL.u32All ^= FACE_bit;
-}
-
-static void r700UpdateLineStipple(struct gl_context * ctx)
-{
- context_t *context = R700_CONTEXT(ctx);
- R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
-
- R600_STATECHANGE(context, sc);
-
- if (ctx->Line.StippleFlag)
- {
- SETbit(r700->PA_SC_MODE_CNTL.u32All, LINE_STIPPLE_ENABLE_bit);
- }
- else
- {
- CLEARbit(r700->PA_SC_MODE_CNTL.u32All, LINE_STIPPLE_ENABLE_bit);
- }
-}
-
-static void r700Enable(struct gl_context * ctx, GLenum cap, GLboolean state) //------------------
-{
- context_t *context = R700_CONTEXT(ctx);
-
- switch (cap) {
- case GL_TEXTURE_1D:
- case GL_TEXTURE_2D:
- case GL_TEXTURE_3D:
- /* empty */
- break;
- case GL_FOG:
- /* empty */
- break;
- case GL_ALPHA_TEST:
- r700SetAlphaState(ctx);
- break;
- case GL_COLOR_LOGIC_OP:
- r700SetLogicOpState(ctx);
- /* fall-through, because logic op overrides blending */
- case GL_BLEND:
- r700SetBlendState(ctx);
- break;
- case GL_CLIP_PLANE0:
- case GL_CLIP_PLANE1:
- case GL_CLIP_PLANE2:
- case GL_CLIP_PLANE3:
- case GL_CLIP_PLANE4:
- case GL_CLIP_PLANE5:
- r700SetClipPlaneState(ctx, cap, state);
- break;
- case GL_DEPTH_TEST:
- r700SetDepthState(ctx);
- break;
- case GL_STENCIL_TEST:
- r700SetStencilState(ctx, state);
- break;
- case GL_CULL_FACE:
- r700UpdateCulling(ctx);
- break;
- case GL_POLYGON_OFFSET_POINT:
- case GL_POLYGON_OFFSET_LINE:
- case GL_POLYGON_OFFSET_FILL:
- r700SetPolygonOffsetState(ctx, state);
- break;
- case GL_SCISSOR_TEST:
- radeon_firevertices(&context->radeon);
- context->radeon.state.scissor.enabled = state;
- radeonUpdateScissor(ctx);
- break;
- case GL_LINE_STIPPLE:
- r700UpdateLineStipple(ctx);
- break;
- case GL_DEPTH_CLAMP:
- r700UpdateWindow(ctx, 0);
- break;
- default:
- break;
- }
-
-}
-
-/**
- * Handle glColorMask()
- */
-static void r700ColorMask(struct gl_context * ctx,
- GLboolean r, GLboolean g, GLboolean b, GLboolean a) //------------------
-{
- context_t *context = R700_CONTEXT(ctx);
- R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
- unsigned int mask = ((r ? 1 : 0) |
- (g ? 2 : 0) |
- (b ? 4 : 0) |
- (a ? 8 : 0));
-
- if (mask != r700->CB_TARGET_MASK.u32All) {
- R600_STATECHANGE(context, cb);
- SETfield(r700->CB_TARGET_MASK.u32All, mask, TARGET0_ENABLE_shift, TARGET0_ENABLE_mask);
- }
-}
-
-/**
- * Change the depth testing function.
- *
- * \note Mesa already filters redundant calls to this function.
- */
-static void r700DepthFunc(struct gl_context * ctx, GLenum func) //--------------------
-{
- r700SetDepthState(ctx);
-}
-
-/**
- * Enable/Disable depth writing.
- *
- * \note Mesa already filters redundant calls to this function.
- */
-static void r700DepthMask(struct gl_context * ctx, GLboolean mask) //------------------
-{
- r700SetDepthState(ctx);
-}
-
-/**
- * Change the culling mode.
- *
- * \note Mesa already filters redundant calls to this function.
- */
-static void r700CullFace(struct gl_context * ctx, GLenum mode) //-----------------
-{
- r700UpdateCulling(ctx);
-}
-
-/* =============================================================
- * Fog
- */
-static void r700Fogfv(struct gl_context * ctx, GLenum pname, const GLfloat * param) //--------------
-{
-}
-
-/**
- * Change the polygon orientation.
- *
- * \note Mesa already filters redundant calls to this function.
- */
-static void r700FrontFace(struct gl_context * ctx, GLenum mode) //------------------
-{
- r700UpdateCulling(ctx);
- r700UpdatePolygonMode(ctx);
-}
-
-static void r700ShadeModel(struct gl_context * ctx, GLenum mode) //--------------------
-{
- context_t *context = R700_CONTEXT(ctx);
- R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
-
- R600_STATECHANGE(context, spi);
-
- /* also need to set/clear FLAT_SHADE bit per param in SPI_PS_INPUT_CNTL_[0-31] */
- switch (mode) {
- case GL_FLAT:
- SETbit(r700->SPI_INTERP_CONTROL_0.u32All, FLAT_SHADE_ENA_bit);
- break;
- case GL_SMOOTH:
- CLEARbit(r700->SPI_INTERP_CONTROL_0.u32All, FLAT_SHADE_ENA_bit);
- break;
- default:
- return;
- }
-}
-
-/* =============================================================
- * Point state
- */
-static void r700PointSize(struct gl_context * ctx, GLfloat size)
-{
- context_t *context = R700_CONTEXT(ctx);
- R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
-
- R600_STATECHANGE(context, su);
-
- /* We need to clamp to user defined range here, because
- * the HW clamping happens only for per vertex point size. */
- size = CLAMP(size, ctx->Point.MinSize, ctx->Point.MaxSize);
-
- /* same size limits for AA, non-AA points */
- size = CLAMP(size, ctx->Const.MinPointSize, ctx->Const.MaxPointSize);
-
- /* format is 12.4 fixed point */
- SETfield(r700->PA_SU_POINT_SIZE.u32All, (int)(size * 8.0),
- PA_SU_POINT_SIZE__HEIGHT_shift, PA_SU_POINT_SIZE__HEIGHT_mask);
- SETfield(r700->PA_SU_POINT_SIZE.u32All, (int)(size * 8.0),
- PA_SU_POINT_SIZE__WIDTH_shift, PA_SU_POINT_SIZE__WIDTH_mask);
-
-}
-
-static void r700PointParameter(struct gl_context * ctx, GLenum pname, const GLfloat * param) //---------------
-{
- context_t *context = R700_CONTEXT(ctx);
- R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
-
- R600_STATECHANGE(context, su);
-
- /* format is 12.4 fixed point */
- switch (pname) {
- case GL_POINT_SIZE_MIN:
- SETfield(r700->PA_SU_POINT_MINMAX.u32All, (int)(ctx->Point.MinSize * 8.0),
- MIN_SIZE_shift, MIN_SIZE_mask);
- r700PointSize(ctx, ctx->Point.Size);
- break;
- case GL_POINT_SIZE_MAX:
- SETfield(r700->PA_SU_POINT_MINMAX.u32All, (int)(ctx->Point.MaxSize * 8.0),
- MAX_SIZE_shift, MAX_SIZE_mask);
- r700PointSize(ctx, ctx->Point.Size);
- break;
- case GL_POINT_DISTANCE_ATTENUATION:
- break;
- case GL_POINT_FADE_THRESHOLD_SIZE:
- break;
- default:
- break;
- }
-}
-
-static int translate_stencil_func(int func)
-{
- switch (func) {
- case GL_NEVER:
- return REF_NEVER;
- case GL_LESS:
- return REF_LESS;
- case GL_EQUAL:
- return REF_EQUAL;
- case GL_LEQUAL:
- return REF_LEQUAL;
- case GL_GREATER:
- return REF_GREATER;
- case GL_NOTEQUAL:
- return REF_NOTEQUAL;
- case GL_GEQUAL:
- return REF_GEQUAL;
- case GL_ALWAYS:
- return REF_ALWAYS;
- }
- return 0;
-}
-
-static int translate_stencil_op(int op)
-{
- switch (op) {
- case GL_KEEP:
- return STENCIL_KEEP;
- case GL_ZERO:
- return STENCIL_ZERO;
- case GL_REPLACE:
- return STENCIL_REPLACE;
- case GL_INCR:
- return STENCIL_INCR_CLAMP;
- case GL_DECR:
- return STENCIL_DECR_CLAMP;
- case GL_INCR_WRAP_EXT:
- return STENCIL_INCR_WRAP;
- case GL_DECR_WRAP_EXT:
- return STENCIL_DECR_WRAP;
- case GL_INVERT:
- return STENCIL_INVERT;
- default:
- WARN_ONCE("Do not know how to translate stencil op");
- return STENCIL_KEEP;
- }
- return 0;
-}
-
-static void r700SetStencilState(struct gl_context * ctx, GLboolean state)
-{
- context_t *context = R700_CONTEXT(ctx);
- R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
- GLboolean hw_stencil = GL_FALSE;
-
- if (ctx->DrawBuffer) {
- struct radeon_renderbuffer *rrbStencil
- = radeon_get_renderbuffer(ctx->DrawBuffer, BUFFER_STENCIL);
- hw_stencil = (rrbStencil && rrbStencil->bo);
- }
-
- if (hw_stencil) {
- R600_STATECHANGE(context, db);
- if (state) {
- SETbit(r700->DB_DEPTH_CONTROL.u32All, STENCIL_ENABLE_bit);
- SETbit(r700->DB_DEPTH_CONTROL.u32All, BACKFACE_ENABLE_bit);
- } else
- CLEARbit(r700->DB_DEPTH_CONTROL.u32All, STENCIL_ENABLE_bit);
- }
-}
-
-static void r700StencilFuncSeparate(struct gl_context * ctx, GLenum face,
- GLenum func, GLint ref, GLuint mask) //---------------------
-{
- context_t *context = R700_CONTEXT(ctx);
- R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
- const unsigned back = ctx->Stencil._BackFace;
-
- R600_STATECHANGE(context, stencil);
- R600_STATECHANGE(context, db);
-
- //front
- SETfield(r700->DB_STENCILREFMASK.u32All, ctx->Stencil.Ref[0],
- STENCILREF_shift, STENCILREF_mask);
- SETfield(r700->DB_STENCILREFMASK.u32All, ctx->Stencil.ValueMask[0],
- STENCILMASK_shift, STENCILMASK_mask);
-
- SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_func(ctx->Stencil.Function[0]),
- STENCILFUNC_shift, STENCILFUNC_mask);
-
- //back
- SETfield(r700->DB_STENCILREFMASK_BF.u32All, ctx->Stencil.Ref[back],
- STENCILREF_BF_shift, STENCILREF_BF_mask);
- SETfield(r700->DB_STENCILREFMASK_BF.u32All, ctx->Stencil.ValueMask[back],
- STENCILMASK_BF_shift, STENCILMASK_BF_mask);
-
- SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_func(ctx->Stencil.Function[back]),
- STENCILFUNC_BF_shift, STENCILFUNC_BF_mask);
-
-}
-
-static void r700StencilMaskSeparate(struct gl_context * ctx, GLenum face, GLuint mask) //--------------
-{
- context_t *context = R700_CONTEXT(ctx);
- R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
- const unsigned back = ctx->Stencil._BackFace;
-
- R600_STATECHANGE(context, stencil);
-
- // front
- SETfield(r700->DB_STENCILREFMASK.u32All, ctx->Stencil.WriteMask[0],
- STENCILWRITEMASK_shift, STENCILWRITEMASK_mask);
-
- // back
- SETfield(r700->DB_STENCILREFMASK_BF.u32All, ctx->Stencil.WriteMask[back],
- STENCILWRITEMASK_BF_shift, STENCILWRITEMASK_BF_mask);
-
-}
-
-static void r700StencilOpSeparate(struct gl_context * ctx, GLenum face,
- GLenum fail, GLenum zfail, GLenum zpass) //--------------------
-{
- context_t *context = R700_CONTEXT(ctx);
- R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
- const unsigned back = ctx->Stencil._BackFace;
-
- R600_STATECHANGE(context, db);
-
- SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.FailFunc[0]),
- STENCILFAIL_shift, STENCILFAIL_mask);
- SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZFailFunc[0]),
- STENCILZFAIL_shift, STENCILZFAIL_mask);
- SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZPassFunc[0]),
- STENCILZPASS_shift, STENCILZPASS_mask);
-
- SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.FailFunc[back]),
- STENCILFAIL_BF_shift, STENCILFAIL_BF_mask);
- SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZFailFunc[back]),
- STENCILZFAIL_BF_shift, STENCILZFAIL_BF_mask);
- SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZPassFunc[back]),
- STENCILZPASS_BF_shift, STENCILZPASS_BF_mask);
-}
-
-static void r700UpdateWindow(struct gl_context * ctx, int id) //--------------------
-{
- context_t *context = R700_CONTEXT(ctx);
- R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
- __DRIdrawable *dPriv = radeon_get_drawable(&context->radeon);
- GLfloat xoffset = dPriv ? (GLfloat) dPriv->x : 0;
- GLfloat yoffset = dPriv ? (GLfloat) dPriv->y + dPriv->h : 0;
- const GLfloat *v = ctx->Viewport._WindowMap.m;
- const GLfloat depthScale = 1.0F / ctx->DrawBuffer->_DepthMaxF;
- const GLboolean render_to_fbo = (ctx->DrawBuffer->Name != 0);
- GLfloat y_scale, y_bias;
-
- if (render_to_fbo) {
- y_scale = 1.0;
- y_bias = 0;
- } else {
- y_scale = -1.0;
- y_bias = yoffset;
- }
-
- GLfloat sx = v[MAT_SX];
- GLfloat tx = v[MAT_TX] + xoffset;
- GLfloat sy = v[MAT_SY] * y_scale;
- GLfloat ty = (v[MAT_TY] * y_scale) + y_bias;
- GLfloat sz = v[MAT_SZ] * depthScale;
- GLfloat tz = v[MAT_TZ] * depthScale;
-
- R600_STATECHANGE(context, vpt);
- R600_STATECHANGE(context, cl);
-
- r700->viewport[id].PA_CL_VPORT_XSCALE.f32All = sx;
- r700->viewport[id].PA_CL_VPORT_XOFFSET.f32All = tx;
-
- r700->viewport[id].PA_CL_VPORT_YSCALE.f32All = sy;
- r700->viewport[id].PA_CL_VPORT_YOFFSET.f32All = ty;
-
- r700->viewport[id].PA_CL_VPORT_ZSCALE.f32All = sz;
- r700->viewport[id].PA_CL_VPORT_ZOFFSET.f32All = tz;
-
- if (ctx->Transform.DepthClamp) {
- r700->viewport[id].PA_SC_VPORT_ZMIN_0.f32All = MIN2(ctx->Viewport.Near, ctx->Viewport.Far);
- r700->viewport[id].PA_SC_VPORT_ZMAX_0.f32All = MAX2(ctx->Viewport.Near, ctx->Viewport.Far);
- SETbit(r700->PA_CL_CLIP_CNTL.u32All, ZCLIP_NEAR_DISABLE_bit);
- SETbit(r700->PA_CL_CLIP_CNTL.u32All, ZCLIP_FAR_DISABLE_bit);
- } else {
- r700->viewport[id].PA_SC_VPORT_ZMIN_0.f32All = 0.0;
- r700->viewport[id].PA_SC_VPORT_ZMAX_0.f32All = 1.0;
- CLEARbit(r700->PA_CL_CLIP_CNTL.u32All, ZCLIP_NEAR_DISABLE_bit);
- CLEARbit(r700->PA_CL_CLIP_CNTL.u32All, ZCLIP_FAR_DISABLE_bit);
- }
-
- r700->viewport[id].enabled = GL_TRUE;
-
- r700SetScissor(context);
-}
-
-
-static void r700Viewport(struct gl_context * ctx,
- GLint x,
- GLint y,
- GLsizei width,
- GLsizei height) //--------------------
-{
- r700UpdateWindow(ctx, 0);
-
- radeon_viewport(ctx, x, y, width, height);
-}
-
-static void r700DepthRange(struct gl_context * ctx, GLclampd nearval, GLclampd farval) //-------------
-{
- r700UpdateWindow(ctx, 0);
-}
-
-static void r700LineWidth(struct gl_context * ctx, GLfloat widthf) //---------------
-{
- context_t *context = R700_CONTEXT(ctx);
- R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
- uint32_t lineWidth = (uint32_t)((widthf * 0.5) * (1 << 4));
-
- R600_STATECHANGE(context, su);
-
- if (lineWidth > 0xFFFF)
- lineWidth = 0xFFFF;
- SETfield(r700->PA_SU_LINE_CNTL.u32All,(uint16_t)lineWidth,
- PA_SU_LINE_CNTL__WIDTH_shift, PA_SU_LINE_CNTL__WIDTH_mask);
-}
-
-static void r700LineStipple(struct gl_context *ctx, GLint factor, GLushort pattern)
-{
- context_t *context = R700_CONTEXT(ctx);
- R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
-
- R600_STATECHANGE(context, sc);
-
- SETfield(r700->PA_SC_LINE_STIPPLE.u32All, pattern, LINE_PATTERN_shift, LINE_PATTERN_mask);
- SETfield(r700->PA_SC_LINE_STIPPLE.u32All, (factor-1), REPEAT_COUNT_shift, REPEAT_COUNT_mask);
- SETfield(r700->PA_SC_LINE_STIPPLE.u32All, 1, AUTO_RESET_CNTL_shift, AUTO_RESET_CNTL_mask);
-}
-
-static void r700SetPolygonOffsetState(struct gl_context * ctx, GLboolean state)
-{
- context_t *context = R700_CONTEXT(ctx);
- R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
-
- R600_STATECHANGE(context, su);
-
- if (state) {
- SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_FRONT_ENABLE_bit);
- SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_BACK_ENABLE_bit);
- SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_PARA_ENABLE_bit);
- } else {
- CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_FRONT_ENABLE_bit);
- CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_BACK_ENABLE_bit);
- CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_PARA_ENABLE_bit);
- }
-}
-
-static void r700PolygonOffset(struct gl_context * ctx, GLfloat factor, GLfloat units) //--------------
-{
- context_t *context = R700_CONTEXT(ctx);
- R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
- GLfloat constant = units;
- GLchar depth = 0;
-
- R600_STATECHANGE(context, poly);
-
- switch (ctx->Visual.depthBits) {
- case 16:
- constant *= 4.0;
- depth = -16;
- break;
- case 24:
- constant *= 2.0;
- depth = -24;
- break;
- }
-
- factor *= 12.0;
- SETfield(r700->PA_SU_POLY_OFFSET_DB_FMT_CNTL.u32All, depth,
- POLY_OFFSET_NEG_NUM_DB_BITS_shift, POLY_OFFSET_NEG_NUM_DB_BITS_mask);
- //r700->PA_SU_POLY_OFFSET_CLAMP.f32All = constant; //???
- r700->PA_SU_POLY_OFFSET_FRONT_SCALE.f32All = factor;
- r700->PA_SU_POLY_OFFSET_FRONT_OFFSET.f32All = constant;
- r700->PA_SU_POLY_OFFSET_BACK_SCALE.f32All = factor;
- r700->PA_SU_POLY_OFFSET_BACK_OFFSET.f32All = constant;
-}
-
-static void r700UpdatePolygonMode(struct gl_context * ctx)
-{
- context_t *context = R700_CONTEXT(ctx);
- R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
-
- R600_STATECHANGE(context, su);
-
- SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DISABLE_POLY_MODE, POLY_MODE_shift, POLY_MODE_mask);
-
- /* Only do something if a polygon mode is wanted, default is GL_FILL */
- if (ctx->Polygon.FrontMode != GL_FILL ||
- ctx->Polygon.BackMode != GL_FILL) {
- GLenum f, b;
-
- /* Handle GL_CW (clock wise and GL_CCW (counter clock wise)
- * correctly by selecting the correct front and back face
- */
- f = ctx->Polygon.FrontMode;
- b = ctx->Polygon.BackMode;
-
- /* Enable polygon mode */
- SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DUAL_MODE, POLY_MODE_shift, POLY_MODE_mask);
-
- switch (f) {
- case GL_LINE:
- SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_LINES,
- POLYMODE_FRONT_PTYPE_shift, POLYMODE_FRONT_PTYPE_mask);
- break;
- case GL_POINT:
- SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_POINTS,
- POLYMODE_FRONT_PTYPE_shift, POLYMODE_FRONT_PTYPE_mask);
- break;
- case GL_FILL:
- SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_TRIANGLES,
- POLYMODE_FRONT_PTYPE_shift, POLYMODE_FRONT_PTYPE_mask);
- break;
- }
-
- switch (b) {
- case GL_LINE:
- SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_LINES,
- POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask);
- break;
- case GL_POINT:
- SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_POINTS,
- POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask);
- break;
- case GL_FILL:
- SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_TRIANGLES,
- POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask);
- break;
- }
- }
-}
-
-static void r700PolygonMode(struct gl_context * ctx, GLenum face, GLenum mode) //------------------
-{
- (void)face;
- (void)mode;
-
- r700UpdatePolygonMode(ctx);
-}
-
-static void r700RenderMode(struct gl_context * ctx, GLenum mode) //---------------------
-{
-}
-
-static void r700ClipPlane( struct gl_context *ctx, GLenum plane, const GLfloat *eq )
-{
- context_t *context = R700_CONTEXT(ctx);
- R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
- GLint p;
- GLint *ip;
-
- p = (GLint) plane - (GLint) GL_CLIP_PLANE0;
- ip = (GLint *)ctx->Transform._ClipUserPlane[p];
-
- R600_STATECHANGE(context, ucp);
-
- r700->ucp[p].PA_CL_UCP_0_X.u32All = ip[0];
- r700->ucp[p].PA_CL_UCP_0_Y.u32All = ip[1];
- r700->ucp[p].PA_CL_UCP_0_Z.u32All = ip[2];
- r700->ucp[p].PA_CL_UCP_0_W.u32All = ip[3];
-}
-
-static void r700SetClipPlaneState(struct gl_context * ctx, GLenum cap, GLboolean state)
-{
- context_t *context = R700_CONTEXT(ctx);
- R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
- GLuint p;
-
- p = cap - GL_CLIP_PLANE0;
-
- R600_STATECHANGE(context, cl);
-
- if (state) {
- r700->PA_CL_CLIP_CNTL.u32All |= (UCP_ENA_0_bit << p);
- r700->ucp[p].enabled = GL_TRUE;
- r700ClipPlane(ctx, cap, NULL);
- } else {
- r700->PA_CL_CLIP_CNTL.u32All &= ~(UCP_ENA_0_bit << p);
- r700->ucp[p].enabled = GL_FALSE;
- }
-}
-
-void r700SetScissor(context_t *context) //---------------
-{
- R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
- unsigned x1, y1, x2, y2;
- int id = 0;
- struct radeon_renderbuffer *rrb;
-
- rrb = radeon_get_colorbuffer(&context->radeon);
- if (!rrb || !rrb->bo) {
- return;
- }
- if (context->radeon.state.scissor.enabled) {
- x1 = context->radeon.state.scissor.rect.x1;
- y1 = context->radeon.state.scissor.rect.y1;
- x2 = context->radeon.state.scissor.rect.x2;
- y2 = context->radeon.state.scissor.rect.y2;
- /* r600 has exclusive BR scissors */
- if (context->radeon.radeonScreen->kernel_mm) {
- x2++;
- y2++;
- }
- } else {
- if (context->radeon.radeonScreen->driScreen->dri2.enabled) {
- x1 = 0;
- y1 = 0;
- x2 = rrb->base.Width;
- y2 = rrb->base.Height;
- } else {
- x1 = rrb->dPriv->x;
- y1 = rrb->dPriv->y;
- x2 = rrb->dPriv->x + rrb->dPriv->w;
- y2 = rrb->dPriv->y + rrb->dPriv->h;
- }
- }
-
- R600_STATECHANGE(context, scissor);
-
- /* screen */
- SETbit(r700->PA_SC_SCREEN_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
- SETfield(r700->PA_SC_SCREEN_SCISSOR_TL.u32All, x1,
- PA_SC_SCREEN_SCISSOR_TL__TL_X_shift, PA_SC_SCREEN_SCISSOR_TL__TL_X_mask);
- SETfield(r700->PA_SC_SCREEN_SCISSOR_TL.u32All, y1,
- PA_SC_SCREEN_SCISSOR_TL__TL_Y_shift, PA_SC_SCREEN_SCISSOR_TL__TL_Y_mask);
-
- SETfield(r700->PA_SC_SCREEN_SCISSOR_BR.u32All, x2,
- PA_SC_SCREEN_SCISSOR_BR__BR_X_shift, PA_SC_SCREEN_SCISSOR_BR__BR_X_mask);
- SETfield(r700->PA_SC_SCREEN_SCISSOR_BR.u32All, y2,
- PA_SC_SCREEN_SCISSOR_BR__BR_Y_shift, PA_SC_SCREEN_SCISSOR_BR__BR_Y_mask);
-
- /* window */
- SETbit(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
- SETfield(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, x1,
- PA_SC_WINDOW_SCISSOR_TL__TL_X_shift, PA_SC_WINDOW_SCISSOR_TL__TL_X_mask);
- SETfield(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, y1,
- PA_SC_WINDOW_SCISSOR_TL__TL_Y_shift, PA_SC_WINDOW_SCISSOR_TL__TL_Y_mask);
-
- SETfield(r700->PA_SC_WINDOW_SCISSOR_BR.u32All, x2,
- PA_SC_WINDOW_SCISSOR_BR__BR_X_shift, PA_SC_WINDOW_SCISSOR_BR__BR_X_mask);
- SETfield(r700->PA_SC_WINDOW_SCISSOR_BR.u32All, y2,
- PA_SC_WINDOW_SCISSOR_BR__BR_Y_shift, PA_SC_WINDOW_SCISSOR_BR__BR_Y_mask);
-
-
- SETfield(r700->PA_SC_CLIPRECT_0_TL.u32All, x1,
- PA_SC_CLIPRECT_0_TL__TL_X_shift, PA_SC_CLIPRECT_0_TL__TL_X_mask);
- SETfield(r700->PA_SC_CLIPRECT_0_TL.u32All, y1,
- PA_SC_CLIPRECT_0_TL__TL_Y_shift, PA_SC_CLIPRECT_0_TL__TL_Y_mask);
- SETfield(r700->PA_SC_CLIPRECT_0_BR.u32All, x2,
- PA_SC_CLIPRECT_0_BR__BR_X_shift, PA_SC_CLIPRECT_0_BR__BR_X_mask);
- SETfield(r700->PA_SC_CLIPRECT_0_BR.u32All, y2,
- PA_SC_CLIPRECT_0_BR__BR_Y_shift, PA_SC_CLIPRECT_0_BR__BR_Y_mask);
-
- r700->PA_SC_CLIPRECT_1_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
- r700->PA_SC_CLIPRECT_1_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
- r700->PA_SC_CLIPRECT_2_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
- r700->PA_SC_CLIPRECT_2_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
- r700->PA_SC_CLIPRECT_3_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
- r700->PA_SC_CLIPRECT_3_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
-
- /* more....2d clip */
- SETbit(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
- SETfield(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, x1,
- PA_SC_GENERIC_SCISSOR_TL__TL_X_shift, PA_SC_GENERIC_SCISSOR_TL__TL_X_mask);
- SETfield(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, y1,
- PA_SC_GENERIC_SCISSOR_TL__TL_Y_shift, PA_SC_GENERIC_SCISSOR_TL__TL_Y_mask);
- SETfield(r700->PA_SC_GENERIC_SCISSOR_BR.u32All, x2,
- PA_SC_GENERIC_SCISSOR_BR__BR_X_shift, PA_SC_GENERIC_SCISSOR_BR__BR_X_mask);
- SETfield(r700->PA_SC_GENERIC_SCISSOR_BR.u32All, y2,
- PA_SC_GENERIC_SCISSOR_BR__BR_Y_shift, PA_SC_GENERIC_SCISSOR_BR__BR_Y_mask);
-
- SETbit(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
- SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, x1,
- PA_SC_VPORT_SCISSOR_0_TL__TL_X_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_X_mask);
- SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, y1,
- PA_SC_VPORT_SCISSOR_0_TL__TL_Y_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_Y_mask);
- SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All, x2,
- PA_SC_VPORT_SCISSOR_0_BR__BR_X_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_X_mask);
- SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All, y2,
- PA_SC_VPORT_SCISSOR_0_BR__BR_Y_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_Y_mask);
-
- r700->viewport[id].enabled = GL_TRUE;
-}
-
-static void r700InitSQConfig(struct gl_context * ctx)
-{
- context_t *context = R700_CONTEXT(ctx);
- R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
- int ps_prio;
- int vs_prio;
- int gs_prio;
- int es_prio;
- int num_ps_gprs;
- int num_vs_gprs;
- int num_gs_gprs;
- int num_es_gprs;
- int num_temp_gprs;
- int num_ps_threads;
- int num_vs_threads;
- int num_gs_threads;
- int num_es_threads;
- int num_ps_stack_entries;
- int num_vs_stack_entries;
- int num_gs_stack_entries;
- int num_es_stack_entries;
-
- R600_STATECHANGE(context, sq);
-
- // SQ
- ps_prio = 0;
- vs_prio = 1;
- gs_prio = 2;
- es_prio = 3;
- switch (context->radeon.radeonScreen->chip_family) {
- case CHIP_FAMILY_R600:
- num_ps_gprs = 192;
- num_vs_gprs = 56;
- num_temp_gprs = 4;
- num_gs_gprs = 0;
- num_es_gprs = 0;
- num_ps_threads = 136;
- num_vs_threads = 48;
- num_gs_threads = 4;
- num_es_threads = 4;
- num_ps_stack_entries = 128;
- num_vs_stack_entries = 128;
- num_gs_stack_entries = 0;
- num_es_stack_entries = 0;
- break;
- case CHIP_FAMILY_RV630:
- case CHIP_FAMILY_RV635:
- num_ps_gprs = 84;
- num_vs_gprs = 36;
- num_temp_gprs = 4;
- num_gs_gprs = 0;
- num_es_gprs = 0;
- num_ps_threads = 144;
- num_vs_threads = 40;
- num_gs_threads = 4;
- num_es_threads = 4;
- num_ps_stack_entries = 40;
- num_vs_stack_entries = 40;
- num_gs_stack_entries = 32;
- num_es_stack_entries = 16;
- break;
- case CHIP_FAMILY_RV610:
- case CHIP_FAMILY_RV620:
- case CHIP_FAMILY_RS780:
- case CHIP_FAMILY_RS880:
- default:
- num_ps_gprs = 84;
- num_vs_gprs = 36;
- num_temp_gprs = 4;
- num_gs_gprs = 0;
- num_es_gprs = 0;
- num_ps_threads = 136;
- num_vs_threads = 48;
- num_gs_threads = 4;
- num_es_threads = 4;
- num_ps_stack_entries = 40;
- num_vs_stack_entries = 40;
- num_gs_stack_entries = 32;
- num_es_stack_entries = 16;
- break;
- case CHIP_FAMILY_RV670:
- num_ps_gprs = 144;
- num_vs_gprs = 40;
- num_temp_gprs = 4;
- num_gs_gprs = 0;
- num_es_gprs = 0;
- num_ps_threads = 136;
- num_vs_threads = 48;
- num_gs_threads = 4;
- num_es_threads = 4;
- num_ps_stack_entries = 40;
- num_vs_stack_entries = 40;
- num_gs_stack_entries = 32;
- num_es_stack_entries = 16;
- break;
- case CHIP_FAMILY_RV770:
- num_ps_gprs = 192;
- num_vs_gprs = 56;
- num_temp_gprs = 4;
- num_gs_gprs = 0;
- num_es_gprs = 0;
- num_ps_threads = 188;
- num_vs_threads = 60;
- num_gs_threads = 0;
- num_es_threads = 0;
- num_ps_stack_entries = 256;
- num_vs_stack_entries = 256;
- num_gs_stack_entries = 0;
- num_es_stack_entries = 0;
- break;
- case CHIP_FAMILY_RV730:
- case CHIP_FAMILY_RV740:
- num_ps_gprs = 84;
- num_vs_gprs = 36;
- num_temp_gprs = 4;
- num_gs_gprs = 0;
- num_es_gprs = 0;
- num_ps_threads = 188;
- num_vs_threads = 60;
- num_gs_threads = 0;
- num_es_threads = 0;
- num_ps_stack_entries = 128;
- num_vs_stack_entries = 128;
- num_gs_stack_entries = 0;
- num_es_stack_entries = 0;
- break;
- case CHIP_FAMILY_RV710:
- num_ps_gprs = 192;
- num_vs_gprs = 56;
- num_temp_gprs = 4;
- num_gs_gprs = 0;
- num_es_gprs = 0;
- num_ps_threads = 144;
- num_vs_threads = 48;
- num_gs_threads = 0;
- num_es_threads = 0;
- num_ps_stack_entries = 128;
- num_vs_stack_entries = 128;
- num_gs_stack_entries = 0;
- num_es_stack_entries = 0;
- break;
- }
-
- r700->sq_config.SQ_CONFIG.u32All = 0;
- if ((context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV610) ||
- (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV620) ||
- (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS780) ||
- (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS880) ||
- (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV710))
- CLEARbit(r700->sq_config.SQ_CONFIG.u32All, VC_ENABLE_bit);
- else
- SETbit(r700->sq_config.SQ_CONFIG.u32All, VC_ENABLE_bit);
-
- if(GL_TRUE == r700->bShaderUseMemConstant)
- {
- CLEARbit(r700->sq_config.SQ_CONFIG.u32All, DX9_CONSTS_bit);
- }
- else
- {
- SETbit(r700->sq_config.SQ_CONFIG.u32All, DX9_CONSTS_bit);
- }
-
- SETbit(r700->sq_config.SQ_CONFIG.u32All, ALU_INST_PREFER_VECTOR_bit);
- SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, PS_PRIO_shift, PS_PRIO_mask);
- SETfield(r700->sq_config.SQ_CONFIG.u32All, vs_prio, VS_PRIO_shift, VS_PRIO_mask);
- SETfield(r700->sq_config.SQ_CONFIG.u32All, gs_prio, GS_PRIO_shift, GS_PRIO_mask);
- SETfield(r700->sq_config.SQ_CONFIG.u32All, es_prio, ES_PRIO_shift, ES_PRIO_mask);
-
- r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All = 0;
- SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All, num_ps_gprs, NUM_PS_GPRS_shift, NUM_PS_GPRS_mask);
- SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All, num_vs_gprs, NUM_VS_GPRS_shift, NUM_VS_GPRS_mask);
- SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All, num_temp_gprs,
- NUM_CLAUSE_TEMP_GPRS_shift, NUM_CLAUSE_TEMP_GPRS_mask);
-
- r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All = 0;
- SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All, num_gs_gprs, NUM_GS_GPRS_shift, NUM_GS_GPRS_mask);
- SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All, num_es_gprs, NUM_ES_GPRS_shift, NUM_ES_GPRS_mask);
-
- r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All = 0;
- SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_ps_threads,
- NUM_PS_THREADS_shift, NUM_PS_THREADS_mask);
- SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_vs_threads,
- NUM_VS_THREADS_shift, NUM_VS_THREADS_mask);
- SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_gs_threads,
- NUM_GS_THREADS_shift, NUM_GS_THREADS_mask);
- SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_es_threads,
- NUM_ES_THREADS_shift, NUM_ES_THREADS_mask);
-
- r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All = 0;
- SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All, num_ps_stack_entries,
- NUM_PS_STACK_ENTRIES_shift, NUM_PS_STACK_ENTRIES_mask);
- SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All, num_vs_stack_entries,
- NUM_VS_STACK_ENTRIES_shift, NUM_VS_STACK_ENTRIES_mask);
-
- r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All = 0;
- SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All, num_gs_stack_entries,
- NUM_GS_STACK_ENTRIES_shift, NUM_GS_STACK_ENTRIES_mask);
- SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All, num_es_stack_entries,
- NUM_ES_STACK_ENTRIES_shift, NUM_ES_STACK_ENTRIES_mask);
-
-}
-
-/**
- * Calculate initial hardware state and register state functions.
- * Assumes that the command buffer and state atoms have been
- * initialized already.
- */
-void r700InitState(struct gl_context * ctx) //-------------------
-{
- context_t *context = R700_CONTEXT(ctx);
- R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
- int id = 0;
-
- r700->TA_CNTL_AUX.u32All = 0;
- SETfield(r700->TA_CNTL_AUX.u32All, 28, TD_FIFO_CREDIT_shift, TD_FIFO_CREDIT_mask);
- r700->VC_ENHANCE.u32All = 0;
- r700->DB_WATERMARKS.u32All = 0;
- SETfield(r700->DB_WATERMARKS.u32All, 4, DEPTH_FREE_shift, DEPTH_FREE_mask);
- SETfield(r700->DB_WATERMARKS.u32All, 16, DEPTH_FLUSH_shift, DEPTH_FLUSH_mask);
- SETfield(r700->DB_WATERMARKS.u32All, 0, FORCE_SUMMARIZE_shift, FORCE_SUMMARIZE_mask);
- SETfield(r700->DB_WATERMARKS.u32All, 4, DEPTH_PENDING_FREE_shift, DEPTH_PENDING_FREE_mask);
- r700->SQ_DYN_GPR_CNTL_PS_FLUSH_REQ.u32All = 0;
- if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) {
- SETfield(r700->TA_CNTL_AUX.u32All, 3, GRADIENT_CREDIT_shift, GRADIENT_CREDIT_mask);
- r700->DB_DEBUG.u32All = 0x82000000;
- SETfield(r700->DB_WATERMARKS.u32All, 16, DEPTH_CACHELINE_FREE_shift, DEPTH_CACHELINE_FREE_mask);
- } else {
- SETfield(r700->TA_CNTL_AUX.u32All, 2, GRADIENT_CREDIT_shift, GRADIENT_CREDIT_mask);
- SETfield(r700->DB_WATERMARKS.u32All, 4, DEPTH_CACHELINE_FREE_shift, DEPTH_CACHELINE_FREE_mask);
- SETbit(r700->SQ_DYN_GPR_CNTL_PS_FLUSH_REQ.u32All, VS_PC_LIMIT_ENABLE_bit);
- }
-
- /* Turn off vgt reuse */
- r700->VGT_REUSE_OFF.u32All = 0;
- SETbit(r700->VGT_REUSE_OFF.u32All, REUSE_OFF_bit);
-
- /* Specify offsetting and clamp values for vertices */
- r700->VGT_MAX_VTX_INDX.u32All = 0xFFFFFF;
- r700->VGT_MIN_VTX_INDX.u32All = 0;
- r700->VGT_INDX_OFFSET.u32All = 0;
-
- /* default shader connections. */
- r700->SPI_VS_OUT_ID_0.u32All = 0x03020100;
- r700->SPI_VS_OUT_ID_1.u32All = 0x07060504;
- r700->SPI_VS_OUT_ID_2.u32All = 0x0b0a0908;
- r700->SPI_VS_OUT_ID_3.u32All = 0x0f0e0d0c;
-
- r700->SPI_THREAD_GROUPING.u32All = 0;
- if (context->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV770)
- SETfield(r700->SPI_THREAD_GROUPING.u32All, 1, PS_GROUPING_shift, PS_GROUPING_mask);
-
- /* 4 clip rectangles */ /* TODO : set these clip rects according to context->currentDraw->numClipRects */
- r700->PA_SC_CLIPRECT_RULE.u32All = 0;
- SETfield(r700->PA_SC_CLIPRECT_RULE.u32All, CLIP_RULE_mask, CLIP_RULE_shift, CLIP_RULE_mask);
-
- if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
- r700->PA_SC_EDGERULE.u32All = 0;
- else
- r700->PA_SC_EDGERULE.u32All = 0xAAAAAAAA;
-
- if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) {
- r700->PA_SC_MODE_CNTL.u32All = 0;
- SETbit(r700->PA_SC_MODE_CNTL.u32All, WALK_ORDER_ENABLE_bit);
- SETbit(r700->PA_SC_MODE_CNTL.u32All, FORCE_EOV_CNTDWN_ENABLE_bit);
- } else {
- r700->PA_SC_MODE_CNTL.u32All = 0x00500000;
- SETbit(r700->PA_SC_MODE_CNTL.u32All, FORCE_EOV_REZ_ENABLE_bit);
- SETbit(r700->PA_SC_MODE_CNTL.u32All, FORCE_EOV_CNTDWN_ENABLE_bit);
- }
-
- /* Do scale XY and Z by 1/W0. */
- r700->bEnablePerspective = GL_TRUE;
-
- CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
- CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
- SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
-
- /* Enable viewport scaling for all three axis */
- SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_X_SCALE_ENA_bit);
- SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_X_OFFSET_ENA_bit);
- SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Y_SCALE_ENA_bit);
- SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Y_OFFSET_ENA_bit);
- SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Z_SCALE_ENA_bit);
- SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Z_OFFSET_ENA_bit);
-
- /* GL uses last vtx for flat shading components */
- SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, PROVOKING_VTX_LAST_bit);
-
- /* Set up vertex control */
- r700->PA_SU_VTX_CNTL.u32All = 0;
- CLEARfield(r700->PA_SU_VTX_CNTL.u32All, QUANT_MODE_mask);
- SETbit(r700->PA_SU_VTX_CNTL.u32All, PIX_CENTER_bit);
- SETfield(r700->PA_SU_VTX_CNTL.u32All, X_ROUND_TO_EVEN,
- PA_SU_VTX_CNTL__ROUND_MODE_shift, PA_SU_VTX_CNTL__ROUND_MODE_mask);
-
- /* to 1.0 = no guard band */
- r700->PA_CL_GB_VERT_CLIP_ADJ.u32All = 0x3F800000; /* 1.0 */
- r700->PA_CL_GB_VERT_DISC_ADJ.u32All = 0x3F800000;
- r700->PA_CL_GB_HORZ_CLIP_ADJ.u32All = 0x3F800000;
- r700->PA_CL_GB_HORZ_DISC_ADJ.u32All = 0x3F800000;
-
- /* Enable all samples for multi-sample anti-aliasing */
- r700->PA_SC_AA_MASK.u32All = 0xFFFFFFFF;
- /* Turn off AA */
- r700->PA_SC_AA_CONFIG.u32All = 0;
-
- r700->SX_MISC.u32All = 0;
-
- r700InitSQConfig(ctx);
-
- r700ColorMask(ctx,
- ctx->Color.ColorMask[0][RCOMP],
- ctx->Color.ColorMask[0][GCOMP],
- ctx->Color.ColorMask[0][BCOMP],
- ctx->Color.ColorMask[0][ACOMP]);
-
- r700Enable(ctx, GL_DEPTH_TEST, ctx->Depth.Test);
- r700DepthMask(ctx, ctx->Depth.Mask);
- r700DepthFunc(ctx, ctx->Depth.Func);
- r700->DB_DEPTH_CLEAR.u32All = 0x3F800000;
- SETbit(r700->DB_RENDER_CONTROL.u32All, STENCIL_COMPRESS_DISABLE_bit);
- SETbit(r700->DB_RENDER_CONTROL.u32All, DEPTH_COMPRESS_DISABLE_bit);
- r700SetDBRenderState(ctx);
-
- r700->DB_ALPHA_TO_MASK.u32All = 0;
- SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET0_shift, ALPHA_TO_MASK_OFFSET0_mask);
- SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET1_shift, ALPHA_TO_MASK_OFFSET1_mask);
- SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET2_shift, ALPHA_TO_MASK_OFFSET2_mask);
- SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET3_shift, ALPHA_TO_MASK_OFFSET3_mask);
-
- /* stencil */
- r700Enable(ctx, GL_STENCIL_TEST, ctx->Stencil._Enabled);
- r700StencilMaskSeparate(ctx, 0, ctx->Stencil.WriteMask[0]);
- r700StencilFuncSeparate(ctx, 0, ctx->Stencil.Function[0],
- ctx->Stencil.Ref[0], ctx->Stencil.ValueMask[0]);
- r700StencilOpSeparate(ctx, 0, ctx->Stencil.FailFunc[0],
- ctx->Stencil.ZFailFunc[0],
- ctx->Stencil.ZPassFunc[0]);
-
- r700UpdateCulling(ctx);
-
- r700SetBlendState(ctx);
- r700SetLogicOpState(ctx);
-
- r700AlphaFunc(ctx, ctx->Color.AlphaFunc, ctx->Color.AlphaRef);
- r700Enable(ctx, GL_ALPHA_TEST, ctx->Color.AlphaEnabled);
-
- r700PointSize(ctx, 1.0);
-
- CLEARfield(r700->PA_SU_POINT_MINMAX.u32All, MIN_SIZE_mask);
- SETfield(r700->PA_SU_POINT_MINMAX.u32All, 0x8000, MAX_SIZE_shift, MAX_SIZE_mask);
-
- r700LineWidth(ctx, 1.0);
-
- r700->PA_SC_LINE_CNTL.u32All = 0;
- CLEARbit(r700->PA_SC_LINE_CNTL.u32All, EXPAND_LINE_WIDTH_bit);
- SETbit(r700->PA_SC_LINE_CNTL.u32All, LAST_PIXEL_bit);
-
- r700ShadeModel(ctx, ctx->Light.ShadeModel);
- r700PolygonMode(ctx, GL_FRONT, ctx->Polygon.FrontMode);
- r700PolygonMode(ctx, GL_BACK, ctx->Polygon.BackMode);
- r700PolygonOffset(ctx, ctx->Polygon.OffsetFactor,
- ctx->Polygon.OffsetUnits);
- r700Enable(ctx, GL_POLYGON_OFFSET_POINT, ctx->Polygon.OffsetPoint);
- r700Enable(ctx, GL_POLYGON_OFFSET_LINE, ctx->Polygon.OffsetLine);
- r700Enable(ctx, GL_POLYGON_OFFSET_FILL, ctx->Polygon.OffsetFill);
-
- /* CB */
- r700BlendColor(ctx, ctx->Color.BlendColor);
-
- r700->CB_CLEAR_RED_R6XX.f32All = 1.0; //r6xx only
- r700->CB_CLEAR_GREEN_R6XX.f32All = 0.0; //r6xx only
- r700->CB_CLEAR_BLUE_R6XX.f32All = 1.0; //r6xx only
- r700->CB_CLEAR_ALPHA_R6XX.f32All = 1.0; //r6xx only
- r700->CB_FOG_RED_R6XX.u32All = 0; //r6xx only
- r700->CB_FOG_GREEN_R6XX.u32All = 0; //r6xx only
- r700->CB_FOG_BLUE_R6XX.u32All = 0; //r6xx only
-
- /* Disable color compares */
- SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_DRAW_ALWAYS,
- CLRCMP_FCN_SRC_shift, CLRCMP_FCN_SRC_mask);
- SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_DRAW_ALWAYS,
- CLRCMP_FCN_DST_shift, CLRCMP_FCN_DST_mask);
- SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_SEL_SRC,
- CLRCMP_FCN_SEL_shift, CLRCMP_FCN_SEL_mask);
-
- /* Zero out source */
- r700->CB_CLRCMP_SRC.u32All = 0x00000000;
-
- /* Put a compare color in for error checking */
- r700->CB_CLRCMP_DST.u32All = 0x000000FF;
-
- /* Set up color compare mask */
- r700->CB_CLRCMP_MSK.u32All = 0xFFFFFFFF;
-
- /* screen/window/view */
- SETfield(r700->CB_SHADER_MASK.u32All, 0xF, (4 * id), OUTPUT0_ENABLE_mask);
-
- context->radeon.hw.all_dirty = GL_TRUE;
-
-}
-
-void r700InitStateFuncs(radeonContextPtr radeon, struct dd_function_table *functions)
-{
- functions->UpdateState = r700InvalidateState;
- functions->AlphaFunc = r700AlphaFunc;
- functions->BlendColor = r700BlendColor;
- functions->BlendEquationSeparate = r700BlendEquationSeparate;
- functions->BlendFuncSeparate = r700BlendFuncSeparate;
- functions->Enable = r700Enable;
- functions->ColorMask = r700ColorMask;
- functions->DepthFunc = r700DepthFunc;
- functions->DepthMask = r700DepthMask;
- functions->CullFace = r700CullFace;
- functions->Fogfv = r700Fogfv;
- functions->FrontFace = r700FrontFace;
- functions->ShadeModel = r700ShadeModel;
- functions->LogicOpcode = r700LogicOpcode;
-
- /* ARB_point_parameters */
- functions->PointParameterfv = r700PointParameter;
-
- /* Stencil related */
- functions->StencilFuncSeparate = r700StencilFuncSeparate;
- functions->StencilMaskSeparate = r700StencilMaskSeparate;
- functions->StencilOpSeparate = r700StencilOpSeparate;
-
- /* Viewport related */
- functions->Viewport = r700Viewport;
- functions->DepthRange = r700DepthRange;
- functions->PointSize = r700PointSize;
- functions->LineWidth = r700LineWidth;
- functions->LineStipple = r700LineStipple;
-
- functions->PolygonOffset = r700PolygonOffset;
- functions->PolygonMode = r700PolygonMode;
-
- functions->RenderMode = r700RenderMode;
-
- functions->ClipPlane = r700ClipPlane;
-
- functions->Scissor = radeonScissor;
-
- functions->DrawBuffer = radeonDrawBuffer;
- functions->ReadBuffer = radeonReadBuffer;
-
- functions->CopyPixels = _mesa_meta_CopyPixels;
- functions->DrawPixels = _mesa_meta_DrawPixels;
- if (radeon->radeonScreen->kernel_mm)
- functions->ReadPixels = radeonReadPixels;
-}
-
+++ /dev/null
-/*
- * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Authors:
- * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
- */
-
-#ifndef _R700_STATE_H
-#define _R700_STATE_H
-
-#include "main/mtypes.h"
-
-#include "r600_context.h"
-
-#include "r700_chip.h"
-
-extern void r700UpdateStateParameters(struct gl_context * ctx, GLuint new_state);
-extern void r700UpdateShaders (struct gl_context * ctx);
-extern void r700UpdateShaderStates(struct gl_context * ctx);
-
-extern void r700UpdateViewportOffset(struct gl_context * ctx);
-
-extern void r700InitState (struct gl_context * ctx);
-extern void r700InitStateFuncs (radeonContextPtr radeon, struct dd_function_table *functions);
-
-extern void r700SetScissor(context_t *context);
-
-#endif /* _R600_SCREEN_H */
+++ /dev/null
-/*
- * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Authors:
- * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
- */
-
-
-#include <stdio.h>
-#include <stdarg.h>
-#include <stdlib.h>
-#include <string.h>
-#include <math.h>
-
-#include "main/imports.h"
-#include "main/mtypes.h"
-
-#include "tnl/t_context.h"
-#include "program/program.h"
-#include "program/prog_parameter.h"
-#include "program/prog_statevars.h"
-
-#include "radeon_debug.h"
-#include "r600_context.h"
-#include "r600_cmdbuf.h"
-#include "r600_emit.h"
-#include "program/programopt.h"
-
-#include "r700_debug.h"
-#include "r700_vertprog.h"
-
-unsigned int Map_Vertex_Output(r700_AssemblerBase *pAsm,
- struct gl_vertex_program *mesa_vp,
- unsigned int unStart)
-{
- unsigned int i;
- unsigned int unBit;
- unsigned int unTotal = unStart;
-
- //!!!!!!! THE ORDER MATCH FS INPUT
-
- unBit = 1 << VERT_RESULT_HPOS;
- if(mesa_vp->Base.OutputsWritten & unBit)
- {
- pAsm->ucVP_OutputMap[VERT_RESULT_HPOS] = unTotal++;
- }
-
- unBit = 1 << VERT_RESULT_COL0;
- if(mesa_vp->Base.OutputsWritten & unBit)
- {
- pAsm->ucVP_OutputMap[VERT_RESULT_COL0] = unTotal++;
- }
-
- unBit = 1 << VERT_RESULT_COL1;
- if(mesa_vp->Base.OutputsWritten & unBit)
- {
- pAsm->ucVP_OutputMap[VERT_RESULT_COL1] = unTotal++;
- }
-
- //TODO : dealing back face.
- unBit = 1 << VERT_RESULT_BFC0;
- if(mesa_vp->Base.OutputsWritten & unBit)
- {
- pAsm->ucVP_OutputMap[VERT_RESULT_BFC0] = unTotal++;
- }
-
- unBit = 1 << VERT_RESULT_BFC1;
- if(mesa_vp->Base.OutputsWritten & unBit)
- {
- pAsm->ucVP_OutputMap[VERT_RESULT_BFC1] = unTotal++;
- }
-
- //TODO : dealing fog.
- unBit = 1 << VERT_RESULT_FOGC;
- if(mesa_vp->Base.OutputsWritten & unBit)
- {
- pAsm->ucVP_OutputMap[VERT_RESULT_FOGC] = unTotal++;
- }
-
- //TODO : dealing point size.
- unBit = 1 << VERT_RESULT_PSIZ;
- if(mesa_vp->Base.OutputsWritten & unBit)
- {
- pAsm->ucVP_OutputMap[VERT_RESULT_PSIZ] = unTotal++;
- }
-
- for(i=0; i<8; i++)
- {
- unBit = 1 << (VERT_RESULT_TEX0 + i);
- if(mesa_vp->Base.OutputsWritten & unBit)
- {
- pAsm->ucVP_OutputMap[VERT_RESULT_TEX0 + i] = unTotal++;
- }
- }
-
- for(i=VERT_RESULT_VAR0; i<VERT_RESULT_MAX; i++)
- {
- unBit = 1 << i;
- if(mesa_vp->Base.OutputsWritten & unBit)
- {
- pAsm->ucVP_OutputMap[i] = unTotal++;
- }
- }
-
- return (unTotal - unStart);
-}
-
-unsigned int Map_Vertex_Input(r700_AssemblerBase *pAsm,
- struct gl_vertex_program *mesa_vp,
- unsigned int unStart)
-{
- int i;
- unsigned int unBit;
- unsigned int unTotal = unStart;
- for(i=0; i<VERT_ATTRIB_MAX; i++)
- {
- unBit = 1 << i;
- if(mesa_vp->Base.InputsRead & unBit)
- {
- pAsm->ucVP_AttributeMap[i] = unTotal++;
- }
- }
- return (unTotal - unStart);
-}
-
-GLboolean Process_Vertex_Program_Vfetch_Instructions(
- struct r700_vertex_program *vp,
- struct gl_vertex_program *mesa_vp)
-{
- int i;
- unsigned int unBit;
- VTX_FETCH_METHOD vtxFetchMethod;
- vtxFetchMethod.bEnableMini = GL_FALSE;
- vtxFetchMethod.mega_fetch_remainder = 0;
-
- for(i=0; i<VERT_ATTRIB_MAX; i++)
- {
- unBit = 1 << i;
- if(mesa_vp->Base.InputsRead & unBit)
- {
- assemble_vfetch_instruction(&vp->r700AsmCode,
- i,
- vp->r700AsmCode.ucVP_AttributeMap[i],
- vp->aos_desc[i].size,
- vp->aos_desc[i].type,
- &vtxFetchMethod);
- }
- }
-
- return GL_TRUE;
-}
-
-GLboolean Process_Vertex_Program_Vfetch_Instructions2(
- struct gl_context *ctx,
- struct r700_vertex_program *vp,
- struct gl_vertex_program *mesa_vp)
-{
- int i;
- context_t *context = R700_CONTEXT(ctx);
-
- VTX_FETCH_METHOD vtxFetchMethod;
- vtxFetchMethod.bEnableMini = GL_FALSE;
- vtxFetchMethod.mega_fetch_remainder = 0;
-
- for(i=0; i<context->nNumActiveAos; i++)
- {
- assemble_vfetch_instruction2(&vp->r700AsmCode,
- vp->r700AsmCode.ucVP_AttributeMap[context->stream_desc[i].element],
- context->stream_desc[i].type,
- context->stream_desc[i].size,
- context->stream_desc[i].element,
- context->stream_desc[i]._signed,
- context->stream_desc[i].normalize,
- context->stream_desc[i].format,
- &vtxFetchMethod);
- }
-
- return GL_TRUE;
-}
-
-void Map_Vertex_Program(struct gl_context *ctx,
- struct r700_vertex_program *vp,
- struct gl_vertex_program *mesa_vp)
-{
- r700_AssemblerBase *pAsm = &(vp->r700AsmCode);
- unsigned int num_inputs;
-
- // R0 will always be used for index into vertex buffer
- pAsm->number_used_registers = 1;
- pAsm->starting_vfetch_register_number = pAsm->number_used_registers;
-
- // Map Inputs: Add 1 to mapping since R0 is used for index
- num_inputs = Map_Vertex_Input(pAsm, mesa_vp, pAsm->number_used_registers);
- pAsm->number_used_registers += num_inputs;
-
- // Create VFETCH instructions for inputs
- if (GL_TRUE != Process_Vertex_Program_Vfetch_Instructions2(ctx, vp, mesa_vp) )
- {
- radeon_error("Calling Process_Vertex_Program_Vfetch_Instructions2 return error. \n");
- return;
- }
-
- // Map Outputs
- pAsm->number_of_exports = Map_Vertex_Output(pAsm, mesa_vp, pAsm->number_used_registers);
-
- pAsm->starting_export_register_number = pAsm->number_used_registers;
-
- pAsm->number_used_registers += pAsm->number_of_exports;
-
- /* Map temporary registers (GPRs) */
- pAsm->starting_temp_register_number = pAsm->number_used_registers;
-
- if(mesa_vp->Base.NumNativeTemporaries >= mesa_vp->Base.NumTemporaries)
- { /* arb uses NumNativeTemporaries */
- pAsm->number_used_registers += mesa_vp->Base.NumNativeTemporaries;
- }
- else
- { /* fix func t_vp uses NumTemporaries */
- pAsm->number_used_registers += mesa_vp->Base.NumTemporaries;
- }
-
- pAsm->flag_reg_index = pAsm->number_used_registers++;
-
- pAsm->uFirstHelpReg = pAsm->number_used_registers;
-}
-
-GLboolean Find_Instruction_Dependencies_vp(struct r700_vertex_program *vp,
- struct gl_vertex_program *mesa_vp)
-{
- GLuint i, j;
- GLint * puiTEMPwrites;
- struct prog_instruction *pILInst;
- InstDeps *pInstDeps;
-
- puiTEMPwrites = (GLint*) MALLOC(sizeof(GLuint)*mesa_vp->Base.NumTemporaries);
- for(i=0; i<mesa_vp->Base.NumTemporaries; i++)
- {
- puiTEMPwrites[i] = -1;
- }
-
- pInstDeps = (InstDeps*)MALLOC(sizeof(InstDeps)*mesa_vp->Base.NumInstructions);
-
- for(i=0; i<mesa_vp->Base.NumInstructions; i++)
- {
- pInstDeps[i].nDstDep = -1;
- pILInst = &(mesa_vp->Base.Instructions[i]);
-
- //Dst
- if(pILInst->DstReg.File == PROGRAM_TEMPORARY)
- {
- //Set lastwrite for the temp
- puiTEMPwrites[pILInst->DstReg.Index] = i;
- }
-
- //Src
- for(j=0; j<3; j++)
- {
- if(pILInst->SrcReg[j].File == PROGRAM_TEMPORARY)
- {
- //Set dep.
- pInstDeps[i].nSrcDeps[j] = puiTEMPwrites[pILInst->SrcReg[j].Index];
- }
- else
- {
- pInstDeps[i].nSrcDeps[j] = -1;
- }
- }
- }
-
- vp->r700AsmCode.pInstDeps = pInstDeps;
-
- FREE(puiTEMPwrites);
-
- return GL_TRUE;
-}
-
-struct r700_vertex_program* r700TranslateVertexShader(struct gl_context *ctx,
- struct gl_vertex_program *mesa_vp)
-{
- context_t *context = R700_CONTEXT(ctx);
-
- R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
-
- struct r700_vertex_program *vp;
- unsigned int i;
-
- vp = calloc(1, sizeof(*vp));
- vp->mesa_program = _mesa_clone_vertex_program(ctx, mesa_vp);
-
- vp->constbo0 = NULL;
-
- if (mesa_vp->IsPositionInvariant)
- {
- _mesa_insert_mvp_code(ctx, vp->mesa_program);
- }
-
- for(i=0; i<context->nNumActiveAos; i++)
- {
- vp->aos_desc[i].size = context->stream_desc[i].size;
- vp->aos_desc[i].stride = context->stream_desc[i].stride;
- vp->aos_desc[i].type = context->stream_desc[i].type;
- vp->aos_desc[i].format = context->stream_desc[i].format;
- }
-
- if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
- {
- vp->r700AsmCode.bR6xx = 1;
- }
-
- //Init_Program
- Init_r700_AssemblerBase(SPT_VP, &(vp->r700AsmCode), &(vp->r700Shader) );
-
- if(GL_TRUE == r700->bShaderUseMemConstant)
- {
- vp->r700AsmCode.bUseMemConstant = GL_TRUE;
- }
- else
- {
- vp->r700AsmCode.bUseMemConstant = GL_FALSE;
- }
-
- vp->r700AsmCode.unAsic = 7;
-
- Map_Vertex_Program(ctx, vp, vp->mesa_program );
-
- if(GL_FALSE == Find_Instruction_Dependencies_vp(vp, vp->mesa_program))
- {
- return NULL;
- }
-
- InitShaderProgram(&(vp->r700AsmCode));
-
- for(i=0; i < MAX_SAMPLERS; i++)
- {
- vp->r700AsmCode.SamplerUnits[i] = vp->mesa_program->Base.SamplerUnits[i];
- }
-
- vp->r700AsmCode.unCurNumILInsts = vp->mesa_program->Base.NumInstructions;
-
- if(GL_FALSE == AssembleInstr(0,
- 0,
- vp->mesa_program->Base.NumInstructions,
- &(vp->mesa_program->Base.Instructions[0]),
- &(vp->r700AsmCode)) )
- {
- return NULL;
- }
-
- if(GL_FALSE == Process_Vertex_Exports(&(vp->r700AsmCode), vp->mesa_program->Base.OutputsWritten) )
- {
- return NULL;
- }
-
- if( GL_FALSE == RelocProgram(&(vp->r700AsmCode), &(vp->mesa_program->Base)) )
- {
- return GL_FALSE;
- }
-
- vp->r700Shader.nRegs = (vp->r700AsmCode.number_used_registers == 0) ? 0
- : (vp->r700AsmCode.number_used_registers - 1);
-
- vp->r700Shader.nParamExports = vp->r700AsmCode.number_of_exports;
-
- vp->translated = GL_TRUE;
-
- return vp;
-}
-
-void r700SelectVertexShader(struct gl_context *ctx)
-{
- context_t *context = R700_CONTEXT(ctx);
- struct r700_vertex_program_cont *vpc;
- struct r700_vertex_program *vp;
- unsigned int i;
- GLboolean match;
- GLbitfield InputsRead;
-
- vpc = (struct r700_vertex_program_cont *)ctx->VertexProgram._Current;
-
- InputsRead = vpc->mesa_program.Base.InputsRead;
- if (vpc->mesa_program.IsPositionInvariant)
- {
- InputsRead |= VERT_BIT_POS;
- }
-
- for (vp = vpc->progs; vp; vp = vp->next)
- {
- match = GL_TRUE;
- for(i=0; i<context->nNumActiveAos; i++)
- {
- if (vp->aos_desc[i].size != context->stream_desc[i].size ||
- vp->aos_desc[i].format != context->stream_desc[i].format)
- {
- match = GL_FALSE;
- break;
- }
- }
- if (match)
- {
- context->selected_vp = vp;
- return;
- }
- }
-
- vp = r700TranslateVertexShader(ctx, &(vpc->mesa_program));
- if(!vp)
- {
- radeon_error("Failed to translate vertex shader. \n");
- return;
- }
- vp->next = vpc->progs;
- vpc->progs = vp;
- context->selected_vp = vp;
- return;
-}
-
-int getTypeSize(GLenum type)
-{
- switch (type)
- {
- case GL_DOUBLE:
- return sizeof(GLdouble);
- case GL_FLOAT:
- return sizeof(GLfloat);
- case GL_INT:
- return sizeof(GLint);
- case GL_UNSIGNED_INT:
- return sizeof(GLuint);
- case GL_SHORT:
- return sizeof(GLshort);
- case GL_UNSIGNED_SHORT:
- return sizeof(GLushort);
- case GL_BYTE:
- return sizeof(GLbyte);
- case GL_UNSIGNED_BYTE:
- return sizeof(GLubyte);
- default:
- assert(0);
- return 0;
- }
-}
-
-static void r700TranslateAttrib(struct gl_context *ctx, GLuint unLoc, int count, const struct gl_client_array *input)
-{
- context_t *context = R700_CONTEXT(ctx);
-
- StreamDesc * pStreamDesc = &(context->stream_desc[context->nNumActiveAos]);
-
- GLuint stride;
-
- stride = (input->StrideB == 0) ? getTypeSize(input->Type) * input->Size
- : input->StrideB;
-
- if (input->Type == GL_DOUBLE || input->Type == GL_UNSIGNED_INT || input->Type == GL_INT
-#if MESA_BIG_ENDIAN
- || getTypeSize(input->Type) != 4
-#endif
- )
- {
- pStreamDesc->type = GL_FLOAT;
-
- if (input->StrideB == 0)
- {
- pStreamDesc->stride = 0;
- }
- else
- {
- pStreamDesc->stride = sizeof(GLfloat) * input->Size;
- }
- pStreamDesc->dwords = input->Size;
- pStreamDesc->is_named_bo = GL_FALSE;
- }
- else
- {
- pStreamDesc->type = input->Type;
- pStreamDesc->dwords = (getTypeSize(input->Type) * input->Size + 3)/ 4;
- if (!input->BufferObj->Name)
- {
- if (input->StrideB == 0)
- {
- pStreamDesc->stride = 0;
- }
- else
- {
- pStreamDesc->stride = (getTypeSize(pStreamDesc->type) * input->Size + 3) & ~3;
- }
-
- pStreamDesc->is_named_bo = GL_FALSE;
- }
- }
-
- pStreamDesc->size = input->Size;
- pStreamDesc->dst_loc = context->nNumActiveAos;
- pStreamDesc->element = unLoc;
- pStreamDesc->format = input->Format;
-
- switch (pStreamDesc->type)
- { //GetSurfaceFormat
- case GL_FLOAT:
- pStreamDesc->_signed = 0;
- pStreamDesc->normalize = GL_FALSE;
- break;
- case GL_SHORT:
- pStreamDesc->_signed = 1;
- pStreamDesc->normalize = input->Normalized;
- break;
- case GL_BYTE:
- pStreamDesc->_signed = 1;
- pStreamDesc->normalize = input->Normalized;
- break;
- case GL_UNSIGNED_SHORT:
- pStreamDesc->_signed = 0;
- pStreamDesc->normalize = input->Normalized;
- break;
- case GL_UNSIGNED_BYTE:
- pStreamDesc->_signed = 0;
- pStreamDesc->normalize = input->Normalized;
- break;
- default:
- case GL_INT:
- case GL_UNSIGNED_INT:
- case GL_DOUBLE:
- assert(0);
- break;
- }
- context->nNumActiveAos++;
-}
-
-void r700SetVertexFormat(struct gl_context *ctx, const struct gl_client_array *arrays[], int count)
-{
- context_t *context = R700_CONTEXT(ctx);
- struct r700_vertex_program *vpc
- = (struct r700_vertex_program *)ctx->VertexProgram._Current;
-
- struct gl_vertex_program * mesa_vp = (struct gl_vertex_program *)&(vpc->mesa_program);
- unsigned int unLoc = 0;
- unsigned int unBit = mesa_vp->Base.InputsRead;
- context->nNumActiveAos = 0;
-
- if (mesa_vp->IsPositionInvariant)
- {
- unBit |= VERT_BIT_POS;
- }
-
- while(unBit)
- {
- if(unBit & 1)
- {
- r700TranslateAttrib(ctx, unLoc, count, arrays[unLoc]);
- }
-
- unBit >>= 1;
- ++unLoc;
- }
- context->radeon.tcl.aos_count = context->nNumActiveAos;
-}
-
-void * r700GetActiveVpShaderBo(struct gl_context * ctx)
-{
- context_t *context = R700_CONTEXT(ctx);
- struct r700_vertex_program *vp = context->selected_vp;;
-
- if (vp)
- return vp->shaderbo;
- else
- return NULL;
-}
-
-void * r700GetActiveVpShaderConstBo(struct gl_context * ctx)
-{
- context_t *context = R700_CONTEXT(ctx);
- struct r700_vertex_program *vp = context->selected_vp;;
-
- if (vp)
- return vp->constbo0;
- else
- return NULL;
-}
-
-GLboolean r700SetupVertexProgram(struct gl_context * ctx)
-{
- context_t *context = R700_CONTEXT(ctx);
- R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
- struct r700_vertex_program *vp = context->selected_vp;
-
- struct gl_program_parameter_list *paramList;
- unsigned int unNumParamData;
- unsigned int ui;
- unsigned int num_sq_vs_gprs;
-
- if(GL_FALSE == vp->loaded)
- {
- if(vp->r700Shader.bNeedsAssembly == GL_TRUE)
- {
- Assemble( &(vp->r700Shader) );
- }
-
- /* Load vp to gpu */
- r600EmitShader(ctx,
- &(vp->shaderbo),
- (GLvoid *)(vp->r700Shader.pProgram),
- vp->r700Shader.uShaderBinaryDWORDSize,
- "VS");
-
- if(GL_TRUE == r700->bShaderUseMemConstant)
- {
- paramList = vp->mesa_program->Base.Parameters;
- if(NULL != paramList)
- {
- unNumParamData = paramList->NumParameters;
- r600AllocShaderConsts(ctx,
- &(vp->constbo0),
- unNumParamData *4*4,
- "VSCON");
- }
- }
-
- vp->loaded = GL_TRUE;
- }
-
- DumpHwBinary(DUMP_VERTEX_SHADER, (GLvoid *)(vp->r700Shader.pProgram),
- vp->r700Shader.uShaderBinaryDWORDSize);
-
- /* TODO : enable this after MemUse fixed *=
- (context->chipobj.MemUse)(context, vp->shadercode.buf->id);
- */
-
- R600_STATECHANGE(context, vs);
- R600_STATECHANGE(context, fs); /* hack */
-
- r700->vs.SQ_PGM_RESOURCES_VS.u32All = 0;
- SETbit(r700->vs.SQ_PGM_RESOURCES_VS.u32All, PGM_RESOURCES__PRIME_CACHE_ON_DRAW_bit);
-
- r700->vs.SQ_ALU_CONST_CACHE_VS_0.u32All = 0; /* set from buffer object. */
-
- r700->vs.SQ_PGM_START_VS.u32All = 0;
-
- SETfield(r700->vs.SQ_PGM_RESOURCES_VS.u32All, vp->r700Shader.nRegs + 1,
- NUM_GPRS_shift, NUM_GPRS_mask);
-
- num_sq_vs_gprs = ((r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All & NUM_VS_GPRS_mask) >> NUM_VS_GPRS_shift);
-
- if((vp->r700Shader.nRegs + 1) > num_sq_vs_gprs)
- {
- /* care! thich changes sq - needs idle state */
- R600_STATECHANGE(context, sq);
- SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All, vp->r700Shader.nRegs + 1,
- NUM_VS_GPRS_shift, NUM_VS_GPRS_mask);
- }
-
- if(vp->r700Shader.uStackSize) /* we don't use branch for now, it should be zero. */
- {
- SETfield(r700->vs.SQ_PGM_RESOURCES_VS.u32All, vp->r700Shader.uStackSize,
- STACK_SIZE_shift, STACK_SIZE_mask);
- }
-
- R600_STATECHANGE(context, spi);
-
- if(vp->mesa_program->Base.OutputsWritten & (1 << VERT_RESULT_PSIZ)) {
- R600_STATECHANGE(context, cl);
- SETbit(r700->PA_CL_VS_OUT_CNTL.u32All, USE_VTX_POINT_SIZE_bit);
- SETbit(r700->PA_CL_VS_OUT_CNTL.u32All, VS_OUT_MISC_VEC_ENA_bit);
- } else if (r700->PA_CL_VS_OUT_CNTL.u32All != 0) {
- R600_STATECHANGE(context, cl);
- CLEARbit(r700->PA_CL_VS_OUT_CNTL.u32All, USE_VTX_POINT_SIZE_bit);
- CLEARbit(r700->PA_CL_VS_OUT_CNTL.u32All, VS_OUT_MISC_VEC_ENA_bit);
- }
-
- SETfield(r700->SPI_VS_OUT_CONFIG.u32All,
- vp->r700Shader.nParamExports ? (vp->r700Shader.nParamExports - 1) : 0,
- VS_EXPORT_COUNT_shift, VS_EXPORT_COUNT_mask);
- SETfield(r700->SPI_PS_IN_CONTROL_0.u32All, vp->r700Shader.nParamExports,
- NUM_INTERP_shift, NUM_INTERP_mask);
-
- /*
- SETbit(r700->SPI_PS_IN_CONTROL_0.u32All, PERSP_GRADIENT_ENA_bit);
- CLEARbit(r700->SPI_PS_IN_CONTROL_0.u32All, LINEAR_GRADIENT_ENA_bit);
- */
-
- /* sent out shader constants. */
- paramList = vp->mesa_program->Base.Parameters;
-
- if(NULL != paramList) {
- /* vp->mesa_program was cloned, not updated by glsl shader api. */
- /* _mesa_reference_program has already checked glsl shProg is ok and set ctx->VertexProgem._Current */
- /* so, use ctx->VertexProgem._Current */
- struct gl_program_parameter_list *paramListOrginal =
- ctx->VertexProgram._Current->Base.Parameters;
-
- _mesa_load_state_parameters(ctx, paramList);
-
- if (paramList->NumParameters > R700_MAX_DX9_CONSTS)
- return GL_FALSE;
-
- R600_STATECHANGE(context, vs_consts);
-
- r700->vs.num_consts = paramList->NumParameters;
-
- unNumParamData = paramList->NumParameters;
-
- for(ui=0; ui<unNumParamData; ui++) {
- if(paramList->Parameters[ui].Type == PROGRAM_UNIFORM)
- {
- r700->vs.consts[ui][0].f32All = paramListOrginal->ParameterValues[ui][0].f;
- r700->vs.consts[ui][1].f32All = paramListOrginal->ParameterValues[ui][1].f;
- r700->vs.consts[ui][2].f32All = paramListOrginal->ParameterValues[ui][2].f;
- r700->vs.consts[ui][3].f32All = paramListOrginal->ParameterValues[ui][3].f;
- }
- else
- {
- r700->vs.consts[ui][0].f32All = paramList->ParameterValues[ui][0].f;
- r700->vs.consts[ui][1].f32All = paramList->ParameterValues[ui][1].f;
- r700->vs.consts[ui][2].f32All = paramList->ParameterValues[ui][2].f;
- r700->vs.consts[ui][3].f32All = paramList->ParameterValues[ui][3].f;
- }
- }
-
- /* Load vp constants to gpu */
- if(GL_TRUE == r700->bShaderUseMemConstant)
- {
- r600EmitShaderConsts(ctx,
- vp->constbo0,
- 0,
- (GLvoid *)&(r700->vs.consts[0][0]),
- unNumParamData * 4 * 4);
- }
- } else
- r700->vs.num_consts = 0;
-
- COMPILED_SUB * pCompiledSub;
- GLuint uj;
- GLuint unConstOffset = r700->vs.num_consts;
- for(ui=0; ui<vp->r700AsmCode.unNumPresub; ui++)
- {
- pCompiledSub = vp->r700AsmCode.presubs[ui].pCompiledSub;
-
- r700->vs.num_consts += pCompiledSub->NumParameters;
-
- for(uj=0; uj<pCompiledSub->NumParameters; uj++)
- {
- r700->vs.consts[uj + unConstOffset][0].f32All = pCompiledSub->ParameterValues[uj][0];
- r700->vs.consts[uj + unConstOffset][1].f32All = pCompiledSub->ParameterValues[uj][1];
- r700->vs.consts[uj + unConstOffset][2].f32All = pCompiledSub->ParameterValues[uj][2];
- r700->vs.consts[uj + unConstOffset][3].f32All = pCompiledSub->ParameterValues[uj][3];
- }
- unConstOffset += pCompiledSub->NumParameters;
- }
-
- return GL_TRUE;
-}
+++ /dev/null
-/*
- * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Authors:
- * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
- */
-
-
-#ifndef _R700_VERTPROG_H_
-#define _R700_VERTPROG_H_
-
-#include "main/glheader.h"
-#include "main/mtypes.h"
-
-#include "r700_shader.h"
-#include "r700_assembler.h"
-
-typedef struct ArrayDesc //TEMP
-{
- GLint size; //number of data element
- GLenum type; //data element type
- GLsizei stride;
- GLenum format; //GL_RGBA or GL_BGRA
-} ArrayDesc;
-
-struct r700_vertex_program
-{
- struct gl_vertex_program *mesa_program; /* Must be first */
-
- struct r700_vertex_program *next;
-
- r700_AssemblerBase r700AsmCode;
- R700_Shader r700Shader;
-
- GLboolean translated;
- GLboolean loaded;
-
- void * shaderbo;
-
- GLuint K0used;
- void * constbo0;
-
- ArrayDesc aos_desc[VERT_ATTRIB_MAX];
-};
-
-struct r700_vertex_program_cont
-{
- struct gl_vertex_program mesa_program;
-
- struct r700_vertex_program *progs;
-};
-
-//Internal
-unsigned int Map_Vertex_Output(r700_AssemblerBase *pAsm,
- struct gl_vertex_program *mesa_vp,
- unsigned int unStart);
-unsigned int Map_Vertex_Input(r700_AssemblerBase *pAsm,
- struct gl_vertex_program *mesa_vp,
- unsigned int unStart);
-GLboolean Process_Vertex_Program_Vfetch_Instructions(
- struct r700_vertex_program *vp,
- struct gl_vertex_program *mesa_vp);
-GLboolean Process_Vertex_Program_Vfetch_Instructions2(
- struct gl_context *ctx,
- struct r700_vertex_program *vp,
- struct gl_vertex_program *mesa_vp);
-void Map_Vertex_Program(struct gl_context *ctx,
- struct r700_vertex_program *vp,
- struct gl_vertex_program *mesa_vp);
-GLboolean Find_Instruction_Dependencies_vp(struct r700_vertex_program *vp,
- struct gl_vertex_program *mesa_vp);
-
-struct r700_vertex_program* r700TranslateVertexShader(struct gl_context *ctx,
- struct gl_vertex_program *mesa_vp);
-
-/* Interface */
-extern void r700SelectVertexShader(struct gl_context *ctx);
-extern void r700SetVertexFormat(struct gl_context *ctx, const struct gl_client_array *arrays[], int count);
-
-extern GLboolean r700SetupVertexProgram(struct gl_context * ctx);
-
-extern void * r700GetActiveVpShaderBo(struct gl_context * ctx);
-
-extern void * r700GetActiveVpShaderConstBo(struct gl_context * ctx);
-
-extern int getTypeSize(GLenum type);
-
-#endif /* _R700_VERTPROG_H_ */
+++ /dev/null
-../radeon/radeon_bo.c
\ No newline at end of file
+++ /dev/null
-../radeon/radeon_bo_int_drm.h
\ No newline at end of file
+++ /dev/null
-../radeon/radeon_bo_legacy.c
\ No newline at end of file
+++ /dev/null
-../radeon/radeon_bo_legacy.h
\ No newline at end of file
+++ /dev/null
-../radeon/radeon_bocs_wrapper.h
\ No newline at end of file
+++ /dev/null
-../radeon/radeon_buffer_objects.c
\ No newline at end of file
+++ /dev/null
-../radeon/radeon_buffer_objects.h
\ No newline at end of file
+++ /dev/null
-../radeon/radeon_chipset.h
\ No newline at end of file
+++ /dev/null
-../radeon/radeon_cmdbuf.h
\ No newline at end of file
+++ /dev/null
-../radeon/radeon_common.c
\ No newline at end of file
+++ /dev/null
-../radeon/radeon_common.h
\ No newline at end of file
+++ /dev/null
-../radeon/radeon_common_context.c
\ No newline at end of file
+++ /dev/null
-../radeon/radeon_common_context.h
\ No newline at end of file
+++ /dev/null
-../radeon/radeon_cs.c
\ No newline at end of file
+++ /dev/null
-../radeon/radeon_cs_int_drm.h
\ No newline at end of file
+++ /dev/null
-../radeon/radeon_cs_legacy.c
\ No newline at end of file
+++ /dev/null
-../radeon/radeon_cs_legacy.h
\ No newline at end of file
+++ /dev/null
-../radeon/radeon_cs_space_drm.c
\ No newline at end of file
+++ /dev/null
-../radeon/radeon_debug.c
\ No newline at end of file
+++ /dev/null
-../radeon/radeon_debug.h
\ No newline at end of file
+++ /dev/null
-../radeon/radeon_dma.c
\ No newline at end of file
+++ /dev/null
-../radeon/radeon_dma.h
\ No newline at end of file
+++ /dev/null
-../radeon/radeon_fbo.c
\ No newline at end of file
+++ /dev/null
-../radeon/radeon_lock.c
\ No newline at end of file
+++ /dev/null
-../radeon/radeon_lock.h
\ No newline at end of file
+++ /dev/null
-../radeon/radeon_mipmap_tree.c
\ No newline at end of file
+++ /dev/null
-../radeon/radeon_mipmap_tree.h
\ No newline at end of file
+++ /dev/null
-../radeon/radeon_pixel_read.c
\ No newline at end of file
+++ /dev/null
-../radeon/radeon_queryobj.c
\ No newline at end of file
+++ /dev/null
-../radeon/radeon_queryobj.h
\ No newline at end of file
+++ /dev/null
-../radeon/radeon_screen.c
\ No newline at end of file
+++ /dev/null
-../radeon/radeon_screen.h
\ No newline at end of file
+++ /dev/null
-../radeon/radeon_span.c
\ No newline at end of file
+++ /dev/null
-../radeon/radeon_span.h
\ No newline at end of file
+++ /dev/null
-../radeon/radeon_tex_copy.c
\ No newline at end of file
+++ /dev/null
-../radeon/radeon_texture.c
\ No newline at end of file
+++ /dev/null
-../radeon/radeon_texture.h
\ No newline at end of file
+++ /dev/null
-../radeon/radeon_tile.c
\ No newline at end of file
+++ /dev/null
-../radeon/radeon_tile.h
\ No newline at end of file
+++ /dev/null
-../../radeon/server/radeon.h
\ No newline at end of file
+++ /dev/null
-../../radeon/server/radeon_dri.h
\ No newline at end of file
+++ /dev/null
-../../radeon/server/radeon_macros.h
\ No newline at end of file
+++ /dev/null
-../../radeon/server/radeon_reg.h
\ No newline at end of file
+++ /dev/null
-/*
- * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Contacts:
- * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
- */
-
-#if !defined (_SQ_MICRO_REG_H)
-#define _SQ_MICRO_REG_H
-
-#if defined(LITTLEENDIAN_CPU)
-#elif defined(BIGENDIAN_CPU)
-#else
-#error "BIGENDIAN_CPU or LITTLEENDIAN_CPU must be defined"
-#endif
-
-/*
- * SQ_ALU_SRC_GPR_BASE value
- */
-
-#define SQ_ALU_SRC_GPR_BASE 0x00000000
-
-/*
- * SQ_ALU_SRC_GPR_SIZE value
- */
-
-#define SQ_ALU_SRC_GPR_SIZE 0x00000080
-
-/*
- * SQ_ALU_SRC_KCACHE0_BASE value
- */
-
-#define SQ_ALU_SRC_KCACHE0_BASE 0x00000080
-
-/*
- * SQ_ALU_SRC_KCACHE0_SIZE value
- */
-
-#define SQ_ALU_SRC_KCACHE0_SIZE 0x00000020
-
-/*
- * SQ_ALU_SRC_KCACHE1_BASE value
- */
-
-#define SQ_ALU_SRC_KCACHE1_BASE 0x000000a0
-
-/*
- * SQ_ALU_SRC_KCACHE1_SIZE value
- */
-
-#define SQ_ALU_SRC_KCACHE1_SIZE 0x00000020
-
-/*
- * SQ_ALU_SRC_CFILE_BASE value
- */
-
-#define SQ_ALU_SRC_CFILE_BASE 0x00000100
-
-/*
- * SQ_ALU_SRC_CFILE_SIZE value
- */
-
-#define SQ_ALU_SRC_CFILE_SIZE 0x00000100
-
-/*
- * SQ_SP_OP_REDUC_BEGIN value
- */
-
-#define SQ_SP_OP_REDUC_BEGIN 0x00000050
-
-/*
- * SQ_SP_OP_REDUC_END value
- */
-
-#define SQ_SP_OP_REDUC_END 0x00000053
-
-/*
- * SQ_SP_OP_TRANS_BEGIN value
- */
-
-#define SQ_SP_OP_TRANS_BEGIN 0x00000060
-
-/*
- * SQ_SP_OP_TRANS_END value
- */
-
-#define SQ_SP_OP_TRANS_END 0x0000007f
-
-/*
- * SQ_CF_WORD0 struct
- */
-
-#define SQ_CF_WORD0_ADDR_SIZE 32
-
-#define SQ_CF_WORD0_ADDR_SHIFT 0
-
-#define SQ_CF_WORD0_ADDR_MASK 0xffffffff
-
-#define SQ_CF_WORD0_MASK \
- (SQ_CF_WORD0_ADDR_MASK)
-
-#define SQ_CF_WORD0_DEFAULT 0xcdcdcdcd
-
-#define SQ_CF_WORD0_GET_ADDR(sq_cf_word0) \
- ((sq_cf_word0 & SQ_CF_WORD0_ADDR_MASK) >> SQ_CF_WORD0_ADDR_SHIFT)
-
-#define SQ_CF_WORD0_SET_ADDR(sq_cf_word0_reg, addr) \
- sq_cf_word0_reg = (sq_cf_word0_reg & ~SQ_CF_WORD0_ADDR_MASK) | (addr << SQ_CF_WORD0_ADDR_SHIFT)
-
-#if defined(LITTLEENDIAN_CPU)
-
- typedef struct _sq_cf_word0_t {
- unsigned int addr : SQ_CF_WORD0_ADDR_SIZE;
- } sq_cf_word0_t;
-
-#elif defined(BIGENDIAN_CPU)
-
- typedef struct _sq_cf_word0_t {
- unsigned int addr : SQ_CF_WORD0_ADDR_SIZE;
- } sq_cf_word0_t;
-
-#endif
-
-typedef union {
- unsigned int val : 32;
- sq_cf_word0_t f;
-} sq_cf_word0_u;
-
-
-/*
- * SQ_CF_WORD1 struct
- */
-
-#define SQ_CF_WORD1_POP_COUNT_SIZE 3
-#define SQ_CF_WORD1_CF_CONST_SIZE 5
-#define SQ_CF_WORD1_COND_SIZE 2
-#define SQ_CF_WORD1_COUNT_SIZE 3
-#define SQ_CF_WORD1_CALL_COUNT_SIZE 6
-#define SQ_CF_WORD1_COUNT_3_SIZE 1
-#define SQ_CF_WORD1_END_OF_PROGRAM_SIZE 1
-#define SQ_CF_WORD1_VALID_PIXEL_MODE_SIZE 1
-#define SQ_CF_WORD1_CF_INST_SIZE 7
-#define SQ_CF_WORD1_WHOLE_QUAD_MODE_SIZE 1
-#define SQ_CF_WORD1_BARRIER_SIZE 1
-
-#define SQ_CF_WORD1_POP_COUNT_SHIFT 0
-#define SQ_CF_WORD1_CF_CONST_SHIFT 3
-#define SQ_CF_WORD1_COND_SHIFT 8
-#define SQ_CF_WORD1_COUNT_SHIFT 10
-#define SQ_CF_WORD1_CALL_COUNT_SHIFT 13
-#define SQ_CF_WORD1_COUNT_3_SHIFT 19
-#define SQ_CF_WORD1_END_OF_PROGRAM_SHIFT 21
-#define SQ_CF_WORD1_VALID_PIXEL_MODE_SHIFT 22
-#define SQ_CF_WORD1_CF_INST_SHIFT 23
-#define SQ_CF_WORD1_WHOLE_QUAD_MODE_SHIFT 30
-#define SQ_CF_WORD1_BARRIER_SHIFT 31
-
-#define SQ_CF_WORD1_POP_COUNT_MASK 0x00000007
-#define SQ_CF_WORD1_CF_CONST_MASK 0x000000f8
-#define SQ_CF_WORD1_COND_MASK 0x00000300
-#define SQ_CF_WORD1_COUNT_MASK 0x00001c00
-#define SQ_CF_WORD1_CALL_COUNT_MASK 0x0007e000
-#define SQ_CF_WORD1_COUNT_3_MASK 0x00080000
-#define SQ_CF_WORD1_END_OF_PROGRAM_MASK 0x00200000
-#define SQ_CF_WORD1_VALID_PIXEL_MODE_MASK 0x00400000
-#define SQ_CF_WORD1_CF_INST_MASK 0x3f800000
-#define SQ_CF_WORD1_WHOLE_QUAD_MODE_MASK 0x40000000
-#define SQ_CF_WORD1_BARRIER_MASK 0x80000000
-
-#define SQ_CF_WORD1_MASK \
- (SQ_CF_WORD1_POP_COUNT_MASK | \
- SQ_CF_WORD1_CF_CONST_MASK | \
- SQ_CF_WORD1_COND_MASK | \
- SQ_CF_WORD1_COUNT_MASK | \
- SQ_CF_WORD1_CALL_COUNT_MASK | \
- SQ_CF_WORD1_COUNT_3_MASK | \
- SQ_CF_WORD1_END_OF_PROGRAM_MASK | \
- SQ_CF_WORD1_VALID_PIXEL_MODE_MASK | \
- SQ_CF_WORD1_CF_INST_MASK | \
- SQ_CF_WORD1_WHOLE_QUAD_MODE_MASK | \
- SQ_CF_WORD1_BARRIER_MASK)
-
-#define SQ_CF_WORD1_DEFAULT 0xcdcdcdcd
-
-#define SQ_CF_WORD1_GET_POP_COUNT(sq_cf_word1) \
- ((sq_cf_word1 & SQ_CF_WORD1_POP_COUNT_MASK) >> SQ_CF_WORD1_POP_COUNT_SHIFT)
-#define SQ_CF_WORD1_GET_CF_CONST(sq_cf_word1) \
- ((sq_cf_word1 & SQ_CF_WORD1_CF_CONST_MASK) >> SQ_CF_WORD1_CF_CONST_SHIFT)
-#define SQ_CF_WORD1_GET_COND(sq_cf_word1) \
- ((sq_cf_word1 & SQ_CF_WORD1_COND_MASK) >> SQ_CF_WORD1_COND_SHIFT)
-#define SQ_CF_WORD1_GET_COUNT(sq_cf_word1) \
- ((sq_cf_word1 & SQ_CF_WORD1_COUNT_MASK) >> SQ_CF_WORD1_COUNT_SHIFT)
-#define SQ_CF_WORD1_GET_CALL_COUNT(sq_cf_word1) \
- ((sq_cf_word1 & SQ_CF_WORD1_CALL_COUNT_MASK) >> SQ_CF_WORD1_CALL_COUNT_SHIFT)
-#define SQ_CF_WORD1_GET_COUNT_3(sq_cf_word1) \
- ((sq_cf_word1 & SQ_CF_WORD1_COUNT_3_MASK) >> SQ_CF_WORD1_COUNT_3_SHIFT)
-#define SQ_CF_WORD1_GET_END_OF_PROGRAM(sq_cf_word1) \
- ((sq_cf_word1 & SQ_CF_WORD1_END_OF_PROGRAM_MASK) >> SQ_CF_WORD1_END_OF_PROGRAM_SHIFT)
-#define SQ_CF_WORD1_GET_VALID_PIXEL_MODE(sq_cf_word1) \
- ((sq_cf_word1 & SQ_CF_WORD1_VALID_PIXEL_MODE_MASK) >> SQ_CF_WORD1_VALID_PIXEL_MODE_SHIFT)
-#define SQ_CF_WORD1_GET_CF_INST(sq_cf_word1) \
- ((sq_cf_word1 & SQ_CF_WORD1_CF_INST_MASK) >> SQ_CF_WORD1_CF_INST_SHIFT)
-#define SQ_CF_WORD1_GET_WHOLE_QUAD_MODE(sq_cf_word1) \
- ((sq_cf_word1 & SQ_CF_WORD1_WHOLE_QUAD_MODE_MASK) >> SQ_CF_WORD1_WHOLE_QUAD_MODE_SHIFT)
-#define SQ_CF_WORD1_GET_BARRIER(sq_cf_word1) \
- ((sq_cf_word1 & SQ_CF_WORD1_BARRIER_MASK) >> SQ_CF_WORD1_BARRIER_SHIFT)
-
-#define SQ_CF_WORD1_SET_POP_COUNT(sq_cf_word1_reg, pop_count) \
- sq_cf_word1_reg = (sq_cf_word1_reg & ~SQ_CF_WORD1_POP_COUNT_MASK) | (pop_count << SQ_CF_WORD1_POP_COUNT_SHIFT)
-#define SQ_CF_WORD1_SET_CF_CONST(sq_cf_word1_reg, cf_const) \
- sq_cf_word1_reg = (sq_cf_word1_reg & ~SQ_CF_WORD1_CF_CONST_MASK) | (cf_const << SQ_CF_WORD1_CF_CONST_SHIFT)
-#define SQ_CF_WORD1_SET_COND(sq_cf_word1_reg, cond) \
- sq_cf_word1_reg = (sq_cf_word1_reg & ~SQ_CF_WORD1_COND_MASK) | (cond << SQ_CF_WORD1_COND_SHIFT)
-#define SQ_CF_WORD1_SET_COUNT(sq_cf_word1_reg, count) \
- sq_cf_word1_reg = (sq_cf_word1_reg & ~SQ_CF_WORD1_COUNT_MASK) | (count << SQ_CF_WORD1_COUNT_SHIFT)
-#define SQ_CF_WORD1_SET_CALL_COUNT(sq_cf_word1_reg, call_count) \
- sq_cf_word1_reg = (sq_cf_word1_reg & ~SQ_CF_WORD1_CALL_COUNT_MASK) | (call_count << SQ_CF_WORD1_CALL_COUNT_SHIFT)
-#define SQ_CF_WORD1_SET_COUNT_3(sq_cf_word1_reg, count_3) \
- sq_cf_word1_reg = (sq_cf_word1_reg & ~SQ_CF_WORD1_COUNT_3_MASK) | (count_3 << SQ_CF_WORD1_COUNT_3_SHIFT)
-#define SQ_CF_WORD1_SET_END_OF_PROGRAM(sq_cf_word1_reg, end_of_program) \
- sq_cf_word1_reg = (sq_cf_word1_reg & ~SQ_CF_WORD1_END_OF_PROGRAM_MASK) | (end_of_program << SQ_CF_WORD1_END_OF_PROGRAM_SHIFT)
-#define SQ_CF_WORD1_SET_VALID_PIXEL_MODE(sq_cf_word1_reg, valid_pixel_mode) \
- sq_cf_word1_reg = (sq_cf_word1_reg & ~SQ_CF_WORD1_VALID_PIXEL_MODE_MASK) | (valid_pixel_mode << SQ_CF_WORD1_VALID_PIXEL_MODE_SHIFT)
-#define SQ_CF_WORD1_SET_CF_INST(sq_cf_word1_reg, cf_inst) \
- sq_cf_word1_reg = (sq_cf_word1_reg & ~SQ_CF_WORD1_CF_INST_MASK) | (cf_inst << SQ_CF_WORD1_CF_INST_SHIFT)
-#define SQ_CF_WORD1_SET_WHOLE_QUAD_MODE(sq_cf_word1_reg, whole_quad_mode) \
- sq_cf_word1_reg = (sq_cf_word1_reg & ~SQ_CF_WORD1_WHOLE_QUAD_MODE_MASK) | (whole_quad_mode << SQ_CF_WORD1_WHOLE_QUAD_MODE_SHIFT)
-#define SQ_CF_WORD1_SET_BARRIER(sq_cf_word1_reg, barrier) \
- sq_cf_word1_reg = (sq_cf_word1_reg & ~SQ_CF_WORD1_BARRIER_MASK) | (barrier << SQ_CF_WORD1_BARRIER_SHIFT)
-
-#if defined(LITTLEENDIAN_CPU)
-
- typedef struct _sq_cf_word1_t {
- unsigned int pop_count : SQ_CF_WORD1_POP_COUNT_SIZE;
- unsigned int cf_const : SQ_CF_WORD1_CF_CONST_SIZE;
- unsigned int cond : SQ_CF_WORD1_COND_SIZE;
- unsigned int count : SQ_CF_WORD1_COUNT_SIZE;
- unsigned int call_count : SQ_CF_WORD1_CALL_COUNT_SIZE;
- unsigned int count_3 : SQ_CF_WORD1_COUNT_3_SIZE;
- unsigned int : 1;
- unsigned int end_of_program : SQ_CF_WORD1_END_OF_PROGRAM_SIZE;
- unsigned int valid_pixel_mode : SQ_CF_WORD1_VALID_PIXEL_MODE_SIZE;
- unsigned int cf_inst : SQ_CF_WORD1_CF_INST_SIZE;
- unsigned int whole_quad_mode : SQ_CF_WORD1_WHOLE_QUAD_MODE_SIZE;
- unsigned int barrier : SQ_CF_WORD1_BARRIER_SIZE;
- } sq_cf_word1_t;
-
-#elif defined(BIGENDIAN_CPU)
-
- typedef struct _sq_cf_word1_t {
- unsigned int barrier : SQ_CF_WORD1_BARRIER_SIZE;
- unsigned int whole_quad_mode : SQ_CF_WORD1_WHOLE_QUAD_MODE_SIZE;
- unsigned int cf_inst : SQ_CF_WORD1_CF_INST_SIZE;
- unsigned int valid_pixel_mode : SQ_CF_WORD1_VALID_PIXEL_MODE_SIZE;
- unsigned int end_of_program : SQ_CF_WORD1_END_OF_PROGRAM_SIZE;
- unsigned int : 1;
- unsigned int count_3 : SQ_CF_WORD1_COUNT_3_SIZE;
- unsigned int call_count : SQ_CF_WORD1_CALL_COUNT_SIZE;
- unsigned int count : SQ_CF_WORD1_COUNT_SIZE;
- unsigned int cond : SQ_CF_WORD1_COND_SIZE;
- unsigned int cf_const : SQ_CF_WORD1_CF_CONST_SIZE;
- unsigned int pop_count : SQ_CF_WORD1_POP_COUNT_SIZE;
- } sq_cf_word1_t;
-
-#endif
-
-typedef union {
- unsigned int val : 32;
- sq_cf_word1_t f;
-} sq_cf_word1_u;
-
-
-/*
- * SQ_CF_ALU_WORD0 struct
- */
-
-#define SQ_CF_ALU_WORD0_ADDR_SIZE 22
-#define SQ_CF_ALU_WORD0_KCACHE_BANK0_SIZE 4
-#define SQ_CF_ALU_WORD0_KCACHE_BANK1_SIZE 4
-#define SQ_CF_ALU_WORD0_KCACHE_MODE0_SIZE 2
-
-#define SQ_CF_ALU_WORD0_ADDR_SHIFT 0
-#define SQ_CF_ALU_WORD0_KCACHE_BANK0_SHIFT 22
-#define SQ_CF_ALU_WORD0_KCACHE_BANK1_SHIFT 26
-#define SQ_CF_ALU_WORD0_KCACHE_MODE0_SHIFT 30
-
-#define SQ_CF_ALU_WORD0_ADDR_MASK 0x003fffff
-#define SQ_CF_ALU_WORD0_KCACHE_BANK0_MASK 0x03c00000
-#define SQ_CF_ALU_WORD0_KCACHE_BANK1_MASK 0x3c000000
-#define SQ_CF_ALU_WORD0_KCACHE_MODE0_MASK 0xc0000000
-
-#define SQ_CF_ALU_WORD0_MASK \
- (SQ_CF_ALU_WORD0_ADDR_MASK | \
- SQ_CF_ALU_WORD0_KCACHE_BANK0_MASK | \
- SQ_CF_ALU_WORD0_KCACHE_BANK1_MASK | \
- SQ_CF_ALU_WORD0_KCACHE_MODE0_MASK)
-
-#define SQ_CF_ALU_WORD0_DEFAULT 0xcdcdcdcd
-
-#define SQ_CF_ALU_WORD0_GET_ADDR(sq_cf_alu_word0) \
- ((sq_cf_alu_word0 & SQ_CF_ALU_WORD0_ADDR_MASK) >> SQ_CF_ALU_WORD0_ADDR_SHIFT)
-#define SQ_CF_ALU_WORD0_GET_KCACHE_BANK0(sq_cf_alu_word0) \
- ((sq_cf_alu_word0 & SQ_CF_ALU_WORD0_KCACHE_BANK0_MASK) >> SQ_CF_ALU_WORD0_KCACHE_BANK0_SHIFT)
-#define SQ_CF_ALU_WORD0_GET_KCACHE_BANK1(sq_cf_alu_word0) \
- ((sq_cf_alu_word0 & SQ_CF_ALU_WORD0_KCACHE_BANK1_MASK) >> SQ_CF_ALU_WORD0_KCACHE_BANK1_SHIFT)
-#define SQ_CF_ALU_WORD0_GET_KCACHE_MODE0(sq_cf_alu_word0) \
- ((sq_cf_alu_word0 & SQ_CF_ALU_WORD0_KCACHE_MODE0_MASK) >> SQ_CF_ALU_WORD0_KCACHE_MODE0_SHIFT)
-
-#define SQ_CF_ALU_WORD0_SET_ADDR(sq_cf_alu_word0_reg, addr) \
- sq_cf_alu_word0_reg = (sq_cf_alu_word0_reg & ~SQ_CF_ALU_WORD0_ADDR_MASK) | (addr << SQ_CF_ALU_WORD0_ADDR_SHIFT)
-#define SQ_CF_ALU_WORD0_SET_KCACHE_BANK0(sq_cf_alu_word0_reg, kcache_bank0) \
- sq_cf_alu_word0_reg = (sq_cf_alu_word0_reg & ~SQ_CF_ALU_WORD0_KCACHE_BANK0_MASK) | (kcache_bank0 << SQ_CF_ALU_WORD0_KCACHE_BANK0_SHIFT)
-#define SQ_CF_ALU_WORD0_SET_KCACHE_BANK1(sq_cf_alu_word0_reg, kcache_bank1) \
- sq_cf_alu_word0_reg = (sq_cf_alu_word0_reg & ~SQ_CF_ALU_WORD0_KCACHE_BANK1_MASK) | (kcache_bank1 << SQ_CF_ALU_WORD0_KCACHE_BANK1_SHIFT)
-#define SQ_CF_ALU_WORD0_SET_KCACHE_MODE0(sq_cf_alu_word0_reg, kcache_mode0) \
- sq_cf_alu_word0_reg = (sq_cf_alu_word0_reg & ~SQ_CF_ALU_WORD0_KCACHE_MODE0_MASK) | (kcache_mode0 << SQ_CF_ALU_WORD0_KCACHE_MODE0_SHIFT)
-
-#if defined(LITTLEENDIAN_CPU)
-
- typedef struct _sq_cf_alu_word0_t {
- unsigned int addr : SQ_CF_ALU_WORD0_ADDR_SIZE;
- unsigned int kcache_bank0 : SQ_CF_ALU_WORD0_KCACHE_BANK0_SIZE;
- unsigned int kcache_bank1 : SQ_CF_ALU_WORD0_KCACHE_BANK1_SIZE;
- unsigned int kcache_mode0 : SQ_CF_ALU_WORD0_KCACHE_MODE0_SIZE;
- } sq_cf_alu_word0_t;
-
-#elif defined(BIGENDIAN_CPU)
-
- typedef struct _sq_cf_alu_word0_t {
- unsigned int kcache_mode0 : SQ_CF_ALU_WORD0_KCACHE_MODE0_SIZE;
- unsigned int kcache_bank1 : SQ_CF_ALU_WORD0_KCACHE_BANK1_SIZE;
- unsigned int kcache_bank0 : SQ_CF_ALU_WORD0_KCACHE_BANK0_SIZE;
- unsigned int addr : SQ_CF_ALU_WORD0_ADDR_SIZE;
- } sq_cf_alu_word0_t;
-
-#endif
-
-typedef union {
- unsigned int val : 32;
- sq_cf_alu_word0_t f;
-} sq_cf_alu_word0_u;
-
-
-/*
- * SQ_CF_ALU_WORD1 struct
- */
-
-#define SQ_CF_ALU_WORD1_KCACHE_MODE1_SIZE 2
-#define SQ_CF_ALU_WORD1_KCACHE_ADDR0_SIZE 8
-#define SQ_CF_ALU_WORD1_KCACHE_ADDR1_SIZE 8
-#define SQ_CF_ALU_WORD1_COUNT_SIZE 7
-#define SQ_CF_ALU_WORD1_ALT_CONST_SIZE 1
-#define SQ_CF_ALU_WORD1_CF_INST_SIZE 4
-#define SQ_CF_ALU_WORD1_WHOLE_QUAD_MODE_SIZE 1
-#define SQ_CF_ALU_WORD1_BARRIER_SIZE 1
-
-#define SQ_CF_ALU_WORD1_KCACHE_MODE1_SHIFT 0
-#define SQ_CF_ALU_WORD1_KCACHE_ADDR0_SHIFT 2
-#define SQ_CF_ALU_WORD1_KCACHE_ADDR1_SHIFT 10
-#define SQ_CF_ALU_WORD1_COUNT_SHIFT 18
-#define SQ_CF_ALU_WORD1_ALT_CONST_SHIFT 25
-#define SQ_CF_ALU_WORD1_CF_INST_SHIFT 26
-#define SQ_CF_ALU_WORD1_WHOLE_QUAD_MODE_SHIFT 30
-#define SQ_CF_ALU_WORD1_BARRIER_SHIFT 31
-
-#define SQ_CF_ALU_WORD1_KCACHE_MODE1_MASK 0x00000003
-#define SQ_CF_ALU_WORD1_KCACHE_ADDR0_MASK 0x000003fc
-#define SQ_CF_ALU_WORD1_KCACHE_ADDR1_MASK 0x0003fc00
-#define SQ_CF_ALU_WORD1_COUNT_MASK 0x01fc0000
-#define SQ_CF_ALU_WORD1_ALT_CONST_MASK 0x02000000
-#define SQ_CF_ALU_WORD1_CF_INST_MASK 0x3c000000
-#define SQ_CF_ALU_WORD1_WHOLE_QUAD_MODE_MASK 0x40000000
-#define SQ_CF_ALU_WORD1_BARRIER_MASK 0x80000000
-
-#define SQ_CF_ALU_WORD1_MASK \
- (SQ_CF_ALU_WORD1_KCACHE_MODE1_MASK | \
- SQ_CF_ALU_WORD1_KCACHE_ADDR0_MASK | \
- SQ_CF_ALU_WORD1_KCACHE_ADDR1_MASK | \
- SQ_CF_ALU_WORD1_COUNT_MASK | \
- SQ_CF_ALU_WORD1_ALT_CONST_MASK | \
- SQ_CF_ALU_WORD1_CF_INST_MASK | \
- SQ_CF_ALU_WORD1_WHOLE_QUAD_MODE_MASK | \
- SQ_CF_ALU_WORD1_BARRIER_MASK)
-
-#define SQ_CF_ALU_WORD1_DEFAULT 0xcdcdcdcd
-
-#define SQ_CF_ALU_WORD1_GET_KCACHE_MODE1(sq_cf_alu_word1) \
- ((sq_cf_alu_word1 & SQ_CF_ALU_WORD1_KCACHE_MODE1_MASK) >> SQ_CF_ALU_WORD1_KCACHE_MODE1_SHIFT)
-#define SQ_CF_ALU_WORD1_GET_KCACHE_ADDR0(sq_cf_alu_word1) \
- ((sq_cf_alu_word1 & SQ_CF_ALU_WORD1_KCACHE_ADDR0_MASK) >> SQ_CF_ALU_WORD1_KCACHE_ADDR0_SHIFT)
-#define SQ_CF_ALU_WORD1_GET_KCACHE_ADDR1(sq_cf_alu_word1) \
- ((sq_cf_alu_word1 & SQ_CF_ALU_WORD1_KCACHE_ADDR1_MASK) >> SQ_CF_ALU_WORD1_KCACHE_ADDR1_SHIFT)
-#define SQ_CF_ALU_WORD1_GET_COUNT(sq_cf_alu_word1) \
- ((sq_cf_alu_word1 & SQ_CF_ALU_WORD1_COUNT_MASK) >> SQ_CF_ALU_WORD1_COUNT_SHIFT)
-#define SQ_CF_ALU_WORD1_GET_ALT_CONST(sq_cf_alu_word1) \
- ((sq_cf_alu_word1 & SQ_CF_ALU_WORD1_ALT_CONST_MASK) >> SQ_CF_ALU_WORD1_ALT_CONST_SHIFT)
-#define SQ_CF_ALU_WORD1_GET_CF_INST(sq_cf_alu_word1) \
- ((sq_cf_alu_word1 & SQ_CF_ALU_WORD1_CF_INST_MASK) >> SQ_CF_ALU_WORD1_CF_INST_SHIFT)
-#define SQ_CF_ALU_WORD1_GET_WHOLE_QUAD_MODE(sq_cf_alu_word1) \
- ((sq_cf_alu_word1 & SQ_CF_ALU_WORD1_WHOLE_QUAD_MODE_MASK) >> SQ_CF_ALU_WORD1_WHOLE_QUAD_MODE_SHIFT)
-#define SQ_CF_ALU_WORD1_GET_BARRIER(sq_cf_alu_word1) \
- ((sq_cf_alu_word1 & SQ_CF_ALU_WORD1_BARRIER_MASK) >> SQ_CF_ALU_WORD1_BARRIER_SHIFT)
-
-#define SQ_CF_ALU_WORD1_SET_KCACHE_MODE1(sq_cf_alu_word1_reg, kcache_mode1) \
- sq_cf_alu_word1_reg = (sq_cf_alu_word1_reg & ~SQ_CF_ALU_WORD1_KCACHE_MODE1_MASK) | (kcache_mode1 << SQ_CF_ALU_WORD1_KCACHE_MODE1_SHIFT)
-#define SQ_CF_ALU_WORD1_SET_KCACHE_ADDR0(sq_cf_alu_word1_reg, kcache_addr0) \
- sq_cf_alu_word1_reg = (sq_cf_alu_word1_reg & ~SQ_CF_ALU_WORD1_KCACHE_ADDR0_MASK) | (kcache_addr0 << SQ_CF_ALU_WORD1_KCACHE_ADDR0_SHIFT)
-#define SQ_CF_ALU_WORD1_SET_KCACHE_ADDR1(sq_cf_alu_word1_reg, kcache_addr1) \
- sq_cf_alu_word1_reg = (sq_cf_alu_word1_reg & ~SQ_CF_ALU_WORD1_KCACHE_ADDR1_MASK) | (kcache_addr1 << SQ_CF_ALU_WORD1_KCACHE_ADDR1_SHIFT)
-#define SQ_CF_ALU_WORD1_SET_COUNT(sq_cf_alu_word1_reg, count) \
- sq_cf_alu_word1_reg = (sq_cf_alu_word1_reg & ~SQ_CF_ALU_WORD1_COUNT_MASK) | (count << SQ_CF_ALU_WORD1_COUNT_SHIFT)
-#define SQ_CF_ALU_WORD1_SET_ALT_CONST(sq_cf_alu_word1_reg, alt_const) \
- sq_cf_alu_word1_reg = (sq_cf_alu_word1_reg & ~SQ_CF_ALU_WORD1_ALT_CONST_MASK) | (alt_const << SQ_CF_ALU_WORD1_ALT_CONST_SHIFT)
-#define SQ_CF_ALU_WORD1_SET_CF_INST(sq_cf_alu_word1_reg, cf_inst) \
- sq_cf_alu_word1_reg = (sq_cf_alu_word1_reg & ~SQ_CF_ALU_WORD1_CF_INST_MASK) | (cf_inst << SQ_CF_ALU_WORD1_CF_INST_SHIFT)
-#define SQ_CF_ALU_WORD1_SET_WHOLE_QUAD_MODE(sq_cf_alu_word1_reg, whole_quad_mode) \
- sq_cf_alu_word1_reg = (sq_cf_alu_word1_reg & ~SQ_CF_ALU_WORD1_WHOLE_QUAD_MODE_MASK) | (whole_quad_mode << SQ_CF_ALU_WORD1_WHOLE_QUAD_MODE_SHIFT)
-#define SQ_CF_ALU_WORD1_SET_BARRIER(sq_cf_alu_word1_reg, barrier) \
- sq_cf_alu_word1_reg = (sq_cf_alu_word1_reg & ~SQ_CF_ALU_WORD1_BARRIER_MASK) | (barrier << SQ_CF_ALU_WORD1_BARRIER_SHIFT)
-
-#if defined(LITTLEENDIAN_CPU)
-
- typedef struct _sq_cf_alu_word1_t {
- unsigned int kcache_mode1 : SQ_CF_ALU_WORD1_KCACHE_MODE1_SIZE;
- unsigned int kcache_addr0 : SQ_CF_ALU_WORD1_KCACHE_ADDR0_SIZE;
- unsigned int kcache_addr1 : SQ_CF_ALU_WORD1_KCACHE_ADDR1_SIZE;
- unsigned int count : SQ_CF_ALU_WORD1_COUNT_SIZE;
- unsigned int alt_const : SQ_CF_ALU_WORD1_ALT_CONST_SIZE;
- unsigned int cf_inst : SQ_CF_ALU_WORD1_CF_INST_SIZE;
- unsigned int whole_quad_mode : SQ_CF_ALU_WORD1_WHOLE_QUAD_MODE_SIZE;
- unsigned int barrier : SQ_CF_ALU_WORD1_BARRIER_SIZE;
- } sq_cf_alu_word1_t;
-
-#elif defined(BIGENDIAN_CPU)
-
- typedef struct _sq_cf_alu_word1_t {
- unsigned int barrier : SQ_CF_ALU_WORD1_BARRIER_SIZE;
- unsigned int whole_quad_mode : SQ_CF_ALU_WORD1_WHOLE_QUAD_MODE_SIZE;
- unsigned int cf_inst : SQ_CF_ALU_WORD1_CF_INST_SIZE;
- unsigned int alt_const : SQ_CF_ALU_WORD1_ALT_CONST_SIZE;
- unsigned int count : SQ_CF_ALU_WORD1_COUNT_SIZE;
- unsigned int kcache_addr1 : SQ_CF_ALU_WORD1_KCACHE_ADDR1_SIZE;
- unsigned int kcache_addr0 : SQ_CF_ALU_WORD1_KCACHE_ADDR0_SIZE;
- unsigned int kcache_mode1 : SQ_CF_ALU_WORD1_KCACHE_MODE1_SIZE;
- } sq_cf_alu_word1_t;
-
-#endif
-
-typedef union {
- unsigned int val : 32;
- sq_cf_alu_word1_t f;
-} sq_cf_alu_word1_u;
-
-
-/*
- * SQ_CF_ALLOC_EXPORT_WORD0 struct
- */
-
-#define SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE_SIZE 13
-#define SQ_CF_ALLOC_EXPORT_WORD0_TYPE_SIZE 2
-#define SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR_SIZE 7
-#define SQ_CF_ALLOC_EXPORT_WORD0_RW_REL_SIZE 1
-#define SQ_CF_ALLOC_EXPORT_WORD0_INDEX_GPR_SIZE 7
-#define SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE_SIZE 2
-
-#define SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE_SHIFT 0
-#define SQ_CF_ALLOC_EXPORT_WORD0_TYPE_SHIFT 13
-#define SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR_SHIFT 15
-#define SQ_CF_ALLOC_EXPORT_WORD0_RW_REL_SHIFT 22
-#define SQ_CF_ALLOC_EXPORT_WORD0_INDEX_GPR_SHIFT 23
-#define SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE_SHIFT 30
-
-#define SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE_MASK 0x00001fff
-#define SQ_CF_ALLOC_EXPORT_WORD0_TYPE_MASK 0x00006000
-#define SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR_MASK 0x003f8000
-#define SQ_CF_ALLOC_EXPORT_WORD0_RW_REL_MASK 0x00400000
-#define SQ_CF_ALLOC_EXPORT_WORD0_INDEX_GPR_MASK 0x3f800000
-#define SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE_MASK 0xc0000000
-
-#define SQ_CF_ALLOC_EXPORT_WORD0_MASK \
- (SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE_MASK | \
- SQ_CF_ALLOC_EXPORT_WORD0_TYPE_MASK | \
- SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR_MASK | \
- SQ_CF_ALLOC_EXPORT_WORD0_RW_REL_MASK | \
- SQ_CF_ALLOC_EXPORT_WORD0_INDEX_GPR_MASK | \
- SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE_MASK)
-
-#define SQ_CF_ALLOC_EXPORT_WORD0_DEFAULT 0xcdcdcdcd
-
-#define SQ_CF_ALLOC_EXPORT_WORD0_GET_ARRAY_BASE(sq_cf_alloc_export_word0) \
- ((sq_cf_alloc_export_word0 & SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE_MASK) >> SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE_SHIFT)
-#define SQ_CF_ALLOC_EXPORT_WORD0_GET_TYPE(sq_cf_alloc_export_word0) \
- ((sq_cf_alloc_export_word0 & SQ_CF_ALLOC_EXPORT_WORD0_TYPE_MASK) >> SQ_CF_ALLOC_EXPORT_WORD0_TYPE_SHIFT)
-#define SQ_CF_ALLOC_EXPORT_WORD0_GET_RW_GPR(sq_cf_alloc_export_word0) \
- ((sq_cf_alloc_export_word0 & SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR_MASK) >> SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR_SHIFT)
-#define SQ_CF_ALLOC_EXPORT_WORD0_GET_RW_REL(sq_cf_alloc_export_word0) \
- ((sq_cf_alloc_export_word0 & SQ_CF_ALLOC_EXPORT_WORD0_RW_REL_MASK) >> SQ_CF_ALLOC_EXPORT_WORD0_RW_REL_SHIFT)
-#define SQ_CF_ALLOC_EXPORT_WORD0_GET_INDEX_GPR(sq_cf_alloc_export_word0) \
- ((sq_cf_alloc_export_word0 & SQ_CF_ALLOC_EXPORT_WORD0_INDEX_GPR_MASK) >> SQ_CF_ALLOC_EXPORT_WORD0_INDEX_GPR_SHIFT)
-#define SQ_CF_ALLOC_EXPORT_WORD0_GET_ELEM_SIZE(sq_cf_alloc_export_word0) \
- ((sq_cf_alloc_export_word0 & SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE_MASK) >> SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE_SHIFT)
-
-#define SQ_CF_ALLOC_EXPORT_WORD0_SET_ARRAY_BASE(sq_cf_alloc_export_word0_reg, array_base) \
- sq_cf_alloc_export_word0_reg = (sq_cf_alloc_export_word0_reg & ~SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE_MASK) | (array_base << SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE_SHIFT)
-#define SQ_CF_ALLOC_EXPORT_WORD0_SET_TYPE(sq_cf_alloc_export_word0_reg, type) \
- sq_cf_alloc_export_word0_reg = (sq_cf_alloc_export_word0_reg & ~SQ_CF_ALLOC_EXPORT_WORD0_TYPE_MASK) | (type << SQ_CF_ALLOC_EXPORT_WORD0_TYPE_SHIFT)
-#define SQ_CF_ALLOC_EXPORT_WORD0_SET_RW_GPR(sq_cf_alloc_export_word0_reg, rw_gpr) \
- sq_cf_alloc_export_word0_reg = (sq_cf_alloc_export_word0_reg & ~SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR_MASK) | (rw_gpr << SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR_SHIFT)
-#define SQ_CF_ALLOC_EXPORT_WORD0_SET_RW_REL(sq_cf_alloc_export_word0_reg, rw_rel) \
- sq_cf_alloc_export_word0_reg = (sq_cf_alloc_export_word0_reg & ~SQ_CF_ALLOC_EXPORT_WORD0_RW_REL_MASK) | (rw_rel << SQ_CF_ALLOC_EXPORT_WORD0_RW_REL_SHIFT)
-#define SQ_CF_ALLOC_EXPORT_WORD0_SET_INDEX_GPR(sq_cf_alloc_export_word0_reg, index_gpr) \
- sq_cf_alloc_export_word0_reg = (sq_cf_alloc_export_word0_reg & ~SQ_CF_ALLOC_EXPORT_WORD0_INDEX_GPR_MASK) | (index_gpr << SQ_CF_ALLOC_EXPORT_WORD0_INDEX_GPR_SHIFT)
-#define SQ_CF_ALLOC_EXPORT_WORD0_SET_ELEM_SIZE(sq_cf_alloc_export_word0_reg, elem_size) \
- sq_cf_alloc_export_word0_reg = (sq_cf_alloc_export_word0_reg & ~SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE_MASK) | (elem_size << SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE_SHIFT)
-
-#if defined(LITTLEENDIAN_CPU)
-
- typedef struct _sq_cf_alloc_export_word0_t {
- unsigned int array_base : SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE_SIZE;
- unsigned int type : SQ_CF_ALLOC_EXPORT_WORD0_TYPE_SIZE;
- unsigned int rw_gpr : SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR_SIZE;
- unsigned int rw_rel : SQ_CF_ALLOC_EXPORT_WORD0_RW_REL_SIZE;
- unsigned int index_gpr : SQ_CF_ALLOC_EXPORT_WORD0_INDEX_GPR_SIZE;
- unsigned int elem_size : SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE_SIZE;
- } sq_cf_alloc_export_word0_t;
-
-#elif defined(BIGENDIAN_CPU)
-
- typedef struct _sq_cf_alloc_export_word0_t {
- unsigned int elem_size : SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE_SIZE;
- unsigned int index_gpr : SQ_CF_ALLOC_EXPORT_WORD0_INDEX_GPR_SIZE;
- unsigned int rw_rel : SQ_CF_ALLOC_EXPORT_WORD0_RW_REL_SIZE;
- unsigned int rw_gpr : SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR_SIZE;
- unsigned int type : SQ_CF_ALLOC_EXPORT_WORD0_TYPE_SIZE;
- unsigned int array_base : SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE_SIZE;
- } sq_cf_alloc_export_word0_t;
-
-#endif
-
-typedef union {
- unsigned int val : 32;
- sq_cf_alloc_export_word0_t f;
-} sq_cf_alloc_export_word0_u;
-
-
-/*
- * SQ_CF_ALLOC_EXPORT_WORD1 struct
- */
-
-#define SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT_SIZE 4
-#define SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM_SIZE 1
-#define SQ_CF_ALLOC_EXPORT_WORD1_VALID_PIXEL_MODE_SIZE 1
-#define SQ_CF_ALLOC_EXPORT_WORD1_CF_INST_SIZE 7
-#define SQ_CF_ALLOC_EXPORT_WORD1_WHOLE_QUAD_MODE_SIZE 1
-#define SQ_CF_ALLOC_EXPORT_WORD1_BARRIER_SIZE 1
-
-#define SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT_SHIFT 17
-#define SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM_SHIFT 21
-#define SQ_CF_ALLOC_EXPORT_WORD1_VALID_PIXEL_MODE_SHIFT 22
-#define SQ_CF_ALLOC_EXPORT_WORD1_CF_INST_SHIFT 23
-#define SQ_CF_ALLOC_EXPORT_WORD1_WHOLE_QUAD_MODE_SHIFT 30
-#define SQ_CF_ALLOC_EXPORT_WORD1_BARRIER_SHIFT 31
-
-#define SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT_MASK 0x001e0000
-#define SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM_MASK 0x00200000
-#define SQ_CF_ALLOC_EXPORT_WORD1_VALID_PIXEL_MODE_MASK 0x00400000
-#define SQ_CF_ALLOC_EXPORT_WORD1_CF_INST_MASK 0x3f800000
-#define SQ_CF_ALLOC_EXPORT_WORD1_WHOLE_QUAD_MODE_MASK 0x40000000
-#define SQ_CF_ALLOC_EXPORT_WORD1_BARRIER_MASK 0x80000000
-
-#define SQ_CF_ALLOC_EXPORT_WORD1_MASK \
- (SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT_MASK | \
- SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM_MASK | \
- SQ_CF_ALLOC_EXPORT_WORD1_VALID_PIXEL_MODE_MASK | \
- SQ_CF_ALLOC_EXPORT_WORD1_CF_INST_MASK | \
- SQ_CF_ALLOC_EXPORT_WORD1_WHOLE_QUAD_MODE_MASK | \
- SQ_CF_ALLOC_EXPORT_WORD1_BARRIER_MASK)
-
-#define SQ_CF_ALLOC_EXPORT_WORD1_DEFAULT 0xcdcc0000
-
-#define SQ_CF_ALLOC_EXPORT_WORD1_GET_BURST_COUNT(sq_cf_alloc_export_word1) \
- ((sq_cf_alloc_export_word1 & SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT_MASK) >> SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT_SHIFT)
-#define SQ_CF_ALLOC_EXPORT_WORD1_GET_END_OF_PROGRAM(sq_cf_alloc_export_word1) \
- ((sq_cf_alloc_export_word1 & SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM_MASK) >> SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM_SHIFT)
-#define SQ_CF_ALLOC_EXPORT_WORD1_GET_VALID_PIXEL_MODE(sq_cf_alloc_export_word1) \
- ((sq_cf_alloc_export_word1 & SQ_CF_ALLOC_EXPORT_WORD1_VALID_PIXEL_MODE_MASK) >> SQ_CF_ALLOC_EXPORT_WORD1_VALID_PIXEL_MODE_SHIFT)
-#define SQ_CF_ALLOC_EXPORT_WORD1_GET_CF_INST(sq_cf_alloc_export_word1) \
- ((sq_cf_alloc_export_word1 & SQ_CF_ALLOC_EXPORT_WORD1_CF_INST_MASK) >> SQ_CF_ALLOC_EXPORT_WORD1_CF_INST_SHIFT)
-#define SQ_CF_ALLOC_EXPORT_WORD1_GET_WHOLE_QUAD_MODE(sq_cf_alloc_export_word1) \
- ((sq_cf_alloc_export_word1 & SQ_CF_ALLOC_EXPORT_WORD1_WHOLE_QUAD_MODE_MASK) >> SQ_CF_ALLOC_EXPORT_WORD1_WHOLE_QUAD_MODE_SHIFT)
-#define SQ_CF_ALLOC_EXPORT_WORD1_GET_BARRIER(sq_cf_alloc_export_word1) \
- ((sq_cf_alloc_export_word1 & SQ_CF_ALLOC_EXPORT_WORD1_BARRIER_MASK) >> SQ_CF_ALLOC_EXPORT_WORD1_BARRIER_SHIFT)
-
-#define SQ_CF_ALLOC_EXPORT_WORD1_SET_BURST_COUNT(sq_cf_alloc_export_word1_reg, burst_count) \
- sq_cf_alloc_export_word1_reg = (sq_cf_alloc_export_word1_reg & ~SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT_MASK) | (burst_count << SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT_SHIFT)
-#define SQ_CF_ALLOC_EXPORT_WORD1_SET_END_OF_PROGRAM(sq_cf_alloc_export_word1_reg, end_of_program) \
- sq_cf_alloc_export_word1_reg = (sq_cf_alloc_export_word1_reg & ~SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM_MASK) | (end_of_program << SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM_SHIFT)
-#define SQ_CF_ALLOC_EXPORT_WORD1_SET_VALID_PIXEL_MODE(sq_cf_alloc_export_word1_reg, valid_pixel_mode) \
- sq_cf_alloc_export_word1_reg = (sq_cf_alloc_export_word1_reg & ~SQ_CF_ALLOC_EXPORT_WORD1_VALID_PIXEL_MODE_MASK) | (valid_pixel_mode << SQ_CF_ALLOC_EXPORT_WORD1_VALID_PIXEL_MODE_SHIFT)
-#define SQ_CF_ALLOC_EXPORT_WORD1_SET_CF_INST(sq_cf_alloc_export_word1_reg, cf_inst) \
- sq_cf_alloc_export_word1_reg = (sq_cf_alloc_export_word1_reg & ~SQ_CF_ALLOC_EXPORT_WORD1_CF_INST_MASK) | (cf_inst << SQ_CF_ALLOC_EXPORT_WORD1_CF_INST_SHIFT)
-#define SQ_CF_ALLOC_EXPORT_WORD1_SET_WHOLE_QUAD_MODE(sq_cf_alloc_export_word1_reg, whole_quad_mode) \
- sq_cf_alloc_export_word1_reg = (sq_cf_alloc_export_word1_reg & ~SQ_CF_ALLOC_EXPORT_WORD1_WHOLE_QUAD_MODE_MASK) | (whole_quad_mode << SQ_CF_ALLOC_EXPORT_WORD1_WHOLE_QUAD_MODE_SHIFT)
-#define SQ_CF_ALLOC_EXPORT_WORD1_SET_BARRIER(sq_cf_alloc_export_word1_reg, barrier) \
- sq_cf_alloc_export_word1_reg = (sq_cf_alloc_export_word1_reg & ~SQ_CF_ALLOC_EXPORT_WORD1_BARRIER_MASK) | (barrier << SQ_CF_ALLOC_EXPORT_WORD1_BARRIER_SHIFT)
-
-#if defined(LITTLEENDIAN_CPU)
-
- typedef struct _sq_cf_alloc_export_word1_t {
- unsigned int : 17;
- unsigned int burst_count : SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT_SIZE;
- unsigned int end_of_program : SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM_SIZE;
- unsigned int valid_pixel_mode : SQ_CF_ALLOC_EXPORT_WORD1_VALID_PIXEL_MODE_SIZE;
- unsigned int cf_inst : SQ_CF_ALLOC_EXPORT_WORD1_CF_INST_SIZE;
- unsigned int whole_quad_mode : SQ_CF_ALLOC_EXPORT_WORD1_WHOLE_QUAD_MODE_SIZE;
- unsigned int barrier : SQ_CF_ALLOC_EXPORT_WORD1_BARRIER_SIZE;
- } sq_cf_alloc_export_word1_t;
-
-#elif defined(BIGENDIAN_CPU)
-
- typedef struct _sq_cf_alloc_export_word1_t {
- unsigned int barrier : SQ_CF_ALLOC_EXPORT_WORD1_BARRIER_SIZE;
- unsigned int whole_quad_mode : SQ_CF_ALLOC_EXPORT_WORD1_WHOLE_QUAD_MODE_SIZE;
- unsigned int cf_inst : SQ_CF_ALLOC_EXPORT_WORD1_CF_INST_SIZE;
- unsigned int valid_pixel_mode : SQ_CF_ALLOC_EXPORT_WORD1_VALID_PIXEL_MODE_SIZE;
- unsigned int end_of_program : SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM_SIZE;
- unsigned int burst_count : SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT_SIZE;
- unsigned int : 17;
- } sq_cf_alloc_export_word1_t;
-
-#endif
-
-typedef union {
- unsigned int val : 32;
- sq_cf_alloc_export_word1_t f;
-} sq_cf_alloc_export_word1_u;
-
-
-/*
- * SQ_CF_ALLOC_EXPORT_WORD1_BUF struct
- */
-
-#define SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE_SIZE 12
-#define SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK_SIZE 4
-
-#define SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE_SHIFT 0
-#define SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK_SHIFT 12
-
-#define SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE_MASK 0x00000fff
-#define SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK_MASK 0x0000f000
-
-#define SQ_CF_ALLOC_EXPORT_WORD1_BUF_MASK \
- (SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE_MASK | \
- SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK_MASK)
-
-#define SQ_CF_ALLOC_EXPORT_WORD1_BUF_DEFAULT 0x0000cdcd
-
-#define SQ_CF_ALLOC_EXPORT_WORD1_BUF_GET_ARRAY_SIZE(sq_cf_alloc_export_word1_buf) \
- ((sq_cf_alloc_export_word1_buf & SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE_MASK) >> SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE_SHIFT)
-#define SQ_CF_ALLOC_EXPORT_WORD1_BUF_GET_COMP_MASK(sq_cf_alloc_export_word1_buf) \
- ((sq_cf_alloc_export_word1_buf & SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK_MASK) >> SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK_SHIFT)
-
-#define SQ_CF_ALLOC_EXPORT_WORD1_BUF_SET_ARRAY_SIZE(sq_cf_alloc_export_word1_buf_reg, array_size) \
- sq_cf_alloc_export_word1_buf_reg = (sq_cf_alloc_export_word1_buf_reg & ~SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE_MASK) | (array_size << SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE_SHIFT)
-#define SQ_CF_ALLOC_EXPORT_WORD1_BUF_SET_COMP_MASK(sq_cf_alloc_export_word1_buf_reg, comp_mask) \
- sq_cf_alloc_export_word1_buf_reg = (sq_cf_alloc_export_word1_buf_reg & ~SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK_MASK) | (comp_mask << SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK_SHIFT)
-
-#if defined(LITTLEENDIAN_CPU)
-
- typedef struct _sq_cf_alloc_export_word1_buf_t {
- unsigned int array_size : SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE_SIZE;
- unsigned int comp_mask : SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK_SIZE;
- unsigned int : 16;
- } sq_cf_alloc_export_word1_buf_t;
-
-#elif defined(BIGENDIAN_CPU)
-
- typedef struct _sq_cf_alloc_export_word1_buf_t {
- unsigned int : 16;
- unsigned int comp_mask : SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK_SIZE;
- unsigned int array_size : SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE_SIZE;
- } sq_cf_alloc_export_word1_buf_t;
-
-#endif
-
-typedef union {
- unsigned int val : 32;
- sq_cf_alloc_export_word1_buf_t f;
-} sq_cf_alloc_export_word1_buf_u;
-
-
-/*
- * SQ_CF_ALLOC_EXPORT_WORD1_SWIZ struct
- */
-
-#define SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X_SIZE 3
-#define SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y_SIZE 3
-#define SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z_SIZE 3
-#define SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W_SIZE 3
-
-#define SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X_SHIFT 0
-#define SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y_SHIFT 3
-#define SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z_SHIFT 6
-#define SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W_SHIFT 9
-
-#define SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X_MASK 0x00000007
-#define SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y_MASK 0x00000038
-#define SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z_MASK 0x000001c0
-#define SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W_MASK 0x00000e00
-
-#define SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_MASK \
- (SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X_MASK | \
- SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y_MASK | \
- SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z_MASK | \
- SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W_MASK)
-
-#define SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_DEFAULT 0x00000dcd
-
-#define SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_GET_SEL_X(sq_cf_alloc_export_word1_swiz) \
- ((sq_cf_alloc_export_word1_swiz & SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X_MASK) >> SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X_SHIFT)
-#define SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_GET_SEL_Y(sq_cf_alloc_export_word1_swiz) \
- ((sq_cf_alloc_export_word1_swiz & SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y_MASK) >> SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y_SHIFT)
-#define SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_GET_SEL_Z(sq_cf_alloc_export_word1_swiz) \
- ((sq_cf_alloc_export_word1_swiz & SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z_MASK) >> SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z_SHIFT)
-#define SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_GET_SEL_W(sq_cf_alloc_export_word1_swiz) \
- ((sq_cf_alloc_export_word1_swiz & SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W_MASK) >> SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W_SHIFT)
-
-#define SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SET_SEL_X(sq_cf_alloc_export_word1_swiz_reg, sel_x) \
- sq_cf_alloc_export_word1_swiz_reg = (sq_cf_alloc_export_word1_swiz_reg & ~SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X_MASK) | (sel_x << SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X_SHIFT)
-#define SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SET_SEL_Y(sq_cf_alloc_export_word1_swiz_reg, sel_y) \
- sq_cf_alloc_export_word1_swiz_reg = (sq_cf_alloc_export_word1_swiz_reg & ~SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y_MASK) | (sel_y << SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y_SHIFT)
-#define SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SET_SEL_Z(sq_cf_alloc_export_word1_swiz_reg, sel_z) \
- sq_cf_alloc_export_word1_swiz_reg = (sq_cf_alloc_export_word1_swiz_reg & ~SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z_MASK) | (sel_z << SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z_SHIFT)
-#define SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SET_SEL_W(sq_cf_alloc_export_word1_swiz_reg, sel_w) \
- sq_cf_alloc_export_word1_swiz_reg = (sq_cf_alloc_export_word1_swiz_reg & ~SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W_MASK) | (sel_w << SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W_SHIFT)
-
-#if defined(LITTLEENDIAN_CPU)
-
- typedef struct _sq_cf_alloc_export_word1_swiz_t {
- unsigned int sel_x : SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X_SIZE;
- unsigned int sel_y : SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y_SIZE;
- unsigned int sel_z : SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z_SIZE;
- unsigned int sel_w : SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W_SIZE;
- unsigned int : 20;
- } sq_cf_alloc_export_word1_swiz_t;
-
-#elif defined(BIGENDIAN_CPU)
-
- typedef struct _sq_cf_alloc_export_word1_swiz_t {
- unsigned int : 20;
- unsigned int sel_w : SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W_SIZE;
- unsigned int sel_z : SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z_SIZE;
- unsigned int sel_y : SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y_SIZE;
- unsigned int sel_x : SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X_SIZE;
- } sq_cf_alloc_export_word1_swiz_t;
-
-#endif
-
-typedef union {
- unsigned int val : 32;
- sq_cf_alloc_export_word1_swiz_t f;
-} sq_cf_alloc_export_word1_swiz_u;
-
-
-/*
- * SQ_ALU_WORD0 struct
- */
-
-#define SQ_ALU_WORD0_SRC0_SEL_SIZE 9
-#define SQ_ALU_WORD0_SRC0_REL_SIZE 1
-#define SQ_ALU_WORD0_SRC0_CHAN_SIZE 2
-#define SQ_ALU_WORD0_SRC0_NEG_SIZE 1
-#define SQ_ALU_WORD0_SRC1_SEL_SIZE 9
-#define SQ_ALU_WORD0_SRC1_REL_SIZE 1
-#define SQ_ALU_WORD0_SRC1_CHAN_SIZE 2
-#define SQ_ALU_WORD0_SRC1_NEG_SIZE 1
-#define SQ_ALU_WORD0_INDEX_MODE_SIZE 3
-#define SQ_ALU_WORD0_PRED_SEL_SIZE 2
-#define SQ_ALU_WORD0_LAST_SIZE 1
-
-#define SQ_ALU_WORD0_SRC0_SEL_SHIFT 0
-#define SQ_ALU_WORD0_SRC0_REL_SHIFT 9
-#define SQ_ALU_WORD0_SRC0_CHAN_SHIFT 10
-#define SQ_ALU_WORD0_SRC0_NEG_SHIFT 12
-#define SQ_ALU_WORD0_SRC1_SEL_SHIFT 13
-#define SQ_ALU_WORD0_SRC1_REL_SHIFT 22
-#define SQ_ALU_WORD0_SRC1_CHAN_SHIFT 23
-#define SQ_ALU_WORD0_SRC1_NEG_SHIFT 25
-#define SQ_ALU_WORD0_INDEX_MODE_SHIFT 26
-#define SQ_ALU_WORD0_PRED_SEL_SHIFT 29
-#define SQ_ALU_WORD0_LAST_SHIFT 31
-
-#define SQ_ALU_WORD0_SRC0_SEL_MASK 0x000001ff
-#define SQ_ALU_WORD0_SRC0_REL_MASK 0x00000200
-#define SQ_ALU_WORD0_SRC0_CHAN_MASK 0x00000c00
-#define SQ_ALU_WORD0_SRC0_NEG_MASK 0x00001000
-#define SQ_ALU_WORD0_SRC1_SEL_MASK 0x003fe000
-#define SQ_ALU_WORD0_SRC1_REL_MASK 0x00400000
-#define SQ_ALU_WORD0_SRC1_CHAN_MASK 0x01800000
-#define SQ_ALU_WORD0_SRC1_NEG_MASK 0x02000000
-#define SQ_ALU_WORD0_INDEX_MODE_MASK 0x1c000000
-#define SQ_ALU_WORD0_PRED_SEL_MASK 0x60000000
-#define SQ_ALU_WORD0_LAST_MASK 0x80000000
-
-#define SQ_ALU_WORD0_MASK \
- (SQ_ALU_WORD0_SRC0_SEL_MASK | \
- SQ_ALU_WORD0_SRC0_REL_MASK | \
- SQ_ALU_WORD0_SRC0_CHAN_MASK | \
- SQ_ALU_WORD0_SRC0_NEG_MASK | \
- SQ_ALU_WORD0_SRC1_SEL_MASK | \
- SQ_ALU_WORD0_SRC1_REL_MASK | \
- SQ_ALU_WORD0_SRC1_CHAN_MASK | \
- SQ_ALU_WORD0_SRC1_NEG_MASK | \
- SQ_ALU_WORD0_INDEX_MODE_MASK | \
- SQ_ALU_WORD0_PRED_SEL_MASK | \
- SQ_ALU_WORD0_LAST_MASK)
-
-#define SQ_ALU_WORD0_DEFAULT 0xcdcdcdcd
-
-#define SQ_ALU_WORD0_GET_SRC0_SEL(sq_alu_word0) \
- ((sq_alu_word0 & SQ_ALU_WORD0_SRC0_SEL_MASK) >> SQ_ALU_WORD0_SRC0_SEL_SHIFT)
-#define SQ_ALU_WORD0_GET_SRC0_REL(sq_alu_word0) \
- ((sq_alu_word0 & SQ_ALU_WORD0_SRC0_REL_MASK) >> SQ_ALU_WORD0_SRC0_REL_SHIFT)
-#define SQ_ALU_WORD0_GET_SRC0_CHAN(sq_alu_word0) \
- ((sq_alu_word0 & SQ_ALU_WORD0_SRC0_CHAN_MASK) >> SQ_ALU_WORD0_SRC0_CHAN_SHIFT)
-#define SQ_ALU_WORD0_GET_SRC0_NEG(sq_alu_word0) \
- ((sq_alu_word0 & SQ_ALU_WORD0_SRC0_NEG_MASK) >> SQ_ALU_WORD0_SRC0_NEG_SHIFT)
-#define SQ_ALU_WORD0_GET_SRC1_SEL(sq_alu_word0) \
- ((sq_alu_word0 & SQ_ALU_WORD0_SRC1_SEL_MASK) >> SQ_ALU_WORD0_SRC1_SEL_SHIFT)
-#define SQ_ALU_WORD0_GET_SRC1_REL(sq_alu_word0) \
- ((sq_alu_word0 & SQ_ALU_WORD0_SRC1_REL_MASK) >> SQ_ALU_WORD0_SRC1_REL_SHIFT)
-#define SQ_ALU_WORD0_GET_SRC1_CHAN(sq_alu_word0) \
- ((sq_alu_word0 & SQ_ALU_WORD0_SRC1_CHAN_MASK) >> SQ_ALU_WORD0_SRC1_CHAN_SHIFT)
-#define SQ_ALU_WORD0_GET_SRC1_NEG(sq_alu_word0) \
- ((sq_alu_word0 & SQ_ALU_WORD0_SRC1_NEG_MASK) >> SQ_ALU_WORD0_SRC1_NEG_SHIFT)
-#define SQ_ALU_WORD0_GET_INDEX_MODE(sq_alu_word0) \
- ((sq_alu_word0 & SQ_ALU_WORD0_INDEX_MODE_MASK) >> SQ_ALU_WORD0_INDEX_MODE_SHIFT)
-#define SQ_ALU_WORD0_GET_PRED_SEL(sq_alu_word0) \
- ((sq_alu_word0 & SQ_ALU_WORD0_PRED_SEL_MASK) >> SQ_ALU_WORD0_PRED_SEL_SHIFT)
-#define SQ_ALU_WORD0_GET_LAST(sq_alu_word0) \
- ((sq_alu_word0 & SQ_ALU_WORD0_LAST_MASK) >> SQ_ALU_WORD0_LAST_SHIFT)
-
-#define SQ_ALU_WORD0_SET_SRC0_SEL(sq_alu_word0_reg, src0_sel) \
- sq_alu_word0_reg = (sq_alu_word0_reg & ~SQ_ALU_WORD0_SRC0_SEL_MASK) | (src0_sel << SQ_ALU_WORD0_SRC0_SEL_SHIFT)
-#define SQ_ALU_WORD0_SET_SRC0_REL(sq_alu_word0_reg, src0_rel) \
- sq_alu_word0_reg = (sq_alu_word0_reg & ~SQ_ALU_WORD0_SRC0_REL_MASK) | (src0_rel << SQ_ALU_WORD0_SRC0_REL_SHIFT)
-#define SQ_ALU_WORD0_SET_SRC0_CHAN(sq_alu_word0_reg, src0_chan) \
- sq_alu_word0_reg = (sq_alu_word0_reg & ~SQ_ALU_WORD0_SRC0_CHAN_MASK) | (src0_chan << SQ_ALU_WORD0_SRC0_CHAN_SHIFT)
-#define SQ_ALU_WORD0_SET_SRC0_NEG(sq_alu_word0_reg, src0_neg) \
- sq_alu_word0_reg = (sq_alu_word0_reg & ~SQ_ALU_WORD0_SRC0_NEG_MASK) | (src0_neg << SQ_ALU_WORD0_SRC0_NEG_SHIFT)
-#define SQ_ALU_WORD0_SET_SRC1_SEL(sq_alu_word0_reg, src1_sel) \
- sq_alu_word0_reg = (sq_alu_word0_reg & ~SQ_ALU_WORD0_SRC1_SEL_MASK) | (src1_sel << SQ_ALU_WORD0_SRC1_SEL_SHIFT)
-#define SQ_ALU_WORD0_SET_SRC1_REL(sq_alu_word0_reg, src1_rel) \
- sq_alu_word0_reg = (sq_alu_word0_reg & ~SQ_ALU_WORD0_SRC1_REL_MASK) | (src1_rel << SQ_ALU_WORD0_SRC1_REL_SHIFT)
-#define SQ_ALU_WORD0_SET_SRC1_CHAN(sq_alu_word0_reg, src1_chan) \
- sq_alu_word0_reg = (sq_alu_word0_reg & ~SQ_ALU_WORD0_SRC1_CHAN_MASK) | (src1_chan << SQ_ALU_WORD0_SRC1_CHAN_SHIFT)
-#define SQ_ALU_WORD0_SET_SRC1_NEG(sq_alu_word0_reg, src1_neg) \
- sq_alu_word0_reg = (sq_alu_word0_reg & ~SQ_ALU_WORD0_SRC1_NEG_MASK) | (src1_neg << SQ_ALU_WORD0_SRC1_NEG_SHIFT)
-#define SQ_ALU_WORD0_SET_INDEX_MODE(sq_alu_word0_reg, index_mode) \
- sq_alu_word0_reg = (sq_alu_word0_reg & ~SQ_ALU_WORD0_INDEX_MODE_MASK) | (index_mode << SQ_ALU_WORD0_INDEX_MODE_SHIFT)
-#define SQ_ALU_WORD0_SET_PRED_SEL(sq_alu_word0_reg, pred_sel) \
- sq_alu_word0_reg = (sq_alu_word0_reg & ~SQ_ALU_WORD0_PRED_SEL_MASK) | (pred_sel << SQ_ALU_WORD0_PRED_SEL_SHIFT)
-#define SQ_ALU_WORD0_SET_LAST(sq_alu_word0_reg, last) \
- sq_alu_word0_reg = (sq_alu_word0_reg & ~SQ_ALU_WORD0_LAST_MASK) | (last << SQ_ALU_WORD0_LAST_SHIFT)
-
-#if defined(LITTLEENDIAN_CPU)
-
- typedef struct _sq_alu_word0_t {
- unsigned int src0_sel : SQ_ALU_WORD0_SRC0_SEL_SIZE;
- unsigned int src0_rel : SQ_ALU_WORD0_SRC0_REL_SIZE;
- unsigned int src0_chan : SQ_ALU_WORD0_SRC0_CHAN_SIZE;
- unsigned int src0_neg : SQ_ALU_WORD0_SRC0_NEG_SIZE;
- unsigned int src1_sel : SQ_ALU_WORD0_SRC1_SEL_SIZE;
- unsigned int src1_rel : SQ_ALU_WORD0_SRC1_REL_SIZE;
- unsigned int src1_chan : SQ_ALU_WORD0_SRC1_CHAN_SIZE;
- unsigned int src1_neg : SQ_ALU_WORD0_SRC1_NEG_SIZE;
- unsigned int index_mode : SQ_ALU_WORD0_INDEX_MODE_SIZE;
- unsigned int pred_sel : SQ_ALU_WORD0_PRED_SEL_SIZE;
- unsigned int last : SQ_ALU_WORD0_LAST_SIZE;
- } sq_alu_word0_t;
-
-#elif defined(BIGENDIAN_CPU)
-
- typedef struct _sq_alu_word0_t {
- unsigned int last : SQ_ALU_WORD0_LAST_SIZE;
- unsigned int pred_sel : SQ_ALU_WORD0_PRED_SEL_SIZE;
- unsigned int index_mode : SQ_ALU_WORD0_INDEX_MODE_SIZE;
- unsigned int src1_neg : SQ_ALU_WORD0_SRC1_NEG_SIZE;
- unsigned int src1_chan : SQ_ALU_WORD0_SRC1_CHAN_SIZE;
- unsigned int src1_rel : SQ_ALU_WORD0_SRC1_REL_SIZE;
- unsigned int src1_sel : SQ_ALU_WORD0_SRC1_SEL_SIZE;
- unsigned int src0_neg : SQ_ALU_WORD0_SRC0_NEG_SIZE;
- unsigned int src0_chan : SQ_ALU_WORD0_SRC0_CHAN_SIZE;
- unsigned int src0_rel : SQ_ALU_WORD0_SRC0_REL_SIZE;
- unsigned int src0_sel : SQ_ALU_WORD0_SRC0_SEL_SIZE;
- } sq_alu_word0_t;
-
-#endif
-
-typedef union {
- unsigned int val : 32;
- sq_alu_word0_t f;
-} sq_alu_word0_u;
-
-
-/*
- * SQ_ALU_WORD1 struct
- */
-
-#define SQ_ALU_WORD1_ENCODING_SIZE 3
-#define SQ_ALU_WORD1_BANK_SWIZZLE_SIZE 3
-#define SQ_ALU_WORD1_DST_GPR_SIZE 7
-#define SQ_ALU_WORD1_DST_REL_SIZE 1
-#define SQ_ALU_WORD1_DST_CHAN_SIZE 2
-#define SQ_ALU_WORD1_CLAMP_SIZE 1
-
-#define SQ_ALU_WORD1_ENCODING_SHIFT 15
-#define SQ_ALU_WORD1_BANK_SWIZZLE_SHIFT 18
-#define SQ_ALU_WORD1_DST_GPR_SHIFT 21
-#define SQ_ALU_WORD1_DST_REL_SHIFT 28
-#define SQ_ALU_WORD1_DST_CHAN_SHIFT 29
-#define SQ_ALU_WORD1_CLAMP_SHIFT 31
-
-#define SQ_ALU_WORD1_ENCODING_MASK 0x00038000
-#define SQ_ALU_WORD1_BANK_SWIZZLE_MASK 0x001c0000
-#define SQ_ALU_WORD1_DST_GPR_MASK 0x0fe00000
-#define SQ_ALU_WORD1_DST_REL_MASK 0x10000000
-#define SQ_ALU_WORD1_DST_CHAN_MASK 0x60000000
-#define SQ_ALU_WORD1_CLAMP_MASK 0x80000000
-
-#define SQ_ALU_WORD1_MASK \
- (SQ_ALU_WORD1_ENCODING_MASK | \
- SQ_ALU_WORD1_BANK_SWIZZLE_MASK | \
- SQ_ALU_WORD1_DST_GPR_MASK | \
- SQ_ALU_WORD1_DST_REL_MASK | \
- SQ_ALU_WORD1_DST_CHAN_MASK | \
- SQ_ALU_WORD1_CLAMP_MASK)
-
-#define SQ_ALU_WORD1_DEFAULT 0xcdcd8000
-
-#define SQ_ALU_WORD1_GET_ENCODING(sq_alu_word1) \
- ((sq_alu_word1 & SQ_ALU_WORD1_ENCODING_MASK) >> SQ_ALU_WORD1_ENCODING_SHIFT)
-#define SQ_ALU_WORD1_GET_BANK_SWIZZLE(sq_alu_word1) \
- ((sq_alu_word1 & SQ_ALU_WORD1_BANK_SWIZZLE_MASK) >> SQ_ALU_WORD1_BANK_SWIZZLE_SHIFT)
-#define SQ_ALU_WORD1_GET_DST_GPR(sq_alu_word1) \
- ((sq_alu_word1 & SQ_ALU_WORD1_DST_GPR_MASK) >> SQ_ALU_WORD1_DST_GPR_SHIFT)
-#define SQ_ALU_WORD1_GET_DST_REL(sq_alu_word1) \
- ((sq_alu_word1 & SQ_ALU_WORD1_DST_REL_MASK) >> SQ_ALU_WORD1_DST_REL_SHIFT)
-#define SQ_ALU_WORD1_GET_DST_CHAN(sq_alu_word1) \
- ((sq_alu_word1 & SQ_ALU_WORD1_DST_CHAN_MASK) >> SQ_ALU_WORD1_DST_CHAN_SHIFT)
-#define SQ_ALU_WORD1_GET_CLAMP(sq_alu_word1) \
- ((sq_alu_word1 & SQ_ALU_WORD1_CLAMP_MASK) >> SQ_ALU_WORD1_CLAMP_SHIFT)
-
-#define SQ_ALU_WORD1_SET_ENCODING(sq_alu_word1_reg, encoding) \
- sq_alu_word1_reg = (sq_alu_word1_reg & ~SQ_ALU_WORD1_ENCODING_MASK) | (encoding << SQ_ALU_WORD1_ENCODING_SHIFT)
-#define SQ_ALU_WORD1_SET_BANK_SWIZZLE(sq_alu_word1_reg, bank_swizzle) \
- sq_alu_word1_reg = (sq_alu_word1_reg & ~SQ_ALU_WORD1_BANK_SWIZZLE_MASK) | (bank_swizzle << SQ_ALU_WORD1_BANK_SWIZZLE_SHIFT)
-#define SQ_ALU_WORD1_SET_DST_GPR(sq_alu_word1_reg, dst_gpr) \
- sq_alu_word1_reg = (sq_alu_word1_reg & ~SQ_ALU_WORD1_DST_GPR_MASK) | (dst_gpr << SQ_ALU_WORD1_DST_GPR_SHIFT)
-#define SQ_ALU_WORD1_SET_DST_REL(sq_alu_word1_reg, dst_rel) \
- sq_alu_word1_reg = (sq_alu_word1_reg & ~SQ_ALU_WORD1_DST_REL_MASK) | (dst_rel << SQ_ALU_WORD1_DST_REL_SHIFT)
-#define SQ_ALU_WORD1_SET_DST_CHAN(sq_alu_word1_reg, dst_chan) \
- sq_alu_word1_reg = (sq_alu_word1_reg & ~SQ_ALU_WORD1_DST_CHAN_MASK) | (dst_chan << SQ_ALU_WORD1_DST_CHAN_SHIFT)
-#define SQ_ALU_WORD1_SET_CLAMP(sq_alu_word1_reg, clamp) \
- sq_alu_word1_reg = (sq_alu_word1_reg & ~SQ_ALU_WORD1_CLAMP_MASK) | (clamp << SQ_ALU_WORD1_CLAMP_SHIFT)
-
-#if defined(LITTLEENDIAN_CPU)
-
- typedef struct _sq_alu_word1_t {
- unsigned int : 15;
- unsigned int encoding : SQ_ALU_WORD1_ENCODING_SIZE;
- unsigned int bank_swizzle : SQ_ALU_WORD1_BANK_SWIZZLE_SIZE;
- unsigned int dst_gpr : SQ_ALU_WORD1_DST_GPR_SIZE;
- unsigned int dst_rel : SQ_ALU_WORD1_DST_REL_SIZE;
- unsigned int dst_chan : SQ_ALU_WORD1_DST_CHAN_SIZE;
- unsigned int clamp : SQ_ALU_WORD1_CLAMP_SIZE;
- } sq_alu_word1_t;
-
-#elif defined(BIGENDIAN_CPU)
-
- typedef struct _sq_alu_word1_t {
- unsigned int clamp : SQ_ALU_WORD1_CLAMP_SIZE;
- unsigned int dst_chan : SQ_ALU_WORD1_DST_CHAN_SIZE;
- unsigned int dst_rel : SQ_ALU_WORD1_DST_REL_SIZE;
- unsigned int dst_gpr : SQ_ALU_WORD1_DST_GPR_SIZE;
- unsigned int bank_swizzle : SQ_ALU_WORD1_BANK_SWIZZLE_SIZE;
- unsigned int encoding : SQ_ALU_WORD1_ENCODING_SIZE;
- unsigned int : 15;
- } sq_alu_word1_t;
-
-#endif
-
-typedef union {
- unsigned int val : 32;
- sq_alu_word1_t f;
-} sq_alu_word1_u;
-
-
-/*
- * SQ_ALU_WORD1_OP2_V2 struct
- */
-
-#define SQ_ALU_WORD1_OP2_V2_SRC0_ABS_SIZE 1
-#define SQ_ALU_WORD1_OP2_V2_SRC1_ABS_SIZE 1
-#define SQ_ALU_WORD1_OP2_V2_UPDATE_EXECUTE_MASK_SIZE 1
-#define SQ_ALU_WORD1_OP2_V2_UPDATE_PRED_SIZE 1
-#define SQ_ALU_WORD1_OP2_V2_WRITE_MASK_SIZE 1
-#define SQ_ALU_WORD1_OP2_V2_OMOD_SIZE 2
-#define SQ_ALU_WORD1_OP2_V2_ALU_INST_SIZE 11
-
-#define SQ_ALU_WORD1_OP2_V2_SRC0_ABS_SHIFT 0
-#define SQ_ALU_WORD1_OP2_V2_SRC1_ABS_SHIFT 1
-#define SQ_ALU_WORD1_OP2_V2_UPDATE_EXECUTE_MASK_SHIFT 2
-#define SQ_ALU_WORD1_OP2_V2_UPDATE_PRED_SHIFT 3
-#define SQ_ALU_WORD1_OP2_V2_WRITE_MASK_SHIFT 4
-#define SQ_ALU_WORD1_OP2_V2_OMOD_SHIFT 5
-#define SQ_ALU_WORD1_OP2_V2_ALU_INST_SHIFT 7
-
-#define SQ_ALU_WORD1_OP2_V2_SRC0_ABS_MASK 0x00000001
-#define SQ_ALU_WORD1_OP2_V2_SRC1_ABS_MASK 0x00000002
-#define SQ_ALU_WORD1_OP2_V2_UPDATE_EXECUTE_MASK_MASK 0x00000004
-#define SQ_ALU_WORD1_OP2_V2_UPDATE_PRED_MASK 0x00000008
-#define SQ_ALU_WORD1_OP2_V2_WRITE_MASK_MASK 0x00000010
-#define SQ_ALU_WORD1_OP2_V2_OMOD_MASK 0x00000060
-#define SQ_ALU_WORD1_OP2_V2_ALU_INST_MASK 0x0003ff80
-
-#define SQ_ALU_WORD1_OP2_V2_MASK \
- (SQ_ALU_WORD1_OP2_V2_SRC0_ABS_MASK | \
- SQ_ALU_WORD1_OP2_V2_SRC1_ABS_MASK | \
- SQ_ALU_WORD1_OP2_V2_UPDATE_EXECUTE_MASK_MASK | \
- SQ_ALU_WORD1_OP2_V2_UPDATE_PRED_MASK | \
- SQ_ALU_WORD1_OP2_V2_WRITE_MASK_MASK | \
- SQ_ALU_WORD1_OP2_V2_OMOD_MASK | \
- SQ_ALU_WORD1_OP2_V2_ALU_INST_MASK)
-
-#define SQ_ALU_WORD1_OP2_V2_DEFAULT 0x0001cdcd
-
-#define SQ_ALU_WORD1_OP2_V2_GET_SRC0_ABS(sq_alu_word1_op2_v2) \
- ((sq_alu_word1_op2_v2 & SQ_ALU_WORD1_OP2_V2_SRC0_ABS_MASK) >> SQ_ALU_WORD1_OP2_V2_SRC0_ABS_SHIFT)
-#define SQ_ALU_WORD1_OP2_V2_GET_SRC1_ABS(sq_alu_word1_op2_v2) \
- ((sq_alu_word1_op2_v2 & SQ_ALU_WORD1_OP2_V2_SRC1_ABS_MASK) >> SQ_ALU_WORD1_OP2_V2_SRC1_ABS_SHIFT)
-#define SQ_ALU_WORD1_OP2_V2_GET_UPDATE_EXECUTE_MASK(sq_alu_word1_op2_v2) \
- ((sq_alu_word1_op2_v2 & SQ_ALU_WORD1_OP2_V2_UPDATE_EXECUTE_MASK_MASK) >> SQ_ALU_WORD1_OP2_V2_UPDATE_EXECUTE_MASK_SHIFT)
-#define SQ_ALU_WORD1_OP2_V2_GET_UPDATE_PRED(sq_alu_word1_op2_v2) \
- ((sq_alu_word1_op2_v2 & SQ_ALU_WORD1_OP2_V2_UPDATE_PRED_MASK) >> SQ_ALU_WORD1_OP2_V2_UPDATE_PRED_SHIFT)
-#define SQ_ALU_WORD1_OP2_V2_GET_WRITE_MASK(sq_alu_word1_op2_v2) \
- ((sq_alu_word1_op2_v2 & SQ_ALU_WORD1_OP2_V2_WRITE_MASK_MASK) >> SQ_ALU_WORD1_OP2_V2_WRITE_MASK_SHIFT)
-#define SQ_ALU_WORD1_OP2_V2_GET_OMOD(sq_alu_word1_op2_v2) \
- ((sq_alu_word1_op2_v2 & SQ_ALU_WORD1_OP2_V2_OMOD_MASK) >> SQ_ALU_WORD1_OP2_V2_OMOD_SHIFT)
-#define SQ_ALU_WORD1_OP2_V2_GET_ALU_INST(sq_alu_word1_op2_v2) \
- ((sq_alu_word1_op2_v2 & SQ_ALU_WORD1_OP2_V2_ALU_INST_MASK) >> SQ_ALU_WORD1_OP2_V2_ALU_INST_SHIFT)
-
-#define SQ_ALU_WORD1_OP2_V2_SET_SRC0_ABS(sq_alu_word1_op2_v2_reg, src0_abs) \
- sq_alu_word1_op2_v2_reg = (sq_alu_word1_op2_v2_reg & ~SQ_ALU_WORD1_OP2_V2_SRC0_ABS_MASK) | (src0_abs << SQ_ALU_WORD1_OP2_V2_SRC0_ABS_SHIFT)
-#define SQ_ALU_WORD1_OP2_V2_SET_SRC1_ABS(sq_alu_word1_op2_v2_reg, src1_abs) \
- sq_alu_word1_op2_v2_reg = (sq_alu_word1_op2_v2_reg & ~SQ_ALU_WORD1_OP2_V2_SRC1_ABS_MASK) | (src1_abs << SQ_ALU_WORD1_OP2_V2_SRC1_ABS_SHIFT)
-#define SQ_ALU_WORD1_OP2_V2_SET_UPDATE_EXECUTE_MASK(sq_alu_word1_op2_v2_reg, update_execute_mask) \
- sq_alu_word1_op2_v2_reg = (sq_alu_word1_op2_v2_reg & ~SQ_ALU_WORD1_OP2_V2_UPDATE_EXECUTE_MASK_MASK) | (update_execute_mask << SQ_ALU_WORD1_OP2_V2_UPDATE_EXECUTE_MASK_SHIFT)
-#define SQ_ALU_WORD1_OP2_V2_SET_UPDATE_PRED(sq_alu_word1_op2_v2_reg, update_pred) \
- sq_alu_word1_op2_v2_reg = (sq_alu_word1_op2_v2_reg & ~SQ_ALU_WORD1_OP2_V2_UPDATE_PRED_MASK) | (update_pred << SQ_ALU_WORD1_OP2_V2_UPDATE_PRED_SHIFT)
-#define SQ_ALU_WORD1_OP2_V2_SET_WRITE_MASK(sq_alu_word1_op2_v2_reg, write_mask) \
- sq_alu_word1_op2_v2_reg = (sq_alu_word1_op2_v2_reg & ~SQ_ALU_WORD1_OP2_V2_WRITE_MASK_MASK) | (write_mask << SQ_ALU_WORD1_OP2_V2_WRITE_MASK_SHIFT)
-#define SQ_ALU_WORD1_OP2_V2_SET_OMOD(sq_alu_word1_op2_v2_reg, omod) \
- sq_alu_word1_op2_v2_reg = (sq_alu_word1_op2_v2_reg & ~SQ_ALU_WORD1_OP2_V2_OMOD_MASK) | (omod << SQ_ALU_WORD1_OP2_V2_OMOD_SHIFT)
-#define SQ_ALU_WORD1_OP2_V2_SET_ALU_INST(sq_alu_word1_op2_v2_reg, alu_inst) \
- sq_alu_word1_op2_v2_reg = (sq_alu_word1_op2_v2_reg & ~SQ_ALU_WORD1_OP2_V2_ALU_INST_MASK) | (alu_inst << SQ_ALU_WORD1_OP2_V2_ALU_INST_SHIFT)
-
-#if defined(LITTLEENDIAN_CPU)
-
- typedef struct _sq_alu_word1_op2_v2_t {
- unsigned int src0_abs : SQ_ALU_WORD1_OP2_V2_SRC0_ABS_SIZE;
- unsigned int src1_abs : SQ_ALU_WORD1_OP2_V2_SRC1_ABS_SIZE;
- unsigned int update_execute_mask : SQ_ALU_WORD1_OP2_V2_UPDATE_EXECUTE_MASK_SIZE;
- unsigned int update_pred : SQ_ALU_WORD1_OP2_V2_UPDATE_PRED_SIZE;
- unsigned int write_mask : SQ_ALU_WORD1_OP2_V2_WRITE_MASK_SIZE;
- unsigned int omod : SQ_ALU_WORD1_OP2_V2_OMOD_SIZE;
- unsigned int alu_inst : SQ_ALU_WORD1_OP2_V2_ALU_INST_SIZE;
- unsigned int : 14;
- } sq_alu_word1_op2_v2_t;
-
-#elif defined(BIGENDIAN_CPU)
-
- typedef struct _sq_alu_word1_op2_v2_t {
- unsigned int : 14;
- unsigned int alu_inst : SQ_ALU_WORD1_OP2_V2_ALU_INST_SIZE;
- unsigned int omod : SQ_ALU_WORD1_OP2_V2_OMOD_SIZE;
- unsigned int write_mask : SQ_ALU_WORD1_OP2_V2_WRITE_MASK_SIZE;
- unsigned int update_pred : SQ_ALU_WORD1_OP2_V2_UPDATE_PRED_SIZE;
- unsigned int update_execute_mask : SQ_ALU_WORD1_OP2_V2_UPDATE_EXECUTE_MASK_SIZE;
- unsigned int src1_abs : SQ_ALU_WORD1_OP2_V2_SRC1_ABS_SIZE;
- unsigned int src0_abs : SQ_ALU_WORD1_OP2_V2_SRC0_ABS_SIZE;
- } sq_alu_word1_op2_v2_t;
-
-#endif
-
-#if defined(LITTLEENDIAN_CPU)
-
- typedef struct _sq_alu_word1_op2_r6xx_t {
- unsigned int src0_abs : SQ_ALU_WORD1_OP2_V2_SRC0_ABS_SIZE;
- unsigned int src1_abs : SQ_ALU_WORD1_OP2_V2_SRC1_ABS_SIZE;
- unsigned int update_execute_mask : SQ_ALU_WORD1_OP2_V2_UPDATE_EXECUTE_MASK_SIZE;
- unsigned int update_pred : SQ_ALU_WORD1_OP2_V2_UPDATE_PRED_SIZE;
- unsigned int write_mask : SQ_ALU_WORD1_OP2_V2_WRITE_MASK_SIZE;
- unsigned int fog_export : 1;
- unsigned int omod : SQ_ALU_WORD1_OP2_V2_OMOD_SIZE;
- unsigned int alu_inst : 10;
- unsigned int : 14;
- } sq_alu_word1_op2_v1_t;
-
-#elif defined(BIGENDIAN_CPU)
-
- typedef struct _sq_alu_word1_op2_r6xx_t {
- unsigned int : 14;
- unsigned int alu_inst : 10;
- unsigned int omod : SQ_ALU_WORD1_OP2_V2_OMOD_SIZE;
- unsigned int fog_export : 1;
- unsigned int write_mask : SQ_ALU_WORD1_OP2_V2_WRITE_MASK_SIZE;
- unsigned int update_pred : SQ_ALU_WORD1_OP2_V2_UPDATE_PRED_SIZE;
- unsigned int update_execute_mask : SQ_ALU_WORD1_OP2_V2_UPDATE_EXECUTE_MASK_SIZE;
- unsigned int src1_abs : SQ_ALU_WORD1_OP2_V2_SRC1_ABS_SIZE;
- unsigned int src0_abs : SQ_ALU_WORD1_OP2_V2_SRC0_ABS_SIZE;
- } sq_alu_word1_op2_v1_t;
-
-#endif
-
-typedef union {
- unsigned int val : 32;
- sq_alu_word1_op2_v2_t f;
- sq_alu_word1_op2_v1_t f6;
-} sq_alu_word1_op2_v2_u;
-
-
-/*
- * SQ_ALU_WORD1_OP3 struct
- */
-
-#define SQ_ALU_WORD1_OP3_SRC2_SEL_SIZE 9
-#define SQ_ALU_WORD1_OP3_SRC2_REL_SIZE 1
-#define SQ_ALU_WORD1_OP3_SRC2_CHAN_SIZE 2
-#define SQ_ALU_WORD1_OP3_SRC2_NEG_SIZE 1
-#define SQ_ALU_WORD1_OP3_ALU_INST_SIZE 5
-
-#define SQ_ALU_WORD1_OP3_SRC2_SEL_SHIFT 0
-#define SQ_ALU_WORD1_OP3_SRC2_REL_SHIFT 9
-#define SQ_ALU_WORD1_OP3_SRC2_CHAN_SHIFT 10
-#define SQ_ALU_WORD1_OP3_SRC2_NEG_SHIFT 12
-#define SQ_ALU_WORD1_OP3_ALU_INST_SHIFT 13
-
-#define SQ_ALU_WORD1_OP3_SRC2_SEL_MASK 0x000001ff
-#define SQ_ALU_WORD1_OP3_SRC2_REL_MASK 0x00000200
-#define SQ_ALU_WORD1_OP3_SRC2_CHAN_MASK 0x00000c00
-#define SQ_ALU_WORD1_OP3_SRC2_NEG_MASK 0x00001000
-#define SQ_ALU_WORD1_OP3_ALU_INST_MASK 0x0003e000
-
-#define SQ_ALU_WORD1_OP3_MASK \
- (SQ_ALU_WORD1_OP3_SRC2_SEL_MASK | \
- SQ_ALU_WORD1_OP3_SRC2_REL_MASK | \
- SQ_ALU_WORD1_OP3_SRC2_CHAN_MASK | \
- SQ_ALU_WORD1_OP3_SRC2_NEG_MASK | \
- SQ_ALU_WORD1_OP3_ALU_INST_MASK)
-
-#define SQ_ALU_WORD1_OP3_DEFAULT 0x0001cdcd
-
-#define SQ_ALU_WORD1_OP3_GET_SRC2_SEL(sq_alu_word1_op3) \
- ((sq_alu_word1_op3 & SQ_ALU_WORD1_OP3_SRC2_SEL_MASK) >> SQ_ALU_WORD1_OP3_SRC2_SEL_SHIFT)
-#define SQ_ALU_WORD1_OP3_GET_SRC2_REL(sq_alu_word1_op3) \
- ((sq_alu_word1_op3 & SQ_ALU_WORD1_OP3_SRC2_REL_MASK) >> SQ_ALU_WORD1_OP3_SRC2_REL_SHIFT)
-#define SQ_ALU_WORD1_OP3_GET_SRC2_CHAN(sq_alu_word1_op3) \
- ((sq_alu_word1_op3 & SQ_ALU_WORD1_OP3_SRC2_CHAN_MASK) >> SQ_ALU_WORD1_OP3_SRC2_CHAN_SHIFT)
-#define SQ_ALU_WORD1_OP3_GET_SRC2_NEG(sq_alu_word1_op3) \
- ((sq_alu_word1_op3 & SQ_ALU_WORD1_OP3_SRC2_NEG_MASK) >> SQ_ALU_WORD1_OP3_SRC2_NEG_SHIFT)
-#define SQ_ALU_WORD1_OP3_GET_ALU_INST(sq_alu_word1_op3) \
- ((sq_alu_word1_op3 & SQ_ALU_WORD1_OP3_ALU_INST_MASK) >> SQ_ALU_WORD1_OP3_ALU_INST_SHIFT)
-
-#define SQ_ALU_WORD1_OP3_SET_SRC2_SEL(sq_alu_word1_op3_reg, src2_sel) \
- sq_alu_word1_op3_reg = (sq_alu_word1_op3_reg & ~SQ_ALU_WORD1_OP3_SRC2_SEL_MASK) | (src2_sel << SQ_ALU_WORD1_OP3_SRC2_SEL_SHIFT)
-#define SQ_ALU_WORD1_OP3_SET_SRC2_REL(sq_alu_word1_op3_reg, src2_rel) \
- sq_alu_word1_op3_reg = (sq_alu_word1_op3_reg & ~SQ_ALU_WORD1_OP3_SRC2_REL_MASK) | (src2_rel << SQ_ALU_WORD1_OP3_SRC2_REL_SHIFT)
-#define SQ_ALU_WORD1_OP3_SET_SRC2_CHAN(sq_alu_word1_op3_reg, src2_chan) \
- sq_alu_word1_op3_reg = (sq_alu_word1_op3_reg & ~SQ_ALU_WORD1_OP3_SRC2_CHAN_MASK) | (src2_chan << SQ_ALU_WORD1_OP3_SRC2_CHAN_SHIFT)
-#define SQ_ALU_WORD1_OP3_SET_SRC2_NEG(sq_alu_word1_op3_reg, src2_neg) \
- sq_alu_word1_op3_reg = (sq_alu_word1_op3_reg & ~SQ_ALU_WORD1_OP3_SRC2_NEG_MASK) | (src2_neg << SQ_ALU_WORD1_OP3_SRC2_NEG_SHIFT)
-#define SQ_ALU_WORD1_OP3_SET_ALU_INST(sq_alu_word1_op3_reg, alu_inst) \
- sq_alu_word1_op3_reg = (sq_alu_word1_op3_reg & ~SQ_ALU_WORD1_OP3_ALU_INST_MASK) | (alu_inst << SQ_ALU_WORD1_OP3_ALU_INST_SHIFT)
-
-#if defined(LITTLEENDIAN_CPU)
-
- typedef struct _sq_alu_word1_op3_t {
- unsigned int src2_sel : SQ_ALU_WORD1_OP3_SRC2_SEL_SIZE;
- unsigned int src2_rel : SQ_ALU_WORD1_OP3_SRC2_REL_SIZE;
- unsigned int src2_chan : SQ_ALU_WORD1_OP3_SRC2_CHAN_SIZE;
- unsigned int src2_neg : SQ_ALU_WORD1_OP3_SRC2_NEG_SIZE;
- unsigned int alu_inst : SQ_ALU_WORD1_OP3_ALU_INST_SIZE;
- unsigned int : 14;
- } sq_alu_word1_op3_t;
-
-#elif defined(BIGENDIAN_CPU)
-
- typedef struct _sq_alu_word1_op3_t {
- unsigned int : 14;
- unsigned int alu_inst : SQ_ALU_WORD1_OP3_ALU_INST_SIZE;
- unsigned int src2_neg : SQ_ALU_WORD1_OP3_SRC2_NEG_SIZE;
- unsigned int src2_chan : SQ_ALU_WORD1_OP3_SRC2_CHAN_SIZE;
- unsigned int src2_rel : SQ_ALU_WORD1_OP3_SRC2_REL_SIZE;
- unsigned int src2_sel : SQ_ALU_WORD1_OP3_SRC2_SEL_SIZE;
- } sq_alu_word1_op3_t;
-
-#endif
-
-typedef union {
- unsigned int val : 32;
- sq_alu_word1_op3_t f;
-} sq_alu_word1_op3_u;
-
-
-/*
- * SQ_TEX_WORD0 struct
- */
-
-#define SQ_TEX_WORD0_TEX_INST_SIZE 5
-#define SQ_TEX_WORD0_BC_FRAC_MODE_SIZE 1
-#define SQ_TEX_WORD0_FETCH_WHOLE_QUAD_SIZE 1
-#define SQ_TEX_WORD0_RESOURCE_ID_SIZE 8
-#define SQ_TEX_WORD0_SRC_GPR_SIZE 7
-#define SQ_TEX_WORD0_SRC_REL_SIZE 1
-#define SQ_TEX_WORD0_ALT_CONST_SIZE 1
-
-#define SQ_TEX_WORD0_TEX_INST_SHIFT 0
-#define SQ_TEX_WORD0_BC_FRAC_MODE_SHIFT 5
-#define SQ_TEX_WORD0_FETCH_WHOLE_QUAD_SHIFT 7
-#define SQ_TEX_WORD0_RESOURCE_ID_SHIFT 8
-#define SQ_TEX_WORD0_SRC_GPR_SHIFT 16
-#define SQ_TEX_WORD0_SRC_REL_SHIFT 23
-#define SQ_TEX_WORD0_ALT_CONST_SHIFT 24
-
-#define SQ_TEX_WORD0_TEX_INST_MASK 0x0000001f
-#define SQ_TEX_WORD0_BC_FRAC_MODE_MASK 0x00000020
-#define SQ_TEX_WORD0_FETCH_WHOLE_QUAD_MASK 0x00000080
-#define SQ_TEX_WORD0_RESOURCE_ID_MASK 0x0000ff00
-#define SQ_TEX_WORD0_SRC_GPR_MASK 0x007f0000
-#define SQ_TEX_WORD0_SRC_REL_MASK 0x00800000
-#define SQ_TEX_WORD0_ALT_CONST_MASK 0x01000000
-
-#define SQ_TEX_WORD0_MASK \
- (SQ_TEX_WORD0_TEX_INST_MASK | \
- SQ_TEX_WORD0_BC_FRAC_MODE_MASK | \
- SQ_TEX_WORD0_FETCH_WHOLE_QUAD_MASK | \
- SQ_TEX_WORD0_RESOURCE_ID_MASK | \
- SQ_TEX_WORD0_SRC_GPR_MASK | \
- SQ_TEX_WORD0_SRC_REL_MASK | \
- SQ_TEX_WORD0_ALT_CONST_MASK)
-
-#define SQ_TEX_WORD0_DEFAULT 0x01cdcd8d
-
-#define SQ_TEX_WORD0_GET_TEX_INST(sq_tex_word0) \
- ((sq_tex_word0 & SQ_TEX_WORD0_TEX_INST_MASK) >> SQ_TEX_WORD0_TEX_INST_SHIFT)
-#define SQ_TEX_WORD0_GET_BC_FRAC_MODE(sq_tex_word0) \
- ((sq_tex_word0 & SQ_TEX_WORD0_BC_FRAC_MODE_MASK) >> SQ_TEX_WORD0_BC_FRAC_MODE_SHIFT)
-#define SQ_TEX_WORD0_GET_FETCH_WHOLE_QUAD(sq_tex_word0) \
- ((sq_tex_word0 & SQ_TEX_WORD0_FETCH_WHOLE_QUAD_MASK) >> SQ_TEX_WORD0_FETCH_WHOLE_QUAD_SHIFT)
-#define SQ_TEX_WORD0_GET_RESOURCE_ID(sq_tex_word0) \
- ((sq_tex_word0 & SQ_TEX_WORD0_RESOURCE_ID_MASK) >> SQ_TEX_WORD0_RESOURCE_ID_SHIFT)
-#define SQ_TEX_WORD0_GET_SRC_GPR(sq_tex_word0) \
- ((sq_tex_word0 & SQ_TEX_WORD0_SRC_GPR_MASK) >> SQ_TEX_WORD0_SRC_GPR_SHIFT)
-#define SQ_TEX_WORD0_GET_SRC_REL(sq_tex_word0) \
- ((sq_tex_word0 & SQ_TEX_WORD0_SRC_REL_MASK) >> SQ_TEX_WORD0_SRC_REL_SHIFT)
-#define SQ_TEX_WORD0_GET_ALT_CONST(sq_tex_word0) \
- ((sq_tex_word0 & SQ_TEX_WORD0_ALT_CONST_MASK) >> SQ_TEX_WORD0_ALT_CONST_SHIFT)
-
-#define SQ_TEX_WORD0_SET_TEX_INST(sq_tex_word0_reg, tex_inst) \
- sq_tex_word0_reg = (sq_tex_word0_reg & ~SQ_TEX_WORD0_TEX_INST_MASK) | (tex_inst << SQ_TEX_WORD0_TEX_INST_SHIFT)
-#define SQ_TEX_WORD0_SET_BC_FRAC_MODE(sq_tex_word0_reg, bc_frac_mode) \
- sq_tex_word0_reg = (sq_tex_word0_reg & ~SQ_TEX_WORD0_BC_FRAC_MODE_MASK) | (bc_frac_mode << SQ_TEX_WORD0_BC_FRAC_MODE_SHIFT)
-#define SQ_TEX_WORD0_SET_FETCH_WHOLE_QUAD(sq_tex_word0_reg, fetch_whole_quad) \
- sq_tex_word0_reg = (sq_tex_word0_reg & ~SQ_TEX_WORD0_FETCH_WHOLE_QUAD_MASK) | (fetch_whole_quad << SQ_TEX_WORD0_FETCH_WHOLE_QUAD_SHIFT)
-#define SQ_TEX_WORD0_SET_RESOURCE_ID(sq_tex_word0_reg, resource_id) \
- sq_tex_word0_reg = (sq_tex_word0_reg & ~SQ_TEX_WORD0_RESOURCE_ID_MASK) | (resource_id << SQ_TEX_WORD0_RESOURCE_ID_SHIFT)
-#define SQ_TEX_WORD0_SET_SRC_GPR(sq_tex_word0_reg, src_gpr) \
- sq_tex_word0_reg = (sq_tex_word0_reg & ~SQ_TEX_WORD0_SRC_GPR_MASK) | (src_gpr << SQ_TEX_WORD0_SRC_GPR_SHIFT)
-#define SQ_TEX_WORD0_SET_SRC_REL(sq_tex_word0_reg, src_rel) \
- sq_tex_word0_reg = (sq_tex_word0_reg & ~SQ_TEX_WORD0_SRC_REL_MASK) | (src_rel << SQ_TEX_WORD0_SRC_REL_SHIFT)
-#define SQ_TEX_WORD0_SET_ALT_CONST(sq_tex_word0_reg, alt_const) \
- sq_tex_word0_reg = (sq_tex_word0_reg & ~SQ_TEX_WORD0_ALT_CONST_MASK) | (alt_const << SQ_TEX_WORD0_ALT_CONST_SHIFT)
-
-#if defined(LITTLEENDIAN_CPU)
-
- typedef struct _sq_tex_word0_t {
- unsigned int tex_inst : SQ_TEX_WORD0_TEX_INST_SIZE;
- unsigned int bc_frac_mode : SQ_TEX_WORD0_BC_FRAC_MODE_SIZE;
- unsigned int : 1;
- unsigned int fetch_whole_quad : SQ_TEX_WORD0_FETCH_WHOLE_QUAD_SIZE;
- unsigned int resource_id : SQ_TEX_WORD0_RESOURCE_ID_SIZE;
- unsigned int src_gpr : SQ_TEX_WORD0_SRC_GPR_SIZE;
- unsigned int src_rel : SQ_TEX_WORD0_SRC_REL_SIZE;
- unsigned int alt_const : SQ_TEX_WORD0_ALT_CONST_SIZE;
- unsigned int : 7;
- } sq_tex_word0_t;
-
-#elif defined(BIGENDIAN_CPU)
-
- typedef struct _sq_tex_word0_t {
- unsigned int : 7;
- unsigned int alt_const : SQ_TEX_WORD0_ALT_CONST_SIZE;
- unsigned int src_rel : SQ_TEX_WORD0_SRC_REL_SIZE;
- unsigned int src_gpr : SQ_TEX_WORD0_SRC_GPR_SIZE;
- unsigned int resource_id : SQ_TEX_WORD0_RESOURCE_ID_SIZE;
- unsigned int fetch_whole_quad : SQ_TEX_WORD0_FETCH_WHOLE_QUAD_SIZE;
- unsigned int : 1;
- unsigned int bc_frac_mode : SQ_TEX_WORD0_BC_FRAC_MODE_SIZE;
- unsigned int tex_inst : SQ_TEX_WORD0_TEX_INST_SIZE;
- } sq_tex_word0_t;
-
-#endif
-
-typedef union {
- unsigned int val : 32;
- sq_tex_word0_t f;
-} sq_tex_word0_u;
-
-
-/*
- * SQ_TEX_WORD1 struct
- */
-
-#define SQ_TEX_WORD1_DST_GPR_SIZE 7
-#define SQ_TEX_WORD1_DST_REL_SIZE 1
-#define SQ_TEX_WORD1_DST_SEL_X_SIZE 3
-#define SQ_TEX_WORD1_DST_SEL_Y_SIZE 3
-#define SQ_TEX_WORD1_DST_SEL_Z_SIZE 3
-#define SQ_TEX_WORD1_DST_SEL_W_SIZE 3
-#define SQ_TEX_WORD1_LOD_BIAS_SIZE 7
-#define SQ_TEX_WORD1_COORD_TYPE_X_SIZE 1
-#define SQ_TEX_WORD1_COORD_TYPE_Y_SIZE 1
-#define SQ_TEX_WORD1_COORD_TYPE_Z_SIZE 1
-#define SQ_TEX_WORD1_COORD_TYPE_W_SIZE 1
-
-#define SQ_TEX_WORD1_DST_GPR_SHIFT 0
-#define SQ_TEX_WORD1_DST_REL_SHIFT 7
-#define SQ_TEX_WORD1_DST_SEL_X_SHIFT 9
-#define SQ_TEX_WORD1_DST_SEL_Y_SHIFT 12
-#define SQ_TEX_WORD1_DST_SEL_Z_SHIFT 15
-#define SQ_TEX_WORD1_DST_SEL_W_SHIFT 18
-#define SQ_TEX_WORD1_LOD_BIAS_SHIFT 21
-#define SQ_TEX_WORD1_COORD_TYPE_X_SHIFT 28
-#define SQ_TEX_WORD1_COORD_TYPE_Y_SHIFT 29
-#define SQ_TEX_WORD1_COORD_TYPE_Z_SHIFT 30
-#define SQ_TEX_WORD1_COORD_TYPE_W_SHIFT 31
-
-#define SQ_TEX_WORD1_DST_GPR_MASK 0x0000007f
-#define SQ_TEX_WORD1_DST_REL_MASK 0x00000080
-#define SQ_TEX_WORD1_DST_SEL_X_MASK 0x00000e00
-#define SQ_TEX_WORD1_DST_SEL_Y_MASK 0x00007000
-#define SQ_TEX_WORD1_DST_SEL_Z_MASK 0x00038000
-#define SQ_TEX_WORD1_DST_SEL_W_MASK 0x001c0000
-#define SQ_TEX_WORD1_LOD_BIAS_MASK 0x0fe00000
-#define SQ_TEX_WORD1_COORD_TYPE_X_MASK 0x10000000
-#define SQ_TEX_WORD1_COORD_TYPE_Y_MASK 0x20000000
-#define SQ_TEX_WORD1_COORD_TYPE_Z_MASK 0x40000000
-#define SQ_TEX_WORD1_COORD_TYPE_W_MASK 0x80000000
-
-#define SQ_TEX_WORD1_MASK \
- (SQ_TEX_WORD1_DST_GPR_MASK | \
- SQ_TEX_WORD1_DST_REL_MASK | \
- SQ_TEX_WORD1_DST_SEL_X_MASK | \
- SQ_TEX_WORD1_DST_SEL_Y_MASK | \
- SQ_TEX_WORD1_DST_SEL_Z_MASK | \
- SQ_TEX_WORD1_DST_SEL_W_MASK | \
- SQ_TEX_WORD1_LOD_BIAS_MASK | \
- SQ_TEX_WORD1_COORD_TYPE_X_MASK | \
- SQ_TEX_WORD1_COORD_TYPE_Y_MASK | \
- SQ_TEX_WORD1_COORD_TYPE_Z_MASK | \
- SQ_TEX_WORD1_COORD_TYPE_W_MASK)
-
-#define SQ_TEX_WORD1_DEFAULT 0xcdcdcccd
-
-#define SQ_TEX_WORD1_GET_DST_GPR(sq_tex_word1) \
- ((sq_tex_word1 & SQ_TEX_WORD1_DST_GPR_MASK) >> SQ_TEX_WORD1_DST_GPR_SHIFT)
-#define SQ_TEX_WORD1_GET_DST_REL(sq_tex_word1) \
- ((sq_tex_word1 & SQ_TEX_WORD1_DST_REL_MASK) >> SQ_TEX_WORD1_DST_REL_SHIFT)
-#define SQ_TEX_WORD1_GET_DST_SEL_X(sq_tex_word1) \
- ((sq_tex_word1 & SQ_TEX_WORD1_DST_SEL_X_MASK) >> SQ_TEX_WORD1_DST_SEL_X_SHIFT)
-#define SQ_TEX_WORD1_GET_DST_SEL_Y(sq_tex_word1) \
- ((sq_tex_word1 & SQ_TEX_WORD1_DST_SEL_Y_MASK) >> SQ_TEX_WORD1_DST_SEL_Y_SHIFT)
-#define SQ_TEX_WORD1_GET_DST_SEL_Z(sq_tex_word1) \
- ((sq_tex_word1 & SQ_TEX_WORD1_DST_SEL_Z_MASK) >> SQ_TEX_WORD1_DST_SEL_Z_SHIFT)
-#define SQ_TEX_WORD1_GET_DST_SEL_W(sq_tex_word1) \
- ((sq_tex_word1 & SQ_TEX_WORD1_DST_SEL_W_MASK) >> SQ_TEX_WORD1_DST_SEL_W_SHIFT)
-#define SQ_TEX_WORD1_GET_LOD_BIAS(sq_tex_word1) \
- ((sq_tex_word1 & SQ_TEX_WORD1_LOD_BIAS_MASK) >> SQ_TEX_WORD1_LOD_BIAS_SHIFT)
-#define SQ_TEX_WORD1_GET_COORD_TYPE_X(sq_tex_word1) \
- ((sq_tex_word1 & SQ_TEX_WORD1_COORD_TYPE_X_MASK) >> SQ_TEX_WORD1_COORD_TYPE_X_SHIFT)
-#define SQ_TEX_WORD1_GET_COORD_TYPE_Y(sq_tex_word1) \
- ((sq_tex_word1 & SQ_TEX_WORD1_COORD_TYPE_Y_MASK) >> SQ_TEX_WORD1_COORD_TYPE_Y_SHIFT)
-#define SQ_TEX_WORD1_GET_COORD_TYPE_Z(sq_tex_word1) \
- ((sq_tex_word1 & SQ_TEX_WORD1_COORD_TYPE_Z_MASK) >> SQ_TEX_WORD1_COORD_TYPE_Z_SHIFT)
-#define SQ_TEX_WORD1_GET_COORD_TYPE_W(sq_tex_word1) \
- ((sq_tex_word1 & SQ_TEX_WORD1_COORD_TYPE_W_MASK) >> SQ_TEX_WORD1_COORD_TYPE_W_SHIFT)
-
-#define SQ_TEX_WORD1_SET_DST_GPR(sq_tex_word1_reg, dst_gpr) \
- sq_tex_word1_reg = (sq_tex_word1_reg & ~SQ_TEX_WORD1_DST_GPR_MASK) | (dst_gpr << SQ_TEX_WORD1_DST_GPR_SHIFT)
-#define SQ_TEX_WORD1_SET_DST_REL(sq_tex_word1_reg, dst_rel) \
- sq_tex_word1_reg = (sq_tex_word1_reg & ~SQ_TEX_WORD1_DST_REL_MASK) | (dst_rel << SQ_TEX_WORD1_DST_REL_SHIFT)
-#define SQ_TEX_WORD1_SET_DST_SEL_X(sq_tex_word1_reg, dst_sel_x) \
- sq_tex_word1_reg = (sq_tex_word1_reg & ~SQ_TEX_WORD1_DST_SEL_X_MASK) | (dst_sel_x << SQ_TEX_WORD1_DST_SEL_X_SHIFT)
-#define SQ_TEX_WORD1_SET_DST_SEL_Y(sq_tex_word1_reg, dst_sel_y) \
- sq_tex_word1_reg = (sq_tex_word1_reg & ~SQ_TEX_WORD1_DST_SEL_Y_MASK) | (dst_sel_y << SQ_TEX_WORD1_DST_SEL_Y_SHIFT)
-#define SQ_TEX_WORD1_SET_DST_SEL_Z(sq_tex_word1_reg, dst_sel_z) \
- sq_tex_word1_reg = (sq_tex_word1_reg & ~SQ_TEX_WORD1_DST_SEL_Z_MASK) | (dst_sel_z << SQ_TEX_WORD1_DST_SEL_Z_SHIFT)
-#define SQ_TEX_WORD1_SET_DST_SEL_W(sq_tex_word1_reg, dst_sel_w) \
- sq_tex_word1_reg = (sq_tex_word1_reg & ~SQ_TEX_WORD1_DST_SEL_W_MASK) | (dst_sel_w << SQ_TEX_WORD1_DST_SEL_W_SHIFT)
-#define SQ_TEX_WORD1_SET_LOD_BIAS(sq_tex_word1_reg, lod_bias) \
- sq_tex_word1_reg = (sq_tex_word1_reg & ~SQ_TEX_WORD1_LOD_BIAS_MASK) | (lod_bias << SQ_TEX_WORD1_LOD_BIAS_SHIFT)
-#define SQ_TEX_WORD1_SET_COORD_TYPE_X(sq_tex_word1_reg, coord_type_x) \
- sq_tex_word1_reg = (sq_tex_word1_reg & ~SQ_TEX_WORD1_COORD_TYPE_X_MASK) | (coord_type_x << SQ_TEX_WORD1_COORD_TYPE_X_SHIFT)
-#define SQ_TEX_WORD1_SET_COORD_TYPE_Y(sq_tex_word1_reg, coord_type_y) \
- sq_tex_word1_reg = (sq_tex_word1_reg & ~SQ_TEX_WORD1_COORD_TYPE_Y_MASK) | (coord_type_y << SQ_TEX_WORD1_COORD_TYPE_Y_SHIFT)
-#define SQ_TEX_WORD1_SET_COORD_TYPE_Z(sq_tex_word1_reg, coord_type_z) \
- sq_tex_word1_reg = (sq_tex_word1_reg & ~SQ_TEX_WORD1_COORD_TYPE_Z_MASK) | (coord_type_z << SQ_TEX_WORD1_COORD_TYPE_Z_SHIFT)
-#define SQ_TEX_WORD1_SET_COORD_TYPE_W(sq_tex_word1_reg, coord_type_w) \
- sq_tex_word1_reg = (sq_tex_word1_reg & ~SQ_TEX_WORD1_COORD_TYPE_W_MASK) | (coord_type_w << SQ_TEX_WORD1_COORD_TYPE_W_SHIFT)
-
-#if defined(LITTLEENDIAN_CPU)
-
- typedef struct _sq_tex_word1_t {
- unsigned int dst_gpr : SQ_TEX_WORD1_DST_GPR_SIZE;
- unsigned int dst_rel : SQ_TEX_WORD1_DST_REL_SIZE;
- unsigned int : 1;
- unsigned int dst_sel_x : SQ_TEX_WORD1_DST_SEL_X_SIZE;
- unsigned int dst_sel_y : SQ_TEX_WORD1_DST_SEL_Y_SIZE;
- unsigned int dst_sel_z : SQ_TEX_WORD1_DST_SEL_Z_SIZE;
- unsigned int dst_sel_w : SQ_TEX_WORD1_DST_SEL_W_SIZE;
- unsigned int lod_bias : SQ_TEX_WORD1_LOD_BIAS_SIZE;
- unsigned int coord_type_x : SQ_TEX_WORD1_COORD_TYPE_X_SIZE;
- unsigned int coord_type_y : SQ_TEX_WORD1_COORD_TYPE_Y_SIZE;
- unsigned int coord_type_z : SQ_TEX_WORD1_COORD_TYPE_Z_SIZE;
- unsigned int coord_type_w : SQ_TEX_WORD1_COORD_TYPE_W_SIZE;
- } sq_tex_word1_t;
-
-#elif defined(BIGENDIAN_CPU)
-
- typedef struct _sq_tex_word1_t {
- unsigned int coord_type_w : SQ_TEX_WORD1_COORD_TYPE_W_SIZE;
- unsigned int coord_type_z : SQ_TEX_WORD1_COORD_TYPE_Z_SIZE;
- unsigned int coord_type_y : SQ_TEX_WORD1_COORD_TYPE_Y_SIZE;
- unsigned int coord_type_x : SQ_TEX_WORD1_COORD_TYPE_X_SIZE;
- unsigned int lod_bias : SQ_TEX_WORD1_LOD_BIAS_SIZE;
- unsigned int dst_sel_w : SQ_TEX_WORD1_DST_SEL_W_SIZE;
- unsigned int dst_sel_z : SQ_TEX_WORD1_DST_SEL_Z_SIZE;
- unsigned int dst_sel_y : SQ_TEX_WORD1_DST_SEL_Y_SIZE;
- unsigned int dst_sel_x : SQ_TEX_WORD1_DST_SEL_X_SIZE;
- unsigned int : 1;
- unsigned int dst_rel : SQ_TEX_WORD1_DST_REL_SIZE;
- unsigned int dst_gpr : SQ_TEX_WORD1_DST_GPR_SIZE;
- } sq_tex_word1_t;
-
-#endif
-
-typedef union {
- unsigned int val : 32;
- sq_tex_word1_t f;
-} sq_tex_word1_u;
-
-
-/*
- * SQ_TEX_WORD2 struct
- */
-
-#define SQ_TEX_WORD2_OFFSET_X_SIZE 5
-#define SQ_TEX_WORD2_OFFSET_Y_SIZE 5
-#define SQ_TEX_WORD2_OFFSET_Z_SIZE 5
-#define SQ_TEX_WORD2_SAMPLER_ID_SIZE 5
-#define SQ_TEX_WORD2_SRC_SEL_X_SIZE 3
-#define SQ_TEX_WORD2_SRC_SEL_Y_SIZE 3
-#define SQ_TEX_WORD2_SRC_SEL_Z_SIZE 3
-#define SQ_TEX_WORD2_SRC_SEL_W_SIZE 3
-
-#define SQ_TEX_WORD2_OFFSET_X_SHIFT 0
-#define SQ_TEX_WORD2_OFFSET_Y_SHIFT 5
-#define SQ_TEX_WORD2_OFFSET_Z_SHIFT 10
-#define SQ_TEX_WORD2_SAMPLER_ID_SHIFT 15
-#define SQ_TEX_WORD2_SRC_SEL_X_SHIFT 20
-#define SQ_TEX_WORD2_SRC_SEL_Y_SHIFT 23
-#define SQ_TEX_WORD2_SRC_SEL_Z_SHIFT 26
-#define SQ_TEX_WORD2_SRC_SEL_W_SHIFT 29
-
-#define SQ_TEX_WORD2_OFFSET_X_MASK 0x0000001f
-#define SQ_TEX_WORD2_OFFSET_Y_MASK 0x000003e0
-#define SQ_TEX_WORD2_OFFSET_Z_MASK 0x00007c00
-#define SQ_TEX_WORD2_SAMPLER_ID_MASK 0x000f8000
-#define SQ_TEX_WORD2_SRC_SEL_X_MASK 0x00700000
-#define SQ_TEX_WORD2_SRC_SEL_Y_MASK 0x03800000
-#define SQ_TEX_WORD2_SRC_SEL_Z_MASK 0x1c000000
-#define SQ_TEX_WORD2_SRC_SEL_W_MASK 0xe0000000
-
-#define SQ_TEX_WORD2_MASK \
- (SQ_TEX_WORD2_OFFSET_X_MASK | \
- SQ_TEX_WORD2_OFFSET_Y_MASK | \
- SQ_TEX_WORD2_OFFSET_Z_MASK | \
- SQ_TEX_WORD2_SAMPLER_ID_MASK | \
- SQ_TEX_WORD2_SRC_SEL_X_MASK | \
- SQ_TEX_WORD2_SRC_SEL_Y_MASK | \
- SQ_TEX_WORD2_SRC_SEL_Z_MASK | \
- SQ_TEX_WORD2_SRC_SEL_W_MASK)
-
-#define SQ_TEX_WORD2_DEFAULT 0xcdcdcdcd
-
-#define SQ_TEX_WORD2_GET_OFFSET_X(sq_tex_word2) \
- ((sq_tex_word2 & SQ_TEX_WORD2_OFFSET_X_MASK) >> SQ_TEX_WORD2_OFFSET_X_SHIFT)
-#define SQ_TEX_WORD2_GET_OFFSET_Y(sq_tex_word2) \
- ((sq_tex_word2 & SQ_TEX_WORD2_OFFSET_Y_MASK) >> SQ_TEX_WORD2_OFFSET_Y_SHIFT)
-#define SQ_TEX_WORD2_GET_OFFSET_Z(sq_tex_word2) \
- ((sq_tex_word2 & SQ_TEX_WORD2_OFFSET_Z_MASK) >> SQ_TEX_WORD2_OFFSET_Z_SHIFT)
-#define SQ_TEX_WORD2_GET_SAMPLER_ID(sq_tex_word2) \
- ((sq_tex_word2 & SQ_TEX_WORD2_SAMPLER_ID_MASK) >> SQ_TEX_WORD2_SAMPLER_ID_SHIFT)
-#define SQ_TEX_WORD2_GET_SRC_SEL_X(sq_tex_word2) \
- ((sq_tex_word2 & SQ_TEX_WORD2_SRC_SEL_X_MASK) >> SQ_TEX_WORD2_SRC_SEL_X_SHIFT)
-#define SQ_TEX_WORD2_GET_SRC_SEL_Y(sq_tex_word2) \
- ((sq_tex_word2 & SQ_TEX_WORD2_SRC_SEL_Y_MASK) >> SQ_TEX_WORD2_SRC_SEL_Y_SHIFT)
-#define SQ_TEX_WORD2_GET_SRC_SEL_Z(sq_tex_word2) \
- ((sq_tex_word2 & SQ_TEX_WORD2_SRC_SEL_Z_MASK) >> SQ_TEX_WORD2_SRC_SEL_Z_SHIFT)
-#define SQ_TEX_WORD2_GET_SRC_SEL_W(sq_tex_word2) \
- ((sq_tex_word2 & SQ_TEX_WORD2_SRC_SEL_W_MASK) >> SQ_TEX_WORD2_SRC_SEL_W_SHIFT)
-
-#define SQ_TEX_WORD2_SET_OFFSET_X(sq_tex_word2_reg, offset_x) \
- sq_tex_word2_reg = (sq_tex_word2_reg & ~SQ_TEX_WORD2_OFFSET_X_MASK) | (offset_x << SQ_TEX_WORD2_OFFSET_X_SHIFT)
-#define SQ_TEX_WORD2_SET_OFFSET_Y(sq_tex_word2_reg, offset_y) \
- sq_tex_word2_reg = (sq_tex_word2_reg & ~SQ_TEX_WORD2_OFFSET_Y_MASK) | (offset_y << SQ_TEX_WORD2_OFFSET_Y_SHIFT)
-#define SQ_TEX_WORD2_SET_OFFSET_Z(sq_tex_word2_reg, offset_z) \
- sq_tex_word2_reg = (sq_tex_word2_reg & ~SQ_TEX_WORD2_OFFSET_Z_MASK) | (offset_z << SQ_TEX_WORD2_OFFSET_Z_SHIFT)
-#define SQ_TEX_WORD2_SET_SAMPLER_ID(sq_tex_word2_reg, sampler_id) \
- sq_tex_word2_reg = (sq_tex_word2_reg & ~SQ_TEX_WORD2_SAMPLER_ID_MASK) | (sampler_id << SQ_TEX_WORD2_SAMPLER_ID_SHIFT)
-#define SQ_TEX_WORD2_SET_SRC_SEL_X(sq_tex_word2_reg, src_sel_x) \
- sq_tex_word2_reg = (sq_tex_word2_reg & ~SQ_TEX_WORD2_SRC_SEL_X_MASK) | (src_sel_x << SQ_TEX_WORD2_SRC_SEL_X_SHIFT)
-#define SQ_TEX_WORD2_SET_SRC_SEL_Y(sq_tex_word2_reg, src_sel_y) \
- sq_tex_word2_reg = (sq_tex_word2_reg & ~SQ_TEX_WORD2_SRC_SEL_Y_MASK) | (src_sel_y << SQ_TEX_WORD2_SRC_SEL_Y_SHIFT)
-#define SQ_TEX_WORD2_SET_SRC_SEL_Z(sq_tex_word2_reg, src_sel_z) \
- sq_tex_word2_reg = (sq_tex_word2_reg & ~SQ_TEX_WORD2_SRC_SEL_Z_MASK) | (src_sel_z << SQ_TEX_WORD2_SRC_SEL_Z_SHIFT)
-#define SQ_TEX_WORD2_SET_SRC_SEL_W(sq_tex_word2_reg, src_sel_w) \
- sq_tex_word2_reg = (sq_tex_word2_reg & ~SQ_TEX_WORD2_SRC_SEL_W_MASK) | (src_sel_w << SQ_TEX_WORD2_SRC_SEL_W_SHIFT)
-
-#if defined(LITTLEENDIAN_CPU)
-
- typedef struct _sq_tex_word2_t {
- unsigned int offset_x : SQ_TEX_WORD2_OFFSET_X_SIZE;
- unsigned int offset_y : SQ_TEX_WORD2_OFFSET_Y_SIZE;
- unsigned int offset_z : SQ_TEX_WORD2_OFFSET_Z_SIZE;
- unsigned int sampler_id : SQ_TEX_WORD2_SAMPLER_ID_SIZE;
- unsigned int src_sel_x : SQ_TEX_WORD2_SRC_SEL_X_SIZE;
- unsigned int src_sel_y : SQ_TEX_WORD2_SRC_SEL_Y_SIZE;
- unsigned int src_sel_z : SQ_TEX_WORD2_SRC_SEL_Z_SIZE;
- unsigned int src_sel_w : SQ_TEX_WORD2_SRC_SEL_W_SIZE;
- } sq_tex_word2_t;
-
-#elif defined(BIGENDIAN_CPU)
-
- typedef struct _sq_tex_word2_t {
- unsigned int src_sel_w : SQ_TEX_WORD2_SRC_SEL_W_SIZE;
- unsigned int src_sel_z : SQ_TEX_WORD2_SRC_SEL_Z_SIZE;
- unsigned int src_sel_y : SQ_TEX_WORD2_SRC_SEL_Y_SIZE;
- unsigned int src_sel_x : SQ_TEX_WORD2_SRC_SEL_X_SIZE;
- unsigned int sampler_id : SQ_TEX_WORD2_SAMPLER_ID_SIZE;
- unsigned int offset_z : SQ_TEX_WORD2_OFFSET_Z_SIZE;
- unsigned int offset_y : SQ_TEX_WORD2_OFFSET_Y_SIZE;
- unsigned int offset_x : SQ_TEX_WORD2_OFFSET_X_SIZE;
- } sq_tex_word2_t;
-
-#endif
-
-typedef union {
- unsigned int val : 32;
- sq_tex_word2_t f;
-} sq_tex_word2_u;
-
-
-/*
- * SQ_VTX_WORD0 struct
- */
-
-#define SQ_VTX_WORD0_VTX_INST_SIZE 5
-#define SQ_VTX_WORD0_FETCH_TYPE_SIZE 2
-#define SQ_VTX_WORD0_FETCH_WHOLE_QUAD_SIZE 1
-#define SQ_VTX_WORD0_BUFFER_ID_SIZE 8
-#define SQ_VTX_WORD0_SRC_GPR_SIZE 7
-#define SQ_VTX_WORD0_SRC_REL_SIZE 1
-#define SQ_VTX_WORD0_SRC_SEL_X_SIZE 2
-#define SQ_VTX_WORD0_MEGA_FETCH_COUNT_SIZE 6
-
-#define SQ_VTX_WORD0_VTX_INST_SHIFT 0
-#define SQ_VTX_WORD0_FETCH_TYPE_SHIFT 5
-#define SQ_VTX_WORD0_FETCH_WHOLE_QUAD_SHIFT 7
-#define SQ_VTX_WORD0_BUFFER_ID_SHIFT 8
-#define SQ_VTX_WORD0_SRC_GPR_SHIFT 16
-#define SQ_VTX_WORD0_SRC_REL_SHIFT 23
-#define SQ_VTX_WORD0_SRC_SEL_X_SHIFT 24
-#define SQ_VTX_WORD0_MEGA_FETCH_COUNT_SHIFT 26
-
-#define SQ_VTX_WORD0_VTX_INST_MASK 0x0000001f
-#define SQ_VTX_WORD0_FETCH_TYPE_MASK 0x00000060
-#define SQ_VTX_WORD0_FETCH_WHOLE_QUAD_MASK 0x00000080
-#define SQ_VTX_WORD0_BUFFER_ID_MASK 0x0000ff00
-#define SQ_VTX_WORD0_SRC_GPR_MASK 0x007f0000
-#define SQ_VTX_WORD0_SRC_REL_MASK 0x00800000
-#define SQ_VTX_WORD0_SRC_SEL_X_MASK 0x03000000
-#define SQ_VTX_WORD0_MEGA_FETCH_COUNT_MASK 0xfc000000
-
-#define SQ_VTX_WORD0_MASK \
- (SQ_VTX_WORD0_VTX_INST_MASK | \
- SQ_VTX_WORD0_FETCH_TYPE_MASK | \
- SQ_VTX_WORD0_FETCH_WHOLE_QUAD_MASK | \
- SQ_VTX_WORD0_BUFFER_ID_MASK | \
- SQ_VTX_WORD0_SRC_GPR_MASK | \
- SQ_VTX_WORD0_SRC_REL_MASK | \
- SQ_VTX_WORD0_SRC_SEL_X_MASK | \
- SQ_VTX_WORD0_MEGA_FETCH_COUNT_MASK)
-
-#define SQ_VTX_WORD0_DEFAULT 0xcdcdcdcd
-
-#define SQ_VTX_WORD0_GET_VTX_INST(sq_vtx_word0) \
- ((sq_vtx_word0 & SQ_VTX_WORD0_VTX_INST_MASK) >> SQ_VTX_WORD0_VTX_INST_SHIFT)
-#define SQ_VTX_WORD0_GET_FETCH_TYPE(sq_vtx_word0) \
- ((sq_vtx_word0 & SQ_VTX_WORD0_FETCH_TYPE_MASK) >> SQ_VTX_WORD0_FETCH_TYPE_SHIFT)
-#define SQ_VTX_WORD0_GET_FETCH_WHOLE_QUAD(sq_vtx_word0) \
- ((sq_vtx_word0 & SQ_VTX_WORD0_FETCH_WHOLE_QUAD_MASK) >> SQ_VTX_WORD0_FETCH_WHOLE_QUAD_SHIFT)
-#define SQ_VTX_WORD0_GET_BUFFER_ID(sq_vtx_word0) \
- ((sq_vtx_word0 & SQ_VTX_WORD0_BUFFER_ID_MASK) >> SQ_VTX_WORD0_BUFFER_ID_SHIFT)
-#define SQ_VTX_WORD0_GET_SRC_GPR(sq_vtx_word0) \
- ((sq_vtx_word0 & SQ_VTX_WORD0_SRC_GPR_MASK) >> SQ_VTX_WORD0_SRC_GPR_SHIFT)
-#define SQ_VTX_WORD0_GET_SRC_REL(sq_vtx_word0) \
- ((sq_vtx_word0 & SQ_VTX_WORD0_SRC_REL_MASK) >> SQ_VTX_WORD0_SRC_REL_SHIFT)
-#define SQ_VTX_WORD0_GET_SRC_SEL_X(sq_vtx_word0) \
- ((sq_vtx_word0 & SQ_VTX_WORD0_SRC_SEL_X_MASK) >> SQ_VTX_WORD0_SRC_SEL_X_SHIFT)
-#define SQ_VTX_WORD0_GET_MEGA_FETCH_COUNT(sq_vtx_word0) \
- ((sq_vtx_word0 & SQ_VTX_WORD0_MEGA_FETCH_COUNT_MASK) >> SQ_VTX_WORD0_MEGA_FETCH_COUNT_SHIFT)
-
-#define SQ_VTX_WORD0_SET_VTX_INST(sq_vtx_word0_reg, vtx_inst) \
- sq_vtx_word0_reg = (sq_vtx_word0_reg & ~SQ_VTX_WORD0_VTX_INST_MASK) | (vtx_inst << SQ_VTX_WORD0_VTX_INST_SHIFT)
-#define SQ_VTX_WORD0_SET_FETCH_TYPE(sq_vtx_word0_reg, fetch_type) \
- sq_vtx_word0_reg = (sq_vtx_word0_reg & ~SQ_VTX_WORD0_FETCH_TYPE_MASK) | (fetch_type << SQ_VTX_WORD0_FETCH_TYPE_SHIFT)
-#define SQ_VTX_WORD0_SET_FETCH_WHOLE_QUAD(sq_vtx_word0_reg, fetch_whole_quad) \
- sq_vtx_word0_reg = (sq_vtx_word0_reg & ~SQ_VTX_WORD0_FETCH_WHOLE_QUAD_MASK) | (fetch_whole_quad << SQ_VTX_WORD0_FETCH_WHOLE_QUAD_SHIFT)
-#define SQ_VTX_WORD0_SET_BUFFER_ID(sq_vtx_word0_reg, buffer_id) \
- sq_vtx_word0_reg = (sq_vtx_word0_reg & ~SQ_VTX_WORD0_BUFFER_ID_MASK) | (buffer_id << SQ_VTX_WORD0_BUFFER_ID_SHIFT)
-#define SQ_VTX_WORD0_SET_SRC_GPR(sq_vtx_word0_reg, src_gpr) \
- sq_vtx_word0_reg = (sq_vtx_word0_reg & ~SQ_VTX_WORD0_SRC_GPR_MASK) | (src_gpr << SQ_VTX_WORD0_SRC_GPR_SHIFT)
-#define SQ_VTX_WORD0_SET_SRC_REL(sq_vtx_word0_reg, src_rel) \
- sq_vtx_word0_reg = (sq_vtx_word0_reg & ~SQ_VTX_WORD0_SRC_REL_MASK) | (src_rel << SQ_VTX_WORD0_SRC_REL_SHIFT)
-#define SQ_VTX_WORD0_SET_SRC_SEL_X(sq_vtx_word0_reg, src_sel_x) \
- sq_vtx_word0_reg = (sq_vtx_word0_reg & ~SQ_VTX_WORD0_SRC_SEL_X_MASK) | (src_sel_x << SQ_VTX_WORD0_SRC_SEL_X_SHIFT)
-#define SQ_VTX_WORD0_SET_MEGA_FETCH_COUNT(sq_vtx_word0_reg, mega_fetch_count) \
- sq_vtx_word0_reg = (sq_vtx_word0_reg & ~SQ_VTX_WORD0_MEGA_FETCH_COUNT_MASK) | (mega_fetch_count << SQ_VTX_WORD0_MEGA_FETCH_COUNT_SHIFT)
-
-#if defined(LITTLEENDIAN_CPU)
-
- typedef struct _sq_vtx_word0_t {
- unsigned int vtx_inst : SQ_VTX_WORD0_VTX_INST_SIZE;
- unsigned int fetch_type : SQ_VTX_WORD0_FETCH_TYPE_SIZE;
- unsigned int fetch_whole_quad : SQ_VTX_WORD0_FETCH_WHOLE_QUAD_SIZE;
- unsigned int buffer_id : SQ_VTX_WORD0_BUFFER_ID_SIZE;
- unsigned int src_gpr : SQ_VTX_WORD0_SRC_GPR_SIZE;
- unsigned int src_rel : SQ_VTX_WORD0_SRC_REL_SIZE;
- unsigned int src_sel_x : SQ_VTX_WORD0_SRC_SEL_X_SIZE;
- unsigned int mega_fetch_count : SQ_VTX_WORD0_MEGA_FETCH_COUNT_SIZE;
- } sq_vtx_word0_t;
-
-#elif defined(BIGENDIAN_CPU)
-
- typedef struct _sq_vtx_word0_t {
- unsigned int mega_fetch_count : SQ_VTX_WORD0_MEGA_FETCH_COUNT_SIZE;
- unsigned int src_sel_x : SQ_VTX_WORD0_SRC_SEL_X_SIZE;
- unsigned int src_rel : SQ_VTX_WORD0_SRC_REL_SIZE;
- unsigned int src_gpr : SQ_VTX_WORD0_SRC_GPR_SIZE;
- unsigned int buffer_id : SQ_VTX_WORD0_BUFFER_ID_SIZE;
- unsigned int fetch_whole_quad : SQ_VTX_WORD0_FETCH_WHOLE_QUAD_SIZE;
- unsigned int fetch_type : SQ_VTX_WORD0_FETCH_TYPE_SIZE;
- unsigned int vtx_inst : SQ_VTX_WORD0_VTX_INST_SIZE;
- } sq_vtx_word0_t;
-
-#endif
-
-typedef union {
- unsigned int val : 32;
- sq_vtx_word0_t f;
-} sq_vtx_word0_u;
-
-
-/*
- * SQ_VTX_WORD1 struct
- */
-
-#define SQ_VTX_WORD1_DST_SEL_X_SIZE 3
-#define SQ_VTX_WORD1_DST_SEL_Y_SIZE 3
-#define SQ_VTX_WORD1_DST_SEL_Z_SIZE 3
-#define SQ_VTX_WORD1_DST_SEL_W_SIZE 3
-#define SQ_VTX_WORD1_USE_CONST_FIELDS_SIZE 1
-#define SQ_VTX_WORD1_DATA_FORMAT_SIZE 6
-#define SQ_VTX_WORD1_NUM_FORMAT_ALL_SIZE 2
-#define SQ_VTX_WORD1_FORMAT_COMP_ALL_SIZE 1
-#define SQ_VTX_WORD1_SRF_MODE_ALL_SIZE 1
-
-#define SQ_VTX_WORD1_DST_SEL_X_SHIFT 9
-#define SQ_VTX_WORD1_DST_SEL_Y_SHIFT 12
-#define SQ_VTX_WORD1_DST_SEL_Z_SHIFT 15
-#define SQ_VTX_WORD1_DST_SEL_W_SHIFT 18
-#define SQ_VTX_WORD1_USE_CONST_FIELDS_SHIFT 21
-#define SQ_VTX_WORD1_DATA_FORMAT_SHIFT 22
-#define SQ_VTX_WORD1_NUM_FORMAT_ALL_SHIFT 28
-#define SQ_VTX_WORD1_FORMAT_COMP_ALL_SHIFT 30
-#define SQ_VTX_WORD1_SRF_MODE_ALL_SHIFT 31
-
-#define SQ_VTX_WORD1_DST_SEL_X_MASK 0x00000e00
-#define SQ_VTX_WORD1_DST_SEL_Y_MASK 0x00007000
-#define SQ_VTX_WORD1_DST_SEL_Z_MASK 0x00038000
-#define SQ_VTX_WORD1_DST_SEL_W_MASK 0x001c0000
-#define SQ_VTX_WORD1_USE_CONST_FIELDS_MASK 0x00200000
-#define SQ_VTX_WORD1_DATA_FORMAT_MASK 0x0fc00000
-#define SQ_VTX_WORD1_NUM_FORMAT_ALL_MASK 0x30000000
-#define SQ_VTX_WORD1_FORMAT_COMP_ALL_MASK 0x40000000
-#define SQ_VTX_WORD1_SRF_MODE_ALL_MASK 0x80000000
-
-#define SQ_VTX_WORD1_MASK \
- (SQ_VTX_WORD1_DST_SEL_X_MASK | \
- SQ_VTX_WORD1_DST_SEL_Y_MASK | \
- SQ_VTX_WORD1_DST_SEL_Z_MASK | \
- SQ_VTX_WORD1_DST_SEL_W_MASK | \
- SQ_VTX_WORD1_USE_CONST_FIELDS_MASK | \
- SQ_VTX_WORD1_DATA_FORMAT_MASK | \
- SQ_VTX_WORD1_NUM_FORMAT_ALL_MASK | \
- SQ_VTX_WORD1_FORMAT_COMP_ALL_MASK | \
- SQ_VTX_WORD1_SRF_MODE_ALL_MASK)
-
-#define SQ_VTX_WORD1_DEFAULT 0xcdcdcc00
-
-#define SQ_VTX_WORD1_GET_DST_SEL_X(sq_vtx_word1) \
- ((sq_vtx_word1 & SQ_VTX_WORD1_DST_SEL_X_MASK) >> SQ_VTX_WORD1_DST_SEL_X_SHIFT)
-#define SQ_VTX_WORD1_GET_DST_SEL_Y(sq_vtx_word1) \
- ((sq_vtx_word1 & SQ_VTX_WORD1_DST_SEL_Y_MASK) >> SQ_VTX_WORD1_DST_SEL_Y_SHIFT)
-#define SQ_VTX_WORD1_GET_DST_SEL_Z(sq_vtx_word1) \
- ((sq_vtx_word1 & SQ_VTX_WORD1_DST_SEL_Z_MASK) >> SQ_VTX_WORD1_DST_SEL_Z_SHIFT)
-#define SQ_VTX_WORD1_GET_DST_SEL_W(sq_vtx_word1) \
- ((sq_vtx_word1 & SQ_VTX_WORD1_DST_SEL_W_MASK) >> SQ_VTX_WORD1_DST_SEL_W_SHIFT)
-#define SQ_VTX_WORD1_GET_USE_CONST_FIELDS(sq_vtx_word1) \
- ((sq_vtx_word1 & SQ_VTX_WORD1_USE_CONST_FIELDS_MASK) >> SQ_VTX_WORD1_USE_CONST_FIELDS_SHIFT)
-#define SQ_VTX_WORD1_GET_DATA_FORMAT(sq_vtx_word1) \
- ((sq_vtx_word1 & SQ_VTX_WORD1_DATA_FORMAT_MASK) >> SQ_VTX_WORD1_DATA_FORMAT_SHIFT)
-#define SQ_VTX_WORD1_GET_NUM_FORMAT_ALL(sq_vtx_word1) \
- ((sq_vtx_word1 & SQ_VTX_WORD1_NUM_FORMAT_ALL_MASK) >> SQ_VTX_WORD1_NUM_FORMAT_ALL_SHIFT)
-#define SQ_VTX_WORD1_GET_FORMAT_COMP_ALL(sq_vtx_word1) \
- ((sq_vtx_word1 & SQ_VTX_WORD1_FORMAT_COMP_ALL_MASK) >> SQ_VTX_WORD1_FORMAT_COMP_ALL_SHIFT)
-#define SQ_VTX_WORD1_GET_SRF_MODE_ALL(sq_vtx_word1) \
- ((sq_vtx_word1 & SQ_VTX_WORD1_SRF_MODE_ALL_MASK) >> SQ_VTX_WORD1_SRF_MODE_ALL_SHIFT)
-
-#define SQ_VTX_WORD1_SET_DST_SEL_X(sq_vtx_word1_reg, dst_sel_x) \
- sq_vtx_word1_reg = (sq_vtx_word1_reg & ~SQ_VTX_WORD1_DST_SEL_X_MASK) | (dst_sel_x << SQ_VTX_WORD1_DST_SEL_X_SHIFT)
-#define SQ_VTX_WORD1_SET_DST_SEL_Y(sq_vtx_word1_reg, dst_sel_y) \
- sq_vtx_word1_reg = (sq_vtx_word1_reg & ~SQ_VTX_WORD1_DST_SEL_Y_MASK) | (dst_sel_y << SQ_VTX_WORD1_DST_SEL_Y_SHIFT)
-#define SQ_VTX_WORD1_SET_DST_SEL_Z(sq_vtx_word1_reg, dst_sel_z) \
- sq_vtx_word1_reg = (sq_vtx_word1_reg & ~SQ_VTX_WORD1_DST_SEL_Z_MASK) | (dst_sel_z << SQ_VTX_WORD1_DST_SEL_Z_SHIFT)
-#define SQ_VTX_WORD1_SET_DST_SEL_W(sq_vtx_word1_reg, dst_sel_w) \
- sq_vtx_word1_reg = (sq_vtx_word1_reg & ~SQ_VTX_WORD1_DST_SEL_W_MASK) | (dst_sel_w << SQ_VTX_WORD1_DST_SEL_W_SHIFT)
-#define SQ_VTX_WORD1_SET_USE_CONST_FIELDS(sq_vtx_word1_reg, use_const_fields) \
- sq_vtx_word1_reg = (sq_vtx_word1_reg & ~SQ_VTX_WORD1_USE_CONST_FIELDS_MASK) | (use_const_fields << SQ_VTX_WORD1_USE_CONST_FIELDS_SHIFT)
-#define SQ_VTX_WORD1_SET_DATA_FORMAT(sq_vtx_word1_reg, data_format) \
- sq_vtx_word1_reg = (sq_vtx_word1_reg & ~SQ_VTX_WORD1_DATA_FORMAT_MASK) | (data_format << SQ_VTX_WORD1_DATA_FORMAT_SHIFT)
-#define SQ_VTX_WORD1_SET_NUM_FORMAT_ALL(sq_vtx_word1_reg, num_format_all) \
- sq_vtx_word1_reg = (sq_vtx_word1_reg & ~SQ_VTX_WORD1_NUM_FORMAT_ALL_MASK) | (num_format_all << SQ_VTX_WORD1_NUM_FORMAT_ALL_SHIFT)
-#define SQ_VTX_WORD1_SET_FORMAT_COMP_ALL(sq_vtx_word1_reg, format_comp_all) \
- sq_vtx_word1_reg = (sq_vtx_word1_reg & ~SQ_VTX_WORD1_FORMAT_COMP_ALL_MASK) | (format_comp_all << SQ_VTX_WORD1_FORMAT_COMP_ALL_SHIFT)
-#define SQ_VTX_WORD1_SET_SRF_MODE_ALL(sq_vtx_word1_reg, srf_mode_all) \
- sq_vtx_word1_reg = (sq_vtx_word1_reg & ~SQ_VTX_WORD1_SRF_MODE_ALL_MASK) | (srf_mode_all << SQ_VTX_WORD1_SRF_MODE_ALL_SHIFT)
-
-#if defined(LITTLEENDIAN_CPU)
-
- typedef struct _sq_vtx_word1_t {
- unsigned int : 9;
- unsigned int dst_sel_x : SQ_VTX_WORD1_DST_SEL_X_SIZE;
- unsigned int dst_sel_y : SQ_VTX_WORD1_DST_SEL_Y_SIZE;
- unsigned int dst_sel_z : SQ_VTX_WORD1_DST_SEL_Z_SIZE;
- unsigned int dst_sel_w : SQ_VTX_WORD1_DST_SEL_W_SIZE;
- unsigned int use_const_fields : SQ_VTX_WORD1_USE_CONST_FIELDS_SIZE;
- unsigned int data_format : SQ_VTX_WORD1_DATA_FORMAT_SIZE;
- unsigned int num_format_all : SQ_VTX_WORD1_NUM_FORMAT_ALL_SIZE;
- unsigned int format_comp_all : SQ_VTX_WORD1_FORMAT_COMP_ALL_SIZE;
- unsigned int srf_mode_all : SQ_VTX_WORD1_SRF_MODE_ALL_SIZE;
- } sq_vtx_word1_t;
-
-#elif defined(BIGENDIAN_CPU)
-
- typedef struct _sq_vtx_word1_t {
- unsigned int srf_mode_all : SQ_VTX_WORD1_SRF_MODE_ALL_SIZE;
- unsigned int format_comp_all : SQ_VTX_WORD1_FORMAT_COMP_ALL_SIZE;
- unsigned int num_format_all : SQ_VTX_WORD1_NUM_FORMAT_ALL_SIZE;
- unsigned int data_format : SQ_VTX_WORD1_DATA_FORMAT_SIZE;
- unsigned int use_const_fields : SQ_VTX_WORD1_USE_CONST_FIELDS_SIZE;
- unsigned int dst_sel_w : SQ_VTX_WORD1_DST_SEL_W_SIZE;
- unsigned int dst_sel_z : SQ_VTX_WORD1_DST_SEL_Z_SIZE;
- unsigned int dst_sel_y : SQ_VTX_WORD1_DST_SEL_Y_SIZE;
- unsigned int dst_sel_x : SQ_VTX_WORD1_DST_SEL_X_SIZE;
- unsigned int : 9;
- } sq_vtx_word1_t;
-
-#endif
-
-typedef union {
- unsigned int val : 32;
- sq_vtx_word1_t f;
-} sq_vtx_word1_u;
-
-
-/*
- * SQ_VTX_WORD1_GPR struct
- */
-
-#define SQ_VTX_WORD1_GPR_DST_GPR_SIZE 7
-#define SQ_VTX_WORD1_GPR_DST_REL_SIZE 1
-
-#define SQ_VTX_WORD1_GPR_DST_GPR_SHIFT 0
-#define SQ_VTX_WORD1_GPR_DST_REL_SHIFT 7
-
-#define SQ_VTX_WORD1_GPR_DST_GPR_MASK 0x0000007f
-#define SQ_VTX_WORD1_GPR_DST_REL_MASK 0x00000080
-
-#define SQ_VTX_WORD1_GPR_MASK \
- (SQ_VTX_WORD1_GPR_DST_GPR_MASK | \
- SQ_VTX_WORD1_GPR_DST_REL_MASK)
-
-#define SQ_VTX_WORD1_GPR_DEFAULT 0x000000cd
-
-#define SQ_VTX_WORD1_GPR_GET_DST_GPR(sq_vtx_word1_gpr) \
- ((sq_vtx_word1_gpr & SQ_VTX_WORD1_GPR_DST_GPR_MASK) >> SQ_VTX_WORD1_GPR_DST_GPR_SHIFT)
-#define SQ_VTX_WORD1_GPR_GET_DST_REL(sq_vtx_word1_gpr) \
- ((sq_vtx_word1_gpr & SQ_VTX_WORD1_GPR_DST_REL_MASK) >> SQ_VTX_WORD1_GPR_DST_REL_SHIFT)
-
-#define SQ_VTX_WORD1_GPR_SET_DST_GPR(sq_vtx_word1_gpr_reg, dst_gpr) \
- sq_vtx_word1_gpr_reg = (sq_vtx_word1_gpr_reg & ~SQ_VTX_WORD1_GPR_DST_GPR_MASK) | (dst_gpr << SQ_VTX_WORD1_GPR_DST_GPR_SHIFT)
-#define SQ_VTX_WORD1_GPR_SET_DST_REL(sq_vtx_word1_gpr_reg, dst_rel) \
- sq_vtx_word1_gpr_reg = (sq_vtx_word1_gpr_reg & ~SQ_VTX_WORD1_GPR_DST_REL_MASK) | (dst_rel << SQ_VTX_WORD1_GPR_DST_REL_SHIFT)
-
-#if defined(LITTLEENDIAN_CPU)
-
- typedef struct _sq_vtx_word1_gpr_t {
- unsigned int dst_gpr : SQ_VTX_WORD1_GPR_DST_GPR_SIZE;
- unsigned int dst_rel : SQ_VTX_WORD1_GPR_DST_REL_SIZE;
- unsigned int : 24;
- } sq_vtx_word1_gpr_t;
-
-#elif defined(BIGENDIAN_CPU)
-
- typedef struct _sq_vtx_word1_gpr_t {
- unsigned int : 24;
- unsigned int dst_rel : SQ_VTX_WORD1_GPR_DST_REL_SIZE;
- unsigned int dst_gpr : SQ_VTX_WORD1_GPR_DST_GPR_SIZE;
- } sq_vtx_word1_gpr_t;
-
-#endif
-
-typedef union {
- unsigned int val : 32;
- sq_vtx_word1_gpr_t f;
-} sq_vtx_word1_gpr_u;
-
-
-/*
- * SQ_VTX_WORD1_SEM struct
- */
-
-#define SQ_VTX_WORD1_SEM_SEMANTIC_ID_SIZE 8
-
-#define SQ_VTX_WORD1_SEM_SEMANTIC_ID_SHIFT 0
-
-#define SQ_VTX_WORD1_SEM_SEMANTIC_ID_MASK 0x000000ff
-
-#define SQ_VTX_WORD1_SEM_MASK \
- (SQ_VTX_WORD1_SEM_SEMANTIC_ID_MASK)
-
-#define SQ_VTX_WORD1_SEM_DEFAULT 0x000000cd
-
-#define SQ_VTX_WORD1_SEM_GET_SEMANTIC_ID(sq_vtx_word1_sem) \
- ((sq_vtx_word1_sem & SQ_VTX_WORD1_SEM_SEMANTIC_ID_MASK) >> SQ_VTX_WORD1_SEM_SEMANTIC_ID_SHIFT)
-
-#define SQ_VTX_WORD1_SEM_SET_SEMANTIC_ID(sq_vtx_word1_sem_reg, semantic_id) \
- sq_vtx_word1_sem_reg = (sq_vtx_word1_sem_reg & ~SQ_VTX_WORD1_SEM_SEMANTIC_ID_MASK) | (semantic_id << SQ_VTX_WORD1_SEM_SEMANTIC_ID_SHIFT)
-
-#if defined(LITTLEENDIAN_CPU)
-
- typedef struct _sq_vtx_word1_sem_t {
- unsigned int semantic_id : SQ_VTX_WORD1_SEM_SEMANTIC_ID_SIZE;
- unsigned int : 24;
- } sq_vtx_word1_sem_t;
-
-#elif defined(BIGENDIAN_CPU)
-
- typedef struct _sq_vtx_word1_sem_t {
- unsigned int : 24;
- unsigned int semantic_id : SQ_VTX_WORD1_SEM_SEMANTIC_ID_SIZE;
- } sq_vtx_word1_sem_t;
-
-#endif
-
-typedef union {
- unsigned int val : 32;
- sq_vtx_word1_sem_t f;
-} sq_vtx_word1_sem_u;
-
-
-/*
- * SQ_VTX_WORD2 struct
- */
-
-#define SQ_VTX_WORD2_OFFSET_SIZE 16
-#define SQ_VTX_WORD2_ENDIAN_SWAP_SIZE 2
-#define SQ_VTX_WORD2_CONST_BUF_NO_STRIDE_SIZE 1
-#define SQ_VTX_WORD2_MEGA_FETCH_SIZE 1
-#define SQ_VTX_WORD2_ALT_CONST_SIZE 1
-
-#define SQ_VTX_WORD2_OFFSET_SHIFT 0
-#define SQ_VTX_WORD2_ENDIAN_SWAP_SHIFT 16
-#define SQ_VTX_WORD2_CONST_BUF_NO_STRIDE_SHIFT 18
-#define SQ_VTX_WORD2_MEGA_FETCH_SHIFT 19
-#define SQ_VTX_WORD2_ALT_CONST_SHIFT 20
-
-#define SQ_VTX_WORD2_OFFSET_MASK 0x0000ffff
-#define SQ_VTX_WORD2_ENDIAN_SWAP_MASK 0x00030000
-#define SQ_VTX_WORD2_CONST_BUF_NO_STRIDE_MASK 0x00040000
-#define SQ_VTX_WORD2_MEGA_FETCH_MASK 0x00080000
-#define SQ_VTX_WORD2_ALT_CONST_MASK 0x00100000
-
-#define SQ_VTX_WORD2_MASK \
- (SQ_VTX_WORD2_OFFSET_MASK | \
- SQ_VTX_WORD2_ENDIAN_SWAP_MASK | \
- SQ_VTX_WORD2_CONST_BUF_NO_STRIDE_MASK | \
- SQ_VTX_WORD2_MEGA_FETCH_MASK | \
- SQ_VTX_WORD2_ALT_CONST_MASK)
-
-#define SQ_VTX_WORD2_DEFAULT 0x000dcdcd
-
-#define SQ_VTX_WORD2_GET_OFFSET(sq_vtx_word2) \
- ((sq_vtx_word2 & SQ_VTX_WORD2_OFFSET_MASK) >> SQ_VTX_WORD2_OFFSET_SHIFT)
-#define SQ_VTX_WORD2_GET_ENDIAN_SWAP(sq_vtx_word2) \
- ((sq_vtx_word2 & SQ_VTX_WORD2_ENDIAN_SWAP_MASK) >> SQ_VTX_WORD2_ENDIAN_SWAP_SHIFT)
-#define SQ_VTX_WORD2_GET_CONST_BUF_NO_STRIDE(sq_vtx_word2) \
- ((sq_vtx_word2 & SQ_VTX_WORD2_CONST_BUF_NO_STRIDE_MASK) >> SQ_VTX_WORD2_CONST_BUF_NO_STRIDE_SHIFT)
-#define SQ_VTX_WORD2_GET_MEGA_FETCH(sq_vtx_word2) \
- ((sq_vtx_word2 & SQ_VTX_WORD2_MEGA_FETCH_MASK) >> SQ_VTX_WORD2_MEGA_FETCH_SHIFT)
-#define SQ_VTX_WORD2_GET_ALT_CONST(sq_vtx_word2) \
- ((sq_vtx_word2 & SQ_VTX_WORD2_ALT_CONST_MASK) >> SQ_VTX_WORD2_ALT_CONST_SHIFT)
-
-#define SQ_VTX_WORD2_SET_OFFSET(sq_vtx_word2_reg, offset) \
- sq_vtx_word2_reg = (sq_vtx_word2_reg & ~SQ_VTX_WORD2_OFFSET_MASK) | (offset << SQ_VTX_WORD2_OFFSET_SHIFT)
-#define SQ_VTX_WORD2_SET_ENDIAN_SWAP(sq_vtx_word2_reg, endian_swap) \
- sq_vtx_word2_reg = (sq_vtx_word2_reg & ~SQ_VTX_WORD2_ENDIAN_SWAP_MASK) | (endian_swap << SQ_VTX_WORD2_ENDIAN_SWAP_SHIFT)
-#define SQ_VTX_WORD2_SET_CONST_BUF_NO_STRIDE(sq_vtx_word2_reg, const_buf_no_stride) \
- sq_vtx_word2_reg = (sq_vtx_word2_reg & ~SQ_VTX_WORD2_CONST_BUF_NO_STRIDE_MASK) | (const_buf_no_stride << SQ_VTX_WORD2_CONST_BUF_NO_STRIDE_SHIFT)
-#define SQ_VTX_WORD2_SET_MEGA_FETCH(sq_vtx_word2_reg, mega_fetch) \
- sq_vtx_word2_reg = (sq_vtx_word2_reg & ~SQ_VTX_WORD2_MEGA_FETCH_MASK) | (mega_fetch << SQ_VTX_WORD2_MEGA_FETCH_SHIFT)
-#define SQ_VTX_WORD2_SET_ALT_CONST(sq_vtx_word2_reg, alt_const) \
- sq_vtx_word2_reg = (sq_vtx_word2_reg & ~SQ_VTX_WORD2_ALT_CONST_MASK) | (alt_const << SQ_VTX_WORD2_ALT_CONST_SHIFT)
-
-#if defined(LITTLEENDIAN_CPU)
-
- typedef struct _sq_vtx_word2_t {
- unsigned int offset : SQ_VTX_WORD2_OFFSET_SIZE;
- unsigned int endian_swap : SQ_VTX_WORD2_ENDIAN_SWAP_SIZE;
- unsigned int const_buf_no_stride : SQ_VTX_WORD2_CONST_BUF_NO_STRIDE_SIZE;
- unsigned int mega_fetch : SQ_VTX_WORD2_MEGA_FETCH_SIZE;
- unsigned int alt_const : SQ_VTX_WORD2_ALT_CONST_SIZE;
- unsigned int : 11;
- } sq_vtx_word2_t;
-
-#elif defined(BIGENDIAN_CPU)
-
- typedef struct _sq_vtx_word2_t {
- unsigned int : 11;
- unsigned int alt_const : SQ_VTX_WORD2_ALT_CONST_SIZE;
- unsigned int mega_fetch : SQ_VTX_WORD2_MEGA_FETCH_SIZE;
- unsigned int const_buf_no_stride : SQ_VTX_WORD2_CONST_BUF_NO_STRIDE_SIZE;
- unsigned int endian_swap : SQ_VTX_WORD2_ENDIAN_SWAP_SIZE;
- unsigned int offset : SQ_VTX_WORD2_OFFSET_SIZE;
- } sq_vtx_word2_t;
-
-#endif
-
-typedef union {
- unsigned int val : 32;
- sq_vtx_word2_t f;
-} sq_vtx_word2_u;
-
-#endif /* _SQ_MICRO_REG_H */
-
-
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