armv7-r/mpu: remove unnecessary ifdef

'armv7-r/mpu.h' is included only when CONFIG_ARCH_CORTEXR4=y. So, it is
always CONFIG_ARCH_CORTEXR4 is defined and we do not need to check or
have codes for the opposite case.

Change-Id: Ia5a46127e187a9b7b0ccf09cf0618443b47d80bf
Signed-off-by: Heesub Shin <heesub.shin@samsung.com>

diff --git a/os/arch/arm/src/armv7-r/mpu.h b/os/arch/arm/src/armv7-r/mpu.h
index 5610096..2b6d276 100644 (file)
--- a/os/arch/arm/src/armv7-r/mpu.h
+++ b/os/arch/arm/src/armv7-r/mpu.h
@@ -899,9 +899,6 @@ static inline void mpu_priv_intsram_wb(uintptr_t base, size_t size, int region)
        /* WB/Write Allocate: TEX(5), C(0), B(1), S(1) */
        regval =                                          /* Not Cacheable  */
                 MPU_RACR_B                             | /* Not Bufferable */
-#if !defined(CONFIG_ARCH_CORTEXR4)
-                MPU_RACR_S                             | /* Shareable      */
-#endif
                 MPU_RACR_TEX(5)                        | /* TEX */
                 MPU_RACR_AP_RWNO;                        /* P:RW   U:NO */
        mpu_set_dracr(regval);
@@ -931,12 +928,9 @@ static inline void mpu_user_intsram_ro(uintptr_t base, size_t size, int region)
        subregions = mpu_subregion(base, size, l2size);
 
        /* The configure the region */
-       /* WB/Write Allocate: TEX(5), C(0), B(1), S(1) except cortex-r4(S(0)) */
+       /* WB/Write Allocate: TEX(5), C(0), B(1), S(1) */
        regval =                                          /* Not Cacheable  */
                 MPU_RACR_B                             | /* Not Bufferable */
-#if !defined(CONFIG_ARCH_CORTEXR4)
-                MPU_RACR_S                             | /* Shareable      */
-#endif
                 MPU_RACR_TEX(5)                        | /* TEX */
                 MPU_RACR_AP_RWNO;                        /* P:RW   U:NO */
        mpu_set_dracr(regval);
@@ -975,12 +969,9 @@ static inline void mpu_user_intsram_wb(uintptr_t base, size_t size, int region)
        subregions = mpu_subregion(base, size, l2size);
 
        /* The configure the region */
-       /* WB/Write Allocate: TEX(5), C(0), B(1), S(1) except cortex-r4(S(0)) */
+       /* WB/Write Allocate: TEX(5), C(0), B(1), S(1) */
        regval =                                          /* Not Cacheable  */
                 MPU_RACR_B                             | /* Not Bufferable */
-#if !defined(CONFIG_ARCH_CORTEXR4)
-                MPU_RACR_S                             | /* Shareable      */
-#endif
                 MPU_RACR_TEX(5)                        | /* TEX            */
                 MPU_RACR_AP_RWRW;                        /* P:RW   U:RW    */
        mpu_set_dracr(regval);