ARM: rockchip: add sram dt nodes and documentation
authorHeiko Stuebner <heiko@sntech.de>
Mon, 17 Jun 2013 20:08:31 +0000 (22:08 +0200)
committerHeiko Stuebner <heiko@sntech.de>
Sat, 1 Mar 2014 15:10:07 +0000 (16:10 +0100)
Add dt-nodes for the sram on rk3066 and rk3188 including the reserved section
needed for smp bringup.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Ulrich Prinz <ulrich.prinz@googlemail.com>
Documentation/devicetree/bindings/arm/rockchip/smp-sram.txt [new file with mode: 0644]
arch/arm/boot/dts/rk3066a.dtsi
arch/arm/boot/dts/rk3188.dtsi

diff --git a/Documentation/devicetree/bindings/arm/rockchip/smp-sram.txt b/Documentation/devicetree/bindings/arm/rockchip/smp-sram.txt
new file mode 100644 (file)
index 0000000..d9416fb
--- /dev/null
@@ -0,0 +1,30 @@
+Rockchip SRAM for smp bringup:
+------------------------------
+
+Rockchip's smp-capable SoCs use the first part of the sram for the bringup
+of the cores. Once the core gets powered up it executes the code that is
+residing at the very beginning of the sram.
+
+Therefore a reserved section sub-node has to be added to the mmio-sram
+declaration.
+
+Required sub-node properties:
+- compatible : should be "rockchip,rk3066-smp-sram"
+
+The rest of the properties should follow the generic mmio-sram discription
+found in ../../misc/sram.txt
+
+Example:
+
+       sram: sram@10080000 {
+               compatible = "mmio-sram";
+               reg = <0x10080000 0x10000>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges;
+
+               smp-sram@10080000 {
+                       compatible = "rockchip,rk3066-smp-sram";
+                       reg = <0x10080000 0x50>;
+               };
+       };
index be5d2b0..4d4dfbb 100644 (file)
                        clock-names = "timer", "pclk";
                };
 
+               sram: sram@10080000 {
+                       compatible = "mmio-sram";
+                       reg = <0x10080000 0x10000>;
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges = <0 0x10080000 0x10000>;
+
+                       smp-sram@0 {
+                               compatible = "rockchip,rk3066-smp-sram";
+                               reg = <0x0 0x50>;
+                       };
+               };
+
                pinctrl@20008000 {
                        compatible = "rockchip,rk3066a-pinctrl";
                        reg = <0x20008000 0x150>;
index 1a26b03..bb36596 100644 (file)
                        interrupts = <GIC_PPI 13 0xf04>;
                };
 
+               sram: sram@10080000 {
+                       compatible = "mmio-sram";
+                       reg = <0x10080000 0x8000>;
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges = <0 0x10080000 0x8000>;
+
+                       smp-sram@0 {
+                               compatible = "rockchip,rk3066-smp-sram";
+                               reg = <0x0 0x50>;
+                       };
+               };
+
                pinctrl@20008000 {
                        compatible = "rockchip,rk3188-pinctrl";
                        reg = <0x20008000 0xa0>,