arm64: dts: qcom: sa8775p: add USB nodes

Add nodes for the USB and it's PHY on sa8775p platform.

Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230428130824.23803-6-quic_shazhuss@quicinc.com

diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index 0737ba3..fa3a2a4 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -455,8 +455,8 @@
                                 <0>,
                                 <0>,
                                 <0>,
-                                <0>,
-                                <0>,
+                                <&usb_0_qmpphy>,
+                                <&usb_1_qmpphy>,
                                 <0>,
                                 <0>,
                                 <0>,
@@ -649,6 +649,241 @@
                        status = "disabled";
                };
 
+               usb_0_hsphy: phy@88e4000 {
+                       compatible = "qcom,sa8775p-usb-hs-phy",
+                                    "qcom,usb-snps-hs-5nm-phy";
+                       reg = <0 0x088e4000 0 0x120>;
+                       clocks = <&rpmhcc RPMH_CXO_CLK>;
+                       clock-names = "ref";
+                       resets = <&gcc GCC_USB2_PHY_PRIM_BCR>;
+
+                       #phy-cells = <0>;
+
+                       status = "disabled";
+               };
+
+               usb_0_qmpphy: phy@88e8000 {
+                       compatible = "qcom,sa8775p-qmp-usb3-uni-phy";
+                       reg = <0 0x088e8000 0 0x2000>;
+
+                       clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
+                                <&gcc GCC_USB_CLKREF_EN>,
+                                <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
+                                <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
+                       clock-names = "aux", "ref", "com_aux", "pipe";
+
+                       resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
+                                <&gcc GCC_USB3PHY_PHY_PRIM_BCR>;
+                       reset-names = "phy", "phy_phy";
+
+                       power-domains = <&gcc USB30_PRIM_GDSC>;
+
+                       #clock-cells = <0>;
+                       clock-output-names = "usb3_prim_phy_pipe_clk_src";
+
+                       #phy-cells = <0>;
+
+                       status = "disabled";
+               };
+
+               usb_0: usb@a6f8800 {
+                       compatible = "qcom,sa8775p-dwc3", "qcom,dwc3";
+                       reg = <0 0x0a6f8800 0 0x400>;
+                       #address-cells = <2>;
+                       #size-cells = <2>;
+                       ranges;
+
+                       clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
+                                <&gcc GCC_USB30_PRIM_MASTER_CLK>,
+                                <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
+                                <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
+                                <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
+                       clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi";
+
+                       assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
+                                         <&gcc GCC_USB30_PRIM_MASTER_CLK>;
+                       assigned-clock-rates = <19200000>, <200000000>;
+
+                       interrupts-extended = <&intc GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>,
+                                             <&pdc 14 IRQ_TYPE_EDGE_RISING>,
+                                             <&pdc 15 IRQ_TYPE_EDGE_RISING>,
+                                             <&pdc 12 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "pwr_event",
+                                         "dp_hs_phy_irq",
+                                         "dm_hs_phy_irq",
+                                         "ss_phy_irq";
+
+                       power-domains = <&gcc USB30_PRIM_GDSC>;
+                       required-opps = <&rpmhpd_opp_nom>;
+
+                       resets = <&gcc GCC_USB30_PRIM_BCR>;
+
+                       interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
+                                       <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
+                       interconnect-names = "usb-ddr", "apps-usb";
+
+                       wakeup-source;
+
+                       status = "disabled";
+
+                       usb_0_dwc3: usb@a600000 {
+                               compatible = "snps,dwc3";
+                               reg = <0 0x0a600000 0 0xe000>;
+                               interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>;
+                               iommus = <&apps_smmu 0x080 0x0>;
+                               phys = <&usb_0_hsphy>, <&usb_0_qmpphy>;
+                               phy-names = "usb2-phy", "usb3-phy";
+                       };
+               };
+
+               usb_1_hsphy: phy@88e6000 {
+                       compatible = "qcom,sa8775p-usb-hs-phy",
+                                    "qcom,usb-snps-hs-5nm-phy";
+                       reg = <0 0x088e6000 0 0x120>;
+                       clocks = <&gcc GCC_USB_CLKREF_EN>;
+                       clock-names = "ref";
+                       resets = <&gcc GCC_USB2_PHY_SEC_BCR>;
+
+                       #phy-cells = <0>;
+
+                       status = "disabled";
+               };
+
+               usb_1_qmpphy: phy@88ea000 {
+                       compatible = "qcom,sa8775p-qmp-usb3-uni-phy";
+                       reg = <0 0x088ea000 0 0x2000>;
+
+                       clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
+                                <&gcc GCC_USB_CLKREF_EN>,
+                                <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>,
+                                <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
+                       clock-names = "aux", "ref", "com_aux", "pipe";
+
+                       resets = <&gcc GCC_USB3_PHY_SEC_BCR>,
+                                <&gcc GCC_USB3PHY_PHY_SEC_BCR>;
+                       reset-names = "phy", "phy_phy";
+
+                       power-domains = <&gcc USB30_SEC_GDSC>;
+
+                       #clock-cells = <0>;
+                       clock-output-names = "usb3_sec_phy_pipe_clk_src";
+
+                       #phy-cells = <0>;
+
+                       status = "disabled";
+               };
+
+               usb_1: usb@a8f8800 {
+                       compatible = "qcom,sa8775p-dwc3", "qcom,dwc3";
+                       reg = <0 0x0a8f8800 0 0x400>;
+                       #address-cells = <2>;
+                       #size-cells = <2>;
+                       ranges;
+
+                       clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
+                                <&gcc GCC_USB30_SEC_MASTER_CLK>,
+                                <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
+                                <&gcc GCC_USB30_SEC_SLEEP_CLK>,
+                                <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>;
+                       clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi";
+
+                       assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
+                                         <&gcc GCC_USB30_SEC_MASTER_CLK>;
+                       assigned-clock-rates = <19200000>, <200000000>;
+
+                       interrupts-extended = <&intc GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
+                                             <&pdc 8 IRQ_TYPE_EDGE_RISING>,
+                                             <&pdc 7 IRQ_TYPE_EDGE_RISING>,
+                                             <&pdc 13 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "pwr_event",
+                                         "dp_hs_phy_irq",
+                                         "dm_hs_phy_irq",
+                                         "ss_phy_irq";
+
+                       power-domains = <&gcc USB30_SEC_GDSC>;
+                       required-opps = <&rpmhpd_opp_nom>;
+
+                       resets = <&gcc GCC_USB30_SEC_BCR>;
+
+                       interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>,
+                                       <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
+                       interconnect-names = "usb-ddr", "apps-usb";
+
+                       wakeup-source;
+
+                       status = "disabled";
+
+                       usb_1_dwc3: usb@a800000 {
+                               compatible = "snps,dwc3";
+                               reg = <0 0x0a800000 0 0xe000>;
+                               interrupts = <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>;
+                               iommus = <&apps_smmu 0x0a0 0x0>;
+                               phys = <&usb_1_hsphy>, <&usb_1_qmpphy>;
+                               phy-names = "usb2-phy", "usb3-phy";
+                       };
+               };
+
+               usb_2_hsphy: phy@88e7000 {
+                       compatible = "qcom,sa8775p-usb-hs-phy",
+                                    "qcom,usb-snps-hs-5nm-phy";
+                       reg = <0 0x088e7000 0 0x120>;
+                       clocks = <&gcc GCC_USB_CLKREF_EN>;
+                       clock-names = "ref";
+                       resets = <&gcc GCC_USB3_PHY_TERT_BCR>;
+
+                       #phy-cells = <0>;
+
+                       status = "disabled";
+               };
+
+               usb_2: usb@a4f8800 {
+                       compatible = "qcom,sa8775p-dwc3", "qcom,dwc3";
+                       reg = <0 0x0a4f8800 0 0x400>;
+                       #address-cells = <2>;
+                       #size-cells = <2>;
+                       ranges;
+
+                       clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>,
+                                <&gcc GCC_USB20_MASTER_CLK>,
+                                <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>,
+                                <&gcc GCC_USB20_SLEEP_CLK>,
+                                <&gcc GCC_USB20_MOCK_UTMI_CLK>;
+                       clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi";
+
+                       assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
+                                         <&gcc GCC_USB20_MASTER_CLK>;
+                       assigned-clock-rates = <19200000>, <200000000>;
+
+                       interrupts-extended = <&intc GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
+                                             <&pdc 10 IRQ_TYPE_EDGE_RISING>,
+                                             <&pdc 9 IRQ_TYPE_EDGE_RISING>;
+                       interrupt-names = "pwr_event",
+                                         "dp_hs_phy_irq",
+                                         "dm_hs_phy_irq";
+
+                       power-domains = <&gcc USB20_PRIM_GDSC>;
+                       required-opps = <&rpmhpd_opp_nom>;
+
+                       resets = <&gcc GCC_USB20_PRIM_BCR>;
+
+                       interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>,
+                                       <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB2 0>;
+                       interconnect-names = "usb-ddr", "apps-usb";
+
+                       wakeup-source;
+
+                       status = "disabled";
+
+                       usb_2_dwc3: usb@a400000 {
+                               compatible = "snps,dwc3";
+                               reg = <0 0x0a400000 0 0xe000>;
+                               interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>;
+                               iommus = <&apps_smmu 0x020 0x0>;
+                               phys = <&usb_2_hsphy>;
+                               phy-names = "usb2-phy";
+                       };
+               };
+
                tcsr_mutex: hwlock@1f40000 {
                        compatible = "qcom,tcsr-mutex";
                        reg = <0x0 0x01f40000 0x0 0x20000>;