dm: ls1021a: Bring in ls1021a dts files from linux kernel

Bring in required device tree files for ls1021a from Linux.
These are initially unchanged and have a number of pieces not needed by U-Boot.

Signed-off-by: Haikun Wang <Haikun.Wang@freescale.com>
Acked-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index f897e6d..09708d9 100644 (file)
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -54,6 +54,9 @@ dtb-$(CONFIG_SOCFPGA) +=                              \
        socfpga_cyclone5_socdk.dtb                      \
        socfpga_cyclone5_socrates.dtb
 
+dtb-$(CONFIG_LS102XA) += ls1021a-qds.dtb \
+       ls1021a-twr.dtb
+
 targets += $(dtb-y)
 
 DTC_FLAGS += -R 4 -p 0x1000

diff --git a/arch/arm/dts/ls1021a-qds.dts b/arch/arm/dts/ls1021a-qds.dts
new file mode 100644 (file)
index 0000000..c89f85e
--- /dev/null
+++ b/arch/arm/dts/ls1021a-qds.dts
@@ -0,0 +1,201 @@
+/*
+ * Freescale ls1021a QDS board device tree source
+ *
+ * Copyright 2013-2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+/dts-v1/;
+#include "ls1021a.dtsi"
+
+/ {
+       model = "LS1021A QDS Board";
+
+       aliases {
+               enet0_rgmii_phy = &rgmii_phy1;
+               enet1_rgmii_phy = &rgmii_phy2;
+               enet2_rgmii_phy = &rgmii_phy3;
+               enet0_sgmii_phy = &sgmii_phy1c;
+               enet1_sgmii_phy = &sgmii_phy1d;
+       };
+};
+
+&dspi0 {
+       bus-num = <0>;
+       status = "okay";
+
+       dspiflash: at45db021d@0 {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "atmel,at45db021d", "atmel,at45", "atmel,dataflash";
+               spi-max-frequency = <16000000>;
+               spi-cpol;
+               spi-cpha;
+               reg = <0>;
+       };
+};
+
+&i2c0 {
+       status = "okay";
+
+       pca9547: mux@77 {
+               reg = <0x77>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               i2c@0 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0x0>;
+
+                       ds3232: rtc@68 {
+                               compatible = "dallas,ds3232";
+                               reg = <0x68>;
+                               interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+                       };
+               };
+
+               i2c@2 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0x2>;
+
+                       ina220@40 {
+                               compatible = "ti,ina220";
+                               reg = <0x40>;
+                               shunt-resistor = <1000>;
+                       };
+
+                       ina220@41 {
+                               compatible = "ti,ina220";
+                               reg = <0x41>;
+                               shunt-resistor = <1000>;
+                       };
+               };
+
+               i2c@3 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0x3>;
+
+                       eeprom@56 {
+                               compatible = "atmel,24c512";
+                               reg = <0x56>;
+                       };
+
+                       eeprom@57 {
+                               compatible = "atmel,24c512";
+                               reg = <0x57>;
+                       };
+
+                       adt7461a@4c {
+                               compatible = "adi,adt7461a";
+                               reg = <0x4c>;
+                       };
+               };
+       };
+};
+
+&ifc {
+       #address-cells = <2>;
+       #size-cells = <1>;
+       /* NOR, NAND Flashes and FPGA on board */
+       ranges = <0x0 0x0 0x0 0x60000000 0x08000000
+                 0x2 0x0 0x0 0x7e800000 0x00010000
+                 0x3 0x0 0x0 0x7fb00000 0x00000100>;
+       status = "okay";
+
+       nor@0,0 {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "cfi-flash";
+               reg = <0x0 0x0 0x8000000>;
+               bank-width = <2>;
+               device-width = <1>;
+       };
+
+       fpga: board-control@3,0 {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "simple-bus";
+               reg = <0x3 0x0 0x0000100>;
+               bank-width = <1>;
+               device-width = <1>;
+               ranges = <0 3 0 0x100>;
+
+               mdio-mux-emi1 {
+                       compatible = "mdio-mux-mmioreg";
+                       mdio-parent-bus = <&mdio0>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0x54 1>; /* BRDCFG4 */
+                       mux-mask = <0xe0>; /* EMI1[2:0] */
+
+                       /* Onboard PHYs */
+                       ls1021amdio0: mdio@0 {
+                               reg = <0>;
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               rgmii_phy1: ethernet-phy@1 {
+                                       reg = <0x1>;
+                               };
+                       };
+
+                       ls1021amdio1: mdio@20 {
+                               reg = <0x20>;
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               rgmii_phy2: ethernet-phy@2 {
+                                       reg = <0x2>;
+                               };
+                       };
+
+                       ls1021amdio2: mdio@40 {
+                               reg = <0x40>;
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               rgmii_phy3: ethernet-phy@3 {
+                                       reg = <0x3>;
+                               };
+                       };
+
+                       ls1021amdio3: mdio@60 {
+                               reg = <0x60>;
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               sgmii_phy1c: ethernet-phy@1c {
+                                       reg = <0x1c>;
+                               };
+                       };
+
+                       ls1021amdio4: mdio@80 {
+                               reg = <0x80>;
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               sgmii_phy1d: ethernet-phy@1d {
+                                       reg = <0x1d>;
+                               };
+                       };
+               };
+       };
+};
+
+&lpuart0 {
+       status = "okay";
+};
+
+&mdio0 {
+       tbi0: tbi-phy@8 {
+               reg = <0x8>;
+               device_type = "tbi-phy";
+       };
+};
+
+&uart0 {
+       status = "okay";
+};
+
+&uart1 {
+       status = "okay";
+};

diff --git a/arch/arm/dts/ls1021a-twr.dts b/arch/arm/dts/ls1021a-twr.dts
new file mode 100644 (file)
index 0000000..34ac82d
--- /dev/null
+++ b/arch/arm/dts/ls1021a-twr.dts
@@ -0,0 +1,88 @@
+/*
+ * Freescale ls1021a TWR board device tree source
+ *
+ * Copyright 2013-2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+/dts-v1/;
+#include "ls1021a.dtsi"
+
+/ {
+       model = "LS1021A TWR Board";
+
+       aliases {
+               enet2_rgmii_phy = &rgmii_phy1;
+               enet0_sgmii_phy = &sgmii_phy2;
+               enet1_sgmii_phy = &sgmii_phy0;
+       };
+};
+
+&dspi1 {
+       bus-num = <0>;
+       status = "okay";
+
+       dspiflash: s25fl064k@0 {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "spansion,s25fl064k";
+               spi-max-frequency = <16000000>;
+               spi-cpol;
+               spi-cpha;
+               reg = <0>;
+       };
+};
+
+&i2c0 {
+       status = "okay";
+};
+
+&i2c1 {
+       status = "okay";
+};
+
+&ifc {
+       #address-cells = <2>;
+       #size-cells = <1>;
+       /* NOR Flash on board */
+       ranges = <0x0 0x0 0x0 0x60000000 0x08000000>;
+       status = "okay";
+
+       nor@0,0 {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "cfi-flash";
+               reg = <0x0 0x0 0x8000000>;
+               bank-width = <2>;
+               device-width = <1>;
+       };
+};
+
+&lpuart0 {
+       status = "okay";
+};
+
+&mdio0 {
+       sgmii_phy0: ethernet-phy@0 {
+               reg = <0x0>;
+       };
+       rgmii_phy1: ethernet-phy@1 {
+               reg = <0x1>;
+       };
+       sgmii_phy2: ethernet-phy@2 {
+               reg = <0x2>;
+       };
+       tbi1: tbi-phy@1f {
+               reg = <0x1f>;
+               device_type = "tbi-phy";
+       };
+};
+
+&uart0 {
+       status = "okay";
+};
+
+&uart1 {
+       status = "okay";
+};

diff --git a/arch/arm/dts/ls1021a.dtsi b/arch/arm/dts/ls1021a.dtsi
new file mode 100644 (file)
index 0000000..434b938
--- /dev/null
+++ b/arch/arm/dts/ls1021a.dtsi
@@ -0,0 +1,370 @@
+/*
+ * Freescale ls1021a SOC common device tree source
+ *
+ * Copyright 2013-2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include "skeleton64.dtsi"
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+       compatible = "fsl,ls1021a";
+       interrupt-parent = <&gic>;
+
+       aliases {
+               serial0 = &lpuart0;
+               serial1 = &lpuart1;
+               serial2 = &lpuart2;
+               serial3 = &lpuart3;
+               serial4 = &lpuart4;
+               serial5 = &lpuart5;
+               sysclk = &sysclk;
+       };
+
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               cpu@f00 {
+                       compatible = "arm,cortex-a7";
+                       device_type = "cpu";
+                       reg = <0xf00>;
+                       clocks = <&cluster1_clk>;
+               };
+
+               cpu@f01 {
+                       compatible = "arm,cortex-a7";
+                       device_type = "cpu";
+                       reg = <0xf01>;
+                       clocks = <&cluster1_clk>;
+               };
+       };
+
+       timer {
+               compatible = "arm,armv7-timer";
+               interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+                            <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+                            <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+                            <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+       };
+
+       pmu {
+               compatible = "arm,cortex-a7-pmu";
+               interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+       };
+
+       soc {
+               compatible = "simple-bus";
+               #address-cells = <2>;
+               #size-cells = <2>;
+               device_type = "soc";
+               interrupt-parent = <&gic>;
+               ranges;
+
+               gic: interrupt-controller@1400000 {
+                       compatible = "arm,cortex-a7-gic";
+                       #interrupt-cells = <3>;
+                       interrupt-controller;
+                       reg = <0x0 0x1401000 0x0 0x1000>,
+                             <0x0 0x1402000 0x0 0x1000>,
+                             <0x0 0x1404000 0x0 0x2000>,
+                             <0x0 0x1406000 0x0 0x2000>;
+                       interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+
+               };
+
+               ifc: ifc@1530000 {
+                       compatible = "fsl,ifc", "simple-bus";
+                       reg = <0x0 0x1530000 0x0 0x10000>;
+                       interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+               };
+
+               dcfg: dcfg@1ee0000 {
+                       compatible = "fsl,ls1021a-dcfg", "syscon";
+                       reg = <0x0 0x1ee0000 0x0 0x10000>;
+                       big-endian;
+               };
+
+               esdhc: esdhc@1560000 {
+                       compatible = "fsl,esdhc";
+                       reg = <0x0 0x1560000 0x0 0x10000>;
+                       interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+                       clock-frequency = <0>;
+                       voltage-ranges = <1800 1800 3300 3300>;
+                       sdhci,auto-cmd12;
+                       big-endian;
+                       bus-width = <4>;
+                       status = "disabled";
+               };
+
+               scfg: scfg@1570000 {
+                       compatible = "fsl,ls1021a-scfg", "syscon";
+                       reg = <0x0 0x1570000 0x0 0x10000>;
+                       big-endian;
+               };
+
+               clockgen: clocking@1ee1000 {
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges = <0x0 0x0 0x1ee1000 0x10000>;
+
+                       sysclk: sysclk {
+                               compatible = "fixed-clock";
+                               #clock-cells = <0>;
+                               clock-output-names = "sysclk";
+                       };
+
+                       cga_pll1: pll@800 {
+                               compatible = "fsl,qoriq-core-pll-2.0";
+                               #clock-cells = <1>;
+                               reg = <0x800 0x10>;
+                               clocks = <&sysclk>;
+                               clock-output-names = "cga-pll1", "cga-pll1-div2",
+                                                    "cga-pll1-div4";
+                       };
+
+                       platform_clk: pll@c00 {
+                               compatible = "fsl,qoriq-core-pll-2.0";
+                               #clock-cells = <1>;
+                               reg = <0xc00 0x10>;
+                               clocks = <&sysclk>;
+                               clock-output-names = "platform-clk", "platform-clk-div2";
+                       };
+
+                       cluster1_clk: clk0c0@0 {
+                               compatible = "fsl,qoriq-core-mux-2.0";
+                               #clock-cells = <0>;
+                               reg = <0x0 0x10>;
+                               clock-names = "pll1cga", "pll1cga-div2", "pll1cga-div4";
+                               clocks = <&cga_pll1 0>, <&cga_pll1 1>, <&cga_pll1 2>;
+                               clock-output-names = "cluster1-clk";
+                       };
+               };
+
+               dspi0: dspi@2100000 {
+                       compatible = "fsl,vf610-dspi";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0x0 0x2100000 0x0 0x10000>;
+                       interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+                       clock-names = "dspi";
+                       clocks = <&platform_clk 1>;
+                       spi-num-chipselects = <5>;
+                       big-endian;
+                       status = "disabled";
+               };
+
+               dspi1: dspi@2110000 {
+                       compatible = "fsl,vf610-dspi";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0x0 0x2110000 0x0 0x10000>;
+                       interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+                       clock-names = "dspi";
+                       clocks = <&platform_clk 1>;
+                       spi-num-chipselects = <5>;
+                       big-endian;
+                       status = "disabled";
+               };
+
+               i2c0: i2c@2180000 {
+                       compatible = "fsl,vf610-i2c";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0x0 0x2180000 0x0 0x10000>;
+                       interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+                       clock-names = "i2c";
+                       clocks = <&platform_clk 1>;
+                       status = "disabled";
+               };
+
+               i2c1: i2c@2190000 {
+                       compatible = "fsl,vf610-i2c";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0x0 0x2190000 0x0 0x10000>;
+                       interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+                       clock-names = "i2c";
+                       clocks = <&platform_clk 1>;
+                       status = "disabled";
+               };
+
+               i2c2: i2c@21a0000 {
+                       compatible = "fsl,vf610-i2c";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0x0 0x21a0000 0x0 0x10000>;
+                       interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+                       clock-names = "i2c";
+                       clocks = <&platform_clk 1>;
+                       status = "disabled";
+               };
+
+               uart0: serial@21c0500 {
+                       compatible = "fsl,16550-FIFO64", "ns16550a";
+                       reg = <0x0 0x21c0500 0x0 0x100>;
+                       interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+                       clock-frequency = <0>;
+                       fifo-size = <15>;
+                       status = "disabled";
+               };
+
+               uart1: serial@21c0600 {
+                       compatible = "fsl,16550-FIFO64", "ns16550a";
+                       reg = <0x0 0x21c0600 0x0 0x100>;
+                       interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+                       clock-frequency = <0>;
+                       fifo-size = <15>;
+                       status = "disabled";
+               };
+
+               uart2: serial@21d0500 {
+                       compatible = "fsl,16550-FIFO64", "ns16550a";
+                       reg = <0x0 0x21d0500 0x0 0x100>;
+                       interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+                       clock-frequency = <0>;
+                       fifo-size = <15>;
+                       status = "disabled";
+               };
+
+               uart3: serial@21d0600 {
+                       compatible = "fsl,16550-FIFO64", "ns16550a";
+                       reg = <0x0 0x21d0600 0x0 0x100>;
+                       interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+                       clock-frequency = <0>;
+                       fifo-size = <15>;
+                       status = "disabled";
+               };
+
+               lpuart0: serial@2950000 {
+                       compatible = "fsl,ls1021a-lpuart";
+                       reg = <0x0 0x2950000 0x0 0x1000>;
+                       interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&sysclk>;
+                       clock-names = "ipg";
+                       status = "disabled";
+               };
+
+               lpuart1: serial@2960000 {
+                       compatible = "fsl,ls1021a-lpuart";
+                       reg = <0x0 0x2960000 0x0 0x1000>;
+                       interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&platform_clk 1>;
+                       clock-names = "ipg";
+                       status = "disabled";
+               };
+
+               lpuart2: serial@2970000 {
+                       compatible = "fsl,ls1021a-lpuart";
+                       reg = <0x0 0x2970000 0x0 0x1000>;
+                       interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&platform_clk 1>;
+                       clock-names = "ipg";
+                       status = "disabled";
+               };
+
+               lpuart3: serial@2980000 {
+                       compatible = "fsl,ls1021a-lpuart";
+                       reg = <0x0 0x2980000 0x0 0x1000>;
+                       interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&platform_clk 1>;
+                       clock-names = "ipg";
+                       status = "disabled";
+               };
+
+               lpuart4: serial@2990000 {
+                       compatible = "fsl,ls1021a-lpuart";
+                       reg = <0x0 0x2990000 0x0 0x1000>;
+                       interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&platform_clk 1>;
+                       clock-names = "ipg";
+                       status = "disabled";
+               };
+
+               lpuart5: serial@29a0000 {
+                       compatible = "fsl,ls1021a-lpuart";
+                       reg = <0x0 0x29a0000 0x0 0x1000>;
+                       interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&platform_clk 1>;
+                       clock-names = "ipg";
+                       status = "disabled";
+               };
+
+               wdog0: watchdog@2ad0000 {
+                       compatible = "fsl,imx21-wdt";
+                       reg = <0x0 0x2ad0000 0x0 0x10000>;
+                       interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&platform_clk 1>;
+                       clock-names = "wdog-en";
+                       big-endian;
+               };
+
+               sai1: sai@2b50000 {
+                       compatible = "fsl,vf610-sai";
+                       reg = <0x0 0x2b50000 0x0 0x10000>;
+                       interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&platform_clk 1>;
+                       clock-names = "sai";
+                       dma-names = "tx", "rx";
+                       dmas = <&edma0 1 47>,
+                              <&edma0 1 46>;
+                       big-endian;
+                       status = "disabled";
+               };
+
+               sai2: sai@2b60000 {
+                       compatible = "fsl,vf610-sai";
+                       reg = <0x0 0x2b60000 0x0 0x10000>;
+                       interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&platform_clk 1>;
+                       clock-names = "sai";
+                       dma-names = "tx", "rx";
+                       dmas = <&edma0 1 45>,
+                              <&edma0 1 44>;
+                       big-endian;
+                       status = "disabled";
+               };
+
+               edma0: edma@2c00000 {
+                       #dma-cells = <2>;
+                       compatible = "fsl,vf610-edma";
+                       reg = <0x0 0x2c00000 0x0 0x10000>,
+                             <0x0 0x2c10000 0x0 0x10000>,
+                             <0x0 0x2c20000 0x0 0x10000>;
+                       interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "edma-tx", "edma-err";
+                       dma-channels = <32>;
+                       big-endian;
+                       clock-names = "dmamux0", "dmamux1";
+                       clocks = <&platform_clk 1>,
+                                <&platform_clk 1>;
+               };
+
+               mdio0: mdio@2d24000 {
+                       compatible = "gianfar";
+                       device_type = "mdio";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0x0 0x2d24000 0x0 0x4000>;
+               };
+
+               usb@8600000 {
+                       compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
+                       reg = <0x0 0x8600000 0x0 0x1000>;
+                       interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
+                       dr_mode = "host";
+                       phy_type = "ulpi";
+               };
+
+               usb3@3100000 {
+                       compatible = "snps,dwc3";
+                       reg = <0x0 0x3100000 0x0 0x10000>;
+                       interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+                       dr_mode = "host";
+               };
+       };
+};