ppc4xx: Changed 460EX/GT OCM TLB and internal SRAM initialization

Expanded OCM TLB to allow access to 64K OCM as well as 256K of
internal SRAM.

Adjusted internal SRAM initialization to match updated user
manual recommendation.

OCM & ISRAM are now mapped as follows:
        physical        virtual         size
ISRAM   0x4_0000_0000   0xE300_0000     256k
OCM     0x4_0004_0000   0xE304_0000     64k

A single TLB was used for this mapping.

Signed-off-by: Dave Mitchell <dmitch71@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>

diff --git a/board/amcc/canyonlands/init.S b/board/amcc/canyonlands/init.S
index 51b46d7..0b66796 100644 (file)
--- a/board/amcc/canyonlands/init.S
+++ b/board/amcc/canyonlands/init.S
@@ -89,7 +89,7 @@ tlbtab:
 #endif
 
        /* TLB-entry for OCM */
-       tlbentry(CONFIG_SYS_OCM_BASE, SZ_16K, 0x00040000, 4, AC_R|AC_W|AC_X|SA_I)
+       tlbentry(CONFIG_SYS_OCM_BASE, SZ_1M, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I)
 
        /* TLB-entry for Local Configuration registers => peripherals */
        tlbentry(CONFIG_SYS_LOCAL_CONF_REGS, SZ_16M, CONFIG_SYS_LOCAL_CONF_REGS, 4, AC_R|AC_W|AC_X|SA_G|SA_I)

diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S
index db34e84..e68cf9b 100644 (file)
--- a/cpu/ppc4xx/start.S
+++ b/cpu/ppc4xx/start.S
@@ -678,9 +678,12 @@ _start:
        /* not all PPC's have internal SRAM usable as L2-cache */
 #if defined(CONFIG_440GX) || \
     defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
-    defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
     defined(CONFIG_460SX)
        mtdcr   L2_CACHE_CFG,r0         /* Ensure L2 Cache is off */
+#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
+       lis     r1, 0x0000
+       ori     r1,r1,0x0008            /* Set L2_CACHE_CFG[RDBW]=1 */
+       mtdcr   L2_CACHE_CFG,r1
 #endif
 
        lis     r2,0x7fff
@@ -705,8 +708,8 @@ _start:
        lis     r1, 0x8003
        ori     r1,r1, 0x0980           /* fourth 64k */
        mtdcr   ISRAM0_SB3CR,r1
-#elif defined(CONFIG_440SPE)
-       lis     r1,0x0000               /* BAS = 0000_0000 */
+#elif defined(CONFIG_440SPE) || defined(CONFIG_460EX) || defined(CONFIG_460GT)
+       lis     r1,0x0000               /* BAS = X_0000_0000 */
        ori     r1,r1,0x0984            /* first 64k */
        mtdcr   ISRAM0_SB0CR,r1
        lis     r1,0x0001
@@ -718,10 +721,20 @@ _start:
        lis     r1, 0x0003
        ori     r1,r1, 0x0984           /* fourth 64k */
        mtdcr   ISRAM0_SB3CR,r1
-#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
-       lis     r1,0x4000               /* BAS = 8000_0000 */
-       ori     r1,r1,0x4580            /* 16k */
-       mtdcr   ISRAM0_SB0CR,r1
+#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
+       lis     r2,0x7fff
+       ori     r2,r2,0xffff
+       mfdcr   r1,ISRAM1_DPC
+       and     r1,r1,r2                /* Disable parity check */
+       mtdcr   ISRAM1_DPC,r1   
+       mfdcr   r1,ISRAM1_PMEG
+       and     r1,r1,r2                /* Disable pwr mgmt */
+       mtdcr   ISRAM1_PMEG,r1
+
+       lis     r1,0x0004               /* BAS = 4_0004_0000 */
+       ori     r1,r1,0x0984            /* 64k */
+       mtdcr   ISRAM1_SB0CR,r1
+#endif
 #elif defined(CONFIG_460SX)
        lis     r1,0x0000               /* BAS = 0000_0000 */
        ori     r1,r1,0x0B84            /* first 128k */

diff --git a/include/configs/canyonlands.h b/include/configs/canyonlands.h
index f8e8801..faf6304 100644 (file)
--- a/include/configs/canyonlands.h
+++ b/include/configs/canyonlands.h
@@ -102,7 +102,7 @@
 #define CONFIG_SYS_FLASH_BASE_PHYS     (((u64)CONFIG_SYS_FLASH_BASE_PHYS_H << 32) |    \
                                         (u64)CONFIG_SYS_FLASH_BASE_PHYS_L)
 
-#define CONFIG_SYS_OCM_BASE            0xE3000000      /* OCM: 16k             */
+#define CONFIG_SYS_OCM_BASE            0xE3000000      /* OCM: 64k             */
 #define CONFIG_SYS_SRAM_BASE           0xE8000000      /* SRAM: 256k           */
 #define CONFIG_SYS_LOCAL_CONF_REGS     0xEF000000