The SYSCLK source is automatically managed when configuring the PLL.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
u16 reg;
switch (div_id) {
- case WM8960_SYSCLKSEL:
- reg = snd_soc_read(codec, WM8960_CLOCK1) & 0x1fe;
- snd_soc_write(codec, WM8960_CLOCK1, reg | div);
- break;
case WM8960_SYSCLKDIV:
reg = snd_soc_read(codec, WM8960_CLOCK1) & 0x1f9;
snd_soc_write(codec, WM8960_CLOCK1, reg | div);
#define WM8960_OPCLKDIV 2
#define WM8960_DCLKDIV 3
#define WM8960_TOCLKSEL 4
-#define WM8960_SYSCLKSEL 5
#define WM8960_SYSCLK_DIV_1 (0 << 1)
#define WM8960_SYSCLK_DIV_2 (2 << 1)