[RISCV] Remove or simplify some StringSwitches in RISCVTargetParser.cpp. NFC

We can iterate over the RISCVCPUInfo table instead of using a
separate StringSwitch.

diff --git a/llvm/lib/TargetParser/RISCVTargetParser.cpp b/llvm/lib/TargetParser/RISCVTargetParser.cpp
index 9e1a805503ab6ef68179f28091ed61a3b219a994..6a357542ef08b3bece1dbb1a466bebd8b29832e5 100644 (file)
--- a/llvm/lib/TargetParser/RISCVTargetParser.cpp
+++ b/llvm/lib/TargetParser/RISCVTargetParser.cpp
@@ -39,40 +39,39 @@ constexpr CPUInfo RISCVCPUInfo[] = {
 #include "llvm/TargetParser/RISCVTargetParserDef.inc"
 };
 
-static CPUKind getCPUByName(StringRef CPU) {
-  return llvm::StringSwitch<CPUKind>(CPU)
-#define PROC(ENUM, NAME, DEFAULT_MARCH) .Case(NAME, CK_##ENUM)
-#include "llvm/TargetParser/RISCVTargetParserDef.inc"
-      .Default(CK_INVALID);
+static const CPUInfo *getCPUInfoByName(StringRef CPU) {
+  for (auto &C : RISCVCPUInfo)
+    if (C.Name == CPU)
+      return &C;
+  return nullptr;
 }
 
 bool parseCPU(StringRef CPU, bool IsRV64) {
-  CPUKind Kind = getCPUByName(CPU);
+  const CPUInfo *Info = getCPUInfoByName(CPU);
 
-  if (Kind == CK_INVALID)
+  if (!Info)
     return false;
-  return RISCVCPUInfo[static_cast<unsigned>(Kind)].is64Bit() == IsRV64;
+  return Info->is64Bit() == IsRV64;
 }
 
 bool parseTuneCPU(StringRef TuneCPU, bool IsRV64) {
   CPUKind Kind = llvm::StringSwitch<CPUKind>(TuneCPU)
-#define PROC(ENUM, NAME, DEFAULT_MARCH) .Case(NAME, CK_##ENUM)
-#define TUNE_PROC(ENUM, NAME) .Case(NAME, CK_##ENUM)
-#include "llvm/TargetParser/RISCVTargetParserDef.inc"
+  #define TUNE_PROC(ENUM, NAME) .Case(NAME, CK_##ENUM)
+  #include "llvm/TargetParser/RISCVTargetParserDef.inc"
       .Default(CK_INVALID);
 
-  if (Kind == CK_INVALID)
-    return false;
-#define TUNE_PROC(ENUM, NAME)                                                  \
-  if (Kind == CK_##ENUM)                                                       \
+  if (Kind != CK_INVALID)
     return true;
-#include "llvm/TargetParser/RISCVTargetParserDef.inc"
-  return RISCVCPUInfo[static_cast<unsigned>(Kind)].is64Bit() == IsRV64;
+
+  // Fallback to parsing as a CPU.
+  return parseCPU(TuneCPU, IsRV64);
 }
 
 StringRef getMArchFromMcpu(StringRef CPU) {
-  CPUKind Kind = getCPUByName(CPU);
-  return RISCVCPUInfo[static_cast<unsigned>(Kind)].DefaultMarch;
+  const CPUInfo *Info = getCPUInfoByName(CPU);
+  if (!Info)
+    return "";
+  return Info->DefaultMarch;
 }
 
 void fillValidCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64) {