radeonsi: Add option for SI scheduler
authorAxel Davy <axel.davy@ens.fr>
Fri, 15 Jan 2016 09:47:42 +0000 (10:47 +0100)
committerAxel Davy <axel.davy@ens.fr>
Thu, 28 Jan 2016 16:22:44 +0000 (17:22 +0100)
Add a debug option to select the LLVM SI Machine Scheduler.
R600_DEBUG=sisched

Signed-off-by: Axel Davy <axel.davy@ens.fr>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
src/gallium/drivers/radeon/r600_pipe_common.c
src/gallium/drivers/radeon/r600_pipe_common.h
src/gallium/drivers/radeonsi/si_pipe.c

index 34fe57b..c827dbd 100644 (file)
@@ -409,6 +409,7 @@ static const struct debug_named_value common_debug_options[] = {
        { "nodcc", DBG_NO_DCC, "Disable DCC." },
        { "nodccclear", DBG_NO_DCC_CLEAR, "Disable DCC fast clear." },
        { "norbplus", DBG_NO_RB_PLUS, "Disable RB+ on Stoney." },
+       { "sisched", DBG_SI_SCHED, "Enable LLVM SI Machine Instruction Scheduler." },
 
        DEBUG_NAMED_VALUE_END /* must be last */
 };
index a8928f2..88e9cbc 100644 (file)
@@ -87,6 +87,7 @@
 #define DBG_NO_DCC             (1llu << 43)
 #define DBG_NO_DCC_CLEAR       (1llu << 44)
 #define DBG_NO_RB_PLUS         (1llu << 45)
+#define DBG_SI_SCHED           (1llu << 46)
 
 #define R600_MAP_BUFFER_ALIGNMENT 64
 
index 0c1ae90..f483f92 100644 (file)
@@ -215,7 +215,11 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen,
        r600_target = radeon_llvm_get_r600_target(triple);
        sctx->tm = LLVMCreateTargetMachine(r600_target, triple,
                                           r600_get_llvm_processor_name(sscreen->b.family),
-                                          "+DumpCode,+vgpr-spilling",
+#if HAVE_LLVM >= 0x0308
+                                          sscreen->b.debug_flags & DBG_SI_SCHED ?
+                                               "+DumpCode,+vgpr-spilling,+si-scheduler" :
+#endif
+                                               "+DumpCode,+vgpr-spilling",
                                           LLVMCodeGenLevelDefault,
                                           LLVMRelocDefault,
                                           LLVMCodeModelDefault);