spi: spi-zynqmp-gqspi: Add two chip select support

ZynqMP GQSPI controller can support up to two chip selects but the current
GQSPI driver only support CS0. With this update and num-cs DT property set
to 2 GQSPI driver can now support two slave devices each connected to one
chip select.

GQSPI driver configures the Lower CS and Upper CS based on the reg DT
property.

Changes tested on ZynqMP board with two SPI-NOR flashes each connected
to a different CS.

Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com>
Link: https://lore.kernel.org/r/20220512145820.20425-1-amit.kumar-mahapatra@xilinx.com
Signed-off-by: Mark Brown <broonie@kernel.org>

diff --git a/drivers/spi/spi-zynqmp-gqspi.c b/drivers/spi/spi-zynqmp-gqspi.c
index 2b5afae..c760aac 100644 (file)
--- a/drivers/spi/spi-zynqmp-gqspi.c
+++ b/drivers/spi/spi-zynqmp-gqspi.c
@@ -134,6 +134,8 @@
 #define GQSPI_DMA_UNALIGN              0x3
 #define GQSPI_DEFAULT_NUM_CS   1       /* Default number of chip selects */
 
+#define GQSPI_MAX_NUM_CS       2       /* Maximum number of chip selects */
+
 #define SPI_AUTOSUSPEND_TIMEOUT                3000
 enum mode_type {GQSPI_MODE_IO, GQSPI_MODE_DMA};
 
@@ -363,8 +365,13 @@ static void zynqmp_qspi_chipselect(struct spi_device *qspi, bool is_high)
        genfifoentry |= GQSPI_GENFIFO_MODE_SPI;
 
        if (!is_high) {
-               xqspi->genfifobus = GQSPI_GENFIFO_BUS_LOWER;
-               xqspi->genfifocs = GQSPI_GENFIFO_CS_LOWER;
+               if (!qspi->chip_select) {
+                       xqspi->genfifobus = GQSPI_GENFIFO_BUS_LOWER;
+                       xqspi->genfifocs = GQSPI_GENFIFO_CS_LOWER;
+               } else {
+                       xqspi->genfifobus = GQSPI_GENFIFO_BUS_UPPER;
+                       xqspi->genfifocs = GQSPI_GENFIFO_CS_UPPER;
+               }
                genfifoentry |= xqspi->genfifobus;
                genfifoentry |= xqspi->genfifocs;
                genfifoentry |= GQSPI_GENFIFO_CS_SETUP;
@@ -1099,6 +1106,7 @@ static int zynqmp_qspi_probe(struct platform_device *pdev)
        struct zynqmp_qspi *xqspi;
        struct device *dev = &pdev->dev;
        struct device_node *np = dev->of_node;
+       u32 num_cs;
 
        ctlr = spi_alloc_master(&pdev->dev, sizeof(*xqspi));
        if (!ctlr)
@@ -1176,8 +1184,19 @@ static int zynqmp_qspi_probe(struct platform_device *pdev)
        if (ret)
                goto clk_dis_all;
 
+       ret = of_property_read_u32(np, "num-cs", &num_cs);
+       if (ret < 0) {
+               ctlr->num_chipselect = GQSPI_DEFAULT_NUM_CS;
+       } else if (num_cs > GQSPI_MAX_NUM_CS) {
+               ret = -EINVAL;
+               dev_err(&pdev->dev, "only %d chip selects are available\n",
+                       GQSPI_MAX_NUM_CS);
+               goto clk_dis_all;
+       } else {
+               ctlr->num_chipselect = num_cs;
+       }
+
        ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
-       ctlr->num_chipselect = GQSPI_DEFAULT_NUM_CS;
        ctlr->mem_ops = &zynqmp_qspi_mem_ops;
        ctlr->setup = zynqmp_qspi_setup_op;
        ctlr->max_speed_hz = clk_get_rate(xqspi->refclk) / 2;