firmware: Fix compile error for FW_PAYLOAD with latest GCC binutils

We get following compile error for FW_PAYLOAD with latest GCC
binutils:
fw_payload.o(.text+0x1961): 15 bytes required for alignment to 16-byte
boundary, but only 14 present

Further investigating, it turn-out to be a known issue with RISC-V
GCC binutils.
(Refer, https://github.com/riscv/riscv-gnu-toolchain/issues/298)

As a work-around, we disable relaxation when including DTB and
PAYLOAD binary in fw_payload.S.

Reported-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Tested-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>

diff --git a/firmware/fw_payload.S b/firmware/fw_payload.S
index 4b4527a..01dce20 100644 (file)
--- a/firmware/fw_payload.S
+++ b/firmware/fw_payload.S
@@ -85,6 +85,14 @@ fw_options:
        add     a0, zero, zero
        ret
 
+       /*
+        * We disable relaxation because use of ".align"
+        * and ".balign" can potentially generate compile
+        * errors with latest RISC-V GCC Binutils.
+        */
+       .option push
+       .option norelax
+
 #ifdef FW_PAYLOAD_FDT_PATH
        .align 4
        .section .text, "ax", %progbits
@@ -103,3 +111,5 @@ payload_bin:
 #else
        .incbin FW_PAYLOAD_PATH
 #endif
+
+       .option pop