drm/amd/pp: Store stable Pstate clocks

User can use to calculate profiling ratios when
set UMD Pstate.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
index e574af1..f68dd08 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
@@ -1189,6 +1189,8 @@ static int cz_phm_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
 
        cz_hwmgr->sclk_dpm.soft_min_clk = table->entries[0].clk;
        cz_hwmgr->sclk_dpm.hard_min_clk = table->entries[0].clk;
+       hwmgr->pstate_sclk = table->entries[0].clk;
+       hwmgr->pstate_mclk = 0;
 
        level = cz_get_max_sclk_level(hwmgr) - 1;
 

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
index 569073e..409a56b 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
@@ -451,6 +451,9 @@ static int rv_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
 
        hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
 
+       hwmgr->pstate_sclk = RAVEN_UMD_PSTATE_GFXCLK;
+       hwmgr->pstate_mclk = RAVEN_UMD_PSTATE_FCLK;
+
        return result;
 }
 

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index b60e50e..11a900b 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -2579,8 +2579,10 @@ static int smu7_get_profiling_clk(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_le
                                break;
                        }
                }
-               if (count < 0 || level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK)
+               if (count < 0 || level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
                        *sclk_mask = 0;
+                       tmp_sclk = hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].clk;
+               }
 
                if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
                        *sclk_mask = hwmgr->dyn_state.vddc_dependency_on_sclk->count-1;
@@ -2595,8 +2597,10 @@ static int smu7_get_profiling_clk(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_le
                                break;
                        }
                }
-               if (count < 0 || level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK)
+               if (count < 0 || level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
                        *sclk_mask = 0;
+                       tmp_sclk =  table_info->vdd_dep_on_sclk->entries[0].clk;
+               }
 
                if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
                        *sclk_mask = table_info->vdd_dep_on_sclk->count - 1;
@@ -2608,6 +2612,9 @@ static int smu7_get_profiling_clk(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_le
                *mclk_mask = golden_dpm_table->mclk_table.count - 1;
 
        *pcie_mask = data->dpm_table.pcie_speed_table.count - 1;
+       hwmgr->pstate_sclk = tmp_sclk;
+       hwmgr->pstate_mclk = tmp_mclk;
+
        return 0;
 }
 
@@ -2619,6 +2626,9 @@ static int smu7_force_dpm_level(struct pp_hwmgr *hwmgr,
        uint32_t mclk_mask = 0;
        uint32_t pcie_mask = 0;
 
+       if (hwmgr->pstate_sclk == 0)
+               smu7_get_profiling_clk(hwmgr, level, &sclk_mask, &mclk_mask, &pcie_mask);
+
        switch (level) {
        case AMD_DPM_FORCED_LEVEL_HIGH:
                ret = smu7_force_dpm_highest(hwmgr);

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index 65b7714..8af7284 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -4178,6 +4178,8 @@ static int vega10_get_profiling_clk_mask(struct pp_hwmgr *hwmgr, enum amd_dpm_fo
                *sclk_mask = VEGA10_UMD_PSTATE_GFXCLK_LEVEL;
                *soc_mask = VEGA10_UMD_PSTATE_SOCCLK_LEVEL;
                *mclk_mask = VEGA10_UMD_PSTATE_MCLK_LEVEL;
+               hwmgr->pstate_sclk = table_info->vdd_dep_on_sclk->entries[VEGA10_UMD_PSTATE_GFXCLK_LEVEL].clk;
+               hwmgr->pstate_mclk = table_info->vdd_dep_on_mclk->entries[VEGA10_UMD_PSTATE_MCLK_LEVEL].clk;
        }
 
        if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
@@ -4219,6 +4221,9 @@ static int vega10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
        uint32_t mclk_mask = 0;
        uint32_t soc_mask = 0;
 
+       if (hwmgr->pstate_sclk == 0)
+               vega10_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask);
+
        switch (level) {
        case AMD_DPM_FORCED_LEVEL_HIGH:
                ret = vega10_force_dpm_highest(hwmgr);

diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index 800d773..6d8183d 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -753,6 +753,8 @@ struct pp_hwmgr {
        enum amd_pp_profile_type current_power_profile;
        bool en_umd_pstate;
        uint32_t power_profile_mode;
+       uint32_t pstate_sclk;
+       uint32_t pstate_mclk;
 };
 
 struct cgs_irq_src_funcs {