iio: adc: ti-ads7950: Fix alignment for DMA safety

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_DMA_MINALIGN definition.

Update the comment to include 'may'.

Fixes: 902c4b2446d4 ("iio: adc: New driver for TI ADS7950 chips")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Acked-by: David Lechner <david@lechnology.com>
Acked-by: Nuno Sá <nuno.sa@analog.com>
Link: https://lore.kernel.org/r/20220508175712.647246-37-jic23@kernel.org

diff --git a/drivers/iio/adc/ti-ads7950.c b/drivers/iio/adc/ti-ads7950.c
index e3658b9..2cc9a9b 100644 (file)
--- a/drivers/iio/adc/ti-ads7950.c
+++ b/drivers/iio/adc/ti-ads7950.c
@@ -102,11 +102,11 @@ struct ti_ads7950_state {
        unsigned int            gpio_cmd_settings_bitmask;
 
        /*
-        * DMA (thus cache coherency maintenance) requires the
+        * DMA (thus cache coherency maintenance) may require the
         * transfer buffers to live in their own cache lines.
         */
        u16 rx_buf[TI_ADS7950_MAX_CHAN + 2 + TI_ADS7950_TIMESTAMP_SIZE]
-                                                       ____cacheline_aligned;
+               __aligned(IIO_DMA_MINALIGN);
        u16 tx_buf[TI_ADS7950_MAX_CHAN + 2];
        u16 single_tx;
        u16 single_rx;