Reorder some power9 insns

The idea being to put instructions that have the same encoding adjacent
to each other.

	* opcodes/ppc-opc.c (powerpc_opcodes): Sort power9 insns by
	major opcode/xop.

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 7c99b06..223fb60 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2015-12-07  Alan Modra  <amodra@gmail.com>
+
+       * opcodes/ppc-opc.c (powerpc_opcodes): Sort power9 insns by
+       major opcode/xop.
+
 2015-12-04  Claudiu Zissulescu  <claziss@synopsys.com>
 
        * arc-dis.c (special_flag_p): Match full mnemonic.

diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index 0ea8d95..5c61c87 100644 (file)
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -3152,34 +3152,34 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"ps_add.",    A  (4,  21,1),  AFRC_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
 {"vperm",      VXA(4,  43),    VXA_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB, VC}},
 {"vsldoi",     VXA(4,  44),    VXASHB_MASK, PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB, SHB}},
-{"ps_sel",     A  (4,  23,0),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
 {"vpermxor",   VXA(4,  45),    VXA_MASK,    PPCVEC2,   PPCNONE,        {VD, VA, VB, VC}},
+{"ps_sel",     A  (4,  23,0),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
 {"vmaddfp",    VXA(4,  46),    VXA_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VC, VB}},
 {"ps_sel.",    A  (4,  23,1),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
 {"vnmsubfp",   VXA(4,  47),    VXA_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VC, VB}},
-{"maddhd",     VXA(4,  48),    VXA_MASK,    POWER9,    PPCNONE,        {RT, RA, RB, RC}},
-{"maddhdu",    VXA(4,  49),    VXA_MASK,    POWER9,    PPCNONE,        {RT, RA, RB, RC}},
-{"maddld",     VXA(4,  51),    VXA_MASK,    POWER9,    PPCNONE,        {RT, RA, RB, RC}},
 {"ps_res",     A  (4,  24,0), AFRAFRC_MASK, PPCPS,     PPCNONE,        {FRT, FRB}},
+{"maddhd",     VXA(4,  48),    VXA_MASK,    POWER9,    PPCNONE,        {RT, RA, RB, RC}},
 {"ps_res.",    A  (4,  24,1), AFRAFRC_MASK, PPCPS,     PPCNONE,        {FRT, FRB}},
-{"ps_mul",     A  (4,  25,0), AFRB_MASK,    PPCPS,     PPCNONE,        {FRT, FRA, FRC}},
+{"maddhdu",    VXA(4,  49),    VXA_MASK,    POWER9,    PPCNONE,        {RT, RA, RB, RC}},
+{"ps_mul",     A  (4,  25,0),  AFRB_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRC}},
 {"ps_mul.",    A  (4,  25,1),  AFRB_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRC}},
+{"maddld",     VXA(4,  51),    VXA_MASK,    POWER9,    PPCNONE,        {RT, RA, RB, RC}},
 {"ps_rsqrte",  A  (4,  26,0), AFRAFRC_MASK, PPCPS,     PPCNONE,        {FRT, FRB}},
 {"ps_rsqrte.", A  (4,  26,1), AFRAFRC_MASK, PPCPS,     PPCNONE,        {FRT, FRB}},
 {"ps_msub",    A  (4,  28,0),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
 {"ps_msub.",   A  (4,  28,1),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
 {"ps_madd",    A  (4,  29,0),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
 {"ps_madd.",   A  (4,  29,1),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
-{"ps_nmsub",   A  (4,  30,0),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
-{"ps_nmsub.",  A  (4,  30,1),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
-{"ps_nmadd",   A  (4,  31,0),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
-{"ps_nmadd.",  A  (4,  31,1),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
-{"ps_cmpo0",   X  (4,  32),    XBF_MASK,    PPCPS,     PPCNONE,        {BF, FRA, FRB}},
 {"vpermr",     VXA(4,  59),    VXA_MASK,    PPCVEC3,   PPCNONE,        {VD, VA, VB, VC}},
+{"ps_nmsub",   A  (4,  30,0),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
 {"vaddeuqm",   VXA(4,  60),    VXA_MASK,    PPCVEC2,   PPCNONE,        {VD, VA, VB, VC}},
+{"ps_nmsub.",  A  (4,  30,1),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
 {"vaddecuq",   VXA(4,  61),    VXA_MASK,    PPCVEC2,   PPCNONE,        {VD, VA, VB, VC}},
+{"ps_nmadd",   A  (4,  31,0),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
 {"vsubeuqm",   VXA(4,  62),    VXA_MASK,    PPCVEC2,   PPCNONE,        {VD, VA, VB, VC}},
+{"ps_nmadd.",  A  (4,  31,1),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
 {"vsubecuq",   VXA(4,  63),    VXA_MASK,    PPCVEC2,   PPCNONE,        {VD, VA, VB, VC}},
+{"ps_cmpo0",   X  (4,  32),    XBF_MASK,    PPCPS,     PPCNONE,        {BF, FRA, FRB}},
 {"vadduhm",    VX (4,  64),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
 {"vmul10ecuq", VX (4,  65),    VX_MASK,     PPCVEC3,       PPCNONE,    {VD, VA, VB}},
 {"vmaxuh",     VX (4,  66),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
@@ -3229,8 +3229,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"nmachhws.",  XO (4, 110,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
 {"vadduqm",    VX (4, 256),    VX_MASK,     PPCVEC2,   PPCNONE,        {VD, VA, VB}},
 {"vmaxsb",     VX (4, 258),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"vcmpnezb",   VXR(4, 263,0),  VXR_MASK,    PPCVEC3,   PPCNONE,        {VD, VA, VB}},
 {"vslb",       VX (4, 260),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
+{"vcmpnezb",   VXR(4, 263,0),  VXR_MASK,    PPCVEC3,   PPCNONE,        {VD, VA, VB}},
 {"vmulosb",    VX (4, 264),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
 {"vrefp",      VX (4, 266),    VXVA_MASK,   PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
 {"vmrglb",     VX (4, 268),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},