* vr4320.igen: New file.

	* Makefile.in (vr4320.igen) : Added.
	* configure.in (mips64vr4320-*-*): Added.
	* configure : Rebuilt.
	* mips.igen : Correct the bfd-names in the mips-ISA model entries.
	Add the vr4320 model entry and mark the vr4320 insn as necessary.

diff --git a/sim/mips/ChangeLog b/sim/mips/ChangeLog
index 2044b41..d6e015e 100644 (file)
--- a/sim/mips/ChangeLog
+++ b/sim/mips/ChangeLog
@@ -1,3 +1,14 @@
+start-sanitize-vr4320
+Tue Mar  3 11:56:29 1998  Gavin Koch  <gavin@cygnus.com>
+
+       * vr4320.igen: New file.
+       * Makefile.in (vr4320.igen) : Added.
+       * configure.in (mips64vr4320-*-*): Added.
+       * configure : Rebuilt.
+       * mips.igen : Correct the bfd-names in the mips-ISA model entries.
+       Add the vr4320 model entry and mark the vr4320 insn as necessary.
+
+end-sanitize-vr4320
 Tue Mar  3 13:58:43 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 
        * sim-main.h (GETFCC): Return an unsigned value.

diff --git a/sim/mips/configure.in b/sim/mips/configure.in
index 817ae0b..e498bd2 100644 (file)
--- a/sim/mips/configure.in
+++ b/sim/mips/configure.in
@@ -150,6 +150,19 @@ case "${target}" in
                        sim_igen_machine="-M r5900"
                        ;;
 # end-sanitize-r5900
+# start-sanitize-vr4320
+  mips64vr4320-*-*)    sim_default_gen=IGEN
+                       sim_use_gen=IGEN
+                       sim_igen_machine="-M mipsIV,vr4320 -G gen-multi-sim=vr4320"
+                       ;;
+# end-sanitize-vr4320
+  mips64vr43*-*-*)     sim_default_gen=IGEN
+                       sim_use_gen=IGEN
+                       sim_igen_machine="-M mipsIV"
+# start-sanitize-vr4320
+                       sim_igen_machine="-M mipsIV,vr4320 -G gen-multi-sim=mipsIV"
+# end-sanitize-vr4320
+                       ;;
 # start-sanitize-vr5400
   mips64vr54*-*-*)     sim_default_gen=IGEN
                        sim_use_gen=IGEN

diff --git a/sim/mips/vr4320.igen b/sim/mips/vr4320.igen
new file mode 100644 (file)
index 0000000..d040363
--- /dev/null
+++ b/sim/mips/vr4320.igen
@@ -0,0 +1,139 @@
+
+
+// Integer Instructions
+// --------------------
+//
+// MulAcc is the Multiply Accumulator.
+//     This register is mapped on the the HI and LO registers.
+//     Upper 32 bits of MulAcc is mapped on to lower 32 bits of HI register.
+//     Lower 32 bits of MulAcc is mapped on to lower 32 bits of LO register.
+
+
+:function:::unsigned64:MulAcc:
+{
+  unsigned64 result = U8_4 (HI, LO);
+  return result;
+}
+
+:function:::void:SET_MulAcc:unsigned64 value
+{
+  *AL4_8 (&HI) = VH4_8 (value);
+  *AL4_8 (&LO) = VL4_8 (value);
+}
+
+:function:::signed64:SignedMultiply:signed32 l, signed32 r
+{
+  signed64 result = (signed64) l * (signed64) r;
+  return result;
+}
+
+:function:::unsigned64:UnsignedMultiply:unsigned32 l, unsigned32 r
+{
+  unsigned64 result = (unsigned64) l * (unsigned64) r;
+  return result;
+}
+
+:function:::unsigned64:Low32Bits:unsigned64 value
+{
+  unsigned64 result = (signed64) (signed32) VL4_8 (value);
+  return result;
+}
+
+:function:::unsigned64:High32Bits:unsigned64 value
+{
+  unsigned64 result = (signed64) (signed32) VH4_8 (value);
+  return result;
+}
+
+
+
+// Multiply and Move LO.
+000000,5.RS,5.RT,5.RD,00100,101000::::MUL
+"mul r<RD>, r<RS>, r<RT>"
+*mipsI,mipsII,mipsIII,mipsIV:
+{
+  SET_MulAcc (SD_, 0 + SignedMultiply (SD_, GPR[RS], GPR[RT]));
+  GPR[RD] = Low32Bits (SD_, MulAcc (SD_));
+}
+
+// Unsigned Multiply and Move LO.
+000000,5.RS,5.RT,5.RD,00101,101000::::MULU
+"mulu r<RD>, r<RS>, r<RT>"
+*mipsI,mipsII,mipsIII,mipsIV:
+{
+  SET_MulAcc (SD_, 0 + UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
+  GPR[RD] = Low32Bits  (SD_, MulAcc (SD_));
+}
+
+// Multiply and Move HI.
+000000,5.RS,5.RT,5.RD,01100,101000::::MULHI
+"mulhi r<RD>, r<RS>, r<RT>"
+*mipsI,mipsII,mipsIII,mipsIV:
+{
+  SET_MulAcc (SD_, 0 + SignedMultiply   (SD_, GPR[RS], GPR[RT]));
+  GPR[RD] = High32Bits (SD_, MulAcc (SD_));
+}
+
+// Unsigned Multiply and Move HI.
+000000,5.RS,5.RT,5.RD,01101,101000::::MULHIU
+"mulhiu r<RD>, r<RS>, r<RT>"
+*mipsI,mipsII,mipsIII,mipsIV:
+{
+  SET_MulAcc (SD_, 0 + UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
+  GPR[RD] = High32Bits (SD_, MulAcc (SD_));
+}
+
+
+// Multiply, Accumulate
+000000,5.RS,5.RT,00000,00000,101000::::MAC
+"mac r<RS>, r<RT>"
+*vr4320:
+{
+  SET_MulAcc (SD_, MulAcc (SD_) + SignedMultiply (SD_, GPR[RS], GPR[RT]));
+}
+
+// D-Multiply, Accumulate
+000000,5.RS,5.RT,00000,00000,101001::::DMAC
+"dmac r<RS>, r<RT>"
+*mipsI,mipsII,mipsIII,mipsIV:
+{
+  LO = MulAcc (SD_) + SignedMultiply (SD_, GPR[RS], GPR[RT]);
+}
+
+// Multiply, Accumulate and Move LO.
+000000,5.RS,5.RT,5.RD,00010,101000::::MACC
+"macc r<RD>, r<RS>, r<RT>"
+*mipsI,mipsII,mipsIII,mipsIV:
+{
+  SET_MulAcc (SD_, MulAcc (SD_) + SignedMultiply (SD_, GPR[RS], GPR[RT]));
+  GPR[RD] = Low32Bits  (SD_, MulAcc (SD_));
+}
+
+// Unsigned Multiply, Accumulate and Move LO.
+000000,5.RS,5.RT,5.RD,00011,101000::::MACCU
+"maccu r<RD>, r<RS>, r<RT>"
+*mipsI,mipsII,mipsIII,mipsIV:
+{
+  SET_MulAcc (SD_, MulAcc (SD_) + UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
+  GPR[RD] = Low32Bits  (SD_, MulAcc (SD_));
+}
+
+// Multiply, Accumulate and Move HI.
+000000,5.RS,5.RT,5.RD,01010,101000::::MACCHI
+"macchi r<RD>, r<RS>, r<RT>"
+*mipsI,mipsII,mipsIII,mipsIV:
+{
+  SET_MulAcc (SD_, MulAcc (SD_) + SignedMultiply (SD_, GPR[RS], GPR[RT]));
+  GPR[RD] = High32Bits (SD_, MulAcc (SD_));
+}
+
+// Unsigned Multiply, Accumulate and Move HI.
+000000,5.RS,5.RT,5.RD,01011,101000::::MACCHIU
+"macchiu r<RD>, r<RS>, r<RT>"
+*mipsI,mipsII,mipsIII,mipsIV:
+{
+  SET_MulAcc (SD_, MulAcc (SD_) + UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
+  GPR[RD] = High32Bits (SD_, MulAcc (SD_));
+
+}
+