nir_lower_io_to_temporaries() does not support tcs so we cannot
assume there are no indirects here. Also the radeonsi backend
(the only backend to support tess) has support for tcs indirects
so there is no need to lower them anyway.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
NIR_PASS_V(nir, nir_split_var_copies);
NIR_PASS_V(nir, nir_lower_var_copies);
- NIR_PASS_V(nir, nir_lower_io_arrays_to_elements_no_indirects);
+ if (nir->info.stage != MESA_SHADER_TESS_CTRL)
+ NIR_PASS_V(nir, nir_lower_io_arrays_to_elements_no_indirects);
if (nir->info.stage == MESA_SHADER_VERTEX) {
/* Needs special handling so drvloc matches the vbo state: */