static int p2sb_child_post_bind(struct udevice *dev)
{
-#if CONFIG_IS_ENABLED(OF_REAL)
- struct p2sb_child_plat *pplat = dev_get_parent_plat(dev);
- int ret;
- u32 pid;
-
- ret = dev_read_u32(dev, "intel,p2sb-port-id", &pid);
- if (ret)
- return ret;
- pplat->pid = pid;
-#endif
+ if (CONFIG_IS_ENABLED(OF_REAL)) {
+ struct p2sb_child_plat *pplat = dev_get_parent_plat(dev);
+ int ret;
+ u32 pid;
+
+ ret = dev_read_u32(dev, "intel,p2sb-port-id", &pid);
+ if (ret)
+ return ret;
+ pplat->pid = pid;
+ }
return 0;
}
static int mmc_of_to_plat(struct udevice *dev)
{
- #if CONFIG_IS_ENABLED(OF_REAL)
+ if (CONFIG_IS_ENABLED(OF_REAL)) {
/* Decode the devicetree data */
struct mmc_plat *plat = dev_get_plat(dev);
const void *blob = gd->fdt_blob;
int node = dev_of_offset(dev);
plat->fifo_depth = fdtdec_get_int(blob, node, "fifo-depth", 0);
- #endif
+ }
- return 0;
+ return 0;
}
static int mmc_probe(struct udevice *dev)
static int clk_fixed_factor_of_to_plat(struct udevice *dev)
{
-#if CONFIG_IS_ENABLED(OF_REAL)
- int err;
- struct clk_fixed_factor *ff = to_clk_fixed_factor(dev);
+ if (CONFIG_IS_ENABLED(OF_REAL)) {
+ int err;
+ struct clk_fixed_factor *ff = to_clk_fixed_factor(dev);
- err = clk_get_by_index(dev, 0, &ff->parent);
- if (err)
- return err;
+ err = clk_get_by_index(dev, 0, &ff->parent);
+ if (err)
+ return err;
- ff->div = dev_read_u32_default(dev, "clock-div", 1);
- ff->mult = dev_read_u32_default(dev, "clock-mult", 1);
-#endif
+ ff->div = dev_read_u32_default(dev, "clock-div", 1);
+ ff->mult = dev_read_u32_default(dev, "clock-mult", 1);
+ }
return 0;
}
struct clk_fixed_rate *plat)
{
struct clk *clk = &plat->clk;
-#if CONFIG_IS_ENABLED(OF_REAL)
- plat->fixed_rate = dev_read_u32_default(dev, "clock-frequency", 0);
-#endif
+ if (CONFIG_IS_ENABLED(OF_REAL))
+ plat->fixed_rate = dev_read_u32_default(dev, "clock-frequency",
+ 0);
+
/* Make fixed rate clock accessible from higher level struct clk */
/* FIXME: This is not allowed */
dev_set_uclass_priv(dev, clk);
static int rk3188_clk_of_to_plat(struct udevice *dev)
{
-#if CONFIG_IS_ENABLED(OF_REAL)
- struct rk3188_clk_priv *priv = dev_get_priv(dev);
+ if (CONFIG_IS_ENABLED(OF_REAL)) {
+ struct rk3188_clk_priv *priv = dev_get_priv(dev);
- priv->cru = dev_read_addr_ptr(dev);
-#endif
+ priv->cru = dev_read_addr_ptr(dev);
+ }
return 0;
}
static int rk3288_clk_of_to_plat(struct udevice *dev)
{
-#if CONFIG_IS_ENABLED(OF_REAL)
- struct rk3288_clk_priv *priv = dev_get_priv(dev);
+ if (CONFIG_IS_ENABLED(OF_REAL)) {
+ struct rk3288_clk_priv *priv = dev_get_priv(dev);
- priv->cru = dev_read_addr_ptr(dev);
-#endif
+ priv->cru = dev_read_addr_ptr(dev);
+ }
return 0;
}
static int rk3368_clk_of_to_plat(struct udevice *dev)
{
-#if CONFIG_IS_ENABLED(OF_REAL)
- struct rk3368_clk_priv *priv = dev_get_priv(dev);
+ if (CONFIG_IS_ENABLED(OF_REAL)) {
+ struct rk3368_clk_priv *priv = dev_get_priv(dev);
- priv->cru = dev_read_addr_ptr(dev);
-#endif
+ priv->cru = dev_read_addr_ptr(dev);
+ }
return 0;
}
static int rk3399_clk_of_to_plat(struct udevice *dev)
{
-#if CONFIG_IS_ENABLED(OF_REAL)
- struct rk3399_clk_priv *priv = dev_get_priv(dev);
+ if (CONFIG_IS_ENABLED(OF_REAL)) {
+ struct rk3399_clk_priv *priv = dev_get_priv(dev);
+
+ priv->cru = dev_read_addr_ptr(dev);
+ }
- priv->cru = dev_read_addr_ptr(dev);
-#endif
return 0;
}
static int rk3399_pmuclk_of_to_plat(struct udevice *dev)
{
-#if CONFIG_IS_ENABLED(OF_REAL)
- struct rk3399_pmuclk_priv *priv = dev_get_priv(dev);
+ if (CONFIG_IS_ENABLED(OF_REAL)) {
+ struct rk3399_pmuclk_priv *priv = dev_get_priv(dev);
+
+ priv->pmucru = dev_read_addr_ptr(dev);
+ }
- priv->pmucru = dev_read_addr_ptr(dev);
-#endif
return 0;
}
static int p2sb_child_post_bind(struct udevice *dev)
{
-#if CONFIG_IS_ENABLED(OF_REAL)
- struct p2sb_child_plat *pplat = dev_get_parent_plat(dev);
- int ret;
- u32 pid;
-
- ret = dev_read_u32(dev, "intel,p2sb-port-id", &pid);
- if (ret)
- return ret;
- pplat->pid = pid;
-#endif
+ if (CONFIG_IS_ENABLED(OF_REAL)) {
+ struct p2sb_child_plat *pplat = dev_get_parent_plat(dev);
+ int ret;
+ u32 pid;
+
+ ret = dev_read_u32(dev, "intel,p2sb-port-id", &pid);
+ if (ret)
+ return ret;
+ pplat->pid = pid;
+ }
return 0;
}
static int fsl_esdhc_of_to_plat(struct udevice *dev)
{
-#if CONFIG_IS_ENABLED(OF_REAL)
struct fsl_esdhc_priv *priv = dev_get_priv(dev);
#if CONFIG_IS_ENABLED(DM_REGULATOR)
struct udevice *vqmmc_dev;
#endif
const void *fdt = gd->fdt_blob;
int node = dev_of_offset(dev);
-
fdt_addr_t addr;
unsigned int val;
+ if (!CONFIG_IS_ENABLED(OF_REAL))
+ return 0;
+
addr = dev_read_addr(dev);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
priv->vs18_enable = 1;
}
#endif
-#endif
+
return 0;
}
return ret;
}
-#if CONFIG_IS_ENABLED(OF_REAL)
- ret = mmc_of_parse(dev, &plat->cfg);
- if (ret)
- return ret;
-#endif
+ if (CONFIG_IS_ENABLED(OF_REAL)) {
+ ret = mmc_of_parse(dev, &plat->cfg);
+ if (ret)
+ return ret;
+ }
mmc = &plat->mmc;
mmc->cfg = &plat->cfg;
static int ftsdc010_mmc_of_to_plat(struct udevice *dev)
{
-#if CONFIG_IS_ENABLED(OF_REAL)
struct ftsdc_priv *priv = dev_get_priv(dev);
struct ftsdc010_chip *chip = &priv->chip;
- chip->name = dev->name;
- chip->ioaddr = dev_read_addr_ptr(dev);
- chip->buswidth = dev_read_u32_default(dev, "bus-width", 4);
- chip->priv = dev;
- priv->fifo_depth = dev_read_u32_default(dev, "fifo-depth", 0);
- priv->fifo_mode = dev_read_bool(dev, "fifo-mode");
- if (dev_read_u32_array(dev, "clock-freq-min-max", priv->minmax, 2)) {
- if (dev_read_u32(dev, "max-frequency", &priv->minmax[1]))
- return -EINVAL;
-
- priv->minmax[0] = 400000; /* 400 kHz */
- } else {
- debug("%s: 'clock-freq-min-max' property was deprecated.\n",
- __func__);
+ if (CONFIG_IS_ENABLED(OF_REAL)) {
+ chip->name = dev->name;
+ chip->ioaddr = dev_read_addr_ptr(dev);
+ chip->buswidth = dev_read_u32_default(dev, "bus-width", 4);
+ chip->priv = dev;
+ priv->fifo_depth = dev_read_u32_default(dev, "fifo-depth", 0);
+ priv->fifo_mode = dev_read_bool(dev, "fifo-mode");
+ if (dev_read_u32_array(dev, "clock-freq-min-max", priv->minmax, 2)) {
+ if (dev_read_u32(dev, "max-frequency", &priv->minmax[1]))
+ return -EINVAL;
+
+ priv->minmax[0] = 400000; /* 400 kHz */
+ } else {
+ debug("%s: 'clock-freq-min-max' property was deprecated.\n",
+ __func__);
+ }
}
-#endif
chip->sclk = priv->minmax[1];
chip->regs = chip->ioaddr;
+
return 0;
}
static int rockchip_dwmmc_of_to_plat(struct udevice *dev)
{
-#if CONFIG_IS_ENABLED(OF_REAL)
struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
struct dwmci_host *host = &priv->host;
+ if (!CONFIG_IS_ENABLED(OF_REAL))
+ return 0;
+
host->name = dev->name;
host->ioaddr = dev_read_addr_ptr(dev);
host->buswidth = dev_read_u32_default(dev, "bus-width", 4);
debug("%s: 'clock-freq-min-max' property was deprecated.\n",
__func__);
}
-#endif
+
return 0;
}
{
int ret = 0;
-#if CONFIG_IS_ENABLED(OF_REAL)
- struct rk3368_sdram_params *plat = dev_get_plat(dev);
+ if (CONFIG_IS_ENABLED(OF_REAL)) {
+ struct rk3368_sdram_params *plat = dev_get_plat(dev);
- ret = regmap_init_mem(dev_ofnode(dev), &plat->map);
- if (ret)
- return ret;
-#endif
+ ret = regmap_init_mem(dev_ofnode(dev), &plat->map);
+ if (ret)
+ return ret;
+ }
return ret;
}
static int rk3188_dmc_of_to_plat(struct udevice *dev)
{
-#if CONFIG_IS_ENABLED(OF_REAL)
struct rk3188_sdram_params *params = dev_get_plat(dev);
int ret;
+ if (!CONFIG_IS_ENABLED(OF_REAL))
+ return 0;
+
/* rk3188 supports only one-channel */
params->num_channels = 1;
ret = dev_read_u32_array(dev, "rockchip,pctl-timing",
ret = regmap_init_mem(dev_ofnode(dev), ¶ms->map);
if (ret)
return ret;
-#endif
return 0;
}
static int rk322x_dmc_of_to_plat(struct udevice *dev)
{
-#if CONFIG_IS_ENABLED(OF_REAL)
struct rk322x_sdram_params *params = dev_get_plat(dev);
const void *blob = gd->fdt_blob;
int node = dev_of_offset(dev);
int ret;
+ if (!CONFIG_IS_ENABLED(OF_REAL))
+ return 0;
+
params->num_channels = 1;
ret = fdtdec_get_int_array(blob, node, "rockchip,pctl-timing",
ret = regmap_init_mem(dev_ofnode(dev), ¶ms->map);
if (ret)
return ret;
-#endif
return 0;
}
static int rk3288_dmc_of_to_plat(struct udevice *dev)
{
-#if CONFIG_IS_ENABLED(OF_REAL)
struct rk3288_sdram_params *params = dev_get_plat(dev);
int ret;
+ if (!CONFIG_IS_ENABLED(OF_REAL))
+ return 0;
+
/* Rk3288 supports dual-channel, set default channel num to 2 */
params->num_channels = 2;
ret = dev_read_u32_array(dev, "rockchip,pctl-timing",
ret = regmap_init_mem(dev_ofnode(dev), ¶ms->map);
if (ret)
return ret;
-#endif
return 0;
}
static int rk3399_dmc_of_to_plat(struct udevice *dev)
{
-#if CONFIG_IS_ENABLED(OF_REAL)
struct rockchip_dmc_plat *plat = dev_get_plat(dev);
int ret;
+ if (!CONFIG_IS_ENABLED(OF_REAL))
+ return 0;
+
ret = dev_read_u32_array(dev, "rockchip,sdram-params",
(u32 *)&plat->sdram_params,
sizeof(plat->sdram_params) / sizeof(u32));
if (ret)
printf("%s: regmap failed %d\n", __func__, ret);
-#endif
return 0;
}
static int rockchip_spi_of_to_plat(struct udevice *bus)
{
-#if CONFIG_IS_ENABLED(OF_REAL)
struct rockchip_spi_plat *plat = dev_get_plat(bus);
struct rockchip_spi_priv *priv = dev_get_priv(bus);
int ret;
- plat->base = dev_read_addr(bus);
+ if (CONFIG_IS_ENABLED(OF_REAL)) {
+ plat->base = dev_read_addr(bus);
- ret = clk_get_by_index(bus, 0, &priv->clk);
- if (ret < 0) {
- debug("%s: Could not get clock for %s: %d\n", __func__,
- bus->name, ret);
- return ret;
- }
+ ret = clk_get_by_index(bus, 0, &priv->clk);
+ if (ret < 0) {
+ debug("%s: Could not get clock for %s: %d\n", __func__,
+ bus->name, ret);
+ return ret;
+ }
- plat->frequency =
- dev_read_u32_default(bus, "spi-max-frequency", 50000000);
- plat->deactivate_delay_us =
- dev_read_u32_default(bus, "spi-deactivate-delay", 0);
- plat->activate_delay_us =
- dev_read_u32_default(bus, "spi-activate-delay", 0);
+ plat->frequency = dev_read_u32_default(bus, "spi-max-frequency",
+ 50000000);
+ plat->deactivate_delay_us =
+ dev_read_u32_default(bus, "spi-deactivate-delay", 0);
+ plat->activate_delay_us =
+ dev_read_u32_default(bus, "spi-activate-delay", 0);
- debug("%s: base=%x, max-frequency=%d, deactivate_delay=%d\n",
- __func__, (uint)plat->base, plat->frequency,
- plat->deactivate_delay_us);
-#endif
+ debug("%s: base=%x, max-frequency=%d, deactivate_delay=%d\n",
+ __func__, (uint)plat->base, plat->frequency,
+ plat->deactivate_delay_us);
+ }
return 0;
}
static int spi_post_probe(struct udevice *bus)
{
-#if CONFIG_IS_ENABLED(OF_REAL)
- struct dm_spi_bus *spi = dev_get_uclass_priv(bus);
+ if (CONFIG_IS_ENABLED(OF_REAL)) {
+ struct dm_spi_bus *spi = dev_get_uclass_priv(bus);
- spi->max_hz = dev_read_u32_default(bus, "spi-max-frequency", 0);
-#endif
+ spi->max_hz = dev_read_u32_default(bus, "spi-max-frequency", 0);
+ }
#if defined(CONFIG_NEEDS_MANUAL_RELOC)
struct dm_spi_ops *ops = spi_get_ops(bus);
static int reloc_done;
/* The timer is available */
rate = timer_get_rate(gd->timer);
timer_get_count(gd->timer, &ticks);
-#if CONFIG_IS_ENABLED(OF_REAL)
- } else if (ret == -EAGAIN) {
+ } else if (CONFIG_IS_ENABLED(OF_REAL) && ret == -EAGAIN) {
/* We have been called so early that the DM is not ready,... */
ofnode node = offset_to_ofnode(-1);
struct rk_timer *timer = NULL;
debug("%s: could not read clock-frequency\n", __func__);
return 0;
}
-#endif
} else {
return 0;
}
static int rockchip_clk_of_to_plat(struct udevice *dev)
{
-#if CONFIG_IS_ENABLED(OF_REAL)
- struct rockchip_timer_priv *priv = dev_get_priv(dev);
+ if (CONFIG_IS_ENABLED(OF_REAL)) {
+ struct rockchip_timer_priv *priv = dev_get_priv(dev);
- priv->timer = dev_read_addr_ptr(dev);
- if (!priv->timer)
- return -ENOENT;
-#endif
+ priv->timer = dev_read_addr_ptr(dev);
+ if (!priv->timer)
+ return -ENOENT;
+ }
return 0;
}
static int timer_pre_probe(struct udevice *dev)
{
-#if CONFIG_IS_ENABLED(OF_REAL)
- struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
- struct clk timer_clk;
- int err;
- ulong ret;
+ if (CONFIG_IS_ENABLED(OF_REAL)) {
+ struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+ struct clk timer_clk;
+ int err;
+ ulong ret;
- /* It is possible that a timer device has a null ofnode */
- if (!dev_has_ofnode(dev))
- return 0;
+ /*
+ * It is possible that a timer device has a null ofnode
+ */
+ if (!dev_has_ofnode(dev))
+ return 0;
- err = clk_get_by_index(dev, 0, &timer_clk);
- if (!err) {
- ret = clk_get_rate(&timer_clk);
- if (IS_ERR_VALUE(ret))
- return ret;
- uc_priv->clock_rate = ret;
- } else {
- uc_priv->clock_rate =
- dev_read_u32_default(dev, "clock-frequency", 0);
+ err = clk_get_by_index(dev, 0, &timer_clk);
+ if (!err) {
+ ret = clk_get_rate(&timer_clk);
+ if (IS_ERR_VALUE(ret))
+ return ret;
+ uc_priv->clock_rate = ret;
+ } else {
+ uc_priv->clock_rate =
+ dev_read_u32_default(dev, "clock-frequency", 0);
+ }
}
-#endif
return 0;
}
if (gd->dm_root == NULL)
return -EAGAIN;
-#if CONFIG_IS_ENABLED(OF_REAL)
- /* Check for a chosen timer to be used for tick */
- node = ofnode_get_chosen_node("tick-timer");
-
- if (ofnode_valid(node) &&
- uclass_get_device_by_ofnode(UCLASS_TIMER, node, &dev)) {
- /*
- * If the timer is not marked to be bound before
- * relocation, bind it anyway.
- */
- if (!lists_bind_fdt(dm_root(), node, &dev, false)) {
- ret = device_probe(dev);
- if (ret)
- return ret;
+ if (CONFIG_IS_ENABLED(OF_REAL)) {
+ /* Check for a chosen timer to be used for tick */
+ node = ofnode_get_chosen_node("tick-timer");
+
+ if (ofnode_valid(node) &&
+ uclass_get_device_by_ofnode(UCLASS_TIMER, node, &dev)) {
+ /*
+ * If the timer is not marked to be bound before
+ * relocation, bind it anyway.
+ */
+ if (!lists_bind_fdt(dm_root(), node, &dev, false)) {
+ ret = device_probe(dev);
+ if (ret)
+ return ret;
+ }
}
}
-#endif
if (!dev) {
/* Fall back to the first available timer */