Use isHvxOperation(SDNode*) instead.
if (Opc == ISD::INLINEASM || Opc == ISD::INLINEASM_BR)
return LowerINLINEASM(Op, DAG);
- if (isHvxOperation(Op)) {
+ if (isHvxOperation(Op.getNode())) {
// If HVX lowering returns nothing, try the default lowering.
if (SDValue V = LowerHvxOperation(Op, DAG))
return V;
SDValue
HexagonTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI)
const {
- SDValue Op(N, 0);
- if (isHvxOperation(Op)) {
+ if (isHvxOperation(N)) {
if (SDValue V = PerformHvxDAGCombine(N, DCI))
return V;
return SDValue();
}
+ SDValue Op(N, 0);
const SDLoc &dl(Op);
unsigned Opc = Op.getOpcode();
findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT)
const override;
- bool isHvxOperation(SDValue Op) const;
bool isHvxOperation(SDNode *N) const;
SDValue LowerHvxOperation(SDValue Op, SelectionDAG &DAG) const;
void LowerHvxOperationWrapper(SDNode *N, SmallVectorImpl<SDValue> &Results,
}
bool
-HexagonTargetLowering::isHvxOperation(SDValue Op) const {
- // If the type of the result, or any operand type are HVX vector types,
- // this is an HVX operation.
- return Subtarget.isHVXVectorType(ty(Op), true) ||
- llvm::any_of(Op.getNode()->ops(),
- [this] (SDValue V) {
- return Subtarget.isHVXVectorType(ty(V), true);
- });
-}
-
-bool
HexagonTargetLowering::isHvxOperation(SDNode *N) const {
// If the type of any result, or any operand type are HVX vector types,
// this is an HVX operation.