setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
- if (Subtarget.is64Bit()) {
- if (!Subtarget.useSoftFloat() && Subtarget.hasAVX512())
- // f32/f64 are legal, f80 is custom.
- setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
- else
- setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
- setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
- } else if (!Subtarget.useSoftFloat()) {
+ if (!Subtarget.useSoftFloat()) {
// We have an algorithm for SSE2->double, and we turn this into a
// 64-bit FILD followed by conditional FADD for other targets.
setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
return Op;
}
+ // Promote i32 to i64 and use a signed conversion on 64-bit targets.
+ if (SrcVT == MVT::i32 && Subtarget.is64Bit()) {
+ N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, N0);
+ return DAG.getNode(ISD::SINT_TO_FP, dl, DstVT, N0);
+ }
+
if (SDValue V = LowerI64IntToFP_AVX512DQ(Op, DAG, Subtarget))
return V;
; AVX512_32-NEXT: popl %ebp
; AVX512_32-NEXT: retl
;
-; AVX512_64-LABEL: u32_to_x:
-; AVX512_64: # %bb.0:
-; AVX512_64-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero
-; AVX512_64-NEXT: vmovd %edi, %xmm1
-; AVX512_64-NEXT: vpor %xmm0, %xmm1, %xmm1
-; AVX512_64-NEXT: vsubsd %xmm0, %xmm1, %xmm0
-; AVX512_64-NEXT: vmovsd %xmm0, -{{[0-9]+}}(%rsp)
-; AVX512_64-NEXT: fldl -{{[0-9]+}}(%rsp)
-; AVX512_64-NEXT: retq
+; CHECK64-LABEL: u32_to_x:
+; CHECK64: # %bb.0:
+; CHECK64-NEXT: movl %edi, %eax
+; CHECK64-NEXT: movq %rax, -{{[0-9]+}}(%rsp)
+; CHECK64-NEXT: fildll -{{[0-9]+}}(%rsp)
+; CHECK64-NEXT: retq
;
; SSE2_32-LABEL: u32_to_x:
; SSE2_32: # %bb.0:
; SSE2_32-NEXT: popl %ebp
; SSE2_32-NEXT: retl
;
-; SSE2_64-LABEL: u32_to_x:
-; SSE2_64: # %bb.0:
-; SSE2_64-NEXT: movl %edi, %eax
-; SSE2_64-NEXT: movq %rax, -{{[0-9]+}}(%rsp)
-; SSE2_64-NEXT: fildll -{{[0-9]+}}(%rsp)
-; SSE2_64-NEXT: retq
-;
; X87-LABEL: u32_to_x:
; X87: # %bb.0:
; X87-NEXT: pushl %ebp