control_block->info = info;
control_block->src = src;
control_block->dst = dst;
- control_block->stride = 0;
+ control_block->stride = (upper_32_bits(dst) << 8) | upper_32_bits(src);
control_block->next = 0;
}
d->cb_list[frame - 1].cb)->next_cb =
to_bcm2711_cbaddr(cb_entry->paddr);
if (frame && !c->is_40bit_channel)
- d->cb_list[frame - 1].cb->next = cb_entry->paddr;
+ d->cb_list[frame - 1].cb->next = to_bcm2711_cbaddr(cb_entry->paddr);
/* update src and dst and length */
if (src && (info & BCM2835_DMA_S_INC)) {
writel(BCM2711_DMA40_ACTIVE | BCM2711_DMA40_PROT | BCM2711_DMA40_CS_FLAGS(c->dreq),
c->chan_base + BCM2711_DMA40_CS);
} else {
- writel(d->cb_list[0].paddr, c->chan_base + BCM2835_DMA_ADDR);
+ writel(BIT(31), c->chan_base + BCM2835_DMA_CS);
+
+ writel(to_bcm2711_cbaddr(d->cb_list[0].paddr),
+ c->chan_base + BCM2835_DMA_ADDR);
writel(BCM2835_DMA_ACTIVE | BCM2835_DMA_CS_FLAGS(c->dreq),
c->chan_base + BCM2835_DMA_CS);
}
d->cb_list[frames - 1].cb)->next_cb =
to_bcm2711_cbaddr(d->cb_list[0].paddr);
else
- d->cb_list[d->frames - 1].cb->next = d->cb_list[0].paddr;
+ d->cb_list[d->frames - 1].cb->next = to_bcm2711_cbaddr(d->cb_list[0].paddr);
return vchan_tx_prep(&c->vc, &d->vd, flags);
}