[InstCombine] add tests for icmp with mul op with known bits; NFC

D114962

diff --git a/llvm/test/Transforms/InstCombine/icmp-mul.ll b/llvm/test/Transforms/InstCombine/icmp-mul.ll
index 77f266b..785f285 100644 (file)
--- a/llvm/test/Transforms/InstCombine/icmp-mul.ll
+++ b/llvm/test/Transforms/InstCombine/icmp-mul.ll
@@ -762,12 +762,102 @@ define i1 @mul_of_bool_no_lz_other_op(i32 %x, i8 %y) {
 ; CHECK-NEXT:    [[B:%.*]] = and i32 [[X:%.*]], 1
 ; CHECK-NEXT:    [[S:%.*]] = sext i8 [[Y:%.*]] to i32
 ; CHECK-NEXT:    [[M:%.*]] = mul nuw nsw i32 [[B]], [[S]]
-; CHECK-NEXT:    [[R:%.*]] = icmp sgt i32 [[M]], 255
+; CHECK-NEXT:    [[R:%.*]] = icmp sgt i32 [[M]], 127
 ; CHECK-NEXT:    ret i1 [[R]]
 ;
   %b = and i32 %x, 1
   %s = sext i8 %y to i32
   %m = mul nuw nsw i32 %b, %s
-  %r = icmp sgt i32 %m, 255
+  %r = icmp sgt i32 %m, 127
+  ret i1 %r
+}
+
+define i1 @mul_of_pow2(i32 %x, i8 %y) {
+; CHECK-LABEL: @mul_of_pow2(
+; CHECK-NEXT:    [[B:%.*]] = and i32 [[X:%.*]], 2
+; CHECK-NEXT:    [[Z:%.*]] = zext i8 [[Y:%.*]] to i32
+; CHECK-NEXT:    [[M:%.*]] = mul nuw nsw i32 [[B]], [[Z]]
+; CHECK-NEXT:    [[R:%.*]] = icmp ugt i32 [[M]], 510
+; CHECK-NEXT:    ret i1 [[R]]
+;
+  %b = and i32 %x, 2
+  %z = zext i8 %y to i32
+  %m = mul i32 %b, %z
+  %r = icmp ugt i32 %m, 510
+  ret i1 %r
+}
+
+define i1 @mul_of_pow2_commute(i32 %x, i32 %y) {
+; CHECK-LABEL: @mul_of_pow2_commute(
+; CHECK-NEXT:    [[X4:%.*]] = and i32 [[X:%.*]], 4
+; CHECK-NEXT:    [[Y8:%.*]] = and i32 [[Y:%.*]], 255
+; CHECK-NEXT:    [[M:%.*]] = mul nuw nsw i32 [[Y8]], [[X4]]
+; CHECK-NEXT:    [[R:%.*]] = icmp ugt i32 [[M]], 1020
+; CHECK-NEXT:    ret i1 [[R]]
+;
+  %x4 = and i32 %x, 4
+  %y8 = and i32 %y, 255
+  %m = mul i32 %y8, %x4
+  %r = icmp ugt i32 %m, 1020
+  ret i1 %r
+}
+
+define i32 @mul_of_pow2s(i32 %x, i32 %y) {
+; CHECK-LABEL: @mul_of_pow2s(
+; CHECK-NEXT:    [[X8:%.*]] = and i32 [[X:%.*]], 8
+; CHECK-NEXT:    [[Y16:%.*]] = and i32 [[Y:%.*]], 16
+; CHECK-NEXT:    [[M:%.*]] = mul nuw nsw i32 [[X8]], [[Y16]]
+; CHECK-NEXT:    [[BIT7:%.*]] = or i32 [[M]], 128
+; CHECK-NEXT:    ret i32 [[BIT7]]
+;
+  %x8 = and i32 %x, 8
+  %y16 = and i32 %y, 16
+  %m = mul i32 %x8, %y16
+  %bit7 = or i32 %m, 128
+  ret i32 %bit7
+}
+
+define i1 @not_mul_of_pow2(i32 %x, i8 %y) {
+; CHECK-LABEL: @not_mul_of_pow2(
+; CHECK-NEXT:    [[Q:%.*]] = and i32 [[X:%.*]], 6
+; CHECK-NEXT:    [[Z:%.*]] = zext i8 [[Y:%.*]] to i32
+; CHECK-NEXT:    [[M:%.*]] = mul nuw nsw i32 [[Q]], [[Z]]
+; CHECK-NEXT:    [[R:%.*]] = icmp ugt i32 [[M]], 1530
+; CHECK-NEXT:    ret i1 [[R]]
+;
+  %q = and i32 %x, 6
+  %z = zext i8 %y to i32
+  %m = mul i32 %q, %z
+  %r = icmp ugt i32 %m, 1530
+  ret i1 %r
+}
+
+define i1 @not_mul_of_pow2_commute(i32 %x, i32 %y) {
+; CHECK-LABEL: @not_mul_of_pow2_commute(
+; CHECK-NEXT:    [[X30:%.*]] = and i32 [[X:%.*]], 12
+; CHECK-NEXT:    [[Y8:%.*]] = and i32 [[Y:%.*]], 255
+; CHECK-NEXT:    [[M:%.*]] = mul nuw nsw i32 [[Y8]], [[X30]]
+; CHECK-NEXT:    [[R:%.*]] = icmp ugt i32 [[M]], 3060
+; CHECK-NEXT:    ret i1 [[R]]
+;
+  %x30 = and i32 %x, 12
+  %y8 = and i32 %y, 255
+  %m = mul i32 %y8, %x30
+  %r = icmp ugt i32 %m, 3060
+  ret i1 %r
+}
+
+define i1 @mul_of_pow2_no_lz_other_op(i32 %x, i8 %y) {
+; CHECK-LABEL: @mul_of_pow2_no_lz_other_op(
+; CHECK-NEXT:    [[B:%.*]] = and i32 [[X:%.*]], 2
+; CHECK-NEXT:    [[S:%.*]] = sext i8 [[Y:%.*]] to i32
+; CHECK-NEXT:    [[M:%.*]] = mul nuw nsw i32 [[B]], [[S]]
+; CHECK-NEXT:    [[R:%.*]] = icmp sgt i32 [[M]], 254
+; CHECK-NEXT:    ret i1 [[R]]
+;
+  %b = and i32 %x, 2
+  %s = sext i8 %y to i32
+  %m = mul nuw nsw i32 %b, %s
+  %r = icmp sgt i32 %m, 254
   ret i1 %r
 }