BINARY_SQ(andnq, "(~%s) & %s")
BINARY_SQ(orq, "%s | %s")
BINARY_SQ(xorq, "%s ^ %s")
+BINARY_SQ(addq, "%s + %s")
+BINARY_SQ(subq, "%s - %s")
UNARY_BW(convsbw, "%s")
UNARY_BW(convubw, "(orc_uint8)%s")
}
+void
+emulate_addq (OrcOpcodeExecutor *ex, int offset, int n)
+{
+ int i;
+ orc_union64 * ORC_RESTRICT ptr0;
+ const orc_union64 * ORC_RESTRICT ptr4;
+ const orc_union64 * ORC_RESTRICT ptr5;
+ orc_union64 var32;
+ orc_union64 var33;
+ orc_union64 var34;
+
+ ptr0 = (orc_union64 *)ex->dest_ptrs[0];
+ ptr4 = (orc_union64 *)ex->src_ptrs[0];
+ ptr5 = (orc_union64 *)ex->src_ptrs[1];
+
+
+ for (i = 0; i < n; i++) {
+ /* 0: loadq */
+ var32 = ptr4[i];
+ /* 1: loadq */
+ var33 = ptr5[i];
+ /* 2: addq */
+ var34.i = var32.i + var33.i;
+ /* 3: storeq */
+ ptr0[i] = var34;
+ }
+
+}
+
+void
+emulate_subq (OrcOpcodeExecutor *ex, int offset, int n)
+{
+ int i;
+ orc_union64 * ORC_RESTRICT ptr0;
+ const orc_union64 * ORC_RESTRICT ptr4;
+ const orc_union64 * ORC_RESTRICT ptr5;
+ orc_union64 var32;
+ orc_union64 var33;
+ orc_union64 var34;
+
+ ptr0 = (orc_union64 *)ex->dest_ptrs[0];
+ ptr4 = (orc_union64 *)ex->src_ptrs[0];
+ ptr5 = (orc_union64 *)ex->src_ptrs[1];
+
+
+ for (i = 0; i < n; i++) {
+ /* 0: loadq */
+ var32 = ptr4[i];
+ /* 1: loadq */
+ var33 = ptr5[i];
+ /* 2: subq */
+ var34.i = var32.i - var33.i;
+ /* 3: storeq */
+ ptr0[i] = var34;
+ }
+
+}
+
void
emulate_convsbw (OrcOpcodeExecutor *ex, int offset, int n)
{
void emulate_andnq (OrcOpcodeExecutor *ex, int i, int n);
void emulate_orq (OrcOpcodeExecutor *ex, int i, int n);
void emulate_xorq (OrcOpcodeExecutor *ex, int i, int n);
+void emulate_addq (OrcOpcodeExecutor *ex, int i, int n);
+void emulate_subq (OrcOpcodeExecutor *ex, int i, int n);
void emulate_convsbw (OrcOpcodeExecutor *ex, int i, int n);
void emulate_convubw (OrcOpcodeExecutor *ex, int i, int n);
void emulate_splatbw (OrcOpcodeExecutor *ex, int i, int n);
{ "andnq", 0, { 8 }, { 8, 8 }, emulate_andnq },
{ "orq", 0, { 8 }, { 8, 8 }, emulate_orq },
{ "xorq", 0, { 8 }, { 8, 8 }, emulate_xorq },
+ { "addq", 0, { 8 }, { 8, 8 }, emulate_addq },
+ { "subq", 0, { 8 }, { 8, 8 }, emulate_subq },
{ "convsbw", 0, { 2 }, { 1 }, emulate_convsbw },
{ "convubw", 0, { 2 }, { 1 }, emulate_convubw },