x86, perfctr: don't use CCCR_OVF_PMI1 on Pentium 4Ds

Currently, setup_p4_watchdog() use CCCR_OVF_PMI1 to enable the counter
overflow interrupts to the second logical core. But this bit doesn't work
on Pentium 4 Ds (model 4, stepping 4) and this patch avoids its use on
these processors. Tested on 4 different machines that have this
specific model with success.

Signed-off-by: Aristeu Rozanski <aris@redhat.com>
Cc: jvillalovos@redhat.com
Signed-off-by: Ingo Molnar <mingo@elte.hu>

diff --git a/arch/x86/kernel/cpu/perfctr-watchdog.c b/arch/x86/kernel/cpu/perfctr-watchdog.c
index de7439f..05cc22d 100644 (file)
--- a/arch/x86/kernel/cpu/perfctr-watchdog.c
+++ b/arch/x86/kernel/cpu/perfctr-watchdog.c
@@ -478,7 +478,13 @@ static int setup_p4_watchdog(unsigned nmi_hz)
                perfctr_msr = MSR_P4_IQ_PERFCTR1;
                evntsel_msr = MSR_P4_CRU_ESCR0;
                cccr_msr = MSR_P4_IQ_CCCR1;
-               cccr_val = P4_CCCR_OVF_PMI1 | P4_CCCR_ESCR_SELECT(4);
+
+               /* Pentium 4 D processors don't support P4_CCCR_OVF_PMI1 */
+               if (boot_cpu_data.x86_model == 4 && boot_cpu_data.x86_mask == 4)
+                       cccr_val = P4_CCCR_OVF_PMI0;
+               else
+                       cccr_val = P4_CCCR_OVF_PMI1;
+               cccr_val |= P4_CCCR_ESCR_SELECT(4);
        }
 
        evntsel = P4_ESCR_EVENT_SELECT(0x3F)